WO2009055586A2

WO2009055586A2 - Channel virtualization for mobile video

Info

Publication number: WO2009055586A2
Application number: PCT/US2008/080982
Authority: WO
Inventors: Mohammad R. Moradi; Yu-Wen Chang (Evan); Afshin Shaybani; Sharath Narahari
Original assignee: Mediaphy Corporation
Priority date: 2007-10-23
Filing date: 2008-10-23
Publication date: 2009-04-30
Also published as: WO2009055586A3

Abstract

Systems, devices, methods, and software are described for the reception of wireless video signals at a receiver. Mobile digital broadcast video signals may be received, the signals corresponding to a series of video channels formatted according to a concatenated transmission standard. This series of video channels may be demodulated. A selected subset of two or more of the demodulated video channels may then be decoded, with the non-selected video channels excluded from decoding. When the number of demodulated channels to be decoded is reduced, various power management techniques are described which may be used to reduce power consumption.

Description

CHANNELVIRTUALIZATION FOR MOBILE VIDEO

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Appln. No. 60/982, 130, filed October 23, 2007, which is incorporated by reference in its entirety for all purposes.

BACKGROUND

[0002] The present invention relates to wireless communications generally and, more specifically, to wireless reception of video signals. There are a variety of different standards that may be used to wirelessly transmit video signals. By way of example, in some countries, mobile television ("Mobile TV") is provided through the Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) standard. In many implementations, ISDB-T includes a narrowband transmission of the same content transmitted at or about the same time as a wideband, high-definition (HD) transmission, but occupying a narrower frequency spectrum. [0003] As such, the Mobile TV tuners may be configured to tune into different frequencies to access various Mobile TV channels, and thus a tunable filter at the front-end of the system may be used. In order to view or record more than one channel, or view one channel and record another, some designs may include multiple tuners, which can be cost prohibitive for many applications. [0004] In a typical ISDB-T implementation, there are a series of consecutive 5.572 MHz bands of spectrum, separated by guard bands. Within each band, a narrowband transmission may be a 428 KHz segment, carrying the same content as the collective 12 segments (approximately 5 MHz) which surround it. There is an alternative provision often referred to as "concatenated transmission," whereby a number of different Mobile TV channels are concatenated and transmitted next to each other in a single 5.572 MHz frequency multiplex.

[0005] Using concatenated transmissions, content may not need to be tied to high definition content and can be independently developed for Mobile applications and audiences. In addition, up to 13 channels may be transmitted in a single 5.572 band in allocated, available spectrum. It may be desirable to realize novel receiver architectures to allow various video functions such as video recording, fast flipping of channels, and picture-in-picture to be provided for concatenated transmissions.

BRIEF DESCRIPTION OF THE DRAWINGS [0006] A further understanding of the nature and advantages of the present invention may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0007] FIG. 1 is a block diagram of a wireless system configured according to various embodiments of the invention.

[0008] FIG. 2 is a block diagram of a device configured according to various embodiments of the invention.

[0009] FIG. 3 is a block diagram illustrating a concatenated transmission according to various embodiments of the invention.

[0010] FIG. 4 is a block diagram of a device providing channel virtualization functionality according to various embodiments of the invention. [0011] FIG. 5 is a block diagram of a device providing a variety of channel selection and storage functionality for channel virtualization according to various embodiments of the invention.

[0012] FIG. 6 is a block diagram of an alternative device providing a variety of channel selection and storage functionality for channel virtualization according to various embodiments of the invention.

[0013] FIG. 7 is a flowchart illustrating a method of selecting video channels for decoding according to various embodiments of the invention.

[0014] FIG. 8 is a flowchart illustrating a method of utilizing different modes of operation in the selection of video channels to be decoded within a concatenated transmission according to various embodiments of the invention. [0015] FIG. 9 is a flowchart illustrating a method of selecting video channels for various stages of processing of a concatenated transmission according to various embodiments of the invention.

[0016] FIG. 10 is a block diagram of a device configured to control use of power during reception of a concatenated transmission of video channels according to various embodiments of the invention.

[0017] FIG. 11 is a block diagram of a device configured to control use of power when storing and selecting video channels for processing of a concatenated transmission according to various embodiments of the invention. [0018] FIG. 12 is a block diagram of a device configured to control use of power during different processing stages for video channels of a concatenated transmission, according to various embodiments of the invention.

[0019] FIG. 13A and 13B are timing diagrams related to reception of bursts of data according to various embodiments of the invention. [0020] FIG. 14A and 14B are block diagrams of component configurations to implement differential clock outputs according to various embodiments of the invention.

[0021] FIG. 15 is a flowchart illustrating a method for reducing power consumption during reception of video channels in a concatenated transmission according to various embodiments of the invention. [0022] FIG. 16 is a flowchart illustrating a method for utilizing different modes of operation to reduce power consumption during reception of video channels within a concatenated transmission according to various embodiments of the invention.

SUMMARY [0023] Systems, devices, processors, and methods are described for the reception of wireless signals at a receiver. In one set of embodiments, mobile digital broadcast video signals are received. These signals correspond to a series of video channels formatted according to a concatenated transmission standard. This series of video channels is demodulated. A selected subset of two or more of the demodulated video channels is decoded, with the non-selected video channels excluded from decoding. During different stages of processing and storage, a variety of techniques may be used to select subsets of the channels from previous stages for further processing or storage.

[0024] In another set of embodiments, mobile digital broadcast video signals are received, again corresponding to a series of video channels formatted according to a concatenated transmission standard. This series of video channels is demodulated. When the number of channels to be decoded is reduced, various power management techniques may be used to reduce power consumption. During different stages of processing and storage, a variety of power management techniques may be used to adapt power consumption to the actual number of channels being processed (e.g., by storing data for fewer channels or processing fewer channels).

DETAILED DESCRIPTION

[0025] Systems, devices, methods, and software are described for the reception of wireless video signals at a receiver. In various embodiments, mobile digital broadcast video signals are received. These signals correspond to a series of video channels formatted according to a concatenated transmission standard. This series of video channels is demodulated. A selected subset of two or more of the demodulated video channels is decoded, with the non- selected video channels excluded from decoding. When the number of channels to be decoded is reduced, various power management techniques may be used to reduce power consumption. During different stages of processing and storage, a variety of techniques may be used to select subsets of the channels from previous stages for further processing or storage; various power management techniques may be used to adapt power consumption to the actual number of channels being processed. Using the techniques described, playback functionality and power consumption may be balanced. [0026] The receiver may be configured to receive and process signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines, and certain resources in the engines may be used for a variety of the different standards. The hardware engines may be individually controlled in a number of aspects. For example, power to and the clock speed of particular hardware engines may be controlled.

[0027] The following description provides examples only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the ensuing description of the embodiments will provide those skilled in the art with an enabling description for implementing embodiments of the invention. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention.

[0028] Thus, various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, it should be appreciated that in alternative embodiments, the methods may be performed in an order different from that described, and that various steps may be added, omitted, or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. [0029] It should also be appreciated that the following systems, methods, and software may individually or collectively be components of a larger system, wherein other procedures may take precedence over or otherwise modify their application. Also, a number of steps may be required before, after, or concurrently with the following embodiments.

[0030] Novel receiver functionality is described for the reception of and processing of signals transmitted according to various mobile digital television standards. Turning first to FIG. 1, an example communications system 100 for implementing embodiments of the invention is illustrated. The system includes a mobile communications device 105. The mobile communications device 105 may be a cellular telephone, other mobile phone, personal digital assistant (PDA), portable video player, portable multimedia player, portable DVD player, laptop personal computer, a television in transportation means (including cars, buses, and trains), portable game console, digital still camera or video camcorder, or other device configured to receive wireless communications signals.

[0031] In the illustrated embodiment, the device 105 communicates with one or more base stations 110. A base station 110 may be one of a collection of base stations utilized as part of a system 100 that communicates with the device 105 using wireless signals. The device 105 may receive a wireless signal including a number of time-multiplexed bursts of data (e.g., a video broadcast signal) from the base station 110. Components of the device may be used to process a number of different standards, and be powered on or off (or otherwise suspended and reactivated) in series between bursts. The device 105 may include a processor with a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. For example, power to particular hardware engines may be switched on and off as a burst is processed through the hardware engines, and the speed of the different hardware engines may be varied. A variety of novel aspects of the system and device 105 will be described in detail below.

[0032] The base station 110 is in communication with a headend unit 115 that routes the communication signals between the network 120 and the base station 110. In other embodiments, other types of infrastructure network devices or sets of devices (e.g., servers or other computers) may also serve as an interface between a network 120 and the base station 110. For example, a headend unit 115 may communicate with a Mobile Switching Center (MSC) that can be configured to operate as an interface between the device 105 and a Public Switched Telephone Network (PSTN). [0033] The network 120 of the illustrated embodiment may be any type of network, and may include, for example, the Internet, an IP network, an intranet, a wide-area network (WAN), a local-area network (LAN), a virtual private network (VPN), the Public Switched Telephone Network (PSTN), or any other type of network supporting data communication between any devices described herein. A network 120 may include both wired and wireless connections, including optical links. The system 100 also includes a data source 125, which may be a server or other computer configured to transmit data (e.g., concatenated video transmission, or other video, audio, or other form of data) to the communications device 105 via the network 120.

[0034] It is worth noting that aspects of the present invention may be applied to a variety of devices (such as communications device 105) generally and, more specifically, may be applied to mobile digital television (MDTV) devices. Aspects of the present invention may be applied to digital video broadcast standards that are either in effect or are at various stages of development. These may include the European standard DVB-H, the Japanese standard ISDB-T, the Korean standards digital audio broadcasting (DAB)-based Terrestrial-DMB and Satellite-DMB, the Chinese standards DTV-M, Terrestrial-Mobile Multimedia Broadcasting (T-MMB), Satellite and terrestrial interaction multimedia (STiMi), and the MediaFLO format proposed by Qualcomm Inc. While certain embodiments of the present invention are described in the context of the ISDB-T standard, it may also be implemented in any of the above or future standards, and as such is not limited to any one particular standard. [0035] Referring to FIG. 2, a block diagram 200 of an example device 105-a is shown which illustrates various embodiments of the invention. The device 105-a may be the mobile communications device 105 of FIG. 1, or a processor, set of processors, or other combination of components integrated therein. In the embodiments described herein, assume an orthogonal frequency division multiplexing (OFDM) system is implemented, while realizing that the principles described are applicable to a multicarrier signal in a range of both wireless and wireline systems. [0036] The device 105 -a may be configured to receive a radio frequency (RF) signal via an antenna 205. As noted above, the device 105-a may be a mobile phone, PDA, iPAC, portable video player, portable multimedia player, portable DVD player, laptop PC, TV in transportation means (including cars, buses, and trains), portable game console, digital still camera or video camcorder, or any other mobile device. Also, while an assumption will be made that the system in certain embodiments implements ISDB-T, other embodiments of the invention may be implemented in a broader, narrower, or otherwise different range of standards.

[0037] The device 105-a includes a number of receiver components, which may include: an RF down-conversion and filtering unit 210, AfD unit 215, symbol synchronization unit 220, FFT unit 225, carrier frequency offset unit 230, equalizer unit 235, de-interleaver unit 240, and decoder unit 245. The device 105-a includes one or more memory units (not explicitly shown in this embodiment, but illustrated elsewhere) used for a variety of purposes. In one embodiment, the radio frequency signal (e.g., including a concatenated ISDB-T transmission) is received via an antenna 205. The desired signal is selected, down-converted, and filtered through the RF down-conversion and filtering unit 210. The output is converted into a digital signal by the AID unit 215. The RF down-conversion and filtering unit 210 and the AfD unit 215 may hereinafter be referred to collectively as an analog processing unit 260 (and may be controlled collectively or individually). It is worth noting that the RF down- conversion and filtering unit 210 or the AJD unit 215 may be external components, or may be integrated to varying degrees on a single chip with the hardware block 265 discussed in greater detail below. Those skilled in the art recognize the various options.

[0038] In one embodiment, this digitized signal is forwarded to and through a series of hardware engines, namely the symbol synchronization unit 220, FFT unit 225, carrier frequency offset unit 230, equalizer unit 235, de-interleaver unit 240, and decoder unit 245. The symbol synchronization unit 220, FFT unit 225, carrier frequency offset unit 230, equalizer unit 235, and de-interleaver unit 240 may be together referred to as the demodulator unit 270, performing the bulk of the PHY layer processing. The decoder unit 245 may perform both PHY and link layer processing. Various functions of the hardware engines may be set up and controlled by a supervisory block 250, also implemented in hardware.

[0039] In one embodiment, a hardware block 265 includes a symbol synchronization unit 220, FFT unit 225, carrier frequency offset unit 230, equalizer unit 235, de-interleaver unit 240, decoder unit 245, and supervisory block 250. Certain set-up, control, and other functions described herein may also be performed by an on or off chip central processing unit (CPU), or a host processor, which may be described as the additional processor unit 255. The additional processor unit 255 may, thus, control certain aspects of the hardware block 265 functionality. Throughout this Detailed Description, various functionality is described as capable of being performed by the supervisory block 250 or the additional processor unit 255. It is worth noting that, in various embodiments, any such functionality may be performed by the supervisory block 250, the additional processor unit 255, or any combination thereof.

[0040] Each respective hardware engine may be a distinct set of multipliers, adders, rounders, and memory configured to perform particular, designated tasks (e.g., symbol synchronization for the symbol synchronization unit 220, fast fourier transform processing for the FFT unit 225, and so on). The distinct set of multipliers, adders, rounders, and memory making up the symbol synchronization unit 220 may, therefore, be separate from (while being in communication with) the distinct set of multipliers, adders, rounders, and memory making up the FFT unit 225, carrier frequency offset unit 230, or equalizer unit 235, for example. Thus, the multipliers, adders, rounders, and memory making up each respective hardware engine may be allocated to performing the functions of the applicable unit, and not to functions of the other units.

[0041] In certain embodiments, resources (e.g., multipliers, adders, rounders, and/or memory) of a particular hardware engine (e.g, the FFT unit 225) may be shared for multiple standards (e.g., DVB-H, DMB, and ISDB-T). Resources (e.g., multipliers, adders, rounders, and/or memory) of a particular hardware engine (e.g, the carrier frequency offset unit 230) may also be different for each standard. For a particular device, some resources may be shared among different standards, while other resources are allocated to particular standards. Although certain units (e.g., symbol synchronization unit 220, equalizer unit 235) may be described broadly as a "hardware engine," the components that make up the unit may be referred to hardware engines, as well. For example, a time-domain interpolation unit and frequency-domain interpolation unit in the equalizer unit 235 could each be referred to individually as a hardware engine.

[0042] Returning to the description of the data path, the digitized signal from the AfD unit 215 is received by the symbol synchronization unit 220, where the signal is grouped into symbols with a symbol boundary properly identified, and the guard periods (typically cyclic prefix) removed. The signal is provided to FFT unit 225, where it is transformed to the frequency domain. The signal is then forwarded to the carrier frequency offset unit 230, where the frequency offset of the signal is corrected (e.g., integer and fractional). The functions of carrier frequency offset unit 230 and symbol synchronization unit 220 may be performed before and/or after the FFT is performed in other embodiments.

[0043] The signal is then processed by the equalizer unit 235. In one embodiment, the equalizer unit 235 processes the signal in the frequency domain. With orthogonality, a frequency-domain equalizer can be implemented separately for each sub-carrier. Since the symbols are separated by some guard time period, the inter-symbol-interference (ISI) may be avoided. Hence, such an equalization simply becomes a one-tap complex scaling. This complex tap coefficient can be determined adaptively through training, and may be updated during data transmission. In other embodiments, other equalizer functions and steps may be performed, for a range of standards. Engines of the equalizer unit 235 may be configured to share some resources among multiple standards, while for other functions certain engines only process a single standard or subset of standards.

[0044] The equalized data is de-interleaved at the de-interleaver unit 240 (for example, in one embodiment, frequency and time de-interleaving are performed). The decoder unit 245 performs error detection and correction (e.g., Viterbi and/or Reed-Solomon) to produce a stream of data. In some embodiments, there may be more than one decoder unit, each performing different decoding functions (for example, there may be an inner and outer decoder unit). The data from the decoder unit 245 is forwarded (perhaps after some additional processing and/or decoding) to an additional processor unit 255 (e.g., an on chip CPU or a host processor) for further processing.

[0045] FIG. 3 illustrates a diagram 300 showing an example of an ISDB-T concatenated transmission. A series of consecutive 5.572 MHz bands of spectrum 305 are shown, separated by guard bands 310. Traditionally, with each band 305, there may be a narrowband transmission in a single 428 KHz segment (e.g., SO), which is often referred to as a 1-seg transmission. This 1-seg transmission may carry the same content as the collective 12 segments 315 which surround it.

[0046] However, the diagram also illustrates a concatenated transmission, whereby mobile video broadcast channels are concatenated and transmitted next to each other in a single 5.572 MHz frequency multiplex. A concatenated transmission may be any wireless transmission wherein different video programs or content (e.g., a different video or graphic, or a different view of a same program) are transmitted in adjacent narrowband frequency slots. Using concatenated transmissions, content may not need to be tied to the surrounding high definition content, and can be independently developed for mobile applications and audiences. The transmission of up to 13 channels 315 (e.g., using 13 segments, SO-S 12, one segment for each channels) may be undertaken in a single 5.572 MHz band in allocated, available spectrum.

[0047] It is worth noting that there may be other types of standards used for concatenated transmissions instead of ISDB-T. In other embodiments, different distributions of segments are possible (e.g., two or three segments may be used for the same content for some transmissions), and the size of the frequency bands may vary. Thus, while in some embodiments there may be 13 channels, in others there may be eight (five wider channels could have higher definition). Concatenated transmissions may include any three or more adjacent frequency bands, as long as each band has different content. [0048] In the following discussion, it may be assumed that 13 different ISDB-T channels in a single 5.572 MHz frequency are received at a wideband receiver capable of receiving the entire 13 segments at once. However, it must be emphasized that the functionality described herein may be used with a number of current and future standards, and a variety of standards, frequency bands, channels sizes, etc. may be used in other embodiments. [0049] Referring to FIG. 4, a block diagram 400 illustrates a device 105-b providing channel virtualization functionality according to various embodiments of the invention. The device 105-b may be the device 105 of FIG. 1 or 2, although the illustrated configuration may be utilized in a number of different processors or devices. The device 105-b includes an antenna 205, analog processing units 260, demodulator unit 270, channel selection unit 405, and decoder unit 245-a. The channel selection unit 405 may be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2. The demodulator unit 270 and decoder unit 245-a may be implemented with the hardware engines described with reference to FIG. 2, or other configurations may be used. In one embodiment, therefore, demodulator unit 270, channel selection unit 405, and decoder unit 245-a may be implemented as hardware block 265.

[0050] An RF signal is received via an antenna 205, and down-converted and digitized by the analog processing units 260. The RF signal may be mobile digital broadcast video signals corresponding to a set of video channels formatted according to the concatenated transmission standard of ISDB-T. The analog processing units 260 may generate a stream of data representative of the mobile digital broadcast video signals. The demodulator unit 270 may demodulate the stream of data (e.g., in what equates to processing in parallel, until the interleaved signals are frequency and time de-interleaved), to generate a demodulated output of each of the set of video channels.

[0051] The channel selection unit 405 may be configured to select a subset the demodulated video channels for further storage and/or processing. In one embodiment, the channel selection unit 405 may select two or more of the demodulated video channels; in other embodiments, the channel selection unit 405 may select one of the demodulated video channels, or may select any number of channels from one to 13.

[0052] Each of 13 virtual channels may be a synthesis of video segments for each of the separate channels, and thus the channel selection unit 405 may effectively function as a synthesizer of the segment stream for processing through the decoder unit 245-a. Depending on the control information, all or a subset of the video data corresponding to 13 channels thus may be pushed through to the decoder unit 245-a. The decoder unit 245-a may be configured to decode the selected subset of video channels (e.g., for display in single or multiview display unit). The decoder unit 245-a may process each channel segment (or set of channels segments) in serial, dedicating a given set of resources to each channel to be decoded, progressing through such channels in round robin fashion.

[0053] Referring next to FIG. 5, a block diagram 500 illustrates a device 550 providing a variety of channel selection functionality for channel virtualization according to various embodiments of the invention.. The device 550 may be the device 105 of FIG. 1, 2, or 4, although the illustrated configuration may be utilized in a number of different processors or devices. The illustrated components of the device 550 include a demodulator unit 270-a (including frequency de-interleaver 505 and time de-interleaver 510), demodulator memory unit 515, channel selection unit 405-a, decoder unit 245-b (including slicer 520, bit de- interleaver 525, and decoder 530), decoder memory unit 535, output selection unit 540, and processor interface 545, each of which may be in communication with each other directly or indirectly. The channel selection unit 405-a and output selection unit 540 may each, or in combination, be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2.

[0054] Mobile digital broadcast video signals corresponding to a set of video channels formatted according to a concatenated transmission standard may be received by the device 550. After some initial processing (e.g., by other components of the demodulator unit 270-a), an equalized stream of data 502 may be generated (e.g., by an equalizer unit (not shown)). The stream of data 502 may be processed by the frequency de-interleaver 505 and time de- interleaver 510 to generate a demodulated stream of data representative a number of video segments corresponding to the complete set (e.g., 13) of video channels.

[0055] As described above, the channel selection unit 405-a may be configured to select a subset of the demodulated video channels for storage at the demodulator memory unit 515 and further processing at the decoder unit 245-b. The same selected video channels may be stored at the demodulator memory unit 515 and processed at the decoder unit 245-b, although in other embodiments only a selected subset of the stored channels are subsequently decoded by the decoder unit 245-b. Thus, the channel selection unit 405-a may be configured to effectively exclude the non-selected channels from further storage and/or decoding, as applicable.

[0056] The video segments for the channels identified for further processing may be forwarded to the decoder unit 245-b which may be configured to perform decoding on the selected subset of video channels (e.g., by accessing the demodulator memory unit 515). The selected demodulated channels may be processed at the decoder unit 245-b by the slicer 520, bit de-interleaver 525, and decoder 530 (e.g., an inner Viterbi decoder) to generate a decoded stream of data representative of the selected channels. In one embodiment, the decoder unit 245-b processes from one to 13 channels sequentially at such throughput speed that the need for parallel processing at each engine in the decoder unit 245-a is eliminated. The clock domain for the decoder unit 245-b may have a dynamically adjustable frequency to provide for efficient serial processing of one to 13 channels (as will be discussed in greater detail below). [0057] An output selection unit 540 may then select a subset of the decoded video channels for further storage and/or processing. In one embodiment, the output selection unit 540 may select two or more of the decoded video channels; in other embodiments, the output selection unit 540 may select one of the demodulated video channels, or may select any number of channels from one to 13. More specifically, the output selection unit 540 may select a subset of the decoded video channels for storage at the decoder memory unit 535 and forwarding to a processor interface 545. The same selected video channels may be stored at the decoder memory unit 535 and forwarded to the processor interface, although in other embodiments only a selected subset of the stored channels are subsequently forwarded. [0058] By way of example, the channel selection unit 405 -a may feed video data corresponding to all 13 channels for processing by the decoder unit 245-b, and the output selection unit 540 may only push one or two selected channels through to the processor interface 545. Alternatively, channel selection unit 405-a may feed video data corresponding to two channels for processing by the decoder unit 245-b, and the output selection unit 540 may only push one or two channels through to the processor interface 545. In still other embodiments, the number of channels selected by the channel selection unit 405-a and output selection unit 540 may be the same. Those skilled in the art recognize a tradeoff, as when more channels are pushed further through the processing chain, they may be available for faster switching, storage for later use, or multiview formats (depending on how far they are pushed through the processing chain). However, this additional functionality may come at a cost of greater power consumption.

[0059] The processor interface 545 may be an interface between certain digital logic and an additional processor (e.g., an on or off chip CPU or host processor, not shown). In one embodiment, the processor interface is to an Applications/Media Processor. The Applications/Media Processor may, for example, store the video data (or particular channels thereof) on external or other system memory, such as an SD card, flash memory, hard disk drive or the like. In the case of a laptop or personal computer, the hard disk or flash memory of the computer may be used for storing of video data to be viewed later. The aggregate bit rate of the processor interface may be equivalent to the sum of bit rates of each individual channel being forwarded.

[0060] The demodulator memory unit 515 and decoder memory unit 535 may be distinct memory regions, and can reside on chip or off chip (or any combination thereof) in the form of a separate memory chip or as part of a Multi-Chip Module (MCM) or System In Package (SiP). For the demodulator memory unit 515 and decoder memory unit 535, the memory space for each may be partitioned into N segments where N is the number of channels to be stored at the particular unit. Pre-assignment of blocks of memory for each and every one of the available channels (e.g., 13 channels in ISDB-T) may be performed, but can result in inefficient usage of available memory as not all channels may be recorded and, for those channels that are recorded, recording times may not be the same. Dynamic assignment of blocks of memory for only those channels that will be processed further may also be undertaken, and may provide greater memory utilization. [0061] One method to record channels is to subdivide the memory into M smaller segments (each with a unique ID) and save the channel information as they come into these small segments. Note that the smaller the segments, the less the chance for inefficient memory usage. An appropriate balance between the size of the segments and processing overhead may be obtained depending on the particular application. Even when memory resources are available both on chip and off, there is reason to judiciously allocate memory to optimally address a number of channels requested by a user for recording and to optimize total recording time for a set of channels selected for recording.

[0062] Referring next to FIG. 6, a block diagram 600 illustrates an alternative device 650 for providing a variety of channel selection and storage functionality for channel virtualization according to various embodiments of the invention. The device 650 may be the device 105 of FIG. 1, 2, or 4, or the device 550 of FIG. 5, although the illustrated configuration may also be utilized in other processors or devices. The illustrated components of the device 650 include a demodulator unit 270-b, first memory unit 605, channel selection unit 405-b, decoder unit (inner) 245-c, second memory unit 610, output selection unit 540-a, outer decoder unit 615, and display unit 620, each of which may be in communication with each other directly or indirectly. The channel selection unit 405-b and output selection unit 540-a may each, or in combination, be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2.

[0063] Mobile digital broadcast video signals corresponding to a set of video channels formatted according to a concatenated transmission standard may be received by the device 650. After some initial processing (e.g., by analog processing units 260), the demodulator unit 270-b may receive a digitized stream of data 602 representative of the set of video channels in the mobile digital broadcast video signals. The stream of data 602 may be processed by the demodulator unit 270-b to generate a demodulated stream of data representative of a number of video segments corresponding to the complete set (e.g., 13) of video channels. The demodulator unit 270-b may, for example, perform symbol synchronization, FFT, frequency offset, equalization, and de-interleaver functions on the complete set of video channels, and the channels may be processed in parallel.

[0064] The channel selection unit 405-b may be configured to select a subset of the demodulated video channels for storage at the first memory unit 605, and then select all or a subset of the stored demodulated signals for further processing at the inner decoder unit 245- c. Thus, while the same selected video channels may be stored at the first memory unit 605 and processed at the decoder unit 245-c, in other embodiments only a selected subset of the stored channels is subsequently decoded by the decoder unit 245-c.

[0065] In one set of embodiments, the device 650 may implement the channel selection process by operating in different modes. For example, in a first mode (a power saving mode), the channel selection unit 405-b selects only one of the demodulated video channels for decoding (and, perhaps, later display). In a second mode, the channel selection unit 405-b selects only two of the demodulated video channels for decoding, and one or both of such signals may then be displayed. In a third mode, the channel selection unit 405-b selects only three of the demodulated video channels for decoding, and one, two, or three of such signals may then be displayed. Other modes are possible, as well.

[0066] Regardless of the mode or the channels selected, video segments for the channels to be processed further may be forwarded to the inner decoder unit 245-c which may be configured to perform decoding on the selected subset of video channels (e.g., from the memory unit 605, where the demodulated channels are stored). The selected demodulated channels may be processed at the inner decoder unit 245-c (e.g., performing Viterbi decoding) to generate a decoded stream of data representative of such channels.

[0067] An output selection unit 540-a may then select all, or a subset, of the decoded video channels (e.g., one, two, or more) for further storage and/or processing. The same selected video channels may be stored at the second memory unit 610 and forwarded to the processor interface, although in other embodiments only a selected subset of the channels stored at the second memory unit 610 are subsequently forwarded. [0068] Thus, the output selection unit 540-a may push only one selected channel through to the outer decoder unit 615, or the number may be two or more. The outer decoder unit 615 may, for example, be configured to perform Reed-Solomon decoding on the selected subset of video channels decoded by the inner decoder unit 245-c, and forward such channels to the display unit 620.

[0069] A display unit 620 (e.g., a display screen on a mobile communications device, or an external display screen) may be configured to display a selected one, or more, of the decoded video channels from the outer decoder unit 615. In one embodiment, the display unit 620 is configured to display a single channel only, regardless of mode. Thus, if operating in the first mode (where only one channel is decoded at a time), there may be increased delay when channels are switched (as the new channel selected must be decoded). For example, in the first mode, when a new channel is selected, the new channel will begin to be decoded instead of continuing to decode the previously selected channel.

[0070] If operating in the second mode (where two channels are decoded at a same time), or other mode where multiple channels are decoded simultaneously, there may be lessened delay when channels are switched (e.g., because a second channel is already being decoded).

To lessen delays in switching, user-identified favorite channels or immediately adjacent channels may be processed further (e.g., stored and decoded) on an ongoing basis so that when selected, less processing need be undertaken before the new channel may be displayed. The display unit 620 may display only a subset of the channels received from the outer decoder unit 615, and may thus effectively be excluding the non-selected decoded video channels from display.

[0071] In other embodiments, the display unit 620 may be configured to display a first and second one of the decoded channels simultaneously in a multiview format (e.g., a split screen, picture-in-picture, or multiple display format). The selection of the particular channel or channels to be viewed may be made by a user of the device 650. The user selection process may be managed by a controller (not shown), such as the supervisory block 250 or additional processor 255 of FIG. 2. By way of example, a user may select the TV channel(s) to be recorded and/or viewed via a graphical user interface (GUI) (not shown). The user may select any one or more of the available channels (e.g., 13 channels), and the type of storage and display desired. The user-selected channel information, and the mode, may dictate which channels are to be stored and/or processed at different processing stages according to predefined or configurable rules on the device 650.

[0072] FIG. 7 is a flowchart illustrating a method 700 of controlling power to hardware engines according to various embodiments of the invention. The method 700 may, for example, be performed in whole or in part with the device 105 of FIG. 1, 2, or 3, the device 550 of FIG. 5, or the device 650 of FIG. 6.

[0073] At block 705, mobile digital broadcast video signals are received corresponding to video channels formatted according to a concatenated transmission standard. At block 710, the video channels of the mobile digital broadcast video signals are demodulated. At block 715, a selected subset of two or more of the demodulated video channels are decoded, with the non-selected video channels excluded from decoding.

[0074] FIG. 8 is a flowchart illustrating a method 800 of utilizing different modes of operation in the selection of video channels to be decoded within a concatenated transmission according to various embodiments of the invention. The method 800 may, for example, be performed in whole or in part with the device 105 of FIG. 1, 2, or 3, the device 550 of FIG. 5, or the device 650 of FIG. 6.

[0075] At block 805, mobile digital broadcast video signals are received which correspond to video channels formatted according to a concatenated transmission standard. At block 810, a stream of data representative of the video channels is generated. At block 815, a first one of the video channels from the stream of data is selected in a first mode. At block 820, in the first mode, the selected video channel is decoded. At block 825, in a second mode, two or more of the video channels from the stream of data are selected. At block 830, in the second mode, the two or more selected video channels are decoded, and the non-selected video channels in the second mode are excluded from decoding. [0076] FIG. 9 is a flowchart illustrating a method 900 of video channel selection during various stages of processing of a concatenated transmission according to various embodiments of the invention. The method 900 may, for example, be performed in whole or in part with the device 105 of FIG. 1, 2, or 3, the device 550 of FIG. 5, or the device 650 of FIG. 6. [0077] At block 905, mobile digital broadcast video signals are received corresponding to video channels formatted according to a concatenated transmission standard. At block 910, a stream of data representative of the video channels is generated. At block 915, the video channels are demodulated. At block 920, a subset of two or more demodulated video channels is selected. At block 925, the selected demodulated video channels are stored, while excluding the non-selected demodulated video channels from storage. [0078] At block 930, Viterbi decoding is performed on the selected video channels. At block 935, the selected Viterbi decoded video channel(s) are stored. At block 940, a subset of first one of the Viterbi decoded video channels is selected. At block 945, Reed-Solomon (RS) decoding is performed on the selected Viterbi decoded video channels. At block 950, operating in a first mode, the first channel is displayed. At block 955, and continuing to operate in a first mode, a switch is made to select, RS decode, and display a second one of the Viterbi decoded channels. At block 960, operating in a second mode, the first and second channels are selected, RS decoded, and displayed in a multiview format.

[0079] As described above, at different stages of processing and storage, a variety of channel selection techniques may be used to select subsets of the channels from previous stages for further processing or storage. Playback functionality may be improved with such techniques, although this improved functionality may come at the expense of power consumption. Therefore, in another set of embodiments, when the number of channels to be decoded is reduced, various power management techniques may be used to reduce power consumption. In addition, during various stages of processing and storage, a variety of power management techniques may be used to adapt power consumption to the actual number of channels being processed.

[0080] Referring to FIG. 10, a block diagram 1000 illustrates a device 105-c configured to control use of power during reception of a concatenated transmission of video channels according to various embodiments of the invention. The device 105-c may be the device 105 of FIG. 1, 2, or 4, although the illustrated configuration may be utilized in a number of different processors or devices. The device 105-c includes an antenna 205, analog processing units 260, demodulator unit 270, power controller unit 1005, and decoder unit 245, each which may communicate with another directly or indirectly. The power controller unit 1005 may be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2, and thus may be integrated with the channel selection unit 405 or output selection unit 540 discussed above. The demodulator unit 270 and decoder unit 245 may be implemented with the hardware engines described with reference to FIG. 2, or other configurations may be used. In one embodiment, therefore, demodulator unit 270, channel selection unit 405, and decoder unit 245 may be implemented as hardware block 265.

[0081] An RF signal is received via an antenna 205, and down-converted and digitized by the analog processing units 260. The RF signal may be mobile digital broadcast video signals corresponding to a set of video channels formatted according to the concatenated transmission standard of ISDB-T. The analog processing units 260 may generate a stream of data representative of the mobile digital broadcast video signals. The demodulator unit 270 may demodulate the stream of data (e.g., in what equates to processing in parallel, until the interleaved signals are frequency and time de-interleaved), to generate a demodulated output of each of the set of video channels .

[0082] The power controller unit 1005 may be configured to identify a change in a number of the demodulated plurality of video channels to be decoded. To do so, the power controller unit 1005 may monitor, or receive data from, the demodulator unit 270, decoder unit 245, or other controller (such as channel selection unit 405). For example, the power controller unit 1005 may identify a decrease in a number of the demodulated video channels to be decoded. In response to such identification, power controller unit 1005 may control an aggregate processing rate of the decoder unit 245 to adapt to the decreased number of video channels to be decoded and thereby reduce power consumption. The decoder unit 245 may be configured to decode the reduced number of demodulated video channels at the controlled rate. Depending on the control information, all or a subset of the video data corresponding to up to n channels thus may be pushed through to the decoder unit 245, adapting an aggregate decoding rate to reduce power consumption. The decoder unit 245 may process a channel segment (or set of channel segments) in serial for each channel to be decoded, dedicating a given set of resources to each such channel for a particular time period, progressing through such channels in round robin fashion. The decoder unit 245 may be configured to decode the selected subset of video channels for display in single or multiview display unit.

[0083] By way of example, the power controller unit 1005 may control the decoder unit 245 (or other engines or processors of the device 105-c) utilizing one, or a combination, of the following techniques. For example, the power controller unit 1005 may be configured to control the aggregate processing rate by withholding power to the decoder unit 245 for an increased proportion of time during the decoding of the reduced number of demodulated video channels. The power controller unit 1005 may withhold power by withholding a clock signal from at least a portion of the decoder unit 245 (e.g., when the decoder unit 245 is a distinct set of hardware engines controlled independently from the clock signal of the demodulator unit 270). Similarly, the power controller unit 1005 may withhold power by powering off a decoder unit 245 (e.g., when the decoder unit 245 is a distinct set of hardware engines controlled independently of the demodulator unit 270). In still another embodiment, the power controller unit 1005 may be configured to control the aggregate processing rate by changing a clock output for a clock domain of the decoder unit 245 from a first frequency to a second, lower frequency to decode the reduced number of demodulated video channels, wherein the clock domain of the decoder unit 245 and a clock domain of the demodulator unit 270 are different clock domains. The clock output for the decoder unit 245 may be accelerated as more channels are to be decoded. It is worth noting that while the above power reduction techniques are described with reference tot the decoder unit 245, they may be applied by the power controller unit 1005 to other engines or processors of the device 105- c. [0084] Referring next to FIG. 11, a block diagram 1100 illustrates a device 1150 configured to control use of power when storing and selecting video channels for processing of a concatenated transmission according to various embodiments of the invention. The device 1150 may be the device 105 of FIG. 1, 2, 4, or 10, although the illustrated configuration may also be utilized in other processors or devices. The illustrated components of the device 1150 include a power controller unit 1005-a, demodulator unit 270-c, first memory unit 1105, channel selection unit 405-c, decoder unit 245-d , second memory unit 1110, output selection unit 540-b, additional processing units 1115, and display unit 1120, and the power controller unit 1005-a may control each of such units. Although depicted separately, the power controller unit 1005-a, channel selection unit 405-c and output selection unit 540-b may each, or in combination, be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2.

[0085] Mobile digital broadcast video signals corresponding to a set of video channels formatted according to a concatenated transmission standard may be received by the device 1150. After some initial processing (e.g., by analog processing units 260), the demodulator unit 270-c may receive a digitized stream of data 1102 representative of the set of video channels in the mobile digital broadcast video signals. The stream of data 1102 may be processed by the demodulator unit 270-c to generate a demodulated stream of data representative of a number of video segments corresponding to the complete set (e.g., 13) of video channels. The demodulator unit 270-c may, for example, perform symbol synchronization, FFT, frequency offset, equalization, and de-interleaver functions on the complete set of video channels, and the channels may be processed in parallel.

[0086] The channel selection unit 405-c may be configured to select a subset of the demodulated video channels for storage at the first memory unit 1105. The power controller unit 1005-a may be configured to control the first memory unit 1105 to power down a portion of memory in response to a decrease in the number of demodulated video channels to be decoded. The power controller unit 1005-a may be configured to control the first memory unit 1105 to power up a portion of memory in response to a increase in the number of demodulated video channels to be decoded. The channel selection unit 405-c may then select all or a subset of the stored demodulated signals for further processing at the decoder unit 245-d. The power controller unit 1005-a may monitor, or receive data from, the channel selection unit 405-c to identify a change in the number of the demodulated plurality of video channels to be decoded. The power controller unit 1005-a may, then, control an aggregate processing rate of the decoder unit 245-d to adapt to the decreased (or increased) number of video channels to be decoded and thereby control power consumption. Note that while the same selected video channels may be stored at the first memory unit 1105 and processed at the decoder unit 245-d, in other embodiments only a selected subset of the stored channels are subsequently decoded by the decoder unit 245-d. Thus, the power controller unit 1005-a may be configured to control power to each unit independently, or the control may be coordinated.

[0087] In one set of embodiments, the device 1150 may implement the channel selection process by operating in different modes. For example, in a first mode (a power saving mode), the channel selection unit 405-c selects only one of the demodulated video channels for decoding. In the first mode, the power controller unit 1005-a may control the decoder unit 245-d to operate at a slower aggregate processing rate for decoding (as only one channel is being decoded). In a second mode, the channel selection unit 405-c selects only two of the demodulated video channels for decoding, and one or both of such signals may then be displayed. In the second mode, the power controller unit 1005-a may control the decoder unit 245-d to operate at a standard aggregate processing rate for decoding. In a third mode, the channel selection unit 405-c selects only three of the demodulated video channels for decoding, and one, two, or three of such signals may then be displayed. In the third mode, the power controller unit 1005-a may control the decoder unit 245-d to operate at an accelerated aggregate processing rate for decoding. Other modes are possible, as well (e.g., decoding all 13 channels at maximum rate).

[0088] Video segments for the channels to be processed further may be forwarded to, or otherwise accessed by, the decoder unit 245-d to perform decoding (e.g., Viterbi decoding) on the selected subset of video channels at the controlled rate. An output selection unit 540-b may then select all, or a subset, of the decoded video channels (e.g., one, two, or more) for further storage and/or processing. The same selected video channels may be stored at the second memory unit 1110 and forwarded to the additional processing units 1115, although in other embodiments only a selected subset of the channels stored at the second memory unit 1110 are subsequently forwarded.

[0089] The power controller unit 1005-a may be configured to control the second memory unit 1110 to power down a portion of memory in response to a decrease in the number of decoded video channels to be stored for additional processing and/or display. The power controller unit 1005-a may be configured to control the second memory unit 1110 to power up a portion of memory in response to an increase in the number of decoded video channels to be stored for additional processing and/or display. The output selection unit 540-b may then select all or a subset of the stored decoded signals for further processing at the additional processing units 1115. The power controller unit 1005-a may monitor, or receive data from, the output selection unit 540-b to identify a change in the number of the decoded video channels to be processed further. The power controller unit 1005-a may, then, control an aggregate processing rate to adapt to the decreased (or increased) number of video channels to be further processed by the additional processing units 1115, and thereby control power consumption.

[0090] Thus, the output selection unit 540-b may push only one selected channel through to the additional processing units 1115 (e.g., which may perform descrambling, Reed-Solomon decoding, media or application functions, etc. on the selected channel), or the number may be two or more. A display unit 1120 (e.g., a display screen on a mobile communications device, or an external display screen) may be configured to display a selected one, or more, of the decoded video channels. The preceding discussion illustrates an example architecture to allow power consumption to be moderated through the processing chain as more or fewer channels are stored and/or processed at different points in the chain. [0091] Referring next to FIG. 12, a block diagram 1200 illustrates a device 1250 configured to control use of power when storing and selecting video channels for processing of a concatenated transmission according to various embodiments of the invention. The device 1250 may be the device 105 of FIG. 1, 2, 4, or 10, or the device 1150 of FIG. 11, although the illustrated configuration may also be utilized in other processors or devices. The illustrated components of the device 1250 include a power controller unit 1005-b, analog processing units 260-a, demodulator unit 270-d, demodulator memory unit 1205, decoder unit (inner) 245-e, decoder memory unit 1210, outer decoder unit 1215, and processor interface 1220; the power controller unit 1005-b may control each of such units. The power controller unit 1005-b may be a controller such as the supervisory block 250 or additional processor 255 of FIG. 2.

[0092] An analog signal 1202 is received (e.g., via an antenna(not shown)), and down- converted and digitized by the analog processing units 260-a. The analog signal 1202 may be mobile digital broadcast video signals corresponding to a set of video channels formatted according to the concatenated transmission standard of ISDB-T. The analog processing units 260-a may generate a stream of data representative of the mobile digital broadcast video signals. To conserve power, the power controller unit 1005-b may be configured to adapt the sampling rate of an A/D unit (not shown) in the analog processing units 260-a based on the channel selected. For example, consider an embodiment wherein only one channel is to be decoded (e.g., post-demodulation, the device 1250 processes one channel only). The A/D unit in the analog processing units 260-a may be controlled by the power controller unit 1005-b to sample at optimal rate depending on the channel selected. Sampling rate may be increased as the selected frequency moves further away from DC (e.g., referring to FIG. 3, if SO is downconverted to DC, the sampling rate would be increased as the selected channel was closer S 12, and decreased as the selected channel was closer to SO).

[0093] The demodulator unit 270-d may demodulate the stream of data (e.g., in what equates to processing in parallel, until the interleaved signals are frequency and time de- interleaved), to generate a demodulated output of each of the set of video channels. Within the demodulator, the FFT unit (not shown) may process the entire 5.572 MHz spectrum encompassing all, for example, 13 channels (regardless of whether one, two, or 13, channels are selected for decoding). The power controller unit 1005-b may, however, optimize power consumption at the FFT unit or at other units of the demodulator unit 270-d depending on the location and number of channels selected. Therefore, while 13 channels may be demodulated in a typical implementation, the power consumption of the demodulator unit 270-d may be modified depending on the location and number of channels to be decoded.

[0094] The demodulated video channels may be stored at the first memory unit 1205 (which may, but need not be, physically distinct from the second memory unit 1210). The power controller unit 1005-b may be configured to control the first memory unit 1205 to power only a region of memory which is proportional to the number of channels selected for further processing (e.g., powering down a portion of memory in response to a decrease in the number of demodulated video channels to be decoded). The power controller unit 1005-b may monitor, or receive data from, the inner decoder unit 245-e to identify a change in the number of the demodulated plurality of video channels to be decoded. The power controller unit 1005-b may, then, control an aggregate processing rate of the inner decoder unit 245-e to adapt to the decreased (or increased) number of video channels to be decoded (e.g., Viterbi decoded by the inner decoder unit 245-e). Note that while the same selected video channels may be stored at the first memory unit 1205 and processed at the decoder unit 245-d, in other embodiments only a selected subset of the stored channels are subsequently decoded. Video segments for the channels to be processed further may be forwarded to, or otherwise accessed by, the decoder unit 245-e to perform decoding on the selected subset of video channels at the controlled rate.

[0095] The decoded video channels (from decoder unit 245-e) may be stored at the second memory unit 1210. The power controller unit 1005-b may control the second memory unit 1210 to power only a region of memory which is proportional to the number of channels selected for further processing by the outer decoder unit 1215 and the processor interface 1220 (e.g., powering down a portion of memory in response to a decrease in the number of decoded video channels to be further processed). These may, for example, be only the channels that are to be displayed, while they may also include other channels to be stored.

[0096] The power controller unit 1005-b may monitor, or receive data from, the outer decoder unit 1215 to identify a change in the number of the video channels to be processed by the outer decoder unit 1215. The power controller unit 1005-b may, then, control an aggregate processing rate of the outer decoder unit 1215 to adapt to the decreased (or increased) number of video channels. By way of example, power controller unit 1005-b may control the aggregate processing rate of the outer decoder unit 1215 to reduce power consumption of the outer decoder unit 1215 in response to a decrease in a number of the decoded plurality of video channels to be displayed and/or stored (for example, by powering down the outer decoder unit 1215 for proportionally more time, or changing the frequency of the clock domain for the outer decoder unit 1215). The outer decoder unit 1215 may be configured to process (e.g., performing Reed-Solomon decoding) only the data from the inner decoder 245 -e that is to be displayed (and, in some embodiments, also process data to be stored off chip). Note that while the same selected video channels may be stored at the second memory unit 1210 and processed at the outer decoder unit 1215, in other embodiments only a selected subset of such stored channels are subsequently processed by the outer decoder unit 1215. [0097] The processor interface 1220 may be an interface between certain digital logic and an additional processor (e.g., an on or off chip CPU or host processor, not shown). In one embodiment, the processor interface is to an Applications/Media Processor. The Applications/Media Processor may, for example, store the video data (or particular channels thereof) on external or other system memory, such as an SD card, flash memory, hard disk drive or the like. In the case of a laptop or personal computer, the hard disk or flash memory of the computer may be used for storing of video data to be viewed later. The aggregate bit rate of the processor interface may be equivalent to the sum of bit rates of each individual channel being forwarded. The power controller unit 1005-b may monitor, or receive data from, the processor interface 1220 or other controller to identify a change in the number of the video channels to be passed through the processor interface 1220. The power controller unit 1005-b may, then, control an aggregate processing rate of the processor interface to adapt to the decreased (or increased) number of video channels using the power reduction techniques described herein. Note that the outer decoder unit 1215 and the processor interface 1220 may each be hardware engines, or other processing units. They may be controlled independently or collectively for power control purposes (e.g., the may be in the same, or different, clock domains).

[0098] A display unit (not shown) may be connected with the processor interface 1220 to receive selected data. The display unit may display a single channel (e.g., when only one channel is being decoded by the inner and outer decoder units 245-e, 1215); display a single channel or display up to two channels in multiview (e.g., when two channels are being decoded by the inner and outer decoder units 245-e, 1215); display a single channel or display more than two channels in multiview (e.g., a three-way or four-way split screen) when operating in the third mode (e.g., when more than two channels are being decoded by the inner and outer decoder units 245-e, 1215). A number of other display alternatives may be used, as well.

[0099] Referring next to FIGS. 13A and 13B, two diagrams 1300 and 1350 illustrate an example power management technique which may be applied to one or more hardware engines or other processing units, or particular components thereof, in different embodiments. These may be the engines and components of the device 105 of FIG. 1, 2, 3, or 11, the device 1150 of FIG. 11, or the device 1250 of FIG. 12, for example. Going from left to right in the diagram 1300 with regard to time, the diagram 1300 illustrates a first received burst 1305 (e.g., at decoder unit 245), which for purposes of example includes channels 12 and 13. The processing of the burst by the applicable engine or component ends at or about time ti_a. At about time t_/α, the selected engine, unit, or particular component thereof is switched to a power saving mode (e.g., by powering down or withholding application of the clock as described above).

[0100] In one embodiment, the time between bursts 1310 is known. The power saving period 1315 (e.g., the time in which the engine or component is turned off or in which clocks are not applied) is determined. This may be based on the time interval between bursts, less a prewake (warm-up) period 1320. Because different engines, units, and components may need different amounts of time to awake and resync, the prewake (warm-up) period 1320 may vary. After the power saving time 1315 has elapsed at or about time t_2α, the power or clock may be reapplied. After the prewake period 1320, the data 1325 is then processed beginning at or about time ts_a-

[0101] Assume that at a time between FIG. 13A and 13 B, it is learned that channel 12 will no longer be decoded. Going from left to right in the diagram 1350 with regard to time, the diagram 1350 illustrates a first received burst 1355 (e.g., at decoder unit 245), which includes only channel 13. The processing of the burst by the applicable engine, unit, or component ends at or about time t^,. At about time t_/j, the selected engine, unit, or particular component thereof is switched to a power saving mode (e.g., by powering down or withholding application of the clock as described above).

[0102] The time between bursts 1360 may be calculated, and this time may be longer because channel 12 no longer will be decoded. The power saving period 1365 (e.g., the time in which the engine or component is turned off or in which clocks are not applied) is determined, and the power saving period may be extended because channel 12 no longer is to be decoded. This may be based on the time interval between bursts, less a prewake (warm- up) period 1370. After the power saving time 1365 has elapsed at or about time t_2b, the power or clock may be reapplied. After the prewake period 1370, the data 1375 is then processed beginning at or about time tøj. [0103] The power saving time may be extended or shortened depending on the number of channels to be decoded, thereby controlling an aggregate processing rate for the decoder unit 245. It is worth noting that the time of arrival of the next burst at the particular hardware engine may also be received, estimated, or otherwise calculated. Using the warm-up period estimates and the estimated time of availability of the next burst, a determination may be made as to whether to: 1) withhold a clock signal from the particular hardware engine, 2) power off the particular hardware engine, or 3) not power down the particular hardware engine because there is not sufficient time between bursts or because the powering off would not result in sufficient (or perhaps any) power savings.

[0104] There are also a number of ways in which clocks and associated domains may be implemented to thereby control an aggregate processing rate for the decoder unit 245 (or other processing unit) and reduce power consumption. Referring first to FIG. 14A, an example clock configuration 1400-a is shown. This may be the configuration employed for the device 105 of FIG. 1, 2, 3, or 11, the device 1150 of FIG. 11, or the device 1250 of FIG. 12, for example. The clock unit 1425-a of FIG. 14-a includes a PLL 1405-a, which receives a clock input from a source (on or off chip), and typically outputs a higher frequency to clock generation unit(s) 1410-a. The clock generation unit(s) 1410-a may be made up of one or more downconverters (e.g., divide-by logic), which receive the output of the PLL 1405-a and modify the signal to generate a particular clock output (e.g., clkl or clkn). Each clock generation unit(s) 1410-a may be applied to a different domain (e.g., assuming n=2, clock generation unit 1 1410-a- 1 may be applied to a domain for the demodulator unit 270, while the second clock generation unit 1410-a-n may be applied to domain decoder unit 245). In some embodiments, the clock generation units 1410-a may be dynamically accelerated or decelerated by changing the divide-by-logic, for example. In such instances, the outputs may be switched temporarily to a local oscillator until the clock generation units 1410-a have settled on the changed speeds. In other embodiments, a clock generation unit 1410-a may be applied to multiple domains and/or domains may be configured to receive a signal from more than one unit 1410-a. [0105] This clock configuration 1400-a also includes a power controller unit 1005-c configured to control the PLL 1405-a and its output frequency. The power controller unit 1005-c may also be configured to control the clock generation unit(s) 1410-a and each of their respective output frequencies. [0106] In one embodiment, the power controller unit 1005-c may access a table in memory 1420 which identifies the frequencies to be applied to different domains for each particular standard (e.g., DVB-H, DMB, or ISDB-T), and in different processing environments. For example, the table may indicate the proper frequency for each domain depending on how many channels will be processed in that domain. The frequency for each domain may be dynamically changed by looking up the appropriate frequency when the channels to be processed at a given stage are changed.

[0107] Referring next to FIG. 14B, an alternative example clock configuration 1400-b is shown. The clock unit 1425-b of FIG. 14B includes a number of PLLs 1405-b, each of which may receive a clock input from a source (on or off chip). In one embodiment, at least a subset of the PLLs 1405-b is local to each domain. Separate voltage inputs and regulators may be used for each of the PLLs 1405-b.

[0108] The clock unit 1425-b of FIG. 14B also includes one (or more) clock generation unit(s) 1410-b for respective PLLs 1405-b. Each clock generation unit(s) 1410-b may be made up of one or more downconverters (e.g., divide-by logic), which receive the output of the respective PLLs 1405-b and modify the signal to generate a particular clock output (e.g., clkl ... clkn). The clock generation unit(s) 1410-b of FIG. 14B may have the same functionality as described with reference to the clock generation unit(s) 1410-a of FIG. 14 A. Similarly, one or more power controller units 1005-d may be configured to control the PLLs 1405-b, clock generation unit(s) 1410-b, and respective output frequencies. It is worth noting that the power down and accelerated domain processing described above may be used alone, or in combination, to best adapt to the number of channels to be processed.

[0109] FIG. 15 is a flowchart 1500 illustrating a method for reducing power consumption during reception of video channels in a concatenated transmission according to various embodiments of the invention. The method 1500 may, for example, be performed in whole or in part with the device 105 of FIG. 1 , 2, 3, or 11 , the device 1150 of FIG. 11 , or the device 1250 of FIG. 12. [0110] At block 1505, mobile digital broadcast video signals are received which correspond to video channels formatted according to a concatenated transmission standard. At block 1510, a stream of data representative of the video channels is generated. At block 1515, in response to a decrease in the number of video channels to be decoded, an aggregate processing rate for decoding is reduced. At block 1520, the decreased number of video channels is decoded at the reduced rate to thereby reduce power consumption.

[0111] FIG. 16 is a flowchart illustrating a method 1600 for utilizing different modes of operation to reduce power consumption during reception of video channels within a concatenated transmission according to various embodiments of the invention. The method 1600 may, for example, be performed in whole or in part with the device 105 of FIG. 1, 2, 3, or 11, the device 1150 of FIG. 11, or the device 1250 of FIG. 12.

[0112] At block 1605, mobile digital broadcast video signals are received which correspond to video channels formatted according to a concatenated transmission standard. At block 1610, a stream of data representative of the video channels is generated. At block 1615, a first one the of video channels from the stream of data is selected in a first mode. At block 1620, continuing in the first mode, the selected video channel is decoded at a first aggregate rate. At block 1625, two or more of the video channels from the stream of data are selected in a second mode. At block 1630, continuing in the second mode, the two or more selected video channels are decoded at a second aggregate rate. [0113] In some embodiments, therefore, a wideband RF device and baseband architecture is described that may concurrently receive and process from one to 13 channels of an ISDB-T concatenated transmission signal. A variable-sampling-rate A/D unit may change sampling frequency based on a channel location index to lessen power consumption. A device may record from one to 13 mobile TV ISDB-T 1-seg channels per 5.572 MHz frequency multiplex using a single receiver demodulator. The recording may be onto internal, external, embedded or PC memory for time-shift viewing. A single-channel fast-flip method is described that negates the need for substantial tuner changes during a channel change, which may reduce channel change time and channel change power consumption. In some embodiments, multiple screens or a multiview format (e.g., picture-in-picture) may show independent video channels using a single receiver/TV tuner.

[0114] Although aspects of the functionality included within this Detailed Description are described above with reference to various embodiments of the device 105 of FIG. 1, 2, 3, 4, or 10, the device 550 of FIG. 5, the device 650 of FIG. 6, the device 1150 of FIG. 11, or the device 1250 of FIG. 12, the functionality may be performed by a variety of other components in this or other types of devices. The functions performed by the functional units (e.g., analog processing units 260, demodulator unit 270, decoder unit 245, channel selection unit 405, output selection unit 540, power controller unit 1005, or any components thereof) may, individually or collectively, be implemented with one or more Application Specific Integrated Circuits (ASICs) adapted to perform some or all of the applicable functions in hardware. Alternatively, certain functions may be performed by one or more other processing units (or cores), on one or more integrated circuits. In other embodiments, other types of integrated circuits may be used (e.g., Structured/Platform ASICs, Field Programmable Gate Arrays (FPGAs) and other Semi-Custom ICs), which may be programmed in any manner known in the art. The functions of each unit, or any component thereof, may also be implemented, in whole or in part, with instructions embodied in a memory, formatted to be executed by one or more general or application-specific processors. It should also be noted that although certain concepts related to sampling rate are set forth, a range of sampling techniques may be employed. Also, while examples of analog and digital filtering are used, certain functionality may be performed in the analog or digital domain.

[0115] It should be noted that the methods and devices discussed above are intended merely to be examples. It must be stressed that various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, it should be appreciated that, in alternative embodiments, the methods may be performed in an order different from that described, and that various steps may be added, omitted or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, it should be emphasized that technology evolves and, thus, many of the elements are exemplary in nature and should not be interpreted to limit the scope of the invention.

[0116] Specific details are given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. [0117] Also, it is noted that the embodiments may be described as a process which is depicted as a flow diagram or block diagram. Although each may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure.

[0118] Moreover, as disclosed herein, the term "memory" or "memory unit" may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage mediums, optical storage mediums, flash memory devices or other computer-readable mediums for storing information. The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, a sim card, other smart cards, and various other mediums capable of storing, containing or carrying instructions or data.

[0119] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a computer-readable medium such as a storage medium. Processors may perform the necessary tasks.

[0120] Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. For example, the above elements may merely be a component of a larger system, wherein other rules may take precedence over or otherwise modify the application of the invention. Also, a number of steps may be undertaken before, during, or after the above elements are considered. Accordingly, the above description should not be taken as limiting the scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. A device for processing mobile digital broadcast video signals formatted according to a concatenated transmission standard, the device comprising: an analog processing unit configured to: receive the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to the concatenated transmission standard; and generate a stream of data representative of the mobile digital broadcast video signals; a demodulator unit, communicatively coupled with the analog processing unit, and configured to demodulate the plurality of video channels from the stream of data; a channel selection unit configured to select a subset comprising two or more of the demodulated plurality of video channels; and a decoder unit, communicatively coupled with the demodulator unit and channel selection unit, and configured to decode the selected subset of video channels.

2. The device of claim 1, wherein, the channel selection unit is further configured to select a subset comprising one of the demodulated video channels; and the decoder unit is configured to decode the selected one video channel.

3. The device of claim 1, further comprising: an output selection unit, communicatively coupled with the decoder unit, and configured to select a subset of the decoded video channels for display.

4. The device of claim 3, further comprising: an outer decoder unit, communicatively coupled with output selection unit, and configured to perform Reed-Solomon decoding on the selected subset of decoded video channels.

5. The device of claim 1, further comprising: a first memory unit, communicatively coupled with the demodulator unit and decoder unit, and configured to store the selected subset comprising two or more of the demodulated plurality of video channels, wherein the non-selected demodulated video channels are excluded from storage in the first memory unit.

6. The device of claim 5, further comprising: a second memory unit, communicatively coupled with the decoder unit, and configured to store a selected subset of the decoded video channels and exclude remaining decoded video channels from storage in the second memory unit.

7. The device of claim 6, further comprising: a display unit, communicatively coupled with the second memory unit, and configured to display a selected one of the video channels from the second memory unit.

8. The device of claim 1, wherein, to demodulate the plurality of video channels, the demodulator unit is configured to frequency de-interleave and time de-interleave a processed version of the stream of data; and to decode the plurality of video channels, the decoder unit is configured to bit de-interleave and perform Viterbi decoding on the selected subset of video channels.

9. The device of claim 1, further comprising: a display unit, communicatively coupled with the decoder unit, and configured to display a first one and a second one of decoded subset of video channels simultaneously in a multiview format.

10. The device of claim 9, wherein, the multiview format comprises a picture-in-picture format; and the device comprises a mobile communications device.

11. The device of claim 1 , wherein, the demodulator unit comprises a first set of one or more hardware engines configured to demodulate the plurality of video channels in parallel; the decoder unit comprises a second set of one or more hardware engines configured to decode the selected subset of video channels by serially processing bursts of each video channel; and the device comprises a processor.

12. A processor for receiving mobile digital broadcast video signals, the processor comprising: a receiver unit configured to receive the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to a concatenated transmission standard; a demodulator unit, communicatively coupled with the receiver unit, and configured to demodulate the plurality of video channels from the mobile digital broadcast video signals; a selection unit, communicatively coupled with the demodulator unit, and configured to select two or more of the plurality of demodulated video channels; and a decoder unit, communicatively coupled with the selection unit, and configured to decode the selected video channels to generate a stream of data comprising a decoded version of the selected video channels.

13. The processor of claim 12, wherein the processor comprises an application specific integrated circuit comprising: a first set of one or more hardware engines configured to perform the demodulation of the plurality of video channels; and a second set of second set of one or more hardware engines configured to perform the decoding of the selected subset of demodulated video channels by serially processing bursts of each video channel.

14. A method for processing mobile digital broadcast video signals, the method comprising: receiving the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to a concatenated transmission standard; generating a stream of data representative of the plurality of video channels; selecting, in a first mode, a first one of the plurality of video channels from the stream of data; decoding, in the first mode, the selected video channel; selecting, in a second mode, two or more of the plurality of video channels from the stream of data; and decoding, in the second mode, the two or more selected video channels and excluding the non-selected video channels of the second mode from decoding.

15. The method of claim 14, further comprising: selecting, in the first mode, a second one of the plurality of video channels from the stream of data; and decoding, in the first mode and after selecting the second video channel, the second video channel instead of continuing to decode the first channel.

16. The method of claim 14, further comprising: selecting, in the second mode, a first one of the two or more decoded video channels for display; and displaying the selected first one of the two or more decoded video channels in a single view mode.

17. The method of claim 14, further comprising: selecting, in the second mode, a second one of the two or more decoded video channels for display; and displaying the selected second one of the two or more decoded video channels instead of continuing to display the first one of the two or more decoded video channels.

18. The method of claim 14, further comprising: storing, in the first mode, the selected video channel while excluding the non- selected, demodulated video channels of the first mode from storage; and storing, in the second mode, the two or more selected video channels while excluding the non-selected, demodulated video channels of the second mode from storage.

19. The method of claim 14, further comprising: displaying, in the second mode, a first one and a second one of decoded subset of video channels simultaneously in a multiview format on a mobile communications device.

20. A method for processing mobile digital broadcast video signals, the method comprising: receiving the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to a concatenated transmission standard; demodulating the plurality of video channels from the mobile digital broadcast video signals; and decoding a selected subset comprising two or more of the demodulated plurality of video channels, excluding the non-selected video channels from decoding.

21. A device for processing mobile digital broadcast video signals formatted according to a concatenated transmission standard, the device comprising: an analog processing unit configured to: receive the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to the concatenated transmission standard; and generate a stream of data representative of the mobile digital broadcast video signals; a demodulator unit, communicatively coupled with the analog processing unit, and configured to demodulate the plurality of video channels from the stream of data; a power controller unit configured to: identify a decrease in a number of the demodulated plurality of video channels to be decoded; and control an aggregate processing rate of a decoder unit to adapt to the decreased number of video channels to be decoded and thereby reduce power consumption; and a decoder unit, communicatively coupled with the demodulator unit and the power controller unit, and configured to decode the reduced number of demodulated video channels at the controlled rate.

22. The device of claim 21 , wherein the power controller unit is configured to control the aggregate processing rate by withholding power to the decoder unit for an increased proportion of time during the decoding of the reduced number of demodulated video channels.

23. The device of claim 22, wherein the power controller unit is configured to withhold power by withholding a clock signal from at least a portion of the decoder unit, the decoder unit comprising a distinct set of hardware engines.

24. The device of claim 22, wherein the power controller unit is configured to withhold power by powering off at least a portion of the decoder unit, the decoder unit comprising a distinct set of hardware engines.

25. The device of claim 21 , wherein the power controller unit is configured to control the aggregate processing rate by changing a clock output for a clock domain of the decoder unit from a first frequency to a second, lower frequency to decode the reduced number of demodulated video channels, wherein the clock domain of the decoder unit and a clock domain of the demodulator unit comprise different clock domains.

26. The device of claim 25, further comprising: an outer decoder unit, communicatively coupled with the decoder unit, and configured to perform additional decoding on a selected subset of the decoded video channels to generate a stream of data to be displayed, wherein the power controller unit is configured to control the aggregate processing rate of the outer decoder unit to reduce power consumption of the outer decoder unit in response to a decrease in a number of the decoded plurality of video channels to be displayed.

27. The device of claim 26, wherein, the outer decoder unit is configured to perform additional decoding on the decoded video channels to generate a stream of data to be stored after the additional decoding; and the power controller unit is configured to control the aggregate processing rate of the outer decoder unit to reduce power consumption of the outer decoder unit in response to a decrease in a number of the decoded plurality of video channels to be stored after the additional decoding.

28. The device of claim 21, further comprising: a first memory unit, communicatively coupled with the power controller unit, and configured to store at least a subset of the demodulated plurality of video channels, wherein the power controller unit is configured to control the first memory unit to power down a portion of memory in response to the identification of the decrease in the number of demodulated video channels to be decoded.

29. The device of claim 28, further comprising: a second memory unit, communicatively coupled with the power controller unit and physically distinct from the first memory unit, and configured to store at least a subset of the decoded plurality of video channels, wherein the power controller unit is configured to control the second memory unit to power down a portion of memory in response to an identification of a decrease in a number of decoded video channels to be displayed.

30. The device of claim 21, wherein, the power controller unit is communicatively coupled with an A/D unit in the analog processing unit, and is configured to adapt the sampling rate of the A/D unit when a channel to be decoded is changed; and the decoder unit is configured to decode only one channel of the plurality of channels.

31. The device of claim 21 , wherein, the mobile digital broadcast video signals comprise orthogonal frequency- division multiplexing (OFDM) signals; the plurality of video channels each comprise a plurality of video segments; and the device comprises a processor.

32. A method of processing mobile digital broadcast video signals formatted according to a concatenated transmission standard, the method comprising: receiving the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to a concatenated transmission standard; generating a stream of data representative of the plurality of video channels; reducing, in response to a decrease in a number of the plurality of video channels to be decoded, an aggregate processing rate for decoding; and decoding the decreased number of video channels at the reduced rate to thereby reduce power consumption.

33. The method of claim 32, wherein the reduction in the aggregate processing rate for decoding comprises at least one of: withholding a clock signal from at least a portion of a set of hardware engines comprising a decoder unit; or powering off at least a portion of a set of hardware engines comprising a decoder unit.

34. The method of claim 32, wherein the reduction in the aggregate processing rate for decoding comprises changing a clock output for a decoder clock domain from a first frequency to a second, lower frequency to decode the reduced number of demodulated video channels, wherein the clock domain for a decoder unit is different from a clock domain for a demodulator unit.

35. A processor for receiving mobile digital broadcast video signals formatted according to a concatenated transmission standard, the processor comprising: a receiver unit configured to generate a stream of data representative of the mobile digital broadcast video signals; a demodulator unit, communicatively coupled with the receiver unit, and configured to demodulate the plurality of video channels from the stream of data; a power controller unit configured to: control, in a first mode, a decoder unit to operate at a first aggregate processing rate when decoding one of the demodulated plurality of video channels; and control, in a second mode, a decoder unit to operate at a second aggregate processing rate when decoding two of the demodulated plurality of video channels; and a decoder unit, communicatively coupled with the demodulator unit and power controller unit and comprising a set of hardware engines, and configured to decode at the first or second aggregate rate.

36. The processor of claim 35, wherein the power controller unit is configured to control aggregate rate in the decoder unit by withholding power to at least a part of the decoder unit for a greater proportion of time in the first mode than the second mode.

37. The processor of claim 35, wherein the power controller unit is configured to control the aggregate processing rate by changing a clock output for a clock domain of the decoder unit from a first frequency in the first mode to a second, higher frequency in the second mode, wherein the clock domain of the decoder unit and a clock domain of the demodulator unit comprise different clock domains.

38. The processor of claim 35, wherein, the processor is configured for use in a mobile communications device; the power controller unit is further configured to control, in a third mode, the decoder unit to operate at a third aggregate processing rate when decoding three of the demodulated plurality of video channels; and the decoder unit is communicatively coupled with a display unit, and the display unit is configured to: display a single channel when the processor is operating in the first mode; display a single channel or display up to two channels in multiview when operating in the second mode; and display a single channel or display more than two channels in multiview when operating in the third mode.

39. The processor of claim 35, wherein, the processor comprises an application specific integrated circuit; the demodulator unit comprises a first set of one or more hardware engines; and the decoder unit comprises a second set of one or more hardware engines.

40. A method for processing mobile digital broadcast video signals, the method comprising: receiving the mobile digital broadcast video signals corresponding to a plurality of video channels formatted according to a concatenated transmission standard; generating a stream of data representative of the plurality of video channels; selecting, in a first mode, a first one of the plurality of video channels from the stream of data; decoding, in the first mode, the selected video channel at a first aggregate rate; selecting, in a second mode, two or more of the plurality of video channels from the stream of data; and decoding, in the second mode, the two or more selected video channels at a second aggregate rate.