WO2009045102A2

WO2009045102A2 - An electronic circuit element with profiled photopatternable dielectric layer

Info

Publication number: WO2009045102A2
Application number: PCT/NL2008/050630
Authority: WO
Inventors: Nicolaas Aldegonda Jan Maria Van Aerle; Joris Pieter Valentijn Maas
Original assignee: Polymer Vision Limited
Priority date: 2007-10-02
Filing date: 2008-10-02
Publication date: 2009-04-09
Also published as: WO2009045102A3; TW200924107A

Abstract

An electronic circuit element is disclosed comprising: a first electronic component and a second electronic component, said first electronic component and said second electronic component being arranged to share a first electrically conducting layer, a second electrically conducting layer; and, an electrically insulating layer spatially arranged between the first electrically conducting layer and a second electrically conducting layer, wherein the electrically insulating layer comprises a photopatternable material having a first thickness in a region covered by the first electronic component and a second thickness in a region covered by the second electronic component. The resulting structure 40 may comprise a plurality of areas 42 of a first thickness an area 41 of a second thickness and optionally a plurality of areas 43 with zero thickness.

Description

Title : AN ELECTRONIC CIRCUIT ELEMENT WITH PROFILED PHOTOPATTERNABLE DIELECTRIC LAYER

FIELD OF THE INVENTION

The invention relates to an electronic circuit component and a device comprising such electronic circuit component. More particularly, the invention relates to a structure comprising a Thin Film Transistor (TFT). The invention further relates to a method of manufacturing an electronic circuit element.

BACKGROUND OF THE INVENTION

Thin Film Transistor (TFT) devices are commonly used in, for example, an active matrix of a display wherein a shared dielectric layer may be used for a suitable dielectric for a TFT gate, a storage capacitor, or for crossings of electrically conducting lines. An active matrix of a display device generally comprises a plurality of display elements, commonly referred to as pixels or dots. In the case of a black and white display, a pixel may be the same as a dot. In the case of a color display, a pixel may comprise a set of dots, for example a set of Red, Green and Blue dots. Both bottom-gate TFT and top-gate TFT may be used. In the case of a bottom-gate TFT, the TFT structure is usually built up starting with a substrate that is provided with a first conducting layer. This conducting layer is subsequently patterned to define a gate line (often also referred to as row-line), a gate electrode of the Thin Film Transistor (TFT) switch and, optionally an electrode of a further electronic component, such as a capacitor or a storage capacitor. The electrically conductive layer is at least partially covered by a non-conducting layer that acts as an insulating layer as well as a dielectric layer. Subsequently, a second electrically conducting layer is provided and is patterned to define any of the following: a data-line (also referred to as a column line or a source line), a source electrode of the TFT, a channel, a drain electrode of the TFT, a pixel electrode and, optionally an electrode of a further electronic component, such as a second electrode of a capacitor. To create a functional TFT a semiconductor layer is also provided either before or after application of the second electrically conducting layer. The semiconductor layer can be further covered with a passivation layer to protect the semiconductor layer.

Electrical shorts between different conducting layers may occur in known TFT structures. The shorts lead to pixel defects or even line defects within a display. An electrical short in the overlapping area between the source and the gate in the TFT structure as well as a short in the crossing column and gate lines may lead to line defects. Electrical shorts between gate and drain electrodes in the drain area of the TFT as well as shorts in the storage capacitor area may lead to a pixel defect or a dot defect.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an electronic circuit element wherein a thickness of the dielectric layer is substantially optimized at least for some electronic components constituting the electronic circuit, and whereas such electronic circuit element may be manufactured in a simple process.

To this end the electronic circuit element according to the invention comprises: a first electronic component and a second electronic component, said first electronic component and said second electronic component being arranged to share: a first electrically conducting layer; a second electrically conducting layer; and a dielectric layer spatially arranged between the first electrically conducting layer and the second electrically conducting layer, the dielectric layer comprising a photopatternable material having a first thickness in a region covered by the first electronic component and a second thickness in a region covered by the second electronic component.

The technical measure of the invention is based on the following insights. It is understood that for a good performance of a TFT, the gate dielectric is preferably kept relatively thin in order to increase the capacitance of the TFT, as an ON-current of the TFT is directly proportional to the gate capacitance and the capacitance is inversely proportional to a thickness of the dielectric layer. A high ON-current can be balanced with a smaller channel width of the TFT. Reducing the channel width will reduce the overlapping area between gate and the source electrode and the area between the gate and drain electrode, thus reducing the risk of line defects and pixel defects caused by shorts at a given constant number of shorts per unit area. For the storage capacitor, a thin dielectric layer is also preferred as this enables a reduction of the capacitor area. For the insulating layer between crossing lines, the insulating layer is preferably as thick as possible to reduce the risk of shorts that otherwise lead to line defects in a display.

In case of high resolution displays, the relative area of crossings between column and gate lines increases. This leads to an increased risk of shorts between column and gate lines. This may also lead to an increase in the RC-time of the gate line. In order to drive a display properly, the R_gateC_gate of the gate line is preferably less than 10% of the selection time (also referred to as line-time). By increasing the thickness of the insulating layer between the crossings, the capacitance of the crossings will decrease, thus reducing

RgateCgate-

Regarding the balance between yield and electrical performance, there is an optimum in the thickness of the dielectric layer in each particular area. As for a parallel plate capacitor, the capacitance can be kept the same by reducing the dielectric layer thickness and reducing the capacitor area, or increasing the dielectric layer thickness and increasing the capacitor area. Reducing the dielectric thickness increases the risk of shorts by small particles between the top and bottom electrode; increasing the capacitor area on the other hand also increases the risk of shorts by particles considering a constant density of particles per unit area. In accordance with the technical measure of the invention the same photopatternable electrically insulating layer may be used for a plurality of electronic components, for example it may be used in: a gate dielectric, a storage capacitor dielectric, an insulator between crossings of electrically conducting lines, wherein a thickness of the photopatternable electrically insulating layer is substantially optimized in view of operational requirements of some, preferably most important electronic components constituting the electronic circuit element according to the invention.

Such thickness modulation of the electrically insulating (dielectric) layer may be achieved by a suitable application of a special photo-exposure technology such as known half-tone technology or diffractive technology. An example of the half-tone exposure is discussed with reference to Figure 1. Alternatively, a known double exposure method may be used. The double exposure technology applies a first mask followed by a second mask. Either the light intensity or the wavelength distribution of the exposing light may be varied between the first and the second exposure.

In this way the photopatternable dielectric layer may be exposed to create different thicknesses in a single process step. Preferably, for this purpose UV-exposure is used. The resulting thicknesses can be optimized with respect to their function and yield, such as, for example, a thick insulating (i.e. dielectric) layer in one area and thin insulating (i.e. dielectric) layer in another area of the electronic circuit element. An embodiment of the electronic circuit element according to the invention will be discussed in more detail with reference to Figure 2.

In an embodiment of the electronic circuit component according to the invention the photopatternable electrically insulating layer comprises an organic material.

Organic photopatternable electrically insulating (dielectric) layers are particularly suitable for manufacturing of active matrices of a display, such as for example a flexible display. It will be appreciated that suitable organic material may comprise some amount of inorganic components, like antimony, fluorine, phosphorus, sulphur, etc. In the case where an organic dielectric material is used as an insulating layer, it is advantageous to provide a further layer of electrically insulating material which is substantially free of charge carriers. This further layer improves electrical characteristics of the dielectric layer, for example electrical breakdown strength is improved. For example, a poly-olefin, or the like may be used for such further layer. In this case a photopatternable material is selected for the top-layer in the stack. The other layers of the insulator layer stack can be dissolved or etched using the photopatternable layer as a mask. Etching can be done either wet or dry. These other layers can be chosen to optimize functionality of the electronic component, like improved electrical breakdown. These other layers may comprise inorganic or organic materials. Alternatively, the further dielectric layers in the stack may be used for protection of the semiconductor of a top gate TFT device.

The photopatternable dielectric layer may be used for a gate dielectric and for a storage capacitor dielectric. Organic layers may be used for manufacturing of flexible displays as they are more flexible then inorganic equivalents and can be applied from a liquid solution by means of simple and relatively inexpensive methods. The latter is preferable for manufacturing of flexible and rollable displays for consumer electronics to substantially minimize cracks in the display layer caused by its deformation when in use. Inorganic layers may also be used. However to avoid problems related to cracks upon bending of the flexible display, the inorganic layer should be less than 500 nm, and preferably be in the order of 100 to 200 nm thickness, and more preferably in the order of 25 to 100 nm thickness. The photopatternable dielectric layer may also be used as the dielectric layer for the storage capacitor and as an insulating layer between the electrically conducting row and column lines, the so-called line crossing, shown in Figure 2. A method of manufacturing an electronic circuit element comprising a first electronic component and a second electronic component according to the invention comprises the steps of:

- depositing a first electrically conductive layer on a substrate for forming a first conductive layer of a first electronic component and of a second electronic component,

- depositing a layer of a photopatternable electrically insulating material, said layer being conceived to be spatially arranged between the first electrically conducting layer and a second electrically conducting layer;

- photopatterning the layer of the photopatternable electrically insulating material for providing a first thickness of said layer in a region covered by the first electronic component and a second thickness of said layer in a region covered by the second electronic component;

- depositing the second layer of the conducting material. Further advantageous embodiments of a method according to the invention are set forth in claims 11-17. The method according to the invention is discussed in further detail with reference to Figure 4.

These and other aspects of the disclosed embodiments of the invention will be further discussed with reference to drawings.

BRIEF DESCRIPTION

Figures Ia, Ib and Ic present a schematic view of an embodiment of a conventional and a half-tone exposure method.

Figure 2 presents in a schematic way an embodiment of a known electronic circuit element.

Figure 3 presents a schematic view of an embodiment of a method according to the invention. Figures 4a and 4b present schematic views of an embodiment of an electronic circuit element manufactured in accordance with a method according to the invention.

Figure 5 presents a schematic view of a further embodiment of the electronic circuit element according to the invention.

Figure 6 presents an embodiment of an electronic device according to the invention.

DETAILED DESCRIPTION

Figure 1 presents a schematic view of an embodiment of a half-tone exposure method. In a conventional exposure method (a) a mask 11 comprising UV- transparent region 1 and UV-non-transparent region 2 may be used. As a result, a suitable photopatternable material 6 arranged on a substrate 8 will be patterned to comprise a suitable series of islands 6a of substantially equal height. In this example layer 6 refers to a positive type photo-resist. In the half-tone exposure method 10 a mask 11a having at least three different areas is used, as shown schematically in Figure 1 (b). An area 4 of the photo-mask 11a is transparent for UV light (similar to area 1 in photomask 11); an area 2 is blocking the UV light and an area 3 is semi-transparent for UV light. Examples of a suitable photo-mask may comprise quartz with patterned chromium for the area 2 and chromium oxide for the area 3. Chromium oxide can be made in a way that the UV-transmission is decreased to for example 10% or 20% of its original value, corresponding to a transmission of the areas 1 or 4. Hence the radiation intensity after passing the semi-transparent area 3 is reduced as shown schematically by 5. Photopatternable materials are sensitive to the degree of UV-light energy. The degree of cross-linking is affected by the amount of UV-light energy to which the material is exposed. In a case of positive type photo-resist, UV-exposure will lead to increased solubility in a base or alkaline developer. In a case of negative photo-resist, UV-exposed areas become insoluble. When a high UV-exposure dose is given, the exposed photoresist will react completely throughout the whole layer thickness. In a case where a lower dose is applied, only part of the exposed photo-resist will react, development will then wash out or remove only part of the layer, leaving a thinner resist layer. The resulting structures after development are shown by 13.

When a positive photosensitive organic layer 6 on top of a layer 8 is exposed to UV light, and subsequently developed, structures result as shown by 6a, 6b. It is noted that in sketch (b) of Figure 1 a use of a half-tone mask is shown for a positive photo resist type and in sketch (c) of Figure 1 a use of a half-tone mask is shown for a negative photo-resist type 7. As shown schematically the use of a semi-transparent region in the litho-mask will give an intermediate resist thickness 6b after development.

It is further noted that apart from using a half-tone mask it is also possible to obtain a similar profiling of the photopatternable insulator layer 6 or 7 using a known diffraction mask. Other techniques to create different thicknesses of the photopatternable electrically insulating layer, preferably in a single processing step can also be used to obtain the same result. For example a known double exposure method can be used. The double exposure technology applies a first mask followed by a second mask. Either the light intensity or the wavelength distribution of the exposing light may be varied between the first and the second exposure.

Figure 2 presents in a schematic way an embodiment of a known electronic circuit element. An active matrix display device generally comprises a plurality of display elements, referred to as pixels or dots. Figure 2 shows a schematic presentation of a single pixel element of a display, based on a so- called bottom-gate TFT. This structure may be built up starting with a substrate that is provided with a first conducting layer. This conducting layer is patterned to define a gate line 22, a gate electrode 23 of a TFT switch and one electrode 32 of the storage capacitor 27. This layer may be directly covered by a non-conducting layer 33 that acts as an insulating layer as well as a dielectric layer. In the outer boundary of the display this non-conducting layer is provided with holes or vias to enable electrical contacting of the gate lines. Optionally, to reduce possible yield loss caused by open gate lines inside the display area, the gate lines can be locally shunted by a second electrically conducting layer 31 through contact holes 30 in the electrically non-conducting layer 33. The same approach of creating shunts between two conducting layers is also possible for the column lines, (not shown here). In the latter case the shunting structure is created by the first conducting layer and contacts the column lines through similar vias. Subsequently a second electrically conducting layer is provided and patterned to define the data -line or column line 21, the source electrode 25 of the TFT, the channel region 24, the drain electrode 26 of the TFT, the pixel electrode 28 and the second electrode of the storage capacitor 27 and optionally the shunting layer 31 for the gate line 22. To create a functional TFT a semiconductor layer may also be provided either before or after application of the second electrically conducting layer (not shown). This semiconductor layer can be further covered with a passivation layer to protect the semiconductor layer. Other designs, like top-gate TFT are possible. In addition, some schematic cross sections are shown, see A-A', B-B', C-C. In all these regions of the display, a thickness of the dielectric layer 33 is the same, which is disadvantageous.

Figure 3 presents a schematic view of an embodiment of a method according to the invention. In accordance with the technical measure of the invention, for the insulator layer a photopatternable insulator layer is selected, which is patterned using a half-tone exposure to yield regions of insulating material having different thicknesses. In organically based active matrices, the electrically non-conducting layer 33, acting as gate dielectric, may be made of an organic layer (see e.g., embodiment 35 of Figure 3). Organic layers may be preferred for manufacturing flexible displays, as they are more flexible than inorganic materials and can be applied from a solution via simple and inexpensive methods and can be used in flexible and rollable displays without leading to cracks in the layer. In a preferred embodiment a photo-patternable material, for example a photo-patternable organic layer, is used as the non-conducting layer 33a, as the structuring can then be done without an additional etching and stripping process step. As a result a structure comprising an insulator with different thicknesses Al, A2, Bl, B2, Cl, C2, C3 is obtained. It will further be appreciated that the different thicknesses Al, A2, Bl, B2, Cl, C2, C3 are substantially different from each other, for example at least 10 — 20 percent different, more preferably 20 - 50 percent different, and most preferably more than 50 per cent different. It will be appreciated that it may be sufficient to form the dielectric layer to comprise two different thicknesses; however an embodiment comprising more regions of a dielectric material with respective specific thickness is contemplated as well. Within each region of a particular thickness, said thickness may vary less than 10 per cent of its value.

It is found to be preferable to start with a thicker layer of the insulating material compared to a layer selected in the prior art, see Figure 3, for example. The variation in thickness of layer 33a is obtained using a halftone mask. In this example the insulating layer is thicker in the crossing area between conductors 29a and 32a as shown in the cross section A-A'. The thickness of the dielectric of the storage capacitor is chosen to be thinner in the storage capacitor area B-B'. In the TFT region, the given example refers to a design in which the channel region exhibits a thinner (C3) dielectric layer, but the major part of the overlapping regions of source -gate and drain-gate areas have a thicker (Cl and C2) dielectric. In this case the risk on shorts is reduced without affecting the ON-current as the dielectric thickness C3 in the channel region 24 of the TFT is still small. It will be appreciated that other designs are possible without departing the scope of the invention.

Figure 4 presents a schematic view of an embodiment of an electronic circuit element manufactured in accordance with a method according to the invention. The method according to the invention comprises the steps of depositing a first electrically conductive layer on a substrate for forming a first conductive layer of a first electronic component and of a second electronic component, depositing a layer of a photopatternable electrically insulating material, said layer being conceived to be spatially arranged between the first electrically conducting layer and a second electrically conducting layer; photopatterning the layer of the photopatternable electrically insulating material for providing a first thickness of said layer in a region covered by the first electronic component and a second thickness of said layer in a region covered by the second electronic component; depositing the second layer of the conducting material. The resulting structure 40 comprises a plurality of areas 42 of a first thickness, an area 41 of a second thickness and optionally a plurality of areas 43 with zero thickness. In sketch (b) of Figure 4 the thus formed electrically insulating layer is shown in superposition with a pixel area 41 of a display matrix, discussed with reference to Figure 2. A region 42a relates to an area where the dielectric material is completely removed.

Figure 5 presents a schematic view of a further embodiment of the electronic circuit element according to the invention. The electrically conducting layers 54, 52 are separated by one ore more electrically insulating layers. Other electrically conducting layers 54, 54a, 54b relate to further conductors used in the electronic circuit. The conductors 51, 54, 54a and 54b are created in the same conducting layer. The electrically insulating layer 50 may be based on a stack of two or more layers 33a, 33b provided that a top- layer 33a comprises a photo-patternable type. The other layer(s) 33b of the insulator layer stack can then be dissolved or etched using the photo- patternable layer 33a as mask. Etching can be done either wet or dry. These other layers can be chosen to optimize for its functionality, such as improved electrical breakdown, or for a protection layer for the semiconductor in the case of a top gate device. The layer indicated as 33b can be either of organic or inorganic type, chosen in such a way that it is optimized for better operational lifetime or functionality or both. For example for the layer 33b an insulating material may be selected which is substantially free of charge carriers. For example, a poly-olefin may be used. An example of an inorganic layer 33b comprises silicon-nitride (SiNx). In the case of a top-gate TFT design, the layer 33b can be added as a protection layer for a suitable semiconductor.

Figure 6 presents an embodiment of an electronic device according to the invention. The electronic apparatus 60 may relate to a mobile phone, a palmtop computer, an electronic organizer, or any other portable electronic device comprising a display cooperating with a housing 62. It is noted that for the display a flexible display may be used. For the latter, the housing 62 may be arranged to be unfoldable and wrappable about a core 63, whereby the flexible display 64 may be conceived to be extended from its collapsed state into an extended state upon use. In order to support the flexible display during use and to protect it from mechanical damage, the housing 62 may comprise rigid portions 63a conceived to at least partially receive and/or support edge portions 64a, 64b of the flexible display. It will be appreciated that during folding and unfolding of the housing 62 some parts of the flexible display 64 undergo deformation, whereas other parts of the flexible display undergo substantially no deformation. In an alternative embodiment of the electronic apparatus according to the invention comprising a flexible display, the flexible display may be arranged to be rollable about a suitable roller arranged in the housing 62. In this case a leading end of the flexible display may be provided with a grip portion for enabling a user to extend the rolled-up flexible display during use. Alternatively, both end portions of the flexible display may be arranged on respective rollers so that the flexible display is extended upon a relative movement of these end portions away from each other. It will be appreciated that other embodiments of the electronic apparatus comprising the flexible display are possible.

It will be appreciated that while specific embodiments of the invention have been described above, that the invention may be practiced otherwise than as described. Figures are provided for illustrative purposes and may not be used for limiting the scope of the invention as is set forth in the appended claims. In addition, isolated features discussed with reference to different figures may be combined.

Claims

1. An electronic circuit element comprising: a first electronic component and a second electronic component, said first electronic component and said second electronic component being arranged to share: a first electrically conducting layer; a second electrically conducting layer; and an electrically insulating layer spatially arranged between the first electrically conducting layer and the second electrically conducting layer, the electrically insulating layer comprising a photopatternable material having a first thickness in a region covered by the first electronic component and a second thickness in a region covered by the second electronic component.

2. An electronic circuit element according to claim 1, wherein the electrically insulating layer comprises a photopatternable organic material.

3. An electronic element according to claim 1 or 2, wherein the first electronic component and/or the second electronic component are selectable from a group comprising a thin film transistor (TFT), a capacitor, or a crossing between electrically conducting lines.

4. An electronic element according to any preceding claim, wherein the electrically insulating layer comprises a bottom-layer of a first electrically insulating material and a top-layer of a second electrically insulating material, said second electrically insulating material being photopatternable.

5. An electronic element according to claim 4, wherein the first electrically insulating material is patterned using the photopatternable electrically conducting layer as a mask for patterning.

6. An electronic element according to claim 5, wherein the first electrically insulating material is patterned using dry etching.

7. An electronic device comprising an electronic circuit element according to any preceding claim.

8. An electronic device according to claim 7, comprising a display.

9. An electronic device according to claim 8 wherein the display is y a flexible display.

10. A method of manufacturing an electronic circuit element comprising a first electronic component and a second electronic component, comprising the steps of: depositing a first electrically conductive layer on a substrate for forming a first conductive layer of a first electronic component and of a second electronic component, depositing a layer of a photopatternable electrically insulating material, said layer being conceived to be spatially arranged between the first electrically conducting layer and a second electrically conducting layer;

- photopatterning the layer of the photopatternable electrically insulating material for providing a first thickness of said layer in a region covered by the first electronic component and a second thickness of said layer in a region covered by the second electronic component; depositing the second layer of the conducting material.

11. A method according to claim 10, further comprising a step of depositing a further layer of electrically insulating material prior to depositing the layer of photopatternable electrically insulating material.

12. A method according to claim 10 or 11, wherein a half-tone mask is used for the step of photopatterning the layer of photopatternable electrically insulating material.

13. A method according to claims 10 or 11 wherein a diffraction mask is used for the step of photopatterning the layer of photopatternable electrically insulating material.

14. A method according to claim 10 or 11, wherein a double exposure method is used for the step of photopatterning the layer of photopatternable electrically insulating material.

15. A method according to claim 14 wherein the double exposure method applies a first exposure using a first mask followed by a second exposure using a second mask.

16. A method according to claim 15 wherein the first exposure and second exposure differ in light intensity.

17. A method according to claim 15 wherein the first exposure and the second exposure use different wavelength distributions of light.