WO2009044205A2

WO2009044205A2 - Correlator for global navigation satellite systems

Info

Publication number: WO2009044205A2
Application number: PCT/GB2008/050898
Authority: WO
Inventors: Tughrul Sati Arslan; Nitin Chaudhary; Zankar Upendrakumar Sevak
Original assignee: The University Court Of The University Of Edinburgh
Priority date: 2007-10-05
Filing date: 2008-10-03
Publication date: 2009-04-09
Also published as: GB0719506D0; WO2009044205A3

Abstract

A correlator and method of correlation for Global Navigation Satellite Systems (GNSS) are disclosed in which a multi-navigation pseudorandom operation is performed on an input satellite signal to provide a correlated output. The input satellite signal is input to an N parallel channel correlator (102). Each parallel channel (301) contains a dynamically allocating multi-resolution control block that controls carrier (404) and code (405) oscillator output frequency and resolution separately in each channel. Each channel may also include a multi-system GNSS pseudo- random block (502), low-power computation blocks and low-power control mechanism.

Description

Correlator for Global Navigation Satellite Systems

The present invention relates generally to the Global Navigation Satellite system, and more particularly to receiving and correlating satellite signals in a correlation receiver systems.

Global Navigation Satellite System (GNSS) is the standard generic term for satellite navigation systems that provide autonomous geo-spatial positioning with global coverage. A GNSS allows small electronic receivers to determine their location (longitude, latitude, and altitude) to within a few meters using time signals transmitted from satellites. The GNSS system comprises United States NAVSTAR Global Positioning System (GPS). Russian (GLONASS), The European Union's Galileo positioning system and many others. An embodiment of the present invention concentrates on targeting GPS (L1 C/A, L2C) and Galileo (E5a, E5b) navigation signal system, described briefly below.

The GPS Orbital constellation consists of 24 satellites or space vehicles (SV) which orbit the earth in 12 hour orbits. The satellites are arranged in a six orbital planes each containing four satellites. The orbital planes are spaced 60 degrees apart from each other and are inclined approximately fifty-five degrees with respect to the equatorial plane. The constellation provides a user with approximately five to eight satellites visible from any point on earth. The Galileo system operated by the European Union consists of 30 satellites or space vehicles (SV). At an orbital altitude of 23 222 km from earth's surface. It consists of 3 orbital planes, each constitutes 9 operational satellites and one active spare per orbital plane and are inclined at fifty-six degrees with respect to the earth's equatorial plane.

Each transmitted GPS signal is a direct sequence spread spectrum signal. The signal available for commercial use is that associated with Standard Positioning service (SPS) and utilises a direct sequence bi-phase spreading signal with a 1 .023 Mchip per second spread rate placed upon a carrier at 1575.42 MHz (L1 C/A) and 1 .023 Mchip and per second spread rate placed upon a carrier at 1227.5 MHz (L2C).

Each transmitted Galileo signal is also a direct sequence spread spectrum signal. Galileo will provide six navigation signals in the frequency ranges 1 ,164-1215 MHz (E5 band), 1 ,260-1 ,300 MHz (E6 band) and 1 ,559-1 ,592 MHz (E2-L1 -E1 band). The present invention targets E5 band as part of it multi navigation correlation approach. E5a-E5b is in the E5 band and utilises a direct sequence bi-phase spreading signal with a 10.23 MHz per second spread rate placed upon a carrier at 1 191.795 MHz.

Each satellite transmits a unique pseudorandom code (also referred to as Gold code) which identifies the particular satellite, and allows signals transmitted simultaneously from several satellites to be received by a receiver, with little interference with one another. The pseudorandom noise (PN) code sequence length is 1 ,023 for (L1 ,C/A), 10230 (CM) - 767250 (CL) for L2C, 10230 for E5a-E5b chips.

A primary goal of a GNSS receiver is to determine the time of arrival of PN codes. This is accomplished by comparing (for each received signal) a locally generated PN reference against the received signal and "tuning" the local reference in time until it is time-aligned with the received signal. This process is called correlation. Correlation means a comparison of two data sequences (typically a sampled signal and a locally generated reference signal), and the accumulated data comparison with a threshold. To acquire and track a navigation satellite signal fine tuning is required. This tuning is done through the oscillators of a correlator unit which are based on a common mathematical principle shown in the equation below.

F_NCO = M f_s/2 ⁿ (1 )

Resolution = f_s/2 ⁿ Where,

FNCO = Output frequency M = Control signal value from processor n = Holding Register Length f_s = Sampling frequency

Conventional (GNSS) receivers achieve this by changing only the nominal frequency factor 'M' and keeping the resolution factor constant. In a strong satellite navigation signal this method can acquire and track a satellite signal very efficiently. But in the case of a weak signal, a high resolution can increase the available signal strength and help fast acquisition and tracking of the navigation signal.

It is therefore desirable to deal with both the strong and weak signals on a dynamic basis to cope with changing reception conditions. It is also desirable to reduce the complexity of the circuitry by using common components wherever possible, such as using common hardware in both the oscillator and multi-system code generators.

A low power and flexible GNSS receiver architecture can provide a user with operational flexibility. Current GNSS expand their capabilities by introducing new codes and frequencies. A GNSS receiver that requires more frequencies to achieve better results will have to add hardware modifications in order to make use of newly available GNSS frequencies. In the near term, a GNSS will be faced with a complex trade-off in order to decide whether the extra complexity is worth the improved performance. So any flexibility within the correlator chip can reduce the need for such trade-offs. Thus, there are good reasons to develop a less complex but more flexible GNSS receiver.

A typical state of the art GNSS receiver can be broken down into various components as shown in FIG 1 . First, an antenna 100, possibly followed by a pre-amp, receives the GNSS signals. After the antenna comes the

RF section 101 that filters and down converts the GHz GNSS signals to an intermediate frequency in the MHz range. The RF section also digitises the signal. The next section is the correlator chip 102 that separates the signal into different channels allocated to each satellite. It mixes the Doppler shifted intermediate frequency signal to the base band and correlates it with a local replica of a GNSS pseudorandom code (PRN). The final components of the GNSS receiver involve processor 103 routines that track the signals, demodulate the navigation message and compute the desired navigation solution.

GNSS receivers are categorised broadly on whether they have a single correlator channel for each satellite or multiplex different satellite signals with one channel. They can be single-channel sequential, single-channel multiplexed or single channel per satellite. In a single channel sequential receiver, each of the satellites is tracked continuously, one at a time for a few seconds, before tracking another satellite. In single channel multiplexing, the sequencing rate is high so that the data from four satellites are viewed simultaneously. In multiple channel receivers, now in more common use, each of the satellites is assigned a single channel, however, this increases circuit complexity. Furthermore, current prior art designs with parallel channels do not operate multi GNSS navigation system frequencies and codes.

According to a first aspect of the present invention, there is provided a correlator for navigation satellite systems, the correlator comprising: an input for receiving a satellite signal; a channel comprising an oscillator operable to provide an oscillator output signal having an oscillator output frequency; and a control circuit operable to control the oscillator output frequency and the oscillator resolution.

Preferably, the control circuit is operable to separately control the oscillator output frequency and the oscillator resolution.

Preferably, the control circuit is operable to dynamically control the oscillator output frequency and oscillator resolution.

Preferably, the oscillator has a configurable resolution.

Preferably, the correlator further comprises a clock generator operable to output a plurality of sampling clock signals.

Preferably, the control circuit is operable to receive the plurality of sampling clock signals and provide to the oscillator a sampling clock signal selected from the plurality of sampling clock signals.

Preferably, the oscillator is operable to dynamically generate the oscillator output frequency from a sampling frequency, control signal value and an accumulator register length, each provided by the control circuit. Preferably, the oscillator is a carrier oscillator.

Alternatively, the oscillator is a code oscillator.

Preferably, the channel comprises a pair of the oscillators comprising a carrier oscillator and a code oscillator operating in parallel.

Preferably, the carrier oscillator and code oscillator are both provided with the sampling frequency by the clock generator.

Preferably, the control circuit is operable to control the oscillator output frequency by providing a clock signal to the oscillator.

Preferably, the control circuit is operable to dynamically configure the oscillator resolution by configuring an accumulator register length in the oscillator.

Preferably, the control circuit is operable to select frequency bins for acquisition and tracking.

Preferably, the correlator comprises a plurality of the channels in parallel with each other.

Preferably, the control circuit is operable to switch off unused channels of the plurality of the channels.

Preferably, the oscillator resolution is dynamically controlled on an individual basis for each used channel of the plurality of the channels. Preferably, the channel further comprises a pseudorandom noise code generator dynamically configurable to be operable with each of a plurality of navigation satellite systems.

Preferably, the control circuit is operable to dynamically configure the pseudorandom noise code generator to be operable with a selected navigation satellite system.

Preferably, the correlator further comprises a processor is operable to dynamically operate the control circuit to control the oscillator resolution.

Preferably, the processor is operable to monitor the satellite signal strength and to dynamically operate the control circuit to control the oscillator resolution responsive to the signal strength.

Preferably, the processor is operable to dynamically operate the control circuit to increase the oscillator resolution to compensate for low satellite signal strength.

Preferably, the processor is operable to monitor an acquisition threshold and to dynamically operate the control circuit to control the oscillator resolution responsive to the acquisition threshold.

Preferably, the correlator comprises a processor operable to dynamically operate the control circuit to configure the pseudorandom noise code generator to be operable with a selected navigation satellite system.

Preferably, the processor is operable to monitor a correlation threshold and to choose a selected navigation satellite system responsive to the correlation threshold. According to a second aspect of the present invention, there is provided a method of correlation for navigation satellite systems, the method comprising the steps: receiving a satellite signal; providing an oscillator output signal having an oscillator output frequency from an oscillator in a channel; and controlling the oscillator output frequency and the oscillator resolution.

Preferably, the oscillator output frequency and the oscillator resolution are controlled separately.

Preferably, the oscillator output frequency and the oscillator resolution are controlled dynamically.

Preferably, the method further comprises the step of outputting a plurality of sampling clock signals from a clock generator.

Preferably, the step of controlling the oscillator output frequency comprises the steps of receiving the plurality of sampling clock signals and providing to the oscillator a sampling clock signal selected from the plurality of sampling clock signals.

Preferably, the method further comprises the step of dynamically generating the oscillator output frequency from a sampling frequency, control signal value and an accumulator register length.

Preferably, the oscillator is a carrier oscillator. Alternatively, the oscillator is a code oscillator.

Preferably, the method comprises providing a pair of the oscillator output signals from a pair of the oscillators in the channel, the pair of the oscillators comprising a carrier oscillator and a code oscillator operating in parallel.

Preferably, the step of controlling the oscillator output frequency comprises the step of providing a clock signal to the oscillator.

Preferably, the step of controlling the oscillator resolution comprises the step of dynamically configuring the oscillator resolution by configuring an accumulator register length in the oscillator.

Preferably, the method further comprises the step of selecting frequency bins for acquisition and tracking.

Preferably, the method further comprises the step of operating a plurality of the channels in parallel with each other.

Preferably, the method further comprises the step of switching off unused channels of the plurality of the channels.

Preferably, the method further comprises the step of dynamically controlling the oscillator resolution on an individual basis for each used channel of the plurality of the channels. Preferably, the method further comprises the step of dynamically configuring a pseudorandom noise code generator to be operable with a selected navigation satellite system.

Preferably, the method further comprises the steps of monitoring the satellite signal strength and dynamically controlling the oscillator resolution responsive to the signal strength.

Preferably, the method further comprises the step of dynamically increasing the oscillator resolution to compensate for low satellite signal strength.

Preferably, the method further comprises the steps of monitoring an acquisition threshold and dynamically controlling the oscillator resolution responsive to the acquisition threshold.

Preferably, the method further comprises the steps of monitoring a correlation threshold and choosing the selected navigation satellite system responsive to the correlation threshold.

An embodiment of the present invention is illustrated by way of example only and not by way of limitation with reference to the figures of the accompanying drawings in which references indicate similar elements and in which:

FIG. 1 is a block diagram representation of a prior art global navigation system.

FIG. 2 is a block diagram representation of a global navigation flexible clock generator and interface with the correlator circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram representation of a global navigation system N channel highly parallel correlator circuit.

FIG. 4 is a block diagram representation of a global positioning system receiver single channel correlator circuit.

FIG. 5 is a block diagram representation of a global navigation system correlator circuit incorporating a flexible multi-resolution oscillator circuit according to an embodiment of the present invention.

FIG. 6 is a block diagram representation of global positioning system correlator circuit incorporating multi resolution oscillators and multi signal system (L1 C/A, L2C, E5a, E5b) Pseudo random code generator.

A preferred embodiment of the present invention is an apparatus for acquiring and tracking multi GNSS with a parallel and multi resolution architecture GNSS receiver. In an embodiment of the present invention, all resolutions selected as being applicable at a given time are processed in parallel. An appropriate resolution is selected in real-time on an individual basis for each active channel.

In an embodiment of the present invention, each correlator unit contains a multi-system pseudorandom noise generator. The parallel channel correlator circuit implements flexible and common use of selected hardware circuitry, therefore reducing overall circuit complexity. The preferred embodiment of the present invention is a low power GNSS domain specific flexible multi resolution correlator which serves as a scalable IP core suitable for System on Chip applications for acquiring and tracking satellites. Novel means of dynamic allocation and configurability provide numerous improvements to current state of the art ASIC designs due to the added flexibility and improvements in functionality.

A multi navigation pseudorandom operation is performed on an input global navigation satellite system signal to provide a correlated output. The input satellite signal is input to an N parallel channel correlator system. Each parallel channel contains a novel dynamically allocating multi resolution control block, multi system GNSS pseudo random block, low power computation blocks and low power control mechanism.

A dynamic allocation multi resolution technique is used to implement an optimal receiver model. It produces a variable, controlled output frequency allowing dynamic correlations to acquire the desired GNSS signals. Providing multi resolution capabilities to adapt receiver results in an increase or decrease in signal strength and, in turn, increases or decreases the computational burden at any given time, and so optimises power consumption and the performance of the receiver.

The optimal model also provides a controlled sampling clock, to implement a variable output frequency for dynamic correlation.

The receiver block design includes a mechanism that controls the Clock Generator and Multi resolution block with a dynamic dependence on the signal acquisition and tracking requirements. Any GNSS signal for which codes are available, can in principle be implemented in the design. For example, a present embodiment includes capability for all of the multi GPS (L1 C/A, L2C) and Galileo (E5a, E5b) navigation signal system pseudorandom code generator system, to create a versatile multi navigation system, but many other combinations can be understood to be possible. The novel control mechanism is used to search for, and acquire the best available satellite signals.

A low power control mechanism is used for the correlator system architecture's interface with the microprocessor, to provide high performance and throughput.

A highly parallel approach is used for the GNSS carrier and code correlation. Each channel can be dynamically allocated to any satellite of any available navigation system.

The amount of data that is necessary for acquisition and tracking purposes is important to any receiver design. During acquisition, the correlation peak is detected and the receiver calculates an envelope to determine if the correlation peak has crossed a threshold value. Within each search bin, the envelope is estimated and compared to a threshold to determine the presence or absence of a signal. The detection is described by a PDF (probability density function) for each cell. The GNSS receiver uses continuous time domain correlation to acquire data to perform the acquisition. The design goal of a GNSS receiver should be to enhance the ability to provide multi resolution data for increasing or decreasing signal strength. This allows appropriate increases or decreases in the computational burden, and therefore directly affects the power consumption and performance of the receiver without any delay. During the acquisition and tracking phase, the carrier frequency and code phase needs to be searched continuously until the signal is detected. Any improvements in this cycle will therefore speed up acquisition and decrease power usage.

To clarify the description of the present invention, the following definitions are provided. A "correlation" means a comparison of two data sequences (typically a sampled signal and a locally generated reference signal), performed by multiplying the two sequences together term by term, summing the result. A "resolution" means a sampling frequency divided by two to the power of oscillator accumulator length as shown in equation 1 . According to above definition, the correlation input is incoming signal from a satellite, which will exhibit a Doppler shift that varies with time due to non-uniform motion of the satellite relative to the receiver. The user clock bias is likely to also vary with time. The net result is that, unless dynamic correlations are applied to the code and carrier numerically controlled oscillators, the GNSS signal will be lost.

An embodiment of the present invention uniquely allows all three components 'M', %' and 'ri, required to tune the resolution and oscillator output frequency to be chosen separately. This provides fine adjustment of the resolution or signal strength in the oscillators, directly optimising the computational burden and resulting in lower power consumption and higher performance of the receiver, while producing the desired output from the numerically controlled oscillators.

Resolution plays an important part in the search of the required signal in both signal acquisition and tracking. By controlling the resolution, the processor can make decisions as to whether to use high resolution during acquisition and tracking phases. Less resolution requires less resource, and by controlling the oscillator components accordingly the processor can select the use of only just enough resolution, so reducing the computational burden in the acquisition and tracking phase. The power consumption of the overall receiver section is also reduced. General GNSS receivers require separate Carrier and Code oscillator blocks to provide the output frequencies required in the correlator circuit. In the present invention, a common oscillator with added multi-resolution functionality is used to satisfy all the frequency requirements of the correlator circuit. Also, it accurately provides the frequency requirements to the multi-system PN code generators. By this means, the design complexity and power are reduced.

The spectrum of each GNSS satellite signal is spread-spectrum modulated using C/A, L2C, E5a and E5b codes. This causes the satellite signal seen by a typical GPS or Galileo receiver to be so weak that they are buried in noise and can only be detected by correlation. To correlate the received signals therefore a locally generated GNSS replica code must be chosen to precisely match the spreading code type, rate and phase. This invention uses a multi system GNSS pseudo random code generator that generates a replica of for example the GPS (C/A, L2C) and Galileo (E5a, E5b) codes dynamically. This pattern is then multiplied bit by bit with the incoming data stream and the results are integrated over a code length to recover the signal.

The process of signal acquisition requires the matching of this integrated output to the actual signal values. Control logic allocates channels to those navigation systems whose satellites are more visible and signal strength is strongest during any given fix, and switches off the rest of the resources. This reduces use of extra functional block resources and reduces power consumption. With reference to FIG 1 , the radio frequency (RF) signal is received by an L-band antenna 100. This signal is filtered and then amplified by a low- noise amplifier (LNA). Next, the signal is down-converted by 101 to a convenient intermediate frequency (IF) and converted from analog-to- digital (A/D). The resultant digitised signal has two binary bits per sample. The next section is the correlator chip 102 that separates the signal into different N parallel channels allocated to each satellite. It mixes the Doppler shifted intermediate frequency signal to base band and correlates it with a local replica of a GNSS pseudorandom code (PRN). The final components of the GNSS receiver involve processor 103 routines that track the signals, demodulate the navigation message and compute the navigation solution.

With reference to FIG 2, the clock generator 201 generates various sampling clock signals to be used by the correlator 102 and other circuits. In this embodiment of the present invention, it provides the numerator factor (f_s) in the resolution calculations. The clock generator block divides the frequency of the basic clock 101 from RF section by 'K' to give internal multi phase set of clocks. The clock generator also produces a clock for the processor 103 to synchronise. The internal multi phase clock or sampling frequency is used in oscillators 501 as shown in FIG 5 and FIG 6. To achieve a precise clock some floating point units are also added without clock delay. To prevent clock skewing, additional delays are inserted.

With reference to FIG 2 and FIG 3, the correlator 102 comprises N parallel channels 301 and a peripheral interface 302. The correlator has three main functions. First, it mixes a signal to base band using the estimated carrier Doppler shift and carrier phase. Second, it mixes the base band signal with a replica of the C/A, L2C, E5a or E5b code using the estimated code phase and code chipping rate. Third, it sums the resulting signal over a C/A, L2C, E5a or E5b code period. All three functions are incorporated in each channel of the correlator depicted in FIG 4. One correlator channel is needed for each satellite to be tracked. A flexible multi resolution block in place of a general carrier and code oscillator in FIG 4, part of each channel is also depicted in FIG 5. These blocks are dynamically allocated to each N parallel channels depending on the GNSS system, appropriate carrier and code frequencies for each channel of Correlator circuit is generated. This makes the system more flexible with respect to using multi navigation systems. Each channel, can be dynamically allocated to respective satellite systems without changing the correlator design and resources. A more detailed diagram where each of the blocks 501 & 502 are shown working in parallel is provided in FIG 6.

With reference to FIG 4, each channel 301 is fed with a 2-bit GPS digital intermediate frequency from the RF section. This 2-bit input signal is first brought to base band using an on-chip digital mixer. The signal is then carrier wiped off into lnphase (I) and Quadrature (Q) signals using Sine Cosine look up tables for phase generation. It is then code wiped off using pseudorandom generators and finally this communication block adds samples over a time interval by using integrate and dump.

This embodiment of the present invention uses a multi resolution oscillator 501 , which is the digital counterpart of an analogue voltage controller. A digital numerically controlled oscillator (NCO), consists of an accumulator, to which an incoming error signal is added. From equation (1 ) the free running output frequency of the NCO 501 depends on f_s the sampling clock frequency, M, the incoming error signal magnitude, and n, the number of bits of the accumulator. General oscillators generate a square wave whose frequency is controlled by the error. The NCO forms an important part of a digital receiver as it is used in the timing recovery. Individual blocks in a single channel 301 of a correlator 102 depicted in FIG 4 are described in more detail below.

The carrier oscillator 404 is used in the carrier tracking loop, to track the phase of the incoming carrier, by changing the phase of the local signal. Based on the carrier discriminator, the error signal is generated. In a general oscillator, this error signal is used to increase or decrease the phase of the locally generated signal, so that it matches with the incoming signal. It is also used to bring the input signal to base band in the mixer block, and must be adjusted away from its nominal value to allow Doppler shift and reference frequency error.

Also, the oscillator output frequency (carrier & code) can be changed by increasing and decreasing the value of 'n' and sampling frequency %'. The Multi resolution oscillator 501 contains a control signal, which generates the output frequency according to the input from the flexible clock generator, and control signals from the processor. It can generate an output frequency for the carrier wipe off and code wipe off circuits in parallel without delaying the circuit execution time. The processor selects, by a process of monitoring the acquisition threshold, whether to change or keep the current oscillator resolution. This information is fed back to the oscillator circuit and the code and carrier is wiped off accordingly.

To produce 406 sine and cosine waves digitally one of the approaches used is the look up table method. It is an extension of the oscillator. The oscillator generates a square waveform. The amplitude is converted to a corresponding sine wave. The k Most Significant Bits of the accumulator register of the oscillator are used to address a lookup table which contains an 'rf bit precision sine and cosine values representing a sinusoidal sequence. The incoming digital data is modulated by the carrier and code. The demodulation process at the receiver involves carrier stripping initially. For the demodulation process, the sine and cosine values are required, and these can be generated using the module 406.

Base-band mixing is the multiplication of an input signal by a complex exponential, where the frequency of the complex exponential approximately matches that of the input signal. The resultant signal is centred at base-band. A complex output signal from the RF section at an intermediate frequency is latched at a sampling frequency generated by the clock generator, which is N times higher, depending on the requirement of the phase generation. The carrier mixer 401 circuits multiply this latched digital input signal by the carrier oscillator 404 to generate a signal at base band. It uses a multiplier-less technique by using 'Exclusive OR' gates. This mixer splits the mixed input signal samples into in-phase and quadrature components.

The code oscillator 405 is used in the code tracking loop. It is similar in function to the carrier oscillator 404. It is also clocked at a sampling clock from clock generator 201 and synthesizes the oscillator required to drive the PN code generator at twice the required chipping rate. A very fine resolution is required to keep the oscillator in phase with the satellite signal. This code phase can be aligned by adjusting the aforementioned three factors of the stated mathematical equation with the satellite phase. The code mixer 402 mixes the input lnphase (I) and Quadrature (Q) samples with the early (E) prompt (P) and late (L) PN codes and it also contains a look up table which maps the lnphase and Quadrature signals output. This mapping reduces the lnphase and Quadrature number representation for more efficient processing. The look up table contains all the possible scenarios for code wipe off from the mixed signal.

The code generator 502 generates the code for GPS and Galileo satellites. The GPS L1 C/A-code signal is generated by binary-phase shift keying (BPSK) modulation of an L1 carrier (1575.42MHz) with a bit stream, which is the modulo-2 addition of 50 bits per second (bps) navigation data with a pseudo-random noise ranging code, C/A, sequence. The C/A-code is chipped at a rate of 1 .023 Mchips/s and repeats every 1 ,023 chips (1 ms period). The C/A-code is a modulo-2 addition of two 1 ,023-chip sequences - G1 and G2i. G2i is a delay-shifted version of another sequence, referred to as G2. The polynomials are used in two 10-stage shift registers, initialised with all 1 's, to generate the G1 and G2 sequences. Modulo two addition results in a derived C/A code.

The L2C navigation data is generated at a 25 bps rate and is convolutionally encoded with rate V2 and constraint length 7 to create a symbol stream of 50 symbols per second (sps). This 50 sps stream is synchronized and modulo-2 added to a 51 1 .5 Kchips/s CM code of 10,230 chips (20 ms). The resulting sequence is chip-by-chip multiplexed with a 51 1 .5 Kchips/s CL code of 767,250 chips (1 .5 s) to generate a combined sequence at 1 .023 Mchips/s. This sequence is subsequently BPSK- modulated by the L2 carrier frequency of 1227.6 MHz to generate the GPS L2C transmitted signal. PN generator uses a 27-stage shift register, which is used to generate all L2C spreading code sequences. Depending on the initial states of the shift register, a particular CM or CL code sequence is selected. The shift register's end states are decoded to re-initialize the shift register with the initial state again. This re-initialization mechanism is used to generate CM codes with a period of 10,230 chips (20 ms period), and CL codes with a period of 767,250 chips (1 .5 s period). The CM code is chip-by-chip multiplexed with CL code, with CM first to generate the L2C code.

The Galileo E5a and E5b signal is generated by binary-phase shift keying (BPSK). It transmits basic data to support navigation and timing functions using 25 bits per second (bps) and 125 bps respectively. Galileo E5 consists of the multiplexing of the four component in which the signal is generated by modulo two additions. This 50 symbols per second (sps) stream is synchronised and modulo-2 added to a 10.23 Mchips/s. The primary codes are based on classical 'Gold codes' with register length up to 25. The secondary codes are predefined with sequences of length up to 100 bits. This sequence is subsequently BPSK-modulated by the E5 carrier frequency of 1 191 .795 MHz to generate the Galileo E5 transmitted signal.

The 2 bit shift register 407 operates on twice the code generator clocking rate. The shift register produces two phase-delayed versions of the code generator output. As a result, there are three replica code phases designated as early (E), prompt (P), and late (L). E and L are typically separated in phase by Vz chips. It generates half chip code frequencies that will be required for the code tracking.

The Accumulate and Dump 403 block integrates the mixer 402 output over a complete code period. There are six separate accumulators for each channel. These represents the correlation of the lnphase and Quadrature signals with the Early, Prompt and Late codes. It also implements the function of a low pass filter. This communication block adds samples over a time interval and at the end of this interval resets, hence the name Integrate and Dump. Importantly, the complex correlation sums drive all subsequent receivers processing. The integrated result of the Accumulate and Dump block over the code length is used to recover the signal. In summary, the incoming signal is mixed with the local signal to convert it to base band. This step is known as carrier wipe off since the resulting signal does not contain any carrier component. The signal is then correlated with prompt (P) C/A, L2C and Galileo E5a, E5b code (this results in a code wipe off) and then the samples are integrated. The Accumulate and Dump acts as a low pass filter and filters the double frequency term in the quadrature mixer output leaving only the correlation value.

FIG 6 depicts the use of multi resolution technique with multi GNSS code generator system in single channels. A decision to go ahead with which GNSS system is made as soon as the integrated sample dataset is compared with the respective thresholds in the processor circuit.

The theory behind the correlator circuit will now be explained in more detail. A received code signal in the presence of thermal noise is dependent on total received power, thermal noise power density and chip rate of the ranging code and carrier frequency. Neglecting the correlation between ranging codes, the real and imaginary correlation sums are used for tracking, acquisition and navigation data demodulation. Normally, input sample rate is the multiple of the chipping rate. If the input signal contains a transmitted waveform matched to a given correlator, the data out in the Acquisition phase will contain a narrow spike corresponding to spanning a width of approximately one chip duration. Each spike will then correspond to the time of arrival information. A square law operation is used in the Acquisition phase to detect these spikes. In one embodiment of the present invention, multi-resolution parallel channels can effectively be used to perform signal tracking as well as acquisition. Thus, allowing the flexible correlator block to acquire the signal information.

During tracking of a GPS signal, the incoming GPS signal will exhibit a Doppler shift that varies with time due to the non uniform motion of the satellite relative to the receiver, and the user clock bias is also likely to vary with time. This therefore leads to two loops; one to maintain lock on PN code, and the other to maintain lock on the carrier. The general approach consists of varying the carrier phase by regularly updating the carrier oscillator frequency through varying only one component, 'M' of equation (1 ). The technique used in the present invention uses all three components of the mathematical equation to maintain all of the correlation energy in the inphase arm and none in the quadrature phase arm. The code tracking is based on an early-late correlation value. When a signal is acquired, the local replica is within a chip time of the incoming signal. The delay locked loop tracks the signal by generating an early and a late signal. These are generated using a 2-bit shift register in FIG 4. The shift register is clocked at twice the code oscillator. The incoming code is correlated with both the early and late code samples. Comparing local and received signals N time offset at a given time. If such a comparison is done every half-chip interval, 2046 for C/A, 20460(CM) & 1534500 (CL) for L2C and 20460 for Galileo E5a and E5b comparisons (or tests) would be required to completely search over one PN epoch. Search bins contain data collected by performing parallel correlation to speed up the acquisition process for each of the several of the satellites in view. Thus data is extracted from the correlator units and passed to the microprocessor. The microprocessor may then perform Acquisition, Tracking and Demodulation. The microprocessor then feeds back control signals to oscillator circuitry, PN circuitry and dump gates in order to maintain proper acquisition and tracking during this operation. In one embodiment of the present invention, the microprocessor also sends feedback signals to the control circuit 503 of the correlator circuitry. According to these control signals the correlator circuit switches off some unused parts in the circuitry, reducing the overall power consumption of the design. Through this control circuit, the microprocessor also sends control signals to the oscillator circuitry, PN circuitry and dump gates in order to maintain proper acquisition and tracking during the operation shown in FIG 6.

The input data stream is denoted as I₁ = i₀, J₁ , ...., I2 = io, h , ■ ■ ■■, I3 = io, h , ...., and I₄ = io, J₁ , ...., is of rate approximately 1 .023 Msamples for C/A, 10.230 Msamples for L2C, E5a and E5b per second respectively. The locally generated pseudo random stream for C/A, L2C, E5a and E5b is denoted as P₁ = po, P₁ , .... P_n-i , P₂ = Po, Pi , .... Pn _{1 5} P₃ = Po₅ Pi , .... P_n- 1 , and P₄ = po, P₁ , .... P_n-i respectively. Each pseudo random stream sequence consists of series of number assuming values of -1 and +1 . Each signal system has its own period of these streams, which repeats itself after that period. Correlator circuit illustrated in FIG 1 multiplies the input data stream (I₁ = i₀, h , ...., I₂ = io, H , ■ ■ ■-, I3 = io, H , ■ ■ ■-, and I₄ = i₀, h , ....,) by the locally generated PN sequence (P₁ = p₀, P₁ , .... P_n-i , P2 = Po, P₁ , .... P_n-I ₁ P₃ = Po. Pi . ■ ■ ■■ P_{n 1} , and P₄ = P₀, P₁ , .... P_n-O and sums the result. If the input data stream contains a signal with this respective PN sequence, and if it is time aligned with the PN sequence, a large output results. If however the locally generated PN sequence is not time aligned with the input data stream, another time alignment must be tried. The second time alignment typically consists of the original data stream shift by half chip to avoid losses due to partial alignment. This general sequencing takes place in each channel and the processed data are provided through an interface to the microprocessor where the acquisition, tracking and navigation process are carried out, since the aforementioned microprocessor makes the control decision for the correlator circuit.

In the correlator circuit, the availability of additional multi resolution provides an added advantage, allowing a choice of how much data needs to be processed, and which frequency bins are to be selected for the acquisition and tracking process. In the current invention, the GNSS receiver can be controlled to react to different signal strengths to reduce the computation burden. This allows compensation for errors in received signal frequency that would otherwise require additional searches to be made for various hypotheses of signal frequency. The time to perform this search may be very lengthy, especially under low input signal-to-noise ratio situations. So in reducing execution time, the GNSS receiver provides a flexible computational path trading-off high resolution-more computation or low resolution-less computation etc. for each search. One result is a faster lock to the navigation satellites and fast time to first fix (TTFF). TTFF is a critical parameter for many portable devices, which run their GNSS only intermittently in order to save power. Modern high sensitivity receivers use large correlator arrays, complete parallel code length search, real or virtual for the fast TTFF at the same time as using the long integration times required by weak signals. This embodiment of the present invention achieves this by searching the signal in dynamically allocated parallel channels. This has only been made possible using extremely efficient system architecture. Also parallel searching of the entire frequency space, satellite and constellation, would use excessive silicon footprint, and therefore be uneconomic. So a novel and efficient approach of dynamic channel allocation has been followed for best performance and reduced silicon footprint. For weak signal signals detection, integration times may extend out to 1 second or more. Such long times are not desirable, as they impact the dynamics that can be tracked, and the data decoding function. An additional technique uses a multi resolution technique to eliminate the need for such long integration times without affecting the performance by a significant degree, by increasing resolution to compensate for low signal strength. As aforementioned, prior art oscillators work on the principle of increasing or decreasing the nominal value TW'which only helps in changing one factor to achieve the required output frequency by keeping the other two components or resolution constant.

Another technique to achieve the desired output frequency could be to control the sampling clock T₅ 'alone, but by doing this the carrier and code phases could be changed. A flexible sampling clock could be achieved by simple digital filters in the clock generator circuit 503. Also, the whole system clock needs to be changed if the sampling frequency is changed quite often and this could result in mismatching with the required carrier frequency and code phase.

Another technique could be to increase or decrease the value of the accumulator register by changing 'ri, which will have a large affect on the oscillator output frequency, being in the denominator. But by doing this alone will have less flexibility as it appears as a power, 2ⁿ. A one bit increase in the oscillator register length will change the output frequency significantly. This embodiment of the present invention provides a flexible controlled oscillator 501 where all the three factors may be changed, with the help of control signals from the microprocessor, to achieve the desired resolution without changing the required output frequency. This, with the multi navigation pseudorandom code generator system will help strengthen the S/N without affecting the receiver performance. The control circuit, with the help of the processor, self monitors the signals and continuously adjusts all three factors and checks other available navigation system satellites and its signal processing and tracking parameters for optimum performance at the current signal strength for each individual satellite. Execution time may be increased or decreased by the intelligent use of the resolution, which results in increase or decrease of the data search bins, which is directly proportional to the power consumption in the circuit.

A particular problem occurs at start up, when receiver has no knowledge of its dynamics. Typically, the receiver will commence assuming higher dynamics. An outdoor level signal search may be made relatively quickly. If a suitable strong signal is not found, however, the receiver must work down the decision tree of options, driven by available information of navigation systems, and the stored knowledge of the appropriate cold start searches of all satellites in question. For weak signals, using a poor accuracy clock would take an unacceptable time (and power), but does become practicable for a good clock aided with good resolution/position/almanac either from on-board memory or alternatively through use of assisted messaging. If a satellite is found however, the decision tree must be re-run in the light of new information. When a fix is achieved, the processor will maintain a check on perceived dynamics, in order to optimise integration and tracking algorithms, and lower dynamics allow the signal to be followed down to lower received signal levels. In some scenarios where a satellite may be temporarily lost, the receiver may have to run multiple dynamics options in parallel to achieve the fastest re- acquisition. In the forgoing, a receiver system has been described for GNSS signal processing applications with a highly parallel circuit, a multi resolution technique and multi navigation satellite PN generator.

Further modifications and improvements may be made without departing from the scope of the invention described by the claims.

Claims

1 . A correlator for navigation satellite systems, the correlator comprising: an input for receiving a satellite signal; a channel comprising an oscillator operable to provide an oscillator output signal having an oscillator output frequency; and a control circuit operable to control the oscillator output frequency and the oscillator resolution.

2. The correlator of claim 1 , wherein the control circuit is operable to separately control the oscillator output frequency and the oscillator resolution.

3. The correlator of claim 1 or claim 2, wherein the control circuit is operable to dynamically control the oscillator output frequency and oscillator resolution.

4. The correlator of any previous claim, wherein the oscillator has a configurable resolution.

5. The correlator of any previous claim, further comprising a clock generator operable to output a plurality of sampling clock signals.

6. The correlator of claim 5, wherein the control circuit is operable to receive the plurality of sampling clock signals and provide to the oscillator a sampling clock signal selected from the plurality of sampling clock signals.

7. The correlator of any previous claim, wherein the oscillator is operable to dynamically generate the oscillator output frequency from a sampling frequency, control signal value and an accumulator register length, each provided by the control circuit.

8. The correlator of any previous claim, wherein the oscillator is a carrier oscillator.

9. The correlator of any of claims 1 to 7, wherein the oscillator is a code oscillator.

10. The correlator of any of claims 1 to 7, wherein the channel comprises a pair of the oscillators comprising a carrier oscillator and a code oscillator operating in parallel.

1 1 . The correlator of claim 10, wherein the carrier a the clock generator.

12. The correlator of any previous claim, wherein the control circuit is operable to control the oscillator output frequency by providing a clock signal to the oscillator.

13. The correlator of any previous claim, wherein the control circuit is operable to dynamically configure the oscillator resolution by configuring an accumulator register length in the oscillator.

14. The correlator of any previous claim, wherein the control circuit is operable to select frequency bins for acquisition and tracking.

15. The correlator of any previous claim, wherein the correlator comprises a plurality of the channels in parallel with each other.

16. The correlator of claim 15, wherein the control circuit is operable to switch off unused channels of the plurality of the channels.

17. The correlator of claim 15 or claim 16, wherein the oscillator resolution is dynamically controlled on an individual basis for each used channel of the plurality of the channels.

18. The correlator of any previous claim, wherein the channel further comprises a pseudorandom noise code generator dynamically configurable to be operable with each of a plurality of navigation satellite systems.

19. The correlator of claim 18, wherein the control circuit is operable to dynamically configure the pseudorandom noise code generator to be operable with a selected navigation satellite system.

20. The correlator of any previous claim, further comprising a processor operable to dynamically operate the control circuit to control the oscillator resolution.

21 . The correlator of claim 20, wherein the processor is operable to monitor the satellite signal strength and to dynamically operate the control circuit to control the oscillator resolution responsive to the signal strength.

22. The correlator of claim 20 or claim 21 , wherein the processor is operable to dynamically operate the control circuit to increase the oscillator resolution to compensate for low satellite signal strength.

23. The correlator of any of claims 20 to 22, wherein the processor is operable to monitor an acquisition threshold and to dynamically operate the control circuit to control the oscillator resolution responsive to the acquisition threshold.

24. The correlator of claims 18, further comprising a processor operable to dynamically operate the control circuit to configure the pseudorandom noise code generator to be operable with a selected navigation satellite system.

25. The correlator of any of claims 20 to 24, wherein the processor is operable to monitor a correlation threshold and to choose a selected navigation satellite system responsive to the correlation threshold.

26. A method of correlation for navigation satellite systems, the method comprising the steps: receiving a satellite signal; providing an oscillator output signal having an oscillator output frequency from an oscillator in a channel; and controlling the oscillator output frequency and the oscillator resolution.

27. The method of claim 26, wherein the oscillator output frequency and the oscillator resolution are controlled separately.

28. The method of claim 26 or claim 27, wherein the oscillator output frequency and the oscillator resolution are controlled dynamically.

29. The method of any of claims 26 to 28 further comprising the step of outputting a plurality of sampling clock signals from a clock generator.

30. The method of claim 29, wherein the step of controlling the oscillator output frequency comprises the steps of receiving the plurality of sampling clock signals and providing to the oscillator a sampling clock signal selected from the plurality of sampling clock signals.

31 . The method of any of claims 26 to 30 further comprising the step of dynamically generating the oscillator output frequency from a sampling frequency, control signal value and an accumulator register length.

32. The method of any of claims 26 to 31 , wherein the oscillator is a carrier oscillator.

33. The method of any of claims 26 to 31 , wherein the oscillator is a code oscillator.

34. The method of any of claims 26 to 31 , further comprising the step of providing a pair of the oscillator output signals from a pair of the oscillators in the channel, the pair of the oscillators comprising a carrier oscillator and a code oscillator operating in parallel.

35. The method of claim 34, wherein the carrier oscillator and code oscillator are both provided with the sampling frequency by the clock generator.

36. The method of any of claims 26 to 35, wherein the step of controlling the oscillator output frequency comprises the step of providing a clock signal to the oscillator.

37. The method of any of claims 26 to 36, wherein the step of controlling the oscillator resolution comprises the step of dynamically configuring the oscillator resolution by configuring an accumulator register length in the oscillator.

38. The method of any of claims 26 to 37, further comprising the step of selecting frequency bins for acquisition and tracking.

39. The method of any of claims 26 to 38, further comprising the step of operating a plurality of the channels in parallel with each other.

40. The method of claim 39, further comprising the step of switching off unused channels of the plurality of the channels.

42. The method of claim 39 or claim 40, further comprising the step of dynamically controlling the oscillator resolution on an individual basis for each used channel of the plurality of the channels.

43. The method of any of claims 26 to 42, further comprising the step of dynamically configuring a pseudorandom noise code generator to be operable with a selected navigation satellite system.

44. The method of any of claims 26 to 43, further comprising the steps of monitoring the satellite signal strength and dynamically controlling the oscillator resolution responsive to the signal strength.

45. The method of claim 44, further comprising the step of dynamically increasing the oscillator resolution to compensate for low satellite signal strength.

46. The method of any of claims 26 to 45, further comprising the steps of monitoring an acquisition threshold and dynamically controlling the oscillator resolution responsive to the acquisition threshold.

47. The method of any of claims 26 to 46, further comprising the steps of monitoring a correlation threshold and choosing a selected navigation satellite system responsive to the correlation threshold.