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WO2008155803A1 - 複数のスレッドを同時に処理する演算装置 - Google Patents

複数のスレッドを同時に処理する演算装置 Download PDF

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Publication number
WO2008155803A1
WO2008155803A1 PCT/JP2007/000661 JP2007000661W WO2008155803A1 WO 2008155803 A1 WO2008155803 A1 WO 2008155803A1 JP 2007000661 W JP2007000661 W JP 2007000661W WO 2008155803 A1 WO2008155803 A1 WO 2008155803A1
Authority
WO
WIPO (PCT)
Prior art keywords
threads
arithmetic device
execution
concurrently processing
instructions
Prior art date
Application number
PCT/JP2007/000661
Other languages
English (en)
French (fr)
Inventor
Norihito Gomyo
Ryuichi Sunayama
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to KR1020097026080A priority Critical patent/KR101031558B1/ko
Priority to JP2009520144A priority patent/JP5099132B2/ja
Priority to PCT/JP2007/000661 priority patent/WO2008155803A1/ja
Priority to CN2007800533574A priority patent/CN101681285B/zh
Priority to EP07790187A priority patent/EP2169553B1/en
Publication of WO2008155803A1 publication Critical patent/WO2008155803A1/ja
Priority to US12/633,840 priority patent/US8516303B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Retry When Errors Occur (AREA)
  • Advance Control (AREA)

Abstract

　単一スレッドの命令列を処理するプロセッサと同等のリトライ成功率を実現する複数スレッドの命令列を同時に処理できるプロセッサを提供するために、演算装置２００に、複数のスレッドを実行する命令実行回路２０１と、各スレッドについての実行状態や再実行を制御する実行制御回路２０２と、を備える。
PCT/JP2007/000661 2007-06-20 2007-06-20 複数のスレッドを同時に処理する演算装置 WO2008155803A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020097026080A KR101031558B1 (ko) 2007-06-20 2007-06-20 복수의 스레드를 동시에 처리하는 연산장치
JP2009520144A JP5099132B2 (ja) 2007-06-20 2007-06-20 複数のスレッドを同時に処理する演算装置
PCT/JP2007/000661 WO2008155803A1 (ja) 2007-06-20 2007-06-20 複数のスレッドを同時に処理する演算装置
CN2007800533574A CN101681285B (zh) 2007-06-20 2007-06-20 同时处理多个线程的运算装置
EP07790187A EP2169553B1 (en) 2007-06-20 2007-06-20 Arithmetic device for concurrently processing a plurality of threads
US12/633,840 US8516303B2 (en) 2007-06-20 2009-12-09 Arithmetic device for concurrently processing a plurality of threads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000661 WO2008155803A1 (ja) 2007-06-20 2007-06-20 複数のスレッドを同時に処理する演算装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/633,840 Continuation US8516303B2 (en) 2007-06-20 2009-12-09 Arithmetic device for concurrently processing a plurality of threads

Publications (1)

Publication Number Publication Date
WO2008155803A1 true WO2008155803A1 (ja) 2008-12-24

Family

ID=40155968

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000661 WO2008155803A1 (ja) 2007-06-20 2007-06-20 複数のスレッドを同時に処理する演算装置

Country Status (6)

Country Link
US (1) US8516303B2 (ja)
EP (1) EP2169553B1 (ja)
JP (1) JP5099132B2 (ja)
KR (1) KR101031558B1 (ja)
CN (1) CN101681285B (ja)
WO (1) WO2008155803A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11372712B2 (en) 2018-11-26 2022-06-28 Fujitsu Limited Processing device and method of controlling processing device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2869202A1 (en) * 2013-11-04 2015-05-06 Universiteit Twente Functional unit for a processor
JP6781089B2 (ja) * 2017-03-28 2020-11-04 日立オートモティブシステムズ株式会社 電子制御装置、電子制御システム、電子制御装置の制御方法
US10922203B1 (en) * 2018-09-21 2021-02-16 Nvidia Corporation Fault injection architecture for resilient GPU computing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154047A (ja) * 1982-03-08 1983-09-13 Hitachi Ltd 端末装置
JPS634339A (ja) * 1986-06-25 1988-01-09 Hitachi Ltd タスク管理方式
JPH07141176A (ja) * 1993-11-19 1995-06-02 Fujitsu Ltd コマンドリトライ制御方式

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154026A (ja) * 1982-03-08 1983-09-13 Hitachi Ltd 情報処理装置のエラ−処理方式
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US6854051B2 (en) * 2000-04-19 2005-02-08 Hewlett-Packard Development Company, L.P. Cycle count replication in a simultaneous and redundantly threaded processor
US7822950B1 (en) * 2003-01-22 2010-10-26 Ubicom, Inc. Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls
US7219185B2 (en) * 2004-04-22 2007-05-15 International Business Machines Corporation Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
JP4486434B2 (ja) * 2004-07-29 2010-06-23 富士通株式会社 命令リトライ検証機能付き情報処理装置および命令リトライ検証方法
US7467325B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Processor instruction retry recovery
US20060184771A1 (en) * 2005-02-11 2006-08-17 International Business Machines Mini-refresh processor recovery as bug workaround method using existing recovery hardware

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154047A (ja) * 1982-03-08 1983-09-13 Hitachi Ltd 端末装置
JPS634339A (ja) * 1986-06-25 1988-01-09 Hitachi Ltd タスク管理方式
JPH07141176A (ja) * 1993-11-19 1995-06-02 Fujitsu Ltd コマンドリトライ制御方式

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2169553A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11372712B2 (en) 2018-11-26 2022-06-28 Fujitsu Limited Processing device and method of controlling processing device

Also Published As

Publication number Publication date
EP2169553A1 (en) 2010-03-31
JPWO2008155803A1 (ja) 2010-08-26
EP2169553B1 (en) 2012-05-16
CN101681285B (zh) 2012-07-25
EP2169553A4 (en) 2011-05-04
CN101681285A (zh) 2010-03-24
US8516303B2 (en) 2013-08-20
US20100088544A1 (en) 2010-04-08
JP5099132B2 (ja) 2012-12-12
KR101031558B1 (ko) 2011-04-27
KR20100021455A (ko) 2010-02-24

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