WO2008029956A1 - Semiconductor integrated circuit device, and wire forming method - Google Patents

Abstract

Provided is a semiconductor integrated circuit device, in which a 3IP(isopropyl-radical)-3V(vinyl-radical)-cyclohexane (OCS) film (20) to appear simultaneously with a copper wiring layer (7) is used, as a film to be formed between copper wires, when the wiring layer is formed. The semiconductor integrated circuit device is characterized by using a barrier property of the OCS film against a copper ion drift. The wire is formed by forming a conductive layer containing copper over an insulating film (4), by patterning the conductive layer to form wires, by forming the OCS film at least between the wires, and by laminating another insulating film on the surface. Alternatively, the wire is formed by forming wiring pattern grooves in an insulating layer having the OCS film on the surface, by forming a conductive layer containing copper, by burying by the Damascene or etch-back method using the OCS film for a terminal detection, and by forming another insulating film on the surface.

Description

 Description Semiconductor integrated circuit device and wiring formation method Technical Field

 The present invention relates to a semiconductor integrated circuit device capable of suppressing a leakage current between wirings, which is a problem when using fine wiring containing copper, and a wiring forming method for realizing wiring of the semiconductor integrated circuit device. . Background art

 Copper wiring or wiring using a conductor layer containing copper is often used in recent ultra-LS I semiconductor devices because of its low resistivity and excellent resistance to electromigration. This low wiring resistance and high migration resistance are reflected in the realization of high-speed operation. In addition, the wiring is filled with an insulating film having a low dielectric constant for higher speed operation, and a combination of a copper wiring and a low dielectric constant film such as porous silica is widely used.

 In order to prevent such diffusion of copper atoms (or ions), a porous Si Si OCH film (relative permittivity k) having a low relative dielectric constant as a wiring interlayer insulating film of the next generation high-density integrated circuit. = 2. 4) has already been proposed. It is assumed that this film is used in combination with a copper wiring having a low wiring resistance as described above and used in a multilayer wiring structure. In addition, tetramethylcyclotetrasiloxane and 6-membered ring vinylsiloxane are known as raw materials for forming such a wiring interlayer insulating film.

In manufacturing the semiconductor device ω, in order to reduce the parasitic capacitance in the wiring portion, in addition to the porous SiOGH described above, porous silica into which meso-sized holes are introduced, porous SiLK (registered trademark), and the like are used. The above-mentioned 亍 tramethylcyclotetrasiloxane (TMCTS) is also used as a raw material for borophosphosilicate glass (BPSG) and phosphosilicate gate glass (PSG). TMCTS is the next generation with Limethyl Phosphite (TMP) and Trimethyl Bora (TMB) Used for BPSG and PSG films.

 As a disadvantage, when miniaturization is advanced by combining such copper wiring and a low dielectric constant film, copper atoms (or ions) diffuse into the insulating film between the wiring, and the wiring It is known that there is a problem that the insulation characteristics between them deteriorate. Such diffusion is received every time a thermal process is performed in the manufacturing process, but it is well known that electric field diffusion occurs in the part where an electric field is applied even after the product is manufactured.

 Patent Document 1 (Japanese Laid-Open Patent Publication No. 2 00 2-3 3 4 8 7 2) discloses an organic-inorganic hybrid film having a main chain in which a part made of siloxane and a part made of an organic molecule are alternately bonded. Is used to prevent copper, which is a wiring material, from diffusing into the interlayer insulating film.

 This technology uses the appearance of barrier properties by the mechanism that copper ions are trapped in the siloxane part due to the magnitude of the interaction between copper ions and siloxane or organic molecules. In addition, the organic molecules play the role of connecting the siloxanes, which has the effect of being reduced in density by the organic molecules.

 In contrast to the above-mentioned Patent Document 1, in the present invention, as described later, the siloxane portion and the copper are spatially separated and shielded by increasing the potential required for diffusion to prevent copper ionization. With this, barrier properties are developed. Since cyclic siloxane is used, it is not necessary to connect the siloxanes with organic molecules as described above, and the low density is still maintained.

Patent Document 2 (Japanese Patent Laid-Open No. 2 0 0 5-4 5 0 5 8) describes S i R ¹ _x R ² _y R ³ _z R ⁴ ₄ _ _{(x + y + Z} ) (silane This is an insulating film made of gas, and any one of R 1−R 4 has a π electron (that is, has a double bond or triple bond). Since the silicon compound obtained by decomposing or reacting this gas has a copper ion diffusion barrier property, this barrier property is used.

 The disclosure of Patent Document 2 is different from the present invention in that it includes a silane derivative having negative electrons.

 When miniaturization is promoted by a combination of the copper wiring and the low relative dielectric constant film as described above, there is a problem that the insulating characteristics between the wirings are deteriorated.

By controlling the molecular weight of the organic side chain of the siloxane moiety, the inventors of the present invention It was discovered that the silica skeleton and copper can be spatially separated to suppress copper ionization, and as a result, a function to suppress copper ion drift can be added to the insulating film itself.

 The present invention is capable of suppressing the problem of deterioration of insulation characteristics between wirings caused by diffusion of copper atoms (or ions) in an insulating film between wirings, and wiring of the semiconductor integrated circuit device. An object of the present invention is to provide a wiring forming method for realizing the above. Disclosure of the invention

 The present invention is a semiconductor integrated circuit device formed on a semiconductor substrate, comprising: a wiring formed from a conductive layer containing copper; and an insulating film provided between the wirings, wherein the insulating film is This is an insulating film that contains 3 IP 3 V-cyclosiloxane film that is exposed at the same time as at least a part of the wiring layer in the middle of the manufacturing process, and suppresses the diffusion of copper that occurs between the wirings in the thermal process of the manufacturing process. The above 3 IP 3 V-cyclosiloxane film is provided to improve the reliability of high-density integrated circuits.

 Further, the reliability can be further improved by contacting the wiring and the 3 I P 3 V-cyclosiloxane film through a barrier metal.

 The wiring structure of such a semiconductor device includes a step of forming a wiring / turn groove in an insulating layer having a 3 IP 3 V-cyclosiloxane film on a flat semiconductor substrate, and a conductive Λ layer containing a copper component. Using the damascene process or an etch back process, removing the conductive layer in a portion other than the groove, and exposing the 3 IP 3 V-cyclosiloxane film, and An insulating film can be formed on the surface, and a wiring process including:

 The conductive layer containing a copper component includes a conductive layer in which a metal layer containing a copper component is formed on a barrier metal layer.

The wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer to form a wiring, and 3 It can be formed by a forming method including: a step of forming an IP 3 V-cyclosiloxane film at least between wirings; and a step of forming another insulating film on the surface. The wiring of the semiconductor integrated circuit device includes a step of forming a conductive layer containing a copper component on an insulating film on a flat semiconductor substrate, a step of patterning the conductive layer, and forming a wiring. Forming a barrier metal layer on at least the side wall of the wiring, forming a 3 IP 3 V-cyclosiloxane film at least between the wirings, and forming another insulating film on the surface. Can be formed. Brief Description of Drawings

 Figures 1 (a), (b), (c), (d), and (e) show the manufacturing process of a semiconductor integrated circuit device.

 FIG. 2 is an example of a cross-sectional view for explaining an integrated circuit to which the present invention is applied.

 3 (a), (b), (c), (d), (e), and (f) are cross-sectional views showing the manufacturing process of the present invention.

 Figures 4 (a) and 4 (b) are diagrams showing the measurement results of the cumulative failure rate of the M IS structure element.

 FIG. 5 is a schematic diagram showing a cross-sectional structure of a measurement sample for measuring the MTF characteristic of an MIS structure element.

 Figures 6 (a), (b), and (c) show the measurement results for the flat band shift.

 FIG. 7 is a diagram showing the measurement results of the MTF characteristics of the MIS structure element.

 FIG. 8 is a graph showing the measurement results of the film thickness dependence of the MTF characteristics of the MIS structure element. BEST MODE FOR CARRYING OUT THE INVENTION

 Embodiments of the present invention will be described in detail with reference to the drawings. In the following description, devices having the same function or similar functions are denoted by the same reference numerals unless there is a special reason.

As described above, the inventors of the present invention control the molecular weight of the organic side chain of the siloxane part to spatially shield between the silica skeleton and copper, thereby suppressing the ionization of copper. We have found that it is possible to add a function of suppressing copper ion drift to the insulating film itself. In other words, when an insulating film is formed by plasma polymerization, Since it has a sun skeleton, 3 IP 3 V-cyclosiloxane with isopropyl group (IP) and vinyl group (V) from each silicon does not allow copper ions to penetrate into the film. On the other hand, MS Q (methylsilsesquioxane) having a methyl group as an organic side chain and S i OC (DMDMOS:

In S i OC) formed by plasma CV D using dimethyldimetoxysilane as a starting material, the molecular structure of the raw material is rarely partially retained, and the barrier property is not seen or extremely small. That is, barrier properties are exhibited when the organic side chain has 2 or more carbon atoms. The chemical bond of these carbon atoms may be a single bond, a double bond, or a triple bond. In the case of a single bond, spatial shielding can be expected, and in the case of multiple bonds, in addition to that, electrical shielding can be expected. In addition, although a cyclic siloxane is taken as an example here, even if the ring is opened, the same effect can be expected when the shielding effect by the organic side chain is present, so that it is not necessarily limited to being cyclic.

 In addition, Cu-MIS (metal alloy using copper as the metal electrode) prepared using cyclic siloxane with organic side chains (3 I P3V—cyclosiloxane; hereinafter also referred to as OCS: Organo-Cyclo-Siloxane). The experimental results for the (insulator-semiconductor) structure are shown in Figs. 4 (a) and 4 (b).

From the results in Fig. 4 (a), it can be seen that the breakdown time is the same for 3 IP 3 V-cyclosiloxane when E> 0 and E <0 are applied. On the other hand, as shown in Fig. 4 (b), S i 0 ₂ (CVD (chemical vapor deposition) film using monosilane and laughing gas) and S i OC (CVD film using DMDMOS) The dielectric breakdown time when E> 0 is applied is short. This is due to the electric field drift of copper ions in the film with an electric field of E> 0 in S i 0 ₂ and S i OC. This means that copper ions cannot drift inside the 3 I P3V-cyclosiloxane, that is, 3 IP 3 V-cyclosiloxane itself has a barrier property. In addition, 3 IP 3 V-cyclosiloxane has a lifetime that is almost an order of magnitude longer than that of SioC under the same measurement conditions. As described above, it can be seen that the electric field drift of copper ions into the 3 IP 3 V-cyclosiloxane film is suppressed. This is because the vinyl group and isopropyl group contained in 3 I P3V-cyclosiloxane are the copper part contained in the electrode and the silica part contained in the film structure. This is thought to be because copper ionization is suppressed by spatially or electrically shielding the copper. Electrical shielding is surplus electrons generated by double and triple bonds

This means that (π electrons) are donated to ionized copper and become neutralized. Spatial shielding prevents copper ionization and ionization for some reason such as lattice defects However, it can be predicted that it can be restored by electrical shielding. In other words, this indicates that an insulating film having a barrier property against copper ion drift can be realized by shielding the silica skeleton (especially oxygen atoms) with an organic side chain. In addition, in the above sense, spatial or electrical shielding depends on the length of the organic side chain (which can be paraphrased as the molecular weight), so it is necessary to optimize the length. It can be predicted that it is possible to optimize the rebarrier property. In other words, by controlling the molecular weight of the organic side chain, it is possible to spatially shield between the silica skeleton and copper and suppress ionization to become copper ions, and as a result, to suppress the copper ion drift number. Can be predicted.

 The above interpretation is correct because MSQ with a cyclic S i 1 o skeleton and organic side chain (methyl group) and S OC (DMDMO S) with a methyl group in the S i — O network have barrier properties. Is seen (or very small) force It can be seen from the fact that 3 I Ρ 3 V-cyclosiloxane with isopropyl and vinyl groups cannot penetrate copper ions into the film.

 First, Fig. 6 (a) shows the measurement results of the flat band shift of the 3 I P 3 V-cyclosiloxane (OC S) M I S structure with a Cu electrode. The MOS capacitor used for the measurement is CuZOCS (200 nm) i O 2 (30 nm) S i M

It is an IS structure. This measurement result is sufficiently small compared to the case of MSQ in Fig. 6 (b). Furthermore, as shown in Fig. 6 (c), even when the electric field strength is measured as high as 1 MVZcm, the flat band shift is negligible, which prevents the copper ions from entering the 3 1 P3 V-cyclosiloxane. It turns out that there is an effect.

Next, Fig. 7 shows the applied electric field dependence of the mean time (MTF) required for a measurement sample having the cross-sectional structure shown in Fig. 5 to reach dielectric breakdown. In the figure, Po-S i 0 ₂ is porous (polyporous) silicon oxide film (1 38 nm), OCS is 3 IP 3 V—cyclosiloxane (0 to 800), B CB is benzocyclopolymerized in plasma Butene (benzocyclobutene). The thickness of the silicon thermal oxide film is 30 nm. For OC S and BCB, an electric field is applied in which the copper electrode has a positive voltage. Figure 7 Force, et al. 3 IP 3 V— Even when the film thickness of chlorosiloxane is as thin as 30 nm, it can be seen that this film has a great effect of suppressing dielectric breakdown.

 FIG. 8 is a graph showing the dependence of MTF on the film thickness of the measurement sample having the structure of FIG.

In the case of OCS, measurements were made for none, 30 and 80 nm, but it can be seen that even when the OCS film thickness is 30 nm, the lifetime is two orders of magnitude longer than that without. In addition, when the electric field dependence data when the film thickness of OCS is 30 are applied to the low electric field side, 1 \ 1 cosine is about 10 years (3 X 1 0 ⁸ seconds). In other words, when an OCS film of 30 nm is formed on porous silica, even when an E> 0 electric field drifting copper ions at a high temperature of 200 ° C is applied, 0.41 \ 1 (; It is possible to maintain insulation for 10 years in strength.In addition, since the actual device operating temperature is about 150 ° C at most, under these conditions, 10 years at higher electric field strength. It is clear that reliability is achieved, for example, with a 45 nm pitch wiring (wiring width 25 nm, spacing 20 nm)

Assuming a 1 V power supply voltage, the field strength greatly exceeds 0.2 MVZcm, indicating that the actual wiring life is even longer.

By using an insulating film having a copper ion drift function as an interlayer insulating film of a semiconductor integrated circuit device or as a side wall with respect to an ordinary interlayer insulating film such as porous silica, an in-plane wiring that does not require a barrier metal It can be used to reinforce weak spots due to the formation of pinholes and pinholes generated in ultrathin barrier metals. In addition, as a countermeasure against leakage current at the same level as the upper surface of the wiring, and CMP (Chemical Mechanical Polishing) used for the embedding process when the wiring is embedded / turned in the groove pattern by the damascene process or the etch knock process. It can also be used as a stopper layer for anisotropic etching processes, and can also be used as a diffusion barrier for diffusion channels formed at the interface with an insulating film formed when an insulating film is formed. . In addition, as the above-mentioned stubber layer, there is no necessity to use the insulating film having the steel ion drift function described above, and a layer that exhibits good selectivity in CMP or anisotropic etching process is used. It is obvious that the insulating film having the copper ion drift function may be provided in the lower layer.

 Furthermore, the insulating film used in the present invention can also be used as a copper ion diffusion barrier on the wiring or at the CMP interface. Conventionally, Si CN having a diffusion barrier property is often used for this part, but in the present invention, by using an insulating film having a diffusion barrier property of a low dielectric constant film, the capacitance between wirings can be reduced. It is possible to reduce the copper ion drift at the interface with the heterogeneous film.

 FIG. 1 is a cross-sectional view illustrating an integrated circuit to which the present invention is applied. Fig. 1 shows a wiring structure that blocks the diffusion of copper ions in the lateral direction by providing a side wall that has barrier properties in parallel with the side wall of the barrier metal, and shows a part of the manufacturing process. Here, in order to avoid complicated explanation, a simple wiring structure is used, but it is apparent that the present invention can be applied to a more complicated wiring structure.

 In FIG. 1 (a), a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (film thickness 20-30 nm) is formed as an etching stopper layer 3 by a CVD (chemical vapor deposition) process. An interlayer insulating film 4 (film thickness: 100 to 150 nm) and a low dielectric constant cap layer 5 (film thickness of about 20 nm) are stacked on the etching stubber layer 3 to form a trench pattern for wiring. The film is formed by a process, and a film 20 (film thickness of 30 nm or less) such as a 3 I P3V-cyclosiloxane film or BCB film having a copper ion barrier property is laminated, and anisotropic etching is performed to form a sidewall.

In FIG. 1 (b), a barrier metal layer 6 (thickness of 10 nm or less) is further laminated, and anisotropic etching is performed to form sidewalls. As a result, a side wall is formed in which the barrier film and the copper ion barrier film are parallel to each other. In FIG. 1 (c), a wiring layer 7 containing copper is laminated, and a buried copper wiring as shown in FIG. 1 (d) is formed by a CMP process or an etching process. At this time, a film 20 such as a 3 IP 3 V-cyclosiloxane film or a BCB film having a barrier property of copper ions is used for detecting the end point of the CMP process or used as a stutter layer for anisotropic etching. Thereafter, a dielectric barrier layer 8 is provided. In FIG. 1 (e), the interlayer insulating film 21 and the plug are further shown on the assumption that the semiconductor device has a multilayer wiring having a wiring layer as an upper layer. In this manufacturing process, for example, an interlayer insulating film 21 is attached, a via hole is formed by etching, and a film 11 having a barrier property is formed on the sidewall of the via hole. This can be formed in the same manner as the sidewall of the barrier metal layer 6 described above, and then the plug layer 12 is formed and embedded.

 FIG. 2 is a cross-sectional view for explaining an integrated circuit to which the present invention is applied. Here, in order to avoid complicated explanation, a simple wiring structure is used. However, it is obvious that the present invention can be applied to a more complicated wiring structure. The cross-sectional structure of FIG. 2 will be described by dividing it into a semiconductor substrate 1, a transistor layer 2, and a multilayer wiring layer. The transistor layer in FIG. 2 includes a diffusion layer that forms a transistor, a gate electrode, a source electrode, and a drain electrode of the transistor, electrodes that supply voltage and current to them, and an interlayer insulating film that insulates each electrode. Is arranged. Although the present invention mainly relates to a wiring layer, the wiring layer has a layer wiring structure in which an aluminum wiring layer and two copper wiring layers are connected by a plug. The copper wiring is in contact with the interlayer insulation film through the barrier metal. In addition, an insulating layer that blocks the diffusion of copper ions is arranged at the same height as the surface of the copper wiring layer. This structure is described below with reference to FIG. FIG. 3 is a diagram illustrating an example of a manufacturing process for forming a wiring layer. Copper wiring is formed by a method known as the damascene process. FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene. In general, a part of the semiconductor manufacturing process can be easily substituted with another manufacturing process, and in the present invention, there is no reason to limit to the following processes.

 In FIG. 3A, a transistor layer 2 is formed on a semiconductor substrate 1, and a silicon nitride film (thickness 20 to 30 nm) is formed as an etching stopper layer 3 by a CVD process. On the etching stopper layer 3, an interlayer insulating film 4 (fl thick 10 0 to 15 0 η m) and a low dielectric constant cap layer 5 (film thickness of about 20 nm) are laminated, and a trench pattern for wiring The barrier metal layer 6 (thickness of 10 nm or less) is laminated.

In FIG. 3 (b), next, anisotropic etching is performed to form the barrier metal layer 6. After forming the wall, the copper wiring layer 7 is formed. A CMP (Chemical Mechanical Polishing) process is used to embed the copper wiring layer in the wiring trench pattern, similar to the usual damascene process. At this time, the low dielectric constant cap layer 5 is used for end point detection. Here, the copper wiring layer is a conductive layer containing copper as a main component. In this wiring process, after forming the rear metal layer 6, the copper wiring layer 7 can be formed without performing anisotropic etching, and then buried by a CMP process. Next, in FIG. 3 (c), the dielectric barrier layer 8, the via interlayer insulating film layer 9 (film thickness 150 to 300 nm) and the etching stopper layer 10 (film thickness 20 to 30 nm) are formed. Then, a via hole is formed by a photolithography process, and a sidewall is formed with a film 11 having a barrier property such as a 3 I P3V-cyclosiloxane film or a BCB film (film thickness of 3 O nm or less), and a plug layer 1 2 is formed. Laminated and anisotropically etched to form plugs.

 Next, in FIG. 3 (d), an interlayer insulating film 13 and an etching stopper layer 14 (thickness 20-30 nm) are stacked, and a trench pattern for wiring is formed by a photolithography process, and the barrier metal layer 1 After stacking 5 (thickness 1 O nm or less), anisotropic etching is performed to form a barrier metal layer 15 (thickness 1 O nm or less) side wall.

 In FIG. 3 (e), a copper wiring layer 16 is formed next, and the copper wiring layer is buried in the wiring groove pattern by the damascene process in the same manner as described above. As described above, FIG. 3 shows an example of a single damascene, but the present invention can be similarly applied to a dual damascene. The thickness of the copper wiring layer varies depending on the current to be applied. In order to obtain a wiring of about 500 to 1 GOO nm after embedding, a copper wiring layer of about 1 to 3 m before the CMP process 1 6 Form.

 In the wiring process shown in FIGS. 3 (d) and 3 (e), after forming the barrier metal layer 15 and forming the copper wiring layer 16 without performing anisotropic etching, as described above, You can also embed by CMP process.

FIG. 3 (f) shows a semiconductor integrated circuit device in which a low dielectric constant insulating film 17 and a protective film 18 are provided on the formed copper wiring layer 16. Industrial applicability

 When copper ions are blocked using the insulating film as described above, for example, a film in which copper ion diffusion occurs can be used as an interlayer insulating film, and the choice of a low dielectric constant film can be expanded. It can also be used as a pore seal (side wall) for ultra-low dielectric constant interlayer insulating films such as porous silica. For example, in the case where the distance between wirings is 0.6 microns, if the 30 nm film in the above example is used, 90% of the insulating film between the wirings and this ultra low dielectric constant interlayer insulating film other than the pore seal And parasitic capacitance between wires can be suppressed. At this time, the insulating film that blocks the copper ions in any case is caused by a pinhole generated when a barrier metal-free wiring structure or an extremely thin / rear metal wiring structure is used. It has the effect of reinforcing the wakespot and can improve the reliability of semiconductor devices.

Claims

Scope of request A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:

Wiring formed from a conductive layer containing copper;

An insulating film provided between the wirings of the wiring, and

The insulating film includes a 3 IP 3 V-cyclosiloxane film that is exposed at the same time as at least a part of the wiring layer during the manufacturing process, and is an insulating film that suppresses copper diffusion that occurs between the wirings. A semiconductor integrated circuit device.

2. The semiconductor integrated circuit device according to claim 1, wherein the wiring and the 3 I P 3 V-cyclosiloxane film are in contact with each other through a barrier metal. A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,

 When forming the wiring of the semiconductor integrated circuit device,

On a flat semiconductor substrate,

Forming a wiring pattern groove in an insulating layer having a 3 I P 3 V-cyclosiloxane film on the surface;

Forming a conductive layer containing a copper component;

Using the damascene process to remove the conductive layer in a portion other than the groove, and simultaneously exposing the 3 IP 3 V-cyclosiloxane film, and forming another insulating film on the surface;

A wiring forming method comprising:

4. The wiring forming method according to claim 3, wherein the conductive layer containing a copper component is a conductive layer in which a metal layer containing a copper component is formed on a barrier metal layer. A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,

 When forming the wiring of the semiconductor integrated circuit device,

On a flat semiconductor substrate,

Forming a conductive layer containing a copper component on the insulating film;

Patterning the conductive layer to form a wiring; 3 a step of forming an IP 3 V-cyclosiloxane film at least between the wirings, a step of forming another insulating film on the surface,

A wiring forming method comprising:

A method of forming a wiring in manufacturing a semiconductor integrated circuit device according to claim 1 or 2,

 When forming the wiring of the semiconductor integrated circuit device,

On a flat semiconductor substrate,

Forming a conductive layer containing a copper component on the insulating film;

Patterning the conductive layer to form a wiring;

Forming a barrier metal layer on at least the sidewall of the wiring;

 A step of forming a 3 I P 3 V-cyclosiloxane film at least between the wirings, a step of forming another insulating film on the surface,

A wiring forming method comprising: