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WO2008091343A1 - Procédés de fabrication de structures semi-conductrices - Google Patents

Procédés de fabrication de structures semi-conductrices Download PDF

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Publication number
WO2008091343A1
WO2008091343A1 PCT/US2007/060865 US2007060865W WO2008091343A1 WO 2008091343 A1 WO2008091343 A1 WO 2008091343A1 US 2007060865 W US2007060865 W US 2007060865W WO 2008091343 A1 WO2008091343 A1 WO 2008091343A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
substrate
etched
etch
Prior art date
Application number
PCT/US2007/060865
Other languages
English (en)
Inventor
Shuji Ikeda
Jeff Wetzel
James V. Beach
Charles Stager
Michael Gotskowski
Andrew Collin Campbell
Original Assignee
Atdf, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atdf, Inc. filed Critical Atdf, Inc.
Priority to PCT/US2007/060865 priority Critical patent/WO2008091343A1/fr
Publication of WO2008091343A1 publication Critical patent/WO2008091343A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present invention relates generally to semiconductor fabrication, and more particularly to a method for defining structures using a combination of spacers and optical lithography.
  • lithographic techniques In the field of the fabrication of semiconductor structures, for example during the production of integrated circuits based on semiconductor . wafers, a large number of the devices on the wafers are fabricated using lithographic techniques.
  • the lithographic techniques often employ masks or mask structures for the patterning and production of the semiconductor structures in subsequent process steps.
  • the mask or mask structures are generally produced so that the patterns are true to size, in correct positions and orientation, and without defects.
  • an image of the pattern is projected onto a photosensitive material coating on a wafer.
  • the image pattern may be either a positive or negative mask image thatis projected onto the coated wafer using an optical lithography system.
  • the optical lithography system emits radiation at a wavelength ⁇ which chemically changes the exposed areas of the coating, usually by polymerizing the coating exposed to the radiation. Depending on the solvent used, the unpolymerized areas are removed, and the desired pattern image remains.
  • Typical optical lithography systems such as steppers, may use radiation at wavelengths such as 365 nm, 248 nm, 193 nm, 157 nm, and 126 nm.
  • 193 nm steppers are commercially available for volume manufacturing, while steppers using 157 nm and 126 nm wavelengths are still being developed.
  • Advanced non-optical lithography systems with shorter wavelengths such as extreme ultraviolet or soft x-rays are now being actively researched for printing complex patterns in submicron ranges.
  • the problem of diffraction limited optics remains, and the drive to using shorter wavelengths provides only limited results.
  • phase-shifting masks to increase the resolution and contrast of optical lithography.
  • Light rays transmitted through adjacent apertures of the mask follow different phases.
  • phase-shifting masks are costly and difficult to manufacture because the phase structure must be closely related to specific geometries of the mask pattern.
  • engineered illumination to help print smaller and smaller features of semiconductor microcircuits. This technique relies upon the use of various patterns of illumination including annular and quadrapole illumination and off-axis illumination. However, these require that the illuminator be extensively modified. Additionally, these methods and assist features are time consuming, expensive, and less efficient.
  • EUV extreme ultraviolet
  • SCALPEL e-beam
  • the disclosure involves methods for fabricating semiconductor structures, including, but not limited to, a MOS structure, a RAM structure, a resistor, a comb structure, a bent structure, a line structure, CD changed structure, a T-structure, an electrically testable structure, and the like.
  • the method may include providing a substrate and depositing a first layer on the substrate followed by the depositing of a second layer on the first layer. A plurality of line structures may be etched into the second layer. Next, a third layer may be deposited on the etched second layer and subsequently etched. The etching of the third layer may expose a portion of the etched second layer. The exposed portion of the second layer may subsequently be removed. The etched third layer may be used as a mask to etch the first layer to form a semiconductor structure in the first layer.
  • the method may also include etching of the substrate, where the first layer may be used a mask.
  • the substrate may subsequently be annealed, in for example, a hydrogen atmosphere, to form a corrugated substrate surface.
  • Another material layer may be deposited on the substrate surface to form a channel of a device such as, but not limited to, a field effect transistor, a multi-gate field effect transistor, a fin field effect transistor, a tri-gate transistor, a FI transistor, a ⁇ transistor channel, or other suitable semiconductor devices.
  • the channel may be perpendicular to the corrugated surface or alternatively, may be parallel to the corrugated surface.
  • Coupled is defined as connected, although not necessarily directly, and not necessarily mechanically.
  • substantially refers to ranges within 10%, preferably within 5%, more preferably within 1%, and most preferably within 0.5% of what is specified.
  • FIGs. 1 through 9 are steps for fabricating a pattern, in accordance with embodiments of the present disclosure.
  • FIGs. 10 through 21 are steps for fabricating a non-planar substrate surface, in accordance with embodiments of the present disclosure.
  • FIG. 22 is a structure having a channel parallel to the corrugation of a substrate surface, in accordance with embodiments of the present disclosure.
  • FIG. 23 is a structure having a channel perpendicular to the corrugation of a substrate surface, in accordance with embodiments of the present disclosure.
  • FIG. 24A is an inverter layout on a conventional substrate having a substantially planar surface, in accordance with embodiments of the present disclosure.
  • FIG. 24B is an inverter layout on a non-planar substrate surface, in accordance with embodiments of the present disclosure.
  • FIG. 25A is a SRAM cell layout on a conventional substrate having a substantially planar surface, in accordance with embodiments of the present disclosure.
  • FIG. 25B is a SRAM cell layout on a non-planar substrate surface, in accordance with embodiments of the present disclosure.
  • FIGs. 26A and 26B are steps for fabricating a bent or crank semiconductor structures, in accordance with embodiments of the present disclosure.
  • FIG. 27 are steps for fabricating bi-directional semiconductors line structure, in accordance with embodiments of the present disclosure.
  • FIG. 28 are steps for fabricating CD changed semiconductor structures, in accordance with embodiments of the present disclosure.
  • FIG. 29 are steps for fabricating semiconductor line structures, in accordance with embodiments of the present disclosure.
  • FIGs. 3OA through 3OE are steps for fabricating T-structures, in accordance with embodiments of the present disclosure.
  • FIG. 31A is an initial pattern used for fabricating an electrically testable line, in accordance with embodiments of the present disclosure.
  • FIG. 31B are steps for fabricating the electrically testable line of FIG. 3 IA, in accordance with embodiments of the present disclosure.
  • FIG. 32A is an initial pattern used for fabricating a testable isolated comb structure, in accordance with embodiments of the present disclosure.
  • FIGs. 32B are steps for fabricating the comb structure of FIG. 32A, in accordance with embodiments of the present disclosure.
  • FIG. 33 are steps for fabricating the resistor structure, in accordance with embodiments of the present disclosure.
  • FIG. 34A is an initial pattern used for fabricating a testable pitch-quadrupled serpentine, in accordance with embodiments of the present disclosure.
  • FIGs. 34B-D are steps for fabricating testable pitch-quadrupled serpentine of FIG. 34A, in accordance with embodiments of the present disclosure.
  • FIG. 35A is an initial pattern used for fabricating a testable pitch-quadrupled comb, in accordance with embodiments of the present disclosure.
  • FIG. 35B are steps for fabricating testable pitch-quadrupled serpentine of FIG. 35A, in accordance with embodiments of the present disclosure.
  • the present disclosure provides fabrication techniques combining spacer defined patterns and optical lithography for creating semiconductor structures.
  • the techniques provide for patterning a range of different shapes.
  • the present disclosure may provide fabrication techniques for patterning layers coupled to a substrate.
  • the techniques of the present disclosure provide for fabricating non- planar (e.g., corrugated) substrate surfaces.
  • the substrate surface may include, without limitation, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a strained silicon-on-insulator (sSOI) substrate, a silicon-germanium-on-insulator (GOI) substrate, a strained silicon-germanium-on-insulator (sGeOI) substrate, or a silicon on sapphire (SoS) substrate.
  • the non-planar feature may be created by fabricating trenches in the surface of the substrate.
  • the trenches may be at half-pitch or at quarter-pitch, allowing for varying periodicity which may change the length of the channel while minimizing the area of the device.
  • spacer refers to a spacer material applied to polysilicon gates prior to implant in many semiconductor devices. If a conformal film is deposited onto an existing feature followed by an isotropic etch, thin residual sidewalls of the material may be added to the feature. If the original feature is subsequently selectively removed, the sidewall material remains and can be used for further processing. In this technique, smaller features may be made as compared to conventional optical lithography. Spacers may also be used to create a line/space pattern with a very small pitch by building up spacer material on both sides of a line/space pattern in a first layer and subsequently removing the first layer. This process, as defined and used in this disclosure, is referred to as "pitch doubling" because the process results in a line/space pattern that has about half the pitch of the original pattern. Fabricating a Patterned Layer
  • a patterned layer may be used as a mask for subsequent fabrication techniques to define the structures on, for example, semiconductor layers and/or substrates.
  • first layer 102 may be deposited on substrate 100 using techniques known in the art. For example, chemical vapor depositions (CVD) methods, plasma enhanced chemical vapor deposition (PECVD) methods, physical vapor deposition (PVD) methods, and/or sputtering methods may be employed to deposit first layer 102 on substrate 100.
  • CVD chemical vapor depositions
  • PECVD plasma enhanced chemical vapor deposition
  • PVD physical vapor deposition
  • sputtering methods may be employed to deposit first layer 102 on substrate 100.
  • a second layer 104 may be deposited on first layer 102.
  • a number of materials maybe deposited to form layers 102 and 104 depending upon the integration approach.
  • Several of these combinations include for layer 102 (SiO 2 , Si, SiN) with similar materials selected for layer 104 (SiO 2 , Si, SiN).
  • Non-limiting examples of the types materials for first layer 102, second layer 104, third layer 108, and fourth layer 110 are shown in Table 1. It is noted that other materials including, without limitation, metallic layers, insulation layers, silicon layers, and other films may be used in any combination.
  • Table 1 Examples of materials used in. the fabrication of a non-planar surface
  • photoresist layer 106 may be deposited and aligned on second layer 104 and may subsequently be patterned using techniques know in the art.
  • photoresist material 106 may be etched at approximately a 1 :1 line-space dimension using techniques such as exposing the photoresist through a mask with an electromagnetic radiation source at some wavelength, ⁇ .
  • photoresist layer 106 may be etched to other line-to-space dimensions that may be a 1-to-l ratio or other ratios that are appropriate based on the end pattern design.
  • the electromagnetic radiation source includes, but is not limited to, ultraviolet light, infrared sources, and the like. Any portion of photoresist layer 106 that has been exposed to the light may be removed, resulting in a patterned photoresist layer, as shown in FIG. 2.
  • second layer 104 may be etched using techniques such as wet or dry etching methods known in the art.
  • third layer 108 may be deposited onto etched second layer 104, as seen in the step shown in FIG. 4, where the deposition may be a symmetric distribution of third layer 108 around second layer 104.
  • the thickness of third layer 108 may be controlled to a fraction of the wavelength ⁇ , e.g., 0.5 ⁇ .
  • third layer 108 may be conformably deposited over the top of the resulting line and space of the structure shown in
  • third layer 108 may be etched using techniques known in the art.
  • the etching process may be selective to second layer 104 such that a top surface of second layer 104 is exposed.
  • the etching step may result in individual, distinguish region of second layer 104 and third layer 108 with an open space between each distinguished region, as shown in FIG. 5.
  • second layer 104 may be removed. In one embodiment, second layer 104 may be removed using an etchant selective to both third layer 108 and first layer 102.
  • fourth layer 110 may be deposited on the resulting structure from FIG. 6. In some respects, fourth layer 110 may be deposited on the resulting structure shown in FIG. 6 or alternatively, on a portion of the resulting structure shown in FIG. 6 (e.g., selectively masking a portion of third layer 108). In one embodiment, fourth layer 110 may be the same material as second layer 104. Referring to Table 1, some non- limiting examples are presented representing the types of materials that may be used.
  • an etching step using an etchant selective to third layer 108 and first layer 102 may be used to etch fourth layer 110, as shown in FIG. 8.
  • an etchant selective to fourth layer 110 and first layer 102 may be used to remove third layer 108.
  • the resulting pattern, a patterning layer, shown in FIG. 9 may be used to create patterns in layers, such as, for example, first layer 102, and/or substrate 100.
  • etching techniques such as wet etch, dry etch, reactive ion etch, or the like may be used to transfer the pattern to the underlying layers (e.g., layer 102 and/or substrate 100). It is noted that some of the steps shown in FIGs. 1-9 may be optional.
  • steps shown in FIGs. 7-9 may be optional in designs where third layer 108 does not need to be selectively masked.
  • the resulting structure shown in FIG. 6 may be used as a mask to etch first layer 102 and/or substrate 100.
  • the level of device integration increases.
  • features such as contact area, junction depth, and line spaces decrease, causing the fabrication of transistors to be more difficult.
  • the NMOS transistors may be fabricated with a predetermined channel length, generally shorter than conventional devices.
  • short channel effects associated with the reduced size of the transistors may result in the malfunction of the NMOS transistors, and the CMOS memory device as a whole.
  • One conventional technique used to increase the channel length is to form a raised source and drain area using selective epitomical growth.
  • An epitaxy layer can be deposited to achieve a predetermined thickness on a portion of substrate where source and drain junctions are formed.
  • the resultant structure includes a source and drain area set higher than the substrate.
  • the raised source and drain structure can effectively increase the channel length, thereby reducing short channel effects
  • the thickness of the epitaxy layer can also influence the efficacy of the transistor. For example, if the epitaxy layer is too thick, the raised source and drain structure may cause an electrical short between the structure and a gate electrode. Similarly, if the epitaxy layer is too thin, the raised source and drain structure may not be effective enough in reducing the short channel effects
  • the present disclosure provides a fabrication technique to create a non-planar, corrugated surface on substrate 100, using some or all the steps shown in FIGs. 1-9.
  • a trench isolation technique step may be performed on substrate 100, creating trenches 101, as shown in FIG. 10.
  • the trench isolation technique may involve using an etching technique, such as reactive ion etching
  • RIE reactive ion etching
  • CMP chemical mechanical polishing
  • photoresist material 106 may be etched at approximately a 1 :1 line-space dimension using techniques such as exposing the photoresist through a mask with an electromagnetic radiation source at some wavelength, ⁇ .
  • the etching process may include controlling the photoresist critical dimension and trim etch process to etch second layer 104 such that about 0.75 ⁇ of second layer and about 5/4 ⁇ space pattern occur, as shown in FIG. 12.
  • the etching of material 108 may create a spacing of 3/4 ⁇ , as shown in FIG. 14.
  • the subsequent removal of second layer 104 is shown in FIG. 15.
  • fourth layer 110 may be deposited and etched, respectively.
  • fourth layer 110 may be etched using an etchant selective to third layer 108 and first layer 102, creating a space of approximately 1/4 ⁇ (FIG. 17)
  • Third layer 108 may subsequently be removed, leaving fourth layer 110, as shown in FIG. 18.
  • Fourth layer 110 may be used as a patterning layer used to create a pattern in substrate
  • fourth layer 110 may be a 1-to-l mask having one-quarter of the original pitch, may be used as a pattern to etch first layer 102, as seen in the step illustrated by FIG. 19.
  • first layer 102 may be etched to form a 1-to-l, 0.25 ⁇ line to 0.25 ⁇ space ratio.
  • first layer 102 may serve as a mask, or a patterning layer for the etching of substrate 100.
  • first layer may be removed using techniques known in the art.
  • substrate 100 resulting from the step shown in FIG. 20 may be annealed in a hydrogen annealing environment.
  • substrate 100 may be subjected to a hydrogen ambient for about 1 to 60 minutes at a temperature of about 800 0 C to about 1000
  • the resultant structure includes a non-planar, corrugated surface of substrate 100, as shown in FIG. 21
  • the above embodiment is an example of a 1 A line and VA space fabrication used to create a non-planar, corrugated surface on a substrate, although other dimensions are contemplated and may be used.
  • the line spacing techniques of U.S. Patent Serial No. 11/220,898 Filed September 7, 2005 entitled “Methods for Fabricating Sub- Resolution Line Space Patterns,” incorporated in its entirety herein by reference may be used to create a line to space ratio that may be etched into a substrate and subsequently be annealed to create, amongst other things, a non-planar, corrugated substrate using the techniques of the present disclosure.
  • the above embodiment shows a corrugated surface in one layer, e.g., a homogenous material such as the substrate material.
  • the corrugated surface may include multiple layers of different semiconductor and/or dielectric materials.
  • the corrugated surface may include a semiconductor layer formed over a dielectric layer.
  • a device including, without limitation, a metal oxide semiconductor (MOS) device may be fabricated on the non-planar or corrugated substrate surface shown in FIG. 21.
  • MOS metal oxide semiconductor
  • FIG. 21 For examples, techniques described in U.S. Serial No. 11/173,230 filed July 1, 2005 entitled “Method of IC Production Using Corrugated Substrates," U.S. Serial No. 11/173,231 filed My 1, 2005 entitled “Integrated Circuit on Corrugated Substrate,” and U.S. Serial No. 11/173,237 filed July 1, 2005 entitled “Segmented Channel MOS Transistor,” incorporated herein by reference each in their entirety, may be used to fabricate devices on non-planar or corrugated surfaces.
  • the device may have a channel parallel to the non-planar substrate surface similar to the structure with channel 150 shown in FIG. 22.
  • the fabrication of devices on these non- planar or corrugated substrates result in a longer channel length, and thus, a smaller drain to source current (I DS ) when compared to conventional devices fabricated on a substantially planar substrate.
  • I DS drain to source current
  • the current between the drain and the source for a MOS device is inversely proportional to the length of the channel using the following voltage-current relation:
  • ⁇ n is the charge-carrier mobility
  • W is the channel width
  • L is the channel length
  • C ox is the capacitance at the channel
  • V GS is the gate to source voltage
  • V 1/ is the threshold voltage
  • Fas is the drain to source voltage.
  • a device may be fabricated with a channel perpendicular to the non- planar substrate surface, similar to the structure with channel 150 shown in FIG. 23.
  • the structure includes devices that include a wider channel width and a larger I DS (using Eq. 1) as compared to devices fabricated on a substantially planar substrate.
  • the present disclosure also contemplates fabricating other devices on the non-planar substrate surface.
  • the devices may include, without limitation, a field effect transistor (FET), a multi-gate field effect transistor, a fin field effect transistor, a tri-gate transistor, a II transistor, and a ⁇ transistor. More generally, the devices may include any devices having a channel region.
  • FET field effect transistor
  • the present disclosure provides, among other advantages, an increase in channel length while minimizing a reduction in area.
  • FIG. 24A 3 an inverter layout including PMOS region 1500 having a channel 1504 width to length ratio of 1 to 1 (W/L) and NMOS region 1502 having a channel 1504 width to length ratio of 2 to 1 (2W/L) is shown.
  • the inverter of FIG. 24A is a conventional, substantially planar substrate surface.
  • the total area of the inverter of FIG. 24B is about 30% less than the area of the inverter of FIG. 24A.
  • the area of a circuit, such as a static random accessory memory (SRAM) circuit may also benefit from the present disclosure.
  • SRAM static random accessory memory
  • FIGs. 125A and 25B a SRAM circuit layout using conventional substantially substrate is compared to a SRAM circuit layout using the non-planar, corrugated substrate of the present disclosure are shown, respectively.
  • the area of the SRAM of FIG. 25B is approximately 17% less than the SRAM of FIG. 25A.
  • a bent or crank structure may be fabricating using the steps shown in
  • FIGs. 26A and 26B The steps shown in FIGs. 26A and 26B are similar to the steps shown in
  • step 2600 of FIG. 26 A a top- view and a profile view of the structure at line A - A'.
  • the structure shown in step 2600 includes a first layer 2652, second layer 2654, and patterned photoresist layer 2656 deposited on a substrate 2650 is shown.
  • step 2602 the pattern of photoresist layer 2656 may be transferred to second layer
  • Patterned photoresist layer 2656 may be subsequently removed.
  • step 2604 third layer 2658 may be deposited on the resultant structure shown in step 2602.
  • an etching technique e.g., wet or dry etch
  • step 2608 second layer 2654 may be removed.
  • a clipping pattern may be defined, as shown in step 2610.
  • fourth layer 2660 may be deposited on the resultant structure of step 2608, and may be subsequently ⁇ patterned. In some embodiments, fourth layer 2660 may expose a portion of third layer 2658.
  • third layer 2658 may be etched.
  • fourth layer 2658 may be etched.
  • step 2660 may be a masking layer to protect a portion of third layer 2658. Therefore, any portions of third layer 2658 that is exposed maybe etched away. Fourth layer 2660 may subsequently be removed using techniques known in the art, and the resultant structure is shown in step 2612.
  • patterned third layer 2658 may be used as a mask to etch portions of first layer 2652.
  • the pattern of third layer 2658 may be transferred to first layer 2652 using techniques such as dry or wet etching.
  • bent or crank patterns may be transferred onto first layer 2652.
  • steps similar to steps 2600 through 2614 of FIG. 26A are performed, but the resultant structure is different due to the patterning of certain layers (e.g., the deposition and patterning of photoresist layer 2656 in step 2600, defining the clipping pattern in step 2610, etc.).
  • step 2700 a top- view and a profile view of the structure at line A-A' is shown.
  • the structure includes a first layer 2752, second layer 2754, and patterned photoresist layer 2656 deposited on a substrate 2750.
  • step 2702 the pattern of photoresist layer 2756 may be transferred to second layer 2754. Patterned photoresist layer 2756 may be subsequently removed using techniques known in the art.
  • third layer 2758 may be deposited on the resultant structure shown in step 2702.
  • an etching technique e.g., wet or dry etch
  • second layer 2754 may be removed, the resultant structure shown in step 2708.
  • a clipping pattern may be defined, as shown in step 2710.
  • fourth layer 2760 may be deposited on various portions of the resultant structure of step 2708, and may be subsequently patterned.
  • third layer 2758 may be etched.
  • a portion of third layer 2758, and more particularly, portions of third layer not protected fourth layer 2760 may be etched away.
  • Fourth layer 2760 may subsequently be removed using techniques known in the art, and the resultant structure is shown in step 2712.
  • patterned third layer 2758 may be used as a mask to etch portions of first layer 2752.
  • the pattern of third layer 2758 may be transferred to first layer 2652 using techniques such as dry or wet etching to form the bi-directional line structure.
  • CD Changed Structure may also be used to fabricate CD changed structure, as shown in FIG. 28.
  • steps 2800 through 2814 are similar to the steps shown in FIGs. 1 through 9.
  • steps 2800 through 2814 are similar to the steps shown in FIGs. 1 through 9.
  • a top-view and a profile view of the structure at line A-A' is shown.
  • the first layer 2852 may be deposited on substrate 2850.
  • Second layer 2854 may be deposited on first layer 2852, and may subsequently be patterned using techniques known in the art.
  • a photoresist layer may be deposited and patterned on 2852.
  • An etching technique, selective to first layer 2852 may be used to etch and pattern second layer 2854 and the photoresist layer may subsequently be removed.
  • third layer 2858 may be deposited on the resultant structure shown in step 2800.
  • an etching technique e.g., wet or dry etch
  • second layer 2854 may be removed.
  • a clipping pattern may be defined, as shown in step 2808.
  • fourth layer 2860 may be deposited on the resultant structure of step 2806, and may be subsequently patterned.
  • third layer 2858 may be etched. In some embodiments, a portion of third layer 2858, and more particularly, portions of third layer not protected by fourth layer 2760 may be etched away. Fourth layer 2860 may subsequently be removed using techniques shown in the art and the resultant structure is shown in step 2810.
  • fifth layer 2862 may be deposited to define an arbitrary pattern.
  • fifth layer 2862 may be deposited on the resultant structure of step 2810 and subsequent patterned using techniques known in the art (e.g., etching, CMPs, etc.).
  • first layer 2852 may be etched in step 2814.
  • the pattern shown in step 2812 maybe transferred to first layer 2852.
  • the present disclosure may also provide techniques for fabricating a series of line having changing directions (relative to the x- and/or y- axis). Referring to FIG. 29, steps for fabricating these lines are shown. In particular;, steps similar to those shown in FIGs. 1-9 are used.
  • First layer 2952 may be deposited on substrate 2950.
  • Second layer 2954 may be deposited on first layer 2952, and may subsequently be patterned using techniques known in the art.
  • a photoresist layer may be deposited and patterned on 2952.
  • An etching technique, selective to first layer 2952 may be used to etch and pattern second layer 2954 and the photoresist layer may subsequently be removed, as shown in step 2900.
  • third layer 2958 may be deposited on the resultant structure shown in step 2900.
  • An etching technique e.g., wet or dry etch
  • second layer 2954 may be removed.
  • a clipping pattern may be defined, as shown in step 2906.
  • fourth layer 2960 may be deposited on v the resultant structure of step 2904, and may be subsequently patterned.
  • third layer 2958 may be etched.
  • a portion of third layer 2958, and more particularly, portions of third layer not protected by fourth layer 2960 may be etched away.
  • Fourth layer 2960 may subsequently be removed using techniques known in the art and the resultant structure is shown in step 2908.
  • patterned third layer 2958 maybe used as a mask to etch portions of first layer 2952.
  • the pattern of third layer 2958 may be transferred to first layer 2952 using techniques such as dry or wet etching to form the bi-directional line structure.
  • T Structures Referring to FIGs. 3OA and 3OB, steps for fabricating an isolated T-structure are shown. The steps are similar to the steps shown in FIGs. 1-9 of the present disclosure.
  • step 3000 of FIG. 30A a top-view and a profile view of a first layer 3052, second layer 3054, and patterned photoresist layer 3056 deposited on a substrate 3050 is shown.
  • step 3002 the pattern of photoresist layer 3056 may be transferred to second layer 3054. Patterned photoresist layer 3056 may be subsequently removed.
  • third layer 3058 may be deposited on the resultant structure shown in step 3002.
  • third layer 3058 may include the same material as second layer 3054.
  • third layer 3058 may be a different material from second layer 3054.
  • an etching technique ⁇ e.g., wet or dry etch
  • fourth layer 3060 may be deposited on the resultant structure shown in step 3006.
  • fourth layer 3060 may be etched using a dry and/or wet etching technique selective to second layer 3054.
  • second layer 3054 may be subsequently removed.
  • a clipping pattern may be defined, as shown in step 3014.
  • fifth layer 3062 may be deposited on various portions of the resultant structure of step 3012, and may be subsequently patterned.
  • step 3016 using the patterned fourth layer 3060 as a mask, first layer 3052 may be etched to form the isolated T-structure.
  • steps shown in FIGs. 30A and 30B may be used to fabricate dense T-structures shown in FIG. 3OC.
  • steps 3000 and 3002 may be performed.
  • step 3004A third material 3058 may be deposited.
  • Third material 3058 may subsequently be etched, resulting in the structure shown in step
  • second material 3054 may be removed.
  • fourth layer 3060 may be deposited on the resultant structure shown in step 3006B.
  • fourth layer may be etched using a dry and or wet etching technique selective to third material 3058 and first layer 3052.
  • third material 3058 may subsequently be removed.
  • a clipping pattern may not be defined, as shown in step 3014A.
  • fifth layer 3062 may be deposited on various portions of the resultant structure of step 3012A, and may be subsequently patterned, exposing a portion of forth layer 3060.
  • fourth layer 3062 may be etched using techniques such as, but not limited to dry and/or wet etch, as shown in step 3016A In particular, the areas of fourth layer 3060 not protected by fifth layer 3062 may be removed. Fifth layer 3062 may subsequently be removed. Next, using the, patterned fourth layer 3060 as a mask, first layer 3052 may be etched to form a dense T-structure, similar to the structure shown in FIG. 3OC.
  • the initial pattern may take account for the size and overlay limitations of the subsequent lithography steps in the pattern creation.
  • the following are examples of using this mix-and-match strategy to create useful, electrically testable devices. These examples are by no means meant to be exhaustive and one of ordinary skill in the art would recognize that many other types of devices are possible with the techniques described herein.
  • an initial pattern that may be used to form an electrically testable line 3170 (resistance serpentine) is shown.
  • Tines 3172 define the initial pitch. This pitch may be doubled by the space process of the present disclosure.
  • the pitch pattern may be fabricated using, for example, a binary mask or an alternating phase shift mask in conjunction with a trim mask.
  • Line 3170 may also include internal taps 3174. In one respect, large areas in the line pattern may allow taps to be attached to the spacer serpentine with conventional optical lithography.
  • steps for fabricating line 3170 are shown. The steps shown in
  • FIG. 31B are similar to the steps shown in FIGs. 1-9.
  • step 3100 shown a top view of the resultant structure
  • first layer 3152 and second layer 3154 may be deposited on substrate 3150 (not shown).
  • Second layer 3154 may be patterned using various techniques known in the art. For example, in one respect, a photoresist layer may be deposited and patterned on 3154. An etching technique, selective to first layer 3152 may be used to etch and pattern second layer 3154 and the photoresist layer may be subsequently removed.
  • third layer 3158 may be deposited on the resultant structure shown in step 3102.
  • an etching technique e.g., wet or dry etch
  • second layer 3154 may be removed using etching techniques known in the art.
  • fourth layer 3160 may be deposited on the resultant structure of step 3102. Fourth layer 3160 may be subsequently patterned.
  • third layer 3158 may be etched.
  • a portion of third layer 3158, and more particularly, portions of third layer not protected by fourth layer 3160 may be etched away.
  • Fourth layer 3160 may subsequently be removed using techniques known in the art resultant structure is shown in step 3106.
  • a fifth layer 3162 may be deposited and subsequently patterned using techniques known in the art.
  • the resultant pattern of step 3108 may be used as a mask to etch portions of first layer 3152, as shown in step 3110.
  • the resultant structure shown 3108 may be transferred to first layer 3152 using techniques such as dry or wet etching to form the line 3170.
  • lines 3272 may be staggered to allow room to connect every other line to a tap. It is noted that the lines may be position in other configurations to allow for easy access to the lines as appropriate for design specifications.
  • initial pattern 3270 as shown in FIG. 32B may be used to form a comb structure.
  • the steps shown in FIG. 32B are similar to the steps shown in FIGs. 1-9.
  • first layer 3252 and second layer 3254 may be deposited on substrate 3250 (not shown).
  • Second layer 3254 may be patterned using various techniques known in the art. For example, in one respect, a photoresist layer may be deposited and patterned on 3254. An etching technique, selective to first layer 3252 may be used to etch and pattern second layer 3254 and the photoresist layer may be subsequently removed.
  • step 3202 third layer 3258 may be deposited on the resultant structure shown in step 3200.
  • an etching technique e.g., wet or dry etch
  • second layer 3154 may be removed using etching techniques known in the art, as shown in step 3204.
  • a fourth layer 3260 may be deposited on the resultant structure of step 3204 and subsequently patterned using techniques known in the art.
  • lithography techniques may be used to define the shape of fourth layer 3260.
  • the resultant pattern of step 3206 may be used as a mask to etch portions of first layer 3252, as shown in step 3208.
  • the resultant structure shown 3206 may be transferred to first layer 3252 using techniques such as dry or wet etching to form comb 3270 of FIG. 32 A.
  • first layer 3352 and second layer 3354 may be deposited on substrate 3350 (not shown).
  • Second layer 3354 may be patterned using various techniques known in the art. For example, in one respect, a photoresist layer may be deposited and patterned on 3354. An etching technique, selective to first layer 3352 may be used to etch and pattern second layer 3354 and the photoresist layer may be subsequently removed.
  • third layer 3358 may be deposited on the resultant structure shown in step 3300.
  • an etching technique e.g., wet or dry etch
  • second layer 3354 and first layer 3352 may be used to etch back third layer 3358, the resultant structure is shown in step 3302.
  • second layer 3354 may be removed using etching techniques known in the art.
  • a clipping pattern may be defined.
  • fourth layer 3360 may be deposited on the resultant structure of step 3302, and may be subsequently patterned.
  • fourth layer 3660 may expose a portion of third layer 3358.
  • third layer 3358 may be etched.
  • fourth layer 3360 may be a masking layer to protect a portion of third layer 3358. Therefore, any portions of third layer 3358 that is exposed (e.g., not protected by fourth layer 3330) may be etched away. Fourth layer 3360 may subsequently be removed using techniques known in the art, and the resultant structure is shown in step 3306.
  • fourth layer 3260 may be deposited on the resultant structure of step 3206 and subsequently patterned using techniques known in the art.
  • lithography techniques may be used to define the shape of fourth layer 3360.
  • the resultant pattern of step 3308 may be used as a mask to etch portions of first layer 3352, as shown in step 3310. In other words, the resultant structure shown 3308 may be transferred to first layer
  • resistor 3370 shown in FIG. 33 A using techniques such as dry or wet etching to form resistor 3370 shown in FIG. 33 A.
  • using a single-spacer process may double the pitch of a dense-line pattern.
  • a quadruple pitch may be fabricated.
  • the advantage of the methods of the present disclosure is a minimum line and minimum trench width in the first pattern that allows two spacer lines to merge in order to make electrical contact. In this way the inner and outer loops of the second spacer traces can be wired independently.
  • Device 3470 includes tines 3472 which define the pitch.
  • the pitch pictured may be quadrupled by the spacer process of the techniques of the present disclosure.
  • the trench width (T w ) is critical, and needs to be less than about 4 times the size of the second spacer line width.
  • the line width (L w ), which allows for electrical connection to the inner loop, is also critical. In one respect, the line width may be less than the quarter pitch.
  • steps for fabricating device 3470 are shown. The steps shown in FIG. 34B are similar to the steps shown in FIGs. 1-9.
  • step 3400 (showing a top view of tihe resultant structure) an initial pattern is established, where first layer 3452 and second layer 3454 may be deposited on substrate 3450 (not shown).
  • Second layer 3454 may be patterned using various techniques known in the art. For example, in one respect, a photoresist layer may be deposited and patterned on 3454. An etching technique, selective to first layer 3452 may be used to etch and pattern second layer 3454 and the photoresist layer may be subsequently removed.
  • third layer 3458 e.g., a first spacer material
  • an etching technique e.g., wet or dry etch
  • a fourth layer 3460 (e.g., a second spacer material) may be deposited.
  • fourth layer 3460 may be deposited on third layer 3458.
  • Fourth layer 3460 may be subsequently patterned.
  • Third layer 3458 may subsequently be removed.
  • fifth layer 3462 may be deposited and patterned to form a clipping layer. Techniques for depositing and patterning layer 3462 are known in the art.
  • third layer 3458 may be etched. In some embodiments, a portion of third layer 3458, and more particularly, portions of third layer not protected by clipping layer 3462 may be etched away.
  • Clipping layer 3462 may subsequently be removed using techniques shown in the art.
  • a sixth layer 3464 may be deposited and subsequently patterned (e.g., using optical lithography) to create tabs using techniques known in the art.
  • the resultant pattern of step 3408 may be used as a mask to etch portions of first layer 3452, as shown in step 3410.
  • the resultant structure shown 3408 may be transferred to first layer 3452 using techniques such as dry or wet etching to form the device 3470.
  • device 3470 may be fabricated using the steps shown in FIGs. 34C and 34D.
  • step 3400A an initial pattern is established, where first layer 3452, second layer 3454, and third layer 3458 may be deposited on substrate 3450 (not shown).
  • first layer 3452 and third layer 3458 may include the same material.
  • third material 3458 may be patterned using techniques of known in the art. For example, in one respect, a photoresist layer may be deposited on third layer 3458 and patterned. An etching technique, selective to second layer 3454 may be used to etch and pattern second layer 3854 and the photoresist layer may subsequently be removed.
  • a fourth layer 3460 (e.g., a spacer layer) may be deposited on the resultant structure of step 3400 and subsequently patterned using techniques known in the art. Subsequently, third material 3458 may be removed.
  • a clipping pattern may be defined.
  • fifth layer 3462 may be deposited on the structure after third material 3458 has been removed.
  • Fifth layer 3452 may be patterned with optical lithography, and may define a clipping pattern.
  • portions of fourth layer 3460 may be removed using techniques known in the art. In particular, portions of fourth layer 3460 not protected by fifth layer 3462 may be etched away.
  • sixth layer 3464 may be deposited on the resultant structure of step
  • sixth layer 3464 may be patterned with optical lithography.
  • optical lithography For example, 193 nm lithography, 248 nm lithography, or e-beam lithography may be used to pattern the layers.
  • the resolution needed, and thus, the type of optical lithography used may depend on the details of the pattern. Therefore, other optical lithography techniques may be used to pattern the layers of present disclosure.
  • the pattern formed from step 3406A may be used to pattern second layer 3454.
  • an etchant selective to first layer 3452 may be used to etch second layer 3454.
  • the resultant structure is shown in step 3408 A.
  • a seventh layer e.g., a second spacer layer
  • seventh layer 3466 may be deposited and may be etched using techniques know in the art.
  • Second layer 3454 may subsequently be removed, and the resultant structure is shown in step 3410A.
  • eighth layer 3468 may be deposited on the structure shown in FIG. 3410. Eighth layer 3468 may be patterned and may be define a clipping area. Using the patterned eighth layer 3468 as a masking layer, portions of seventh layer 3466 may be etched using an etchant selective to layer second 3452. A ninth layer, layer 3470 may be deposited after portions of layer 3466 are removed. Eighth layer 348 may subsequently be removed. Next, using, for example, optical lithography, ninth layer 3470 may be patterned to define pads, as shown in step 3414A.
  • step 3416A the resultant pattern of step 3414A may be used as a mask to etch portions of first layer 3452.
  • the resultant structure shown 3416A may be transferred to first layer 3452 using techniques such as dry or wet etching to form the device 3470.
  • the steps shown in FIGs. 1-9 may be applied to the fabrication of electrically testable pitch-quadrupled comb structure shown in step 3510 shown of FIG. 35B.
  • the initial pattern 3570 shown is one example of many different approaches, and one of ordinary skill in the art would recognize that combs of different pitches may also be fabricated.
  • Device 3570 includes tines 3572 which define the pitch.
  • the pitch pictured may be quadrupled by the spacer process of the techniques of the present disclosure.
  • the trench width (T w ) is critical, and needs to be less than about 4 times the size of the second spacer line width.
  • the line width (L w ), which allows for electrical connection to the inner loop, is also critical. In one respect, the line width may be less than the quarter pitch.
  • step 3500 (showing a top view of the resultant structure) an initial pattern is established, where first layer 3552 and second layer 3554 may be deposited on substrate 3550 (not shown).
  • Second layer 3554 may be patterned using various techniques known in the art. For example, in one respect, a photoresist layer may be deposited and patterned on 3554. An etching technique, selective to first layer 3552 may be used to etch and pattern second layer 3554 and the photoresist layer may be subsequently removed.
  • third layer 3558 e.g., a first spacer material
  • an etching technique e.g., wet or dry etch
  • Second layer 3552 may subsequently be removed.
  • a fourth layer 3560 (e.g., a second spacer material) may be deposited.
  • fourth layer 3560 may be deposited and may be subsequently patterned.
  • third material 3558 may be removed using techniques known in the art.
  • 3562 may be deposited and patterned to form a clipping layer. Techniques for depositing and patterning layer 3562 are known in the art.
  • third layer 3558 may be etched.
  • a portion of third layer 3558, and more particularly, portions of third layer not protected by clipping layer 3562 may be etched away.
  • Clipping layer 3562 may subsequently be removed using techniques shown in the art. The resultant structure is shown in step 3508.
  • a sixth layer 3564 may be deposited and subsequently patterned to create tabs using techniques known in the art (e.g., optical lithography).
  • the resultant pattern of step 3508 may be used as a mask to etch portions of first layer 3552, as shown in step 3510.
  • the resultant structure shown 3508 may be transferred to first layer 3552 using techniques such as dry or wet etching to form the device 3570.

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Abstract

L'invention concerne des procédés de fabrication de structures semi-conductrices. Une première couche peut être déposée sur un substrat, en faisant suivre par le dépôt d'une seconde couche sur la première couche. Une pluralité de structures de ligne peuvent être gravées dans la seconde couche. Une troisième couche, déposée sur la pluralité de structures de ligne de la seconde couche, peut ultérieurement être gravée pour exposer la pluralité de structures de ligne dans la seconde couche. La pluralité de structures de ligne dans la seconde couche peuvent être retirées, laissant une troisième couche gravée. La troisième couche gravée peut être utilisée en tant que masque pour graver la première couche pour former une structure semi-conductrice dans la première couche. À certains égards, les procédés peuvent comprendre des étapes consistant à graver le substrat à l'aide de la première couche gravée. Les procédés peuvent également comprendre le recuit du substrat gravé pour former une surface de substrat ondulée.
PCT/US2007/060865 2007-01-22 2007-01-22 Procédés de fabrication de structures semi-conductrices WO2008091343A1 (fr)

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