WO2008088532A2

WO2008088532A2 - Light emission control for a display device

Info

Publication number: WO2008088532A2
Application number: PCT/US2007/025288
Authority: WO
Inventors: Kazuyoshi Kawabe
Original assignee: Eastman Kodak Company
Priority date: 2006-12-26
Filing date: 2007-12-11
Publication date: 2008-07-24
Also published as: JP2008158439A; WO2008088532A3

Abstract

The aim of the invention is to reduce power consumption in an active matrix. type display device. A first drive transistor (2) and a second drive transistor (4) form a static memory. A data voltage from a data line (7) is input into the static memory via a gate transistor (5) and stored in the static memory. To the first and second driver transistors, first (1) and second (3) organic EL elements are connected, in which one of the first and second driver transistors is set capable of light emission and the other incapable of light emission. With this arrangement, light emission according to the data voltage is carried out.

Description

LIGHT EMISSION CONTROL FOR A DISPLAY DEVICE

This application claims priority of Japanese Patent Application No. 2006-349915 filed December 26, 2006 which is incorporated herein by reference in its entirety. FIELD OF THE INVENTION

The present invention relates to an active matrix type display device having a transistor for controlling data import for every pixel.

BACKGROUND OF THE INVENTION

An active matrix type display panel is widely prevailing as a display since the panel is adapted to higher resolution. An active matrix type display requires an active element with respect to each of the pixels for determining the state of display thereof. In particular, in a current-driving type organic EL display, a driver transistor capable of continuously providing current to the organic EL element is provided. Where a driver transistor is formed using an amorphous or poly-silicon thin film transistor (Thin Film Transistor: TFT), constant property of the TFT cannot be readily attained.

Some methods using circuit technology have been proposed for amending the TFT property. One of those methods is digital driving (See WO 2005-116971A1).

The digital driving, however, requires dividing of one frame period into a plurality of sub-frame periods, and writing data into a pixel, for controlling whether or not to emit light during a sub-frame period in which a constant light emission period is defined. This results in an increase of power consumption for data transfer. That is, in a case in which one frame period is divided into eight sub-frames, for example, as it is necessary to access the pixel eight or more times in one frame period, an amount of power eight times the amount of power which is consumed in a normal case is consumed. This leads to a demand to reduce power consumption by a digitally driven display panel. SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided an active matrix type display device, wherein each pixel includes a selection transistor for controlling digital data input from a data line; a static memory having a pair of transistors and disposed between a positive power supply and a negative power supply, the static memory storing input digital data when one of the pair of transistors is turned on while the other transistor is turned off according to the digital data which is input when the selection transistor turns on; and a light-emissive element for emitting light according to current flowing through either one of the pair of transistors in the static memory, whereby light emission of the light-emissive element is controlled according to the input data.

In the above, the static memory may include a first transistor having one of a source or drain connected to a power supply and a gate connected to an output side of the selection transistor, to be turned on or off in response to the digital data, and a second transistor having one end connected to the power supply and a gate connected to another end one of a drain or source of the first transistor, to be turned on or off in response to an on/off state of the first transistor, another end of the second transistor is connected to the gate of the first transistor and the output side of the selection transistor, and the first transistor and the second transistor are complementarity turned on in response to the digital data input. In the above, the first transistor and the second transistor may be respectively connected, at the respective other ends thereof, to two light-emissive elements, including a light-emissive element which emits light, and another light-emissive element which is light-shielded.

In the above, between the light-emissive element which is light- shielded and one of the first transistor and the second transistor, to which the light-emissive element which is light-shielded is connected, a switching transistor may be provided, having a gate connected to another end of another one of the first transistor and the second transistor and polarity inverted from polarity of the other one of the first transistor and the second transistor, the switching transistor preventing current from flowing into the light-emissive element which is light-shielded. In the above, a light-emissive element may be connected to another end of one of the first transistor and the second transistor, and a switching transistor may be connected to another one of the first transistor and the second transistor, which has a gate connected to another end of the other one of the first transistor and the second transistor and polarity inverted in polarity compared to the one of the first transistor and the second transistor, the switching transistor preventing current which flows thereinto when the other of the first transistor and the second transistor is turned on.

In the above, the active matrix type display device may further comprise a frame memory for storing digital data for at least one frame, wherein the frame memory supplies digital data to the data line. In the above, the active matrix type display device may further comprise gate lines each arranged for every pixel row, to be driven by a gate driver to thereby control the selection transistor, wherein the gate driver is able to individually sequentially select a row within a predetermined range, so only that data on a pixel within a range selected can be updated. In the above, the frame memory may be able to store, with respect to each pixel, one-bit digital data and a plurality of bits of digital data, and supply one-bit digital data in_one frame to the data line in a case of a monochrome pixel memory display mode, and a plurality of bits of digital data in_a plurality of sub-frames to the data line in a case of a variable contrast mode. In the above, either one of the one-bit digital data and the plurality of bits of digital data supplied from the frame memory may be selectable with respect to a data line in each column, so that a display mode can be partially changed. In the above, the light-emissive element may be an organic EL element. As described above, according to the present invention, as each pixel has a static memory, and the data once written thereinto is maintained until the power supply is turned off, refreshing is unnecessary. Therefore, in displaying an image without change, power consumption can be reduced

BRIEF DESCRIPTION OFTHE DRAWINGS FIG. 1 A is a diagram showing a pixel equivalent circuit in a first embodiment;

FIG. IB is a diagram showing a pixel equivalent circuit and a layout thereof;

FIG 2 is a diagram showing an overall structure of an organic EL display; FIG. 3 is a diagram showing an internal structure of a data driver; FIG 4 is a diagram explaining a partial update process; FIG 5 is a diagram showing an internal structure of a gate driver; FIG 6 A is a diagram showing a pixel equivalent circuit in a second embodiment; and

FIG. 6B is a diagram showing another pixel equivalent circuit in the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION In the following, embodiments of the present invention will be described based on the accompanying drawings. (Embodiment 1)

FIGS. IA and IB show a structure of a pixel circuit according to the present invention. In particular, FIG. 1 A shows a pixel equivalent circuit; FIG. 1 B shows a pixel circuit layout viewed from the side opposite the light emission surface. This pixel circuit includes a first organic EL element (a light-emissive element) 1 which contributes to light emission, a first driver transistor (a first transistor) 2 for driving the first organic EL element 1 , a second organic EL element (a light-emissive element) 3 which does not contribute to light emission, a second driver transistor (a second transistor) 4 for driving the second organic EL element 3, and a gate transistor

5 for controlling supply of data voltage supplied to the data line 7 to a gate terminal of the first driver transistor 2. The gate transistor is controlled by a gate line 6 which receives a selection signal. As described above, this pixel circuit requires no holding capacitor, which is conventionally required to hold data voltage. The first driver transistor 2, the second driver transistor 4, and the gate transistor 5 are all formed using P-type TFT's in this example.

The anode of the first organic EL element 1 is connected to the drain terminal of the first driver transistor 2 and the gate terminal of the second driver transistor 4. The gate terminal of the first driver transistor 2 is connected to the anode of the second organic EL element 3, the drain terminal of the second driver transistor 4, and the source terminal of the gate transistor 5. The gate terminal of the gate transistor 5 is connected to the gate line 6, while the drain terminal thereof is connected to the data line 7. The source terminals of the first driver transistor 2 and second driver transistor 4 are connected to the power supply line 8, and the cathodes of the first organic EL element 1 and second organic EL element 3 are connected to the cathode electrode 9.

When the gate line 6 is selected (that is, made low), the gate transistor 5 is turned on. Thereupon, the data voltage supplied to the data line 7 is imported into the inside of the pixel circuit via the gate transistor 5.

With the data voltage low, the first driver transistor 2 is turned on. With the first driver transistor 2 turned on, the anode of the first organic EL element 1 is connected to the power supply line 8 to which power supply voltage VDD is supplied, so that current flows into the first organic EL element 1, which then emits light. At the same time, the gate terminal of the second driver transistor 4 comes to have the voltage VDD. As a result, the second driver transistor 4 is turned off, and the potential of the anode of the second organic EL element 3 drops to the cathode potential VSS. As the cathode potential VSS is supplied to the gate terminal of the first driver transistor 2, the state resulting from the written data voltage low is maintained during a period when the VDD and VSS continue to be supplied even after the gate line 6 is made high, and the gate transistor 5 is accordingly turned off.

Meanwhile, when the data voltage is high, the first driver transistor 2 is turned off, and the potential of the anode of the first organic EL element 1 drops to the cathode potential VSS. As the cathode potential VSS is supplied to the gate terminal of the second driver transistor 2, the second driver transistor 4 is turned on, and the anode of the second organic EL element 3 is connected to the power supply line 8 to which the power supply voltage VDD is supplied. Accordingly, current flows into the second organic EL element 3.

As the anode potential of the second organic EL element 3 is introduced to the gate terminal of the first driver transistor 2, so that the anode potential of the second organic EL element 3 becomes equal to the power supply voltage VDD, the state resulting from the written data voltage high is maintained during a period when VDD and VSS are still being supplied, even after the gate line 6 is turned high, and the gate transistor 5 is accordingly turned on.

The state of light emission of the first organic EL element 1 determines the state of light emission of the pixel as the second organic EL element 3 does not contribute to light emission. To manufacture the second organic EL element 3 which does not contribute to light emission, there is one way in which an element (any element showing resistance) which does not emit light, different from the first organic EL element 1 , is formed. This, however, results in a complicated manufacturing process due to the need to manufacture two kinds of elements, that is, the first organic EL element 1 which emits light and the organic EL element 3 which does not emit light. To address this point, preferably, these elements are both formed using the same type of elements, and the second organic

EL element 3 is light-shielded using a wire which constitutes a pixel circuit so that light leakage from the light emission surface to the outside is prevented.

With a top emission structure in which the light can be extracted from the side opposite the pixel circuit, light-shielding may be achieved by affixing the substrate where the pixel circuit is formed to an opposed substrate which is a glass substrate coated with a light shielding film, such as a black matrix, at a position thereon which is suitable to light-shield the second organic EL element 3.

In any case, a preferable layout is such that the second organic EL element 3, which does not contribute to light emission, has a small light emission area, and the first organic EL element 1 , which contributes to light emission, has a large light emission area, as shown in FIG. IB.

FIG 2 shows an overall structure of an organic EL display which includes a pixel memory array 10 where the pixels 13 shown in FIGS. IA and IB are arranged in a matrix, a gate driver 11 for driving the gate line 6, and the data driver 12 for driving the data line 7. The power supply line 8 and the cathode electrode 9 are commonly used by all pixels, and respectively receive VDD and VSS externally supplied.

It should be noted that use of a high performance transistor formed in a process using low temperature poly-silicon allows formation of the gate driver 11 and the data driver 12 on the glass substrate where the pixel 13 is formed. However, in digital driving, for which a frame memory is required as a frame image is divided into a plurality of sub-frames, it is more practicable to form the data driver 12 in the form of a driver IC and the gate driver 11 on the glass substrate where the pixel 13 is formed. Therefore, the following description relies on this structure.

FIG 3 shows an interior structure of the data driver 12. Here, data which includes, for full-color display, video data which contains red (R), green (G), blue (B), and optionally white (W) and is to be transferred in units of one or more pixels and a clock signal and a timing signal for transferring the video data is externally input to the input processing section 14. The video data in the input data is accumulated as video data for one line in the input processing section 14, and then transferred to, and stored in, the frame memory 15 in units of one line. The video data for one screen is read from the frame memory 15 in units of one line, and then output in units of one line by the output processing section 16 to the organic EL panel 17. The organic EL panel 17 reflects the supplied video data in display. It should be noted that a timing signal for transferring the video signal to the frame memory 15, a reading operation, a timing signal for outputting the video signal to the organic EL panel 17 are not described here.

In a structure in which the frame memory 15 is provided between the input processing section 14 and the output processing section 16, as described above, when video data is once stored in the frame memory 15, it is thereafter possible to supply video data to the organic EL panel 17 even without external supply of video data, as the video data can be supplied from the frame memory 15. In other words, it is unnecessary to keep externally inputting video data in order to continue display. This arrangement can reduce power consumption necessary in data transfer from the outside. Therefore, this arrangement is often employed in an LCD (Liquid Crystal Display) mounted in a portable terminal, for which low power consumption is indispensable. In digital driving, generally, each of the sub-frame data is updated in units of one screen in each sub-frame period. This leads to increase of power consumption due to scanning. In this embodiment, however, power consumption can be similarly reduced even in digital driving because a static memory, which does not require refreshing, is incorporated in the pixel, as shown in FIGS. IA and IB, and driven using the method described below.

Here, a portable terminal, such as a laptop, a portable phone, and a portable music player, may often present functional display, such as an electronic mail, a menu screen, and so forth, for encouraging a simple operation, while a video and motion picture may also be often shown, and a conventional pixel circuit without an incorporated statistic memory constantly requires periodic refreshing even when showing a rarely changing simple image for providing a function. Therefore, power is constantly consumed for the refreshing even while showing an image that is not changing.

Consequently, a digitally driven pixel circuit consumes a large amount of power, even larger than that which is consumed by a conventional analogue-driven pixel circuit which also consumes a large amount of power. In view of the above, utmost suppression of the frequency of refreshing is desired. A static memory incorporated in the pixel circuit can keep holding the data once written therein as long as the power is kept on, though the storage capacity offered thereby is as small as one bit. Therefore, active utilization of this function makes it possible to avoid frequent refreshing.

Here, most of the electronic mails and menu screen images are shown in a black character with white background, and characterized in that only the character typed by the user or the portion selected by the user is updated. In consideration of this characteristic feature, combination of the pixel circuit having a built-in static memory, shown in FIG. 1 , and partial update for partially rewriting an image makes it possible to reduce power consumption. This will be described in further detail below with reference to FIG. 4. FIG 4 shows an example in which an image stored in the frame memory 15 capable of storing seven-bit data per pixel, incorporated in the data driver 12, and also in the pixel memory array 10 capable of storing one-bit data per pixel, is partially updated. Specifically, the bit EO in the seven-bit data stored in the frame memory 15 is used for one-bit pixel memory display, and the remaining bits DO to D5 are used for six-bit variable contrast display. That is, as described above, the frame memory 15 is constructed capable of storing two types of data at the same time.

Suppose that the areas A and B are both displayed in the one-bit pixel memory display mode, and that only the area A needs to be updated. In this case, when a signal for updating the bit EO of the area A in the frame memory 15 and promoting reflection of the updated result in display is externally input, the seven-bit data is read from the frame memory 15, sequentially from the top line M to the bottom line N in the area A. Thereafter, a data selection signal for designating which of the bit EO and the bits DO to D5 in the seven-bit data is to be selected is made high the bit EO is select for lines M to N. Then, the output processing section 16 outputs the data on the bit EO to the pixel memory array 10, and the data on the lines M to N in the pixel memory array 10 is updated using the data on the bit EO stored in the frame memory 15. It should be noted that, in the above, only the data on the area A is actually updated, while the data on the area B is merely re-written with the same data. In the case where the area A is in the variable contrast display mode and the area B is in the one-bit pixel memory display mode, the lines M to N in the area A are updated in the variable contrast display mode. In this case, the data selection signal is made low for the area A, whereby the bits DO to D5 are selected. The area A is updated using sub-frame data in the respective sub-frames, while the area B is re-written with the same data. In the case where the area B is in the variable contrast display mode, the whole of the screen image is placed in the variable contrast display mode, hi this case, the data selection signals are set low for all lines.

As described above, in updating a specific portion in the one-bit monochrome pixel memory display mode, and/or in displaying a specific area in the variable contrast display mode, the refreshing operation can be minimized as the area to be updated is limited. Therefore, power consumption can be further reduced.

In partial update as described above, the gate driver 11 plays an important part. That is, a gate driver 11 incorporating a decoder can directly access a desired line. This can offer high flexibility, and facilitate partial update. For example, in accessing up to 256 lines, it is possible to designate a line for direct selection for every line by inputting eight-bit data (selection data) for the line to be selected into an eight-bit control line. A decoder is effective in a case, such as a memory, in which random addressing is frequency utilized, as described above. However, in a display which employs sequential addressing in which the lines are sequentially addressed from the top line to the bottom line, a decoder requires relatively complicated control with a large overhead as a result.

In sequential addressing, an address can be updated (+1) using a shift register by inputting one clock. In random accessing, on the other hand, it is always necessary to designate a specified address. In addition, an increase in the number of lines leads to an increase in the number of addresses, resulting in a larger decode circuit with a reduced operation speed. Therefore, in application to random access for a high resolution display, a higher performance transistor is preferably employed.

Moreover, formation of the gate driver 11 in the form of a driver IC or incorporation in the data driver 12 is more effective than the structure, such as is shown in FIG. 2, in which the gate driver 11 is formed on the glass substrate where the pixel 13 is formed. In sequential addressing using a shift register, dividing the gate driver 11 , as shown in FIG. 5, helps to achieve more effective partial update.

FIG 5 shows a structure in which the pixel memory array 10 is divided into three blocks, namely, an upper portion (a), a middle portion (b), and a lower portion (c), and the gate driver 11 is divided into an upper gate driver portion 11 a for driving the gate lines in the upper portion (a) of the pixel memory array 10, the middle gate driver portion 1 Ib for driving the gate lines in the middle portion (b), and the lower gate driver portion 11 c for driving the gate lines in the lower portion (c). A clock to be input to the shift register and enable control lines enb 1 to 3 for reflecting an output of the shift register in the gate line is commonly used by the three divided gate driver portions 11a, l ib, 11 c in FIG 5. This, however, is not an exclusive example, and dedicated clocks and enable control lines may be provided with respect to the respective divided gate driver portions' 11a, l ib, 11 c so that the respective divided gate driver portions 11a, l ib, 11 c are independently driven. Selection pulses are supplied from an input ain to the upper gate driver portion 11a, from the input bin to the middle gate driver portion l ib, and from the input cin to the lower gate driver portion l ie, respectively. The supplied selection pulses are transferred to the shift register according to a clock (a horizontal synchronism signal or a signal in synchronism therewith) for changing the line to be selected, so that the line to be selected is sequentially changed. Alternatively, the line to be selected can be determined according to the enable signals enb 1 to 3.

In a mode in which data is supplied to the whole of the organic EL panel to display, a selection pulse is input from the input ain to set two connection signals con_ab, con_bc, to be described later, high. As a result, the gate driver 11 operates as a single unit overall. The selection pulse is sequentially transferred to the shift register, so that the gate line is sequentially selected. Meanwhile, when only the upper portion (a) needs to be updated, the connection signals con_ab and con_bc are set low before a selection pulse is supplied via the input ain.

In the following, an example of updating the middle portion (b) alone, or the middle portion (b) and the lower portion (c), will be described.

The connection signals con_ab, con_bc are used to control connection between the divided gate driver portions 11a and lib and between the divided gate driver portions lib and 11 c, respectively. Specifically, in response to the connection signals con_ab and con_bc being high, the connection is established. In response to the connection signals con_ab and con_bc being low, the connection is released. With the connection released, selection pulses externally input through the input bin and cin can be input to the shift registers of the respective divided gate driver portions l ib, 11 c.

In the following, an example of updating the area A displayed in the pixel memory display mode is described. Specifically, as the area A is fully contained in the block b, it is sufficient to cause the divided gate driver portion lib alone to operate. In the above, non-selection pulses are kept input to the inputs ain, cin of the divided gate driver portions 11a, 1 Ic to control such that the pixels in the blocks a, c are not updated.

By inputting a selection pulse into the input bin of the divided gate driver portion l ib and continuously inputting a clock until the selection pulse is stored in the shift register for the line L, the line L is selected, and data on the line L is updated. Thereafter, by repeating this process up to the line M, data on the area A in the pixel memory array is updated by way of sequential addressing for every line in the order from the lines L to M, using the method shown in FIG 4.

As described above, in update of one-bit data alone, the area A alone or the whole of the block B may be designated as an object to update. In this case, control may be performed such that all of the enable signals enb 1 to 3 are set high all the time so that the selection data (data for setting the gate lines for the respective lines in the state of being selected (for example, low)) for the shift register is reflected intact at the output. Alternatively, any of the enable signals enb 1 to 3 for enabling the lines may be selected, so that the selection data for the shift register is reflected in the output. By selecting one of the enable signals enb 1 to 3, the gate line is selected for every third line, and by sequentially selecting a different enable signal enb 1 to 3, the line to be selected can be sequentially changed for every third line.

In the case where the area A is in the variable contrast mode, the whole of the block b is set as an object to update and controlled by digital driving using the divided gate driver portion 1 Ib. A method for controlling the divided gate driver portion 1 Ib when digital driving is employed is not described here as the method is described in detail in WO 2005-11691 Al .

To partially update an area which bridges over two blocks, like the area B shown in FIG. 5, the connection signal con_bc is initially set high to thereby connect the divided gate driver portions l ib, 1 Ic to each other so that the blocks b, c are driven as one block.

In the above, if the area B is in the one-bit pixel memory display mode, it is possible to designate the area B alone as an object to update. However, if the area B is in the variable contrast display mode, the blocks b and c are both designated as an object to update.

Here, it should be noted that, although the gate driver 11 is divided into three portions in the above-described example, the gate driver 11 may alternatively be divided into upper and lower portions or into four portions. Further, it may be arranged such that some of the divided gate driver portions may be arranged on the left side, with the rest on the right side. Use of the divided gate driver portions, as describe, enables partial update by way of sequential addressing using a shift register. This arrangement, however, is not very suitable when the partial update is frequently applied, as the freedom in designation of the area to be updated is relatively small compared to a case in which random addressing using a decoder is employed. Meanwhile, sequential addressing is more suitable than random addressing when variable contrast display is often applied. That is, selection of a suitable structure according to the environment in which display is carried out is desired. In any case, active utilization of the above-described partial update can eliminate refreshing, which would otherwise be required, when showing the same image in the pixel memory display mode. Therefore, the number of applications of refreshing is reduced, and power consumption by the organic EL display for digital driving can be accordingly reduced.

(Embodiment 2)

FIGS. 6 A and 6B show a pixel circuit in which an N-type switching transistor 18 is provided between the second organic EL element 3 and the second driver transistor 4. This structure can further reduce the power consumption.

In the pixel circuit shown in FIG 6 A, the source terminal of the N-type switching transistor 18 is connected to the anode of the second organic EL element 3, the gate terminal thereof is connected to the drain terminal of the first driver transistor 2, the anode of the first organic EL element 1 , and the gate terminal of the second driver transistor 4, and the drain terminal thereof is connected to the drain terminal of the second driver transistor 4, the gate terminal of the first driver transistor 2, and the source terminal of the gate transistor 5. As the N-type switching transistor 18 is provided between the second driver transistor 4 and the second organic EL element 3, the switching transistor 18 blocks the current flowing into the second organic EL element 3 while the first organic EL element 1 remains off, that is, the second driver transistor 4 remains on. As a result, no extra current flows.

FIG 6B shows a pixel circuit shown in FIG 6 A with the second organic EL element 3 omitted therefrom so that the source terminal of the switching transistor 18 is directly connected to the cathode.

As described above, employment of the switching transistor 18 makes it possible to prevent extra power consumption, which would otherwise be caused, when the first organic EL element 1 remains off. As a result, power consumption can be further reduced.

It should be noted that, although a P-type first driver transistor, a P-type second driver transistor, and a P-type gate transistor are used in the above described example, N-type transistors may be respectively used instead. When N-type driver transistors are employed, the organic EL element is preferably arranged between the driver transistor and the positive power supply, rather than between the driver transistor and the^' negative power supply. In the above, it is preferable to provide a way for maintaining the voltage to be applied to the organic EL element at a predetermined value. When an N-type gate transistor 5 is employed, the polarity of the gate line 6 is inverted.

Parts List

1 first organic EL element

2 first driver transistor

3 second organic EL element

4 second driver transistor

5 gate transistor

6 gate line

7 data line

8 power supply line

9 cathode electrode

10 pixel memory array

11 gate driver

11a divided gate driver portion lib divided gate driver portion l ie divided gate driver portion

12 data driver

13 pixels

14 processing section

15 frame memory

16 processing section

17 organic EL panel

18 switching transistor

Claims

CLAIMS:

1. An active matrix type display device, wherein each pixels comprises: a selection transistor for controlling digital data input from a data line; a static memory having a pair of transistors and disposed between a positive power supply and a negative power supply, the static memory for storing input digital data when one of the pair of transistors is turned on while the other transistor is turned off according to the digital data which is input when the selection transistor turns on; and a light-emissive element for emitting light according to current flowing through either one of the pair of transistors in the static memory, whereby light emission of the light-emissive element is controlled according to the input data.

2. The active matrix type display device according to claim 1 , wherein: the static memory includes a first transistor having one end connected to a power supply and a gate connected to an output side of the selection transistor, to be turned on or off in response to the digital data, and a second transistor having one end connected to the power supply and a gate connected to another end of the first transistor, to be turned on or off in response to an on/off state of the first transistor, another end of the second transistor is connected to the gate of the first transistor and the output side of the selection transistor, and the first transistor and the second transistor are complementarily turned on in response to the digital data input.

3. The active matrix type display device according to claim 2, wherein the first transistor and the second transistor are respectively connected, at the respective other ends thereof, to two light-emissive elements, including a light-emissive element which emits light and another light-emissive element which is light-shielded.

4. The active matrix type display device according to claim 3, wherein, between the light-emissive element which is light-shielded and one of the first transistor and the second transistor, to which the light-emissive element which is light-shielded is connected, a switching transistor is provided, which has a gate connected to the other end of another one of the first transistor and the second transistor and polarity inverted from the polarity of the other one of the first transistor and the second transistor, the switching transistor preventing current from flowing into the light-emissive element which is light-shielded.

5. The active matrix type display device according to claim 2, wherein: a light-emissive element is connected to the other end of one of the first transistor and the second transistor, and a switching transistor is connected to another one of the first transistor and the second transistor, having a gate connected to the other end of the other one of the first transistor and the second transistor and polarity inverted from the polarity of the one of the first transistor and the second transistor, the switching transistor preventing current from flowing into the other one of the first transistor and the second transistor when the other one of the first transistor and the second transistor is turned on.

6. The active matrix type display device according to claim 1 , further comprising: a frame memory for storing digital data for at least one frame, wherein the frame memory supplies digital data to the data line.

7. The active matrix type display device according to claim 6, further comprising: gate lines each arranged for every pixel row, to be driven by a gate driver to thereby control the selection transistor, wherein the gate driver is able to sequentially select a row solely within a predetermined range, so that data on a pixel solely within a range selected can be updated.

8. The active matrix type display device according to claim 6, wherein the frame memory stores, for each pixel, one-bit digital data and a plurality of bits of digital data, and supplies the one-bit digital data in one frame to the data line in a case of a monochrome pixel memory display mode, and supplies the plurality of bits of digital data in a plurality of sub-frames to the data line in a case of a variable contrast mode.

9. The active matrix type display device according to claim 8, wherein either one of the one-bit digital data and the plurality of bits of digital data supplied from the frame memory is selectable with respect to a data line in each column, so that a display mode is partially changeable.

10. The active matrix type display device according to claim 1 , wherein the light-emissive element is an organic EL element.