WO2008043652A2

WO2008043652A2 - Electronic system

Info

Publication number: WO2008043652A2
Application number: PCT/EP2007/059909
Authority: WO
Inventors: Juergen Sauler; Reinhard Weiberle; Bernd Mueller; Matthias Knauss; Udo Schulz; Yorck Collani; Rainer Gmehlich; Rolf Kurrer
Original assignee: Robert Bosch Gmbh
Priority date: 2006-10-10
Filing date: 2007-09-19
Publication date: 2008-04-17
Also published as: DE102006048172A1; WO2008043652A3; EP2082296A2

Abstract

The invention relates to a system with several execution units, at least one execution unit (2A) carrying out programmes in an event controlled manner and an other execution unit (2B) carrying out programmes in only a time controlled manner.

Description

description

title

Electronic system

The invention relates to a system with a plurality of execution units, which is particularly suitable for controlling an engine.

Electronic systems may have multiple integrated execution units. The execution units may be a complete microprocessor, a CPU (Central Processing Unit) or else a calculation unit, such as a floating point calculation unit FPU (Floating Point Unit) or an arithmetic logic calculation unit ALU (Arithmetic Logic Unit). Further possible execution units are digital signal processors or co-processors. So-called dual-core systems have two processor cores or cores, which are integrated on one chip. With dual-core computer architectures, the computer cores can execute different programs at the same time. In such systems, the execution units may be either identical or different. For example, there are systems with a plurality of execution units which, in addition to a multi-purpose or generally usable computer core, have a dedicated computer core, for example a digital signal processor DSP for signal processing. Such dual or multi-core

Computer architectures are characterized by a very low power consumption, so that the heat output generated is lower. In addition, systems with multiple execution units have a lower electromagnetic radiation compared to single-core systems, which achieve an increase in performance or performance through a clock frequency increase.

One distinguishes between time-controlled and event-driven systems. For example, there are event-driven bus systems such as CAN or time-controlled bus systems. Event-controlled bus systems are highly flexible and can be used in a variety of ways. At high loads, the behavior of an event-driven bus system with respect to a message transmitted over the bus is not well predictable without sophisticated scheduling. Therefore, in safety-relevant application gram, the messages transmitted over a bus, usually a timed transmission of messages, such as TTP / C, Flexray, TTCAN preferred. With timed transmission of messages over the bus, the transfer behavior no longer depends on the load, thus increasing the predictability, predictability, and clarity of the system.

Also at the operating system level, programs can be executed time-controlled or event-controlled. For example, OSEK-Time is a purely timed operating system standard. Both event- and time-controlled systems have advantages and disadvantages in the respective fields of application. In a case of conflict in which an event-driven request meets a timed request, conventional systems specify which request has a higher priority and thus is processed first. The low-priority request must then wait, so that the timed strategy or the event-driven strategy can no longer be met.

It is therefore the object of the present invention to provide a system which ensures efficient execution of both time controlled and event driven programs.

This object is achieved according to the system with the features specified in claim 1.

The invention provides a system having a plurality of execution units, wherein at least one execution unit executes programs in an event-controlled manner and at least one other execution unit executes programs in a time-controlled manner.

In one embodiment of the system according to the invention, the execution units are formed by a microprocessor, a co-processor, an arithmetic logic unit A-LU, a digital signal processor DSP, or by a floating-point calculation unit FPU (Floating Point Unit).

In a preferred embodiment of the system according to the invention, the programs to be executed thereon are identified such that it can be detected whether they are to be event-controlled or time-controlled. In one embodiment of the system according to the invention, interrupts are blocked in the timed execution of the program.

In an alternative embodiment of the system according to the invention, interrupts are not blocked in the timed execution of the program.

In one possible embodiment of the system according to the invention, this is formed by a dual-core system with two execution units.

In one embodiment of the system according to the invention, the multiprocessor system has at least three execution units.

In one embodiment of the system according to the invention, at least two execution units of the three execution units execute the same program simultaneously in a comparison operating mode (VM).

In one embodiment of the system according to the invention, the program is executed at the same time by at least two execution units.

In one embodiment of the system according to the invention, a switching and a comparison circuit is provided, to which all execution units are connected.

In one embodiment of the system according to the invention, the multiprocessor system can be switched between a performance operating mode (PM) and a comparison operating mode (VM).

In one embodiment of the system according to the invention, this has a first group of execution units, each of which executes programs in an event-controlled manner, and a second group of execution units, each of which executes programs in a time-controlled manner.

In one embodiment of the inventive system, one set of execution units is switchable between a performance mode of operation (PM) and a comparison mode of operation (VM) independently of the other set of execution units.

In this case, the two groups of execution units preferably each have at least two execution units. In one embodiment of the system according to the invention, the switching and comparison circuit in each of the two groups of execution units, when switched in the comparison mode of operation (VM), performs a majority decision on the basis of the signals delivered by the execution units of that group and switches that signal on Further data processing, which has the least signal deviation to the other, issued by the execution units of this group signals.

In one embodiment of the system according to the invention, an execution unit operated in a comparison operating mode VM has high signal deviations from the remaining execution units of the same group of output signals, then performs a self-test in a performance operating mode PM.

In this case, the execution unit is preferably deactivated when the self-test shows that this execution unit is faulty.

In one possible embodiment of the system according to the invention, a predetermined angular position of an engine crankshaft achieved during the event-controlled execution of a program constitutes a triggering event.

The system according to the invention can be used in particular for controlling a motor.

The engine may be, for example, an electric motor or an internal combustion engine.

In the following, preferred embodiments of the system according to the invention will be described with reference to the attached figures to explain features essential to the invention.

Show it:

Figure 1 is a block diagram of a possible embodiment of the invention

system;

FIG. 2 shows a dual-core system for illustrating a possible embodiment of the system according to the invention; FIG. 3 shows a dual-core system for illustrating a further embodiment of the system according to the invention;

4 shows a dual-core system for illustrating a further embodiment of the system according to the invention.

As can be seen from FIG. 1, a switching and comparison circuit 1 is connected on the input side to N + 1 execution units 2 and receives logic input signals E ₀ , Ei, E ₂ , E ₃ ... E _N from the execution units 2 -i. The switching and comparison unit 1 contains a comparison logic IA and a switching logic IB.

The system 3 or multiprocessor system shown in FIG. 1 can be operated in at least two operating modes. In a first operating mode for increasing performance, which is also referred to as a performance operating mode PM, the execution units 1-i or cores process different programs or tasks in parallel. The execution units 2-i can be any execution units 2-i for executing a calculation instruction, for example a processor, a floating point calculation unit FPU, a digital signal processor DSP, a co-processor or an arithmetic logical calculation unit ALU. The execution of the programs by the various execution units 2-i in the performance mode PM can be carried out synchronously or asynchronously. In the power mode, no redundant processing takes place, but the execution units 2-i carry out different calculations or programs in parallel. In pure performance mode PM, all input signals E, are switched to respective output signals A ₁ and passed.

In addition to the use of a higher-performance calculation system, the second reason for a multi-core architecture is to increase the security of the signal processing by redundantly executing the same program by a plurality of execution units 2-i. In this second operating mode, which is also referred to as safety mode or comparative mode VM, the results or logic output signals of the execution units are compared by the switching and comparison circuit 1, so that an error or a signal deviation by a Comparison can be detected on agreement. In the pure comparison operating mode VM, therefore, all the input signals E ₁ are only routed or imaged to exactly one single output signal A ₁ . Mixed forms are possible. The configurable switching logic IB indicates how many output connections or output signals A ₁ are provided. Furthermore, the switching logic IB stores which input signals E _{1 contribute} to which of the output signals A ₁ . In the switching logic IB thus a mapping function is stored, the input signals E, different output signals A, assign.

The processing logic IA determines at each output signal A ₁ how the input signals contribute to the respective output signal. For example, the output signal A _{0 is} generated by the input signals Ei, ..., E _N. For M = I, this simply corresponds to switching through an input signal. For M = 2, two input signals Ei, E ₂ are compared with each other. This comparison can be performed synchronously or asynchronously by the circuit 1. The comparison can be done bit by bit or alternatively only significant bits are compared. With M> 3 there are different possibilities. A first possibility is that all signals are compared with each other and an error is detected in the presence of at least two different values, which is optionally signaled by the switching and comparison circuit 1. Another possibility is to make a K m selection, where K> M / 2. This is realized in one embodiment by the provision of comparators. Optionally, a first error signal is generated when one of the input signals is detected as being different from the other input signals. In a second error signal different from the first error signal, all three input signals may differ from one another. In a further embodiment, the input signal values are fed to a further calculation unit which, for example, calculates an average value or a median value or performs a fault-tolerant algorithm FTA. In a fault-tolerant algorithm, the extreme values of the input signal values are canceled or ignored, and an averaging is carried out over the remaining signal values. In one embodiment, averaging occurs over the entire set of the remaining signal values. In an alternative embodiment, an averaging is carried out via a subset of the remaining signal values that is easy to form in the hardware. While only one addition and one division need to be made in averaging, FTM, FTA, or median generation require partial sorting of the input signal values. In one embodiment, if the signal deviations or extreme values are sufficiently large, an error signal is optionally output or displayed. The various mentioned possibilities for signal processing to a signal represent comparison operations. The processing logic IA determines the exact design of the comparison operation to be performed for each output signal A ₁ and thus also for the input signals E ₁ . The combination of the information within the switching logic IB, ie the assignment function of the comparison operation per output signal or per function indicated in the processing logic IA. onswert represents operating mode information and sets the operating mode. This information is usually multivalued and represented by more than one logical bit. In the event that only two execution units 2-i are provided, and thus only one comparison mode exists, all the information in the operating mode can be compensated for a single logical bit.

A changeover of the system 3 from the performance operating mode PM to a comparison operating mode VM is generally carried out in that the execution units 2-i, which are mapped to different signal outputs in the performance operating mode PM, are in the comparison operating mode VM can be mapped or switched through to the same signal output. This is preferably achieved by providing a subset of execution units 2-i in which all input signals E "to be taken into account in the subset are switched directly to corresponding output signals A ₁ in the performance operating mode PM, while the input signals In the comparison mode VM all are mapped to a single signal output or switched to this. Alternatively, a switch can be realized by changing pairings.

Between the different operating modes, the software can be used to switch dynamically during operation. In one embodiment, the switching is triggered by the execution of special switching commands or switching instructions, special instruction sequences, explicitly marked instructions or by accessing specific addresses by at least one of the execution units 2-i of the system 3.

Switching between the safety mode VM, in which a redundant processing and testing takes place and the performance or performance mode PM, in which an increase in performance is achieved by separate program processing, is carried out by the switching device 1. In one embodiment, carried to switch a Kenn - Drawing the programs, application programs, program parts or even the program commands by an identifier, which can be seen whether these program commands are security-relevant, that must be processed in the comparison mode VM operation, or the performance or performance mode PM can be made accessible , The identification can be done by a bit in the program instruction. Alternatively, the following sequence can be identified by a special program command. In the comparison operating mode VM, the calculation of the results or output signals of the execution units 2-i with synchronous execution on the different execution units 2-i takes the same amount of time. The results are then simultaneously available in the safety mode VM with synchronous processing of the switching device 1. If the results agree, the corresponding data will be released. If there is a signal deviation, a predetermined error reaction occurs.

If the system 3 is in the performance mode PM, the programs are processed in parallel and comparators or comparisons within the switching and comparison circuit 1 are not activated.

FIG. 2 shows a possible embodiment of the system 3 according to the invention. In the embodiment shown in FIG. 2, the system 3 has a dual-core system with two execution units 2A, 2B. In the embodiment shown in FIG. 2, the execution unit 2A executes programs exclusively event-controlled (ET: Event Triggered) and the other execution unit 2B executes programs exclusively time-controlled (TT: Time Triggered). The two execution units 2 A, 2 B are connected to a switching and comparison circuit 1, which is described in detail in connection with FIG. The execution units 2A, 2B may be a microprocessor, a co-processor, an arithmetic logic unit ALU, a digital signal processor DSP, a floating-point calculation unit FPU, or any arbitrary calculation unit. The programs or tasks running on the cores or execution units 2A, 2B are marked in such a way that it is possible to detect whether they are to be executed in an event-controlled or time-controlled manner. The programs can be application programs or programs of the operating system BS. For example, in the multiprocessor system 3 according to the invention, as shown in FIG. 2, a first part of the operating system BS runs on the execution unit 2A, while another part of the operating system BS is executed on the execution unit 2B. Preferably, it is determined for each output or thread or task or process offline whether it has event-triggered or event-triggered ET or timed or time-triggered TT expired. The number of processes or programs is divided into programs that are event-driven and programs that are time-controlled. When a program or process for scheduling or assignment to a processor core is pending online, it is checked to which type of programs the process belongs. In one possible embodiment, it is determined by means of an identifier provided in the program whether this program or this program part or this task is to be executed in an event-controlled or time-controlled manner. An event-controlled program part is executed in the case of FIG. 2 In the embodiment shown, the execution unit 2A and a time-controlled program part are assigned to the execution unit 2B.

In a further embodiment of the system 3 according to the invention, interrupts that can occur in the system are also assigned offline to the various operating modes. Optionally, these interrupt-specific programs or tasks are assigned functionally, so that preferably a corresponding assignment also takes place for the execution units 2.

In one possible embodiment, interrupts are blocked in a scheduled execution of a program for an execution unit.

In another embodiment, only time interrupts are allowed in the timed execution of a program.

In the embodiment shown in FIG. 2, the system 3 is a dual-core system with two execution units 2A, 2B. In further embodiments, the system 3 has at least three execution units 2. At least two execution units 2 of three execution units in a comparison operating mode VM preferably execute the same program. In one possible embodiment, the program executed simultaneously by the two execution units 2 is executed in a time-controlled manner.

In one possible embodiment of the system 3 according to the invention, the system 3 has a first group of execution units 2, each of which executes programs in an event-controlled manner, and a second group of execution units 2, which execute programs in a time-controlled manner. For example, each group in turn has two execution units 2, so that the system 3 in this embodiment contains a total of four execution units 2.

In this case, preferably the first group of execution units 2 can be switched over independently of the second group of execution units 2 between a performance operating mode PM and a comparison operating mode VM. For example, two execution units 2 of the first group of execution units 2 in a performance mode PM independently operate on different programs, while execution units 2 of the other group simultaneously execute the same program in the compare operation mode VM. The group of execution units 2 includes In a preferred embodiment, at least two execution units 2 each. The execution units 2 are connected to the switching and comparison circuit 1. When the execution units 2 are switched in the comparison operating mode VM, the switching and comparison circuit 1 preferably performs a majority decision based on the signals output by the execution units 2 of this group and switches the signal for further data processing which gives the least signal deviation the other output from the execution units 2 of this group signals.

In a preferred embodiment, an execution unit 2 operated in the comparison operating mode VM has its output signal having a high signal deviation from the remaining execution units 2 of the same group of output signals output, then performs a self-test in a performance operating mode PM. If this self-test indicates that the execution unit 2 is actually faulty, this is subsequently deactivated in one possible embodiment.

The system 3 according to the invention is particularly suitable for a motor control. In the case of a motor control, on the one hand there are predominantly time-controlled processes or programs which run in a fixed time frame, for example a safety monitoring or a driver request inquiry. On the other hand, there are event-controlled processes, in particular processes or programs that run synchronously with the crankshaft. The rotational speed of a crankshaft for driving a piston within an engine is not absolutely constant. Therefore, a sensor, for example an angle sensor, which indicates the angle of rotation of the crankshaft is provided on the crankshaft. If the crankshaft reaches a specified angular position, the angle sensor triggers an interrupt, which represents an event. During the event-driven execution of a program and when the event occurs, the program or the task is triggered or its execution triggered. Another example of such events is, for example, a flag issued by a program to indicate that the program is finished. Such events can trigger a software or hardware interrupt.

In the timed execution of a program, a program is started or triggered when a system clock reaches a certain time value. In such a timed execution of a program, the execution of the programs is usually done periodically. For example, certain sensors are read out every 1 ms, a control program is called for an actuator every 10 ms, a monitoring program is called every 20 ms and a temperature sensor is read out every 40 ms. The longest period duration is for example 40 ms, so that the program calls repeat every 40 ms.

The system 3 according to the invention makes it possible to decouple event-controlled programs from time-controlled programs. In particular, it is possible to ensure that a logically sequential sequence of crank-synchronous processes or event-triggered programs are not interrupted by timed programs, so that the number of task changes, including the administration time required for this purpose, is minimized. Conversely, it is ensured with the system 3 according to the invention that a logically consecutive sequence of time-controlled programs or processes is not interrupted by crankshaft-synchronous processes. As a result, the effort required to manage the program changes is minimized and the administrative overhead saved can be used effectively for a performance or performance gain. In addition, the system 3 according to the invention leads to a reduction of the complexity, since conflict cases with all their difficult-to-understand individual characteristics are avoided. This also facilitates the coding of software for the inventive system 3 considerably.

In a preferred embodiment of the system 3 according to the invention, all programs or tasks in the comparison mode VM are also time-controlled. The scheduling then triggers a sufficiently high prioritized interrupt on the event triggered part when a process or a program to be executed in the comparison operating mode VM occurs, so that event-triggered execution units 2 then execute the process in parallel, ie. H. can run VM in compare mode.

FIG. 3 shows a further embodiment of the system 3 according to the invention. In this embodiment, the first execution unit 2A executes programs not only event-triggered or event-triggered (ET), but additionally executes further program parts which are time-controlled (TT). The other execution unit 2B of the dual-core system 3 shown in FIG. 3 executes programs in a time-controlled manner. Such an embodiment is used in particular when the timed portion of the programs is significantly larger than the event-driven portion of the programs. The relatively small proportion of event-driven programs is executed by a single core or by a single execution unit 2A. Preferably, in this embodiment, in particular those time-controlled programs or operating system parts are executed by the execution unit 2A, which match the event-triggered programs also executed there. FIG. 4 shows a further embodiment of the system 3 according to the invention, in which case the event-triggered programs are divided between the two processors or execution units 2A, 2B, while the time-controlled program parts are executed exclusively by the first execution unit 2A. The embodiment shown in FIG. 4 is particularly suitable for systems in which the proportion of event-controlled programs or tasks is substantially greater than the proportion of time-controlled program parts.

The system 3 according to the invention is suitable for applications in which requirements are present both for time-controlled and for event-controlled execution of programs. The system 3 is used such that at least one execution unit 2 runs in a timed scheme, while the other execution unit 2 runs in an event-driven scheme. Thus, the two system strategies can be fulfilled simultaneously, without one strategy having a detrimental effect on the other strategy.

The system 3 according to the invention does not require separate optimization of the respective scheduling method for the time-controlled and event-controlled programs. The system 3 according to the invention is relatively simple in structure and less complex, since certain conflicts can not occur at all. This leads to a cost reduction in the variety, maintainability, traceability and testing of programs. By separating into event-controlled and time-controlled programs, a significant reduction in the number of task changes is achieved.

The system 3 according to the invention is particularly suitable for driving an engine. This engine may be, for example, an internal combustion engine, but also an electric motor.

Claims

claims

1. System with several execution units, wherein at least one execution unit (2A) executes programs event-controlled and at least one other execution unit (2B) executes programs only time-controlled.

2. System according to claim 1, wherein the execution unit (2) by a CPU, a co-processor, an arithmetic logic unit (ALU), a digital signal processor (DSP), or a floating point calculation unit FPU (Floating Point Unit) is formed.

3. System according to claim 1, wherein the programs to be executed are characterized in such a way that it is possible to detect whether they are to be executed in an event-controlled or time-controlled manner.

4. The system of claim 1, wherein interrupts are blocked in the timed execution of a program.

The system of claim 1, wherein interrupts are not blocked in the timed execution of a program.

The system of claim 1, wherein the system is a dual-core system having two execution units (2 A, 2 B).

The system of claim 1, wherein the system comprises at least three execution units (2).

8. System according to claim 6, wherein at least two execution units (2) of the three execution units in one Compare operation mode (VM) run the same program at the same time.

9. System according to claim 7, wherein the program is executed by at least two execution units (2) simultaneously time-controlled.

10. System according to claim 1, wherein a switching and comparison circuit (1) is provided, to which all execution units (2) are connected.

The system of claim 1, wherein the system (3) is switchable between a performance mode of operation (PM) and a comparison mode of operation (VM).

The system of claim 1, wherein the system (3) comprises a first group of execution units (2) each executing programs in an event-driven manner and a second group of execution units (2) each scheduling programs.

The system of claim 12, wherein one group of execution units (2) is switchable between a performance mode of operation (PM) and a comparison mode of operation (VM) independently of the other group of execution units (2).

The system of claim 12, wherein each of the two groups of execution units (2) has at least two execution units.

15. A system according to claim 14, wherein the switching and comparison circuit (1) in each of the two groups of execution units (2), when switched to the comparison operating mode (VM), makes a majority decision on the basis of the execution units (2). carries out signals emitted by this group and switches through that signal for further data processing which has the lowest signal deviation from the remaining signals emitted by the execution units (2) of this group.

A system according to claim 15, wherein an execution unit (2) operating in a comparative operation mode (VM) has a high signal deviation from the remaining execution units (2) of the same group of output signals, then in a performance mode of operation (PM) Self-test runs.

17. The system of claim 16, wherein an execution unit (2) is deactivated when the self-test indicates that this execution unit (2) is faulty.

18. The system of claim 1, wherein in the event-driven execution of a program, a predetermined angular position of an engine crankshaft forms a triggering event.

19. Use of the system (3) according to claim 1 for controlling an engine.

20. Use of the system according to claim 19, wherein the motor is formed by an electric motor.

21. Use of the system according to claim 19, wherein the engine is formed by an internal combustion engine.