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WO2007071787A1 - Procede de simplification d'une sequence de finition et structure obtenue par le procede - Google Patents

Procede de simplification d'une sequence de finition et structure obtenue par le procede Download PDF

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Publication number
WO2007071787A1
WO2007071787A1 PCT/EP2006/070177 EP2006070177W WO2007071787A1 WO 2007071787 A1 WO2007071787 A1 WO 2007071787A1 EP 2006070177 W EP2006070177 W EP 2006070177W WO 2007071787 A1 WO2007071787 A1 WO 2007071787A1
Authority
WO
WIPO (PCT)
Prior art keywords
donor substrate
sequence
thin layer
substrate
detachment
Prior art date
Application number
PCT/EP2006/070177
Other languages
English (en)
Inventor
Eric Neyret
Alice Boussagol
Nadia Ben Mohamed
Original Assignee
S.O.I.Tec Silicon On Insulator Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0513127A external-priority patent/FR2895563B1/fr
Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to DE112006003447T priority Critical patent/DE112006003447B4/de
Publication of WO2007071787A1 publication Critical patent/WO2007071787A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the field of the invention is the formation of structures comprising a thin layer made of a semi conducting material on a support substrate, by transferring the thin layer from a donor substrate to the support substrate.
  • Such structures are usually obtained by the use of a transfer process including steps to:
  • the invention more particularly relates, but is not limited, to the formation of structures with a particularly thin layer, in other words the thickness of the thin layer is typically less than 1000 Angstroms, and in particular less than 500 Angstroms.
  • SMART CUT ® type processes are an example of a transfer process for making structures of this type comprising a thin layer of semi conducting material on a support substrate. They correspond to a preferred embodiment of the invention.
  • the structures thus formed may for example be of the
  • SeOI semiconductor On Insulator
  • This type of treatment of the structure obtained directly after detachment typically consists of a sequence of finishing operations. This sequence judiciously leads to one or several steps aimed at thinning the structure obtained after detachment, with one or several steps aimed at smoothing the free surface of the said structure.
  • Thinning of the part of the donor substrate transferred onto the support substrate after detachment, to form the target thickness required for the thin layer may typically be implemented by one or several sacrificial oxidation and / or polishing operations.
  • a polishing operation is usually not desirable. Such an operation reduces the uniformity of the thickness of the transferred layer. Thus, when a polishing operation is built into the finishing sequence, it is impossible to guarantee that the standard deviation of the thickness of the transferred layer is less than 5 A over the entire thin layer.
  • Application of a sacrificial oxidation operation is limited. Such an operation tends to make some pre ⁇ existing defects pass through (leading to the formation of HF type defects) , particularly when a large part of the thickness of the transferred layer is eliminated.
  • an intermediate thermal annealing operation is usually made between two sacrificial oxidation steps, each of these two steps being designed only for limited thinning.
  • a fast thermal annealing is typically done under a controlled atmosphere using a mode commonly called RTA (Rapid Thermal Annealing) .
  • the finishing treatment step may be based on a "basic" sequence (that could be repeated) including a sequence consisting of a sacrificial oxidation operation followed by an RTA operation.
  • a single RTA operation cannot be efficient, particularly in terms of reducing the surface roughness, when it is implemented on the surface obtained directly after detachment.
  • the Applicant has proposed to combine a step to create a weakened zone formed by co-implantation with a finishing treatment step based on a "basic" sequence (that may possibly be repeated) including an RTA operation followed by a sacrificial oxidation operation.
  • the formation of a structure with a specified final thickness leads to additional calibration of equipment that depends on the residual thickness of the layer to be treated.
  • calibration of the lamps of an RTA type furnace is calibrated as a function of the thickness of the upper layer of an SeOI structure.
  • the finishing operation sequence selected as being preferred consists of repeating the sequencing of a rapid thermal annealing operation with a sacrificial oxidation operation.
  • This preferred sequence also called RTA/Sacrox/RTA/Sacrox (where "Sacrox" denotes a sacrificial oxidation) has the advantage of being high performance in terms of quality. But it has the disadvantage of including a large number of operations.
  • a first purpose of the invention is to simplify the finishing step, particularly by reducing the necessary number of operations without correspondingly risking compromising the quality of the final structure.
  • Another purpose of the invention is intended more precisely to authorise the use of a finishing treatment simpler than the preferred RTA/Sacrox/RTA/Sacrox sequence, particularly when forming a thin layer structure .
  • the invention discloses a process for the formation of a structure comprising a thin layer made of a semi conducting material on a substrate, including steps to create a weakened zone within the thickness of a donor substrate, to bring the donor substrate into intimate contact with a support substrate, to detach the donor substrate at the weakened zone to transfer part of the donor substrate onto the support substrate, to treat the said part of the donor substrate transferred onto the support substrate to form the said thin layer, the said treatment consisting of a sequence of finishing operations; the process being characterised in that:
  • - detachment is achieved by the application of a heat treatment to develop weakening of the weakened zone, without initiating thermal detachment of the said part of the donor substrate; and application of an energy pulse provoking self-maintained detachment of the said part of the donor substrate;
  • sequence of finishing operations is a sequence simplified by eliminating the first or the last operation of a sequence consisting of repeating the sequencing of a smoothing operation of the free surface of the said part of the donor substrate transferred onto the support substrate, with a thinning operation of the said part of the donor substrate transferred onto the support substrate.
  • the simplified sequence is obtained by eliminating the last operation, and consists of a smoothing operation inserted between two thinning operations;
  • the smoothing operation is a thermal annealing
  • the thermal annealing is a rapid thermal annealing RTA; - the two smoothing operations by rapid thermal annealing RTA are merged into a single batch annealing operation with a smoothing effect equivalent to at least two rapid thermal annealing RTA operations, performed before the thinning operation; - the thinning operation is a sacrificial oxidation operation; the thermal budget of the treatment for development of weakening corresponds to 60% or more (and preferably 80% or more) of the thermal budget leading to a purely thermal detachment;
  • the heat treatment for development of weakening is an isothermal annealing at 35O 0 C for a duration of between two and three hours;
  • the weakened zone is created by implantation of species in the thickness of the donor substrate, the said implantation being applied by implantation of a single species or by co-implantation of at least two different species;
  • the invention relates to an SeOI structure with a thin layer made of a semi conducting material on a support substrate, an insulating layer being inserted between the thin layer and the substrate, the thickness of the thin layer being less than 1000 Angstroms, and particularly less than 500 Angstroms, characterised in that the density of HF defects in the thin layer is less than 0.3/cm 2 , and in particular is less than 0.2/cm 2 .
  • the surface roughness of the thin layer as measured by scanning over a surface with an area equal to 10*10 ⁇ m 2 is less than 5 A RMS, over the entire surface;
  • the standard deviation of the thickness of the thin layer is less than 5 A, over the entire surface.
  • FIG. 1 is a map illustrating the presence of through defects in a thin layer of a structure obtained by use of a process according to the state of the art, particularly at the edge of the wafer;
  • - Figure 2 is a map illustrating the small number of through defects in a thin layer obtained by the use of one possible embodiment of the process according to the invention
  • - Figures 3a to 3d illustrate the different steps in the process according to the invention
  • - Figure 4 is a diagram illustrating the gain in terms of roughness obtained by the use of one possible embodiment of the process according to the invention.
  • the sequence of finishing operations selected as being preferred consists of repeating the sequence of a rapid thermal annealing
  • RTA sacrificial oxidation
  • a first simplification could consist of eliminating the last operation in the preferred RTA/Sacrox/RTA/Sacrox sequence to use a first simplified RTA/Sacrox/RTA sequence. But this first simplified sequence is not satisfactory, particularly for the formation of a structure with a thin layer. This simplified RTA/Sacrox/RTA sequence could generate "HF" type defects with a depth greater than the thickness of the thin layer of the final structure (so-called through defects) .
  • these defects are located particularly in a dense zone Zd located at the edge of the wafer.
  • This phenomenon varies in intensity, depending on operating conditions of the steps of forming the weakened zone and of detachment. And obviously, the thinner the thin layer of the final structure, the more the phenomenon becomes problematic.
  • the dense zone Zd corresponds to the zone at the edge of the wafer at which detachment is initiated. Therefore, it is a rougher zone than the remainder of the wafer, and this cannot be completely cured by the first
  • the extensive thinning also done during a single sacrificial oxidation operation so that the end result obtained is a thin layer with a specified fine thickness, leads to the formation of HF type through defects.
  • through defects cannot be cured by RTA type annealing.
  • the defects formed by the thinning operation cannot be cured by the final RTA smoothing operation.
  • a second simplification could consist of eliminating the first operation in the preferred
  • RTA/Sacrox/RTA/Sacrox sequence to replace it with a second simplified RTA/Sacrox/RTA sequence.
  • This second simplified sequence is not satisfactory either. Apart from possible problems of through defects, this second simplified sequence can also generate roughness problems, particularly at the edge of the wafer . As mentioned above, a dense rough zone is observed at the edge of the wafer immediately after detachment. The use of a single RTA smoothing operation cannot compensate for this edge roughness at the dense zone Zd.
  • Figures 3a - 3c show the different steps in one possible embodiment of the process according to the invention.
  • Figure 3a shows a donor substrate 1, for example a silicon substrate oxidised on its surface 4, subject to implantation shown diagrammatically by arrows, of species to create a weakened zone 3 within the thickness of the donor substrate 1.
  • the implantation of atomic species may be a simple implantation (i.e. implantation of a single atomic species) , for example such as an implantation of hydrogen, helium or rare gases.
  • the implantation of atomic species may also be a co- implantation of atomic species (i.e. successive or simultaneous implantation of at least two different atomic species) , for example a co-implantation of hydrogen and helium.
  • Some examples of implantation conditions include the following:
  • the dose is between 5 and 7 x 10 16 cm “2 , and the energy is between 10 and 200 keV. Preferably, the dose is 5.7 x 10 16 cm “2 and the energy is 37 keV.
  • Co-implantation of helium and hydrogen In general, for helium the dose is between 0.5 x 10 16 cm “2 and 3 x 10 16 cm “2 and the energy is between 10 and 200 keV (preferably dose between 1 x 10 16 cm “2 and 2 x 10 16 cm “2 and energy about 50 keV) ; and for hydrogen the dose is between 0.5 x 10 16 cm-2 and 3 x 10 16 cm “2 and the energy is between 10 and 200 keV (preferably dose between 1 x 10 16 cm “2 and 2 x 10 16 cm “2 , and energy about 30 keV) .
  • Figure 3b shows the step during which the donor substrate 1 is brought into intimate contact with a support substrate 7 through its face 4.
  • the detachment step generally consists of thermal annealing during which a spontaneous detachment occurs. In other words, it is a purely thermal detachment.
  • This invention proposes to use another detachment mode, namely a detachment made by:
  • the heat treatment applied herein to develop weakening is interrupted before detachment is initialised.
  • the weakening development heat treatment applied within the framework of the invention is designed to apply a thermal budget (duration and temperature pair) close to the thermal budget necessary to result in a purely thermal detachment.
  • thermal budget applied in the context of the invention corresponds to 60% or more, and preferably 80% or more, of the thermal budget leading to a purely thermal detachment.
  • the heat treatment to develop weakening is done in the form of an isothermal annealing at 35O 0 C for a duration of between two and three hours.
  • the heat treatment to develop weakening applied during detachment will also enable consolidation of the bonding interface between the donor substrate and the support substrate in intimate contact.
  • Figure 3c shows the actual detachment of a part of the donor substrate 5 with regard to the remainder 6 of donor substrate 1, using application of an input energy pulse, preferably with short duration and limited amplitude.
  • the part 5 is thus transferred onto the support substrate 7.
  • this energy input may be composed of a mechanical stress shown diagrammatically by arrow 10 in Figure 3c.
  • One non-limitative way of making this mechanical input is to use equipment similar to that conventionally used to separate the wafers after application of a purely thermal detachment (the term automatic separation machine is also used) .
  • the mechanical force applied by such separation equipment may be sufficient to cause self- maintained detachment.
  • the detachment obtained is self-maintained particularly in the sense that, unlike a purely mechanical detachment, there is no movement of a tool along the weakened zone.
  • these surfaces have a relatively smooth surface condition, and the free face 9 of the thin layer 5 transferred onto the donor substrate in particular has much lower roughness than it has with classical solutions using spontaneous detachment during thermal annealing
  • the structure obtained after detachment treated by the said simplified sequence is the structure including the support substrate
  • the purpose of this sequence is to thin the part 5 to obtain the target thickness for the thin layer, to reduce the surface roughness and guarantee good quality in terms of defects.
  • the end result after this treatment is the required final structure including the thin layer 8 (particularly with the target thickness) on the support substrate 7 (see Figure 3d) .
  • the simplified sequence is the first simplified sequence mentioned above, namely the RTA/Sacrox/RTA sequence.
  • this first mode is advantageous in the framework of the formation of structures with a thin layer (thickness less than 1000 Angstroms and particularly less than 500 Angstroms) particularly in that it provides a means of preventing the appearance of through defects.
  • this first embodiment can lead to the formation of a 300 mm diameter SOI structure, for which the silicon thin layer is 350 Angstroms thick and for which the density of "HF" type defects is less than 0.3 defects / cm 2 , or even less than 0.2 defects / cm 2 .
  • the production of an RTA annealing immediately after "self-maintained" detachment provides a means of avoiding the appearance of holes that could open up after application of the sacrificial oxidation operation.
  • the second RTA annealing can then complete the cure of residual defects, while slightly further reducing the surface roughness of the thin layer.
  • Figure 2 is a map similar to that in Figure 1 illustrating the small number of through defects in a particularly thin layer (thickness 350 Angstroms) obtained by use of this first possible embodiment.
  • the invention also plans to use a single annealing operation, instead of two RTA annealing operations; this single annealing operation having an equivalent or even better smoothing effect than two RTA operations.
  • such a single annealing operation may consist of annealing in a furnace (also called "Batch Anneal”.
  • the simplified sequence then consists of a thermal batch annealing operation followed by a sacrificial oxidation operation.
  • “Batch Annealing” may be done under a hydrogen and / or argon atmosphere for a duration of between five minutes and four hours.
  • the simplified sequence is the second simplified sequence mentioned above, namely the Sacrox/RTA/Sacrox sequence.
  • this embodiment prevents the appearance of through defects, it also provides a means of achieving particularly low roughness at the edge of the wafer.
  • Figure 4 shows a measurement of the roughness R obtained by a scan across a 30*30 ⁇ m 2 area of the thin layer of the final structure, using an atomic force microscope AFM at the edge of the wafer (see round marks) and at the centre of the wafer (see square marks) .
  • the thin layer is more precisely a silicon layer with an SOI structure with a thickness of 1000 Angstroms.
  • This Figure 4 compares the surface roughness of the thin layer during use of the simplified Sacrox/RTA/Sacrox finishing sequence following detachment conforming with that disclosed in the invention (case A, at the left in Figure 4) and following a purely thermal detachment (case B, at the right in Figure 4) .
  • the rapid thermal annealing RTA operation is conventionally done for a duration of a few seconds or a few tens of seconds under a controlled atmosphere.
  • the said structure is annealed at a high temperature, for example of the order of 900 0 C to 1300 0 C for 1 to 16 seconds.
  • the controlled atmosphere may be an atmosphere comprising a mix of argon and hydrogen, or an atmosphere of pure argon, or an atmosphere of pure hydrogen.
  • the sacrificial oxidation operation is broken down in a manner conventionally known in itself into an oxidation step and a de-oxidation step, a heat treatment being inserted between the oxidation step and the de-oxidation step .
  • the oxidation step is preferably carried out at a temperature of between 700 0 C and HOO 0 C.
  • the oxidation atmosphere may also contain hydrochloric acid, both in dry method and in wet method.
  • the oxidation step leads to the formation of an oxide layer on the surface of the thin layer.
  • the heat treatment may be carried out at constant or variable temperature.
  • the heat treatment is preferably done at a temperature between 1100 and 1200 0 C under an oxidising atmosphere.
  • the de-oxidation step performed after the heat treatment removes the oxide layer formed during the oxidation step. For example, it is done by immersing the structure for a few minutes into a solution of 10% to 20% hydrofluoric acid.
  • sacrificial oxidation as being a preferred form of a thinning operation.
  • the invention is absolutely not limited to this preferred form, and includes other types of thinning operations, for example such as dry etching
  • the invention also covers "thin layer on support substrate" structures, and particularly SeOI structures obtained by use of the process according to the first aspect of the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

Selon un premier aspect, la présente invention concerne un procédé de formation d'une structure comprenant une couche mince (8) constituée d'un matériau semi-conducteur sur un substrat (7), dont les étapes consistent à créer une zone affaiblie (3) à l'intérieur de l'épaisseur d'un substrat donneur (1), à mettre le substrat donneur (1) en contact intime avec un substrat support (7), à détacher le substrat donneur (1) au niveau de la zone affaiblie (3) pour transférer une partie (5) du substrat donneur (1) sur le substrat support (7), à traiter ladite partie (5) du substrat donneur transférée sur le substrat support pour constituer ladite couche mince (8), ledit traitement consistant en une séquence d'opérations de finition. Le procédé est caractérisé en ce que le détachement est réalisé par l'application d'un traitement thermique pour développer l'affaiblissement de la zone affaiblie (3), sans initier le détachement thermique de ladite partie du substrat donneur, et l'application d'une impulsion d'énergie (10) provoquant un détachement autonome de ladite partie (5) du substrat donneur; et en ce que la séquence d'opérations de finition est une séquence simplifiée par l'élimination de la première ou de la dernière opération d'une séquence consistant à répéter le séquençage d'une opération de lissage de la surface libre (9) de ladite partie (5) du substrat donneur transférée sur le substrat support, avec une opération d'amincissement de ladite partie (5) du substrat donneur transférée sur le substrat support.
PCT/EP2006/070177 2005-12-22 2006-12-22 Procede de simplification d'une sequence de finition et structure obtenue par le procede WO2007071787A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112006003447T DE112006003447B4 (de) 2005-12-22 2006-12-22 Prozess zur Ausbildung einer Anordnung, die eine Dünnschicht aufweist

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0513127 2005-12-22
FR0513127A FR2895563B1 (fr) 2005-12-22 2005-12-22 Procede de simplification d'une sequence de finition et structure obtenue par le procede
US11/356,926 US7514341B2 (en) 2005-12-22 2006-02-16 Finishing process for the manufacture of a semiconductor structure
US11/356,926 2006-02-16

Publications (1)

Publication Number Publication Date
WO2007071787A1 true WO2007071787A1 (fr) 2007-06-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010049497A1 (fr) * 2008-10-30 2010-05-06 S.O.I.Tec Silicon On Insulator Technologies Procédé de détachement de couches semi-conductrices à basse température
CN103377879A (zh) * 2012-04-17 2013-10-30 国际商业机器公司 深度受温度控制的释放层的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1193749A2 (fr) * 2000-09-29 2002-04-03 Canon Kabushiki Kaisha Méthode de recuit d'un SOI et méthode de fabrication d'un SOI
US20040166650A1 (en) * 2003-02-26 2004-08-26 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer and SOI wafer
US20040248380A1 (en) * 2003-06-06 2004-12-09 Cecile Aulnette Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer
US20050014346A1 (en) * 2001-11-29 2005-01-20 Kiyoshi Mitani Production method for soi wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1193749A2 (fr) * 2000-09-29 2002-04-03 Canon Kabushiki Kaisha Méthode de recuit d'un SOI et méthode de fabrication d'un SOI
US20050014346A1 (en) * 2001-11-29 2005-01-20 Kiyoshi Mitani Production method for soi wafer
US20040166650A1 (en) * 2003-02-26 2004-08-26 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer and SOI wafer
US20040248380A1 (en) * 2003-06-06 2004-12-09 Cecile Aulnette Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010049497A1 (fr) * 2008-10-30 2010-05-06 S.O.I.Tec Silicon On Insulator Technologies Procédé de détachement de couches semi-conductrices à basse température
FR2938119A1 (fr) * 2008-10-30 2010-05-07 Soitec Silicon On Insulator Procede de detachement de couches semi-conductrices a basse temperature
CN102197473A (zh) * 2008-10-30 2011-09-21 S.O.I.Tec绝缘体上硅技术公司 低温下剥离半导体层的方法
KR101304245B1 (ko) * 2008-10-30 2013-09-05 소이텍 저온에서 반도체층들을 분리하는 방법
US8623740B2 (en) 2008-10-30 2014-01-07 Soitec Method of detaching semi-conductor layers at low temperature
KR101446977B1 (ko) * 2008-10-30 2014-10-07 소이텍 저온에서 반도체층들을 분리하는 방법
CN103377879A (zh) * 2012-04-17 2013-10-30 国际商业机器公司 深度受温度控制的释放层的制造方法

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