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WO2007045377A1 - Procede pour commander un circuit numerique, et circuit numerique correspondant - Google Patents

Procede pour commander un circuit numerique, et circuit numerique correspondant Download PDF

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Publication number
WO2007045377A1
WO2007045377A1 PCT/EP2006/009760 EP2006009760W WO2007045377A1 WO 2007045377 A1 WO2007045377 A1 WO 2007045377A1 EP 2006009760 W EP2006009760 W EP 2006009760W WO 2007045377 A1 WO2007045377 A1 WO 2007045377A1
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WO
WIPO (PCT)
Prior art keywords
operations
components
voltage level
digital circuit
voltage
Prior art date
Application number
PCT/EP2006/009760
Other languages
German (de)
English (en)
Inventor
Thomas Schweizer
Tobias Oppold
Julio Oliveira Filho
Wolfgang Rosenstiel
Tommy Kuhn
Original Assignee
Universität Tübingen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universität Tübingen filed Critical Universität Tübingen
Priority to EP06806137A priority Critical patent/EP1941339A1/fr
Publication of WO2007045377A1 publication Critical patent/WO2007045377A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to a method for controlling a digital circuit having at least two components for performing different operations and at least one control unit for outputting control commands and for driving the components in dependence on an operation to be performed.
  • the invention also relates to a digital circuit, a method for configuring a digital circuit, a digital storage medium and a computer program product.
  • timing critical blocks of the circuit operate on the normal supply voltage, whereas in time uncritical blocks work with a second, lower supply voltage.
  • Another known way of reducing the power consumption is to reduce the clock frequency of a digital circuit, since the power consumption is directly proportional to the clock frequency and square dependent on the supply voltage.
  • Approaches that provide a reduction in clock frequency seek to identify non-critical digital circuit performance or operating modes that may or may be run at lower clock frequencies.
  • the reduction in the supply voltage usually results in such delays in the signal propagation in a digital circuit that the clock frequency must also be adjusted or the delays otherwise compensated by clock management.
  • DVS Dynamic Voltage Scaling or Dynamic Voltage Adjustment
  • AVS Adaptive Voltage Scaling or Adaptive Voltage Adjustment
  • DVS and AVS require an adjustment of the clock frequency and additional functions in the hardware and / or the operating system. DVS and AVS are therefore worthwhile only if very long idle times of a circuit are to be expected.
  • a dynamic voltage control is provided, in which case both the supply voltage and the clock frequency of the processor are set so low that the application software is just processed correctly.
  • CVS Current Voltage Scaling
  • ASIC design application specific integrated circuit
  • FPGA field programmable gate array
  • a method for controlling a digital circuit having at least two components for carrying out different operations and at least one control unit for outputting control commands and for controlling the components as a function of an operation to be executed, in which a voltage level for the components is determined by means of the at least one control unit is selected depending on the operation to be performed and / or other constraints.
  • the method according to the invention is thus a combination of temporal voltage adaptation and spatial voltage adaptation.
  • the components are supplied with alternating supply voltages, depending on the operation to be carried out or other boundary conditions, for example a concatenation of several operations.
  • the different components can be subjected to alternating supply voltages. This means that each component or each stress island individually depending on one to be executed operation and thereby the supply voltage of these components or voltage islands can be changed at runtime.
  • it is thus not spatially fixed voltage islands that can be supplied dynamically with different supply voltage, but each component can be made only during the term to a voltage island with respect to the adjacent component different supply voltage.
  • control unit of a circuit such as a finite state machine (FSM) not only controls components for selecting a data path, such as a multiplexer, but also a voltage switch, especially transistors, with which the supply voltage for a component is selected.
  • FSM finite state machine
  • a voltage switch especially transistors, with which the supply voltage for a component is selected.
  • switching between two or more voltage levels beyond a supply voltage can also be reduced so far, for example, to zero that functional units or components are completely switched off to reduce the leakage currents, the more and more important with the ever smaller feature sizes of modern semiconductor technologies win.
  • the prerequisite for this is, of course, that components or functional units are not required in every clock cycle.
  • the selection of a voltage level for a component to perform a particular operation is part of the processing of one or more control instructions causing the operation to be performed.
  • the selection of the voltage level keeps pace with the execution of the control commands for performing the individual operations.
  • Components that can be subjected to different voltage levels can generally be components for communication, components for storage and components for calculation. Specifically, for example, multiplexers, registers, memory blocks, buses and arithmetic logic Units, so-called ALUs are subjected to different voltage levels.
  • the method according to the invention thus operates preferably on a command basis in which a suitable supply voltage is stored or determined for a control command to be processed, in order to ensure that the operation to be executed can be completed within the prescribed cycle time, but at the same time the supply voltage is lowered so that a reduction the energy intake is achieved.
  • the spatial and temporal voltage adaptation is thus implemented at the command level, it comes into play at the runtime of a program to be processed and is thus reconfigurable in principle. Reconfigurable is also considered when the temporal and spatial voltage adjustment is realized for example by means of no longer variable control commands in a read-only memory. It is essential that the spatial and temporal voltage adaptation is implemented at the command level, so that it can be reconfigured in principle, for example by replacing a read-only memory, after the actual production of an integrated circuit.
  • the inventive method can be used in coarse-grained, reconfigurable architectures, but also in the design of ASICS (application-specific integrated circuit), in which the function to be performed is fixed, but individual operations are also triggered by a possibly hard-wired control unit.
  • ASICS application-specific integrated circuit
  • the method according to the invention for reducing the power consumption can be realized.
  • development tools for realizing the spatial-temporal voltage adaptation according to the invention can be integrated into software tools for hardware synthesis.
  • Coarse granular configurable circuits are currently being manufactured and sold, for example, by NEC under the designation DRP (Dynamically Reconfigurable Processor) and by PACT under the designation XPP (Extreme Processor Platform).
  • the components are at least partially designed as functional units for performing different arithmetic and logical operations, in particular so-called ALUs, each component is assigned a control unit and / or at least one component and associated control unit are provided in a reconfigurable processing unit.
  • a reconfigurable architecture in which, according to the invention, different processing units are subjected to different supply voltages depending on the operations to be performed.
  • reconfiguring an overall operation to be performed also adjusts the associated voltage configuration because the voltage configuration is implemented as well as performing the commands at the control command level.
  • the selection of the voltage level can be done by the control unit directly or indirectly, with the interposition of a another selection level, in particular a memory to be made.
  • an operator chaining is provided as a further boundary condition in which at least two individual operations are linked without buffering the result.
  • operator chaining so-called operation chaining
  • operation chaining may influence the selection of the voltage level such that, when multiple operations are concatenated, they are executed at a higher voltage level to complete the end result in a timely manner.
  • a high voltage level is selected for first predetermined operations, in particular additions, a low voltage level and for second predetermined operations, in particular multiplications.
  • the selection and optionally the corresponding switching of a voltage level for the functional unit occurs at each clock or for a few clocks, in particular less than ten to twenty clocks.
  • the optimum voltage level in terms of power consumption and the total processing time can be selected for each sub-operation within an application to be executed. Since according to the invention a spatial-temporal chip adaptation is provided, the realization of the dynamic voltage adjustment, for example, take place only when an assignment of individual sub-operations has already been made to certain processing units of a digital circuit. A division into sub-operations, including the assignment of the sub-operations to individual processing units, chosen for achieving an optimum processing time can still be optimized in terms of power consumption in a subsequent step, without changing the processing time for the entire operation to be performed. The goal of a significantly reduced power consumption can be achieved without compromising the performance of a digital circuit. In particular, when a voltage adjustment takes place at each cycle, particularly high savings in the energy absorbed can be achieved. However, the advantages according to the invention also already appear when a voltage adjustment of the individual functional units is performed only for a few cycles.
  • the selection and, where appropriate, the corresponding switching of a voltage level for the functional unit takes place for each control command for one operation or for a few control commands, in particular less than ten to twenty control commands.
  • the realization of the method according to the invention at the command level makes it possible to select the optimum supply voltage for the operation corresponding to the control command for each control command.
  • the selection of a supply voltage can, as already mentioned, be carried out on the basis of fixed allocations, so that, for example, always carry out with low supply voltage and multiplications always high supply voltage to the required execution time for addition and multiplication largely together equalize.
  • no clock change takes place independently of the selection of the voltage level.
  • the voltage switching can be done without having to wait for transients to a new clock frequency.
  • Dispensing with a change in the circuit clock makes it possible to apply different supply voltages to the individual processing units of a digital circuit, both spatially and temporally, without adversely affecting the overall performance of the digital circuit.
  • control commands required for an operation to be executed and the voltage level to be selected for the operation to be executed are stored as a further control command in a memory of the control unit.
  • the spatial and temporal voltage adaptation of the method according to the invention is implemented at the command level and is thus reconfigurable in principle.
  • the stored in memory control commands are retrieved at runtime of a program on the digital circuit and according to these control commands, the supply voltage of individual functional units is set.
  • a digital circuit having at least two components and at least one control unit for outputting control commands and for driving the components as a function of an operation to be performed, wherein a voltage changeover switch for applying the components with different voltage levels in response to a switching - state is provided, wherein the control unit comprises means, in particular a memory, are accessible via the information, with which voltage level the components are to be charged when performing different operations and / or as a function of further boundary conditions.
  • the storage of the control voltage relating to the supply voltage and its allocation to control commands to be processed in the course of a partial operation are made possible.
  • the application of the components with different supply voltages is then realized by means of the voltage switch, which is controlled by the control unit directly or with the interposition of a further selection level, in particular a memory.
  • the provision of a context memory for information regarding the spatio-temporal voltage adaptation allows the realization of a digital circuit with reconfigurable dynamic spatial and temporal voltage adaptation.
  • the processing unit has a voltage level converter, wherein the voltage level converter can be switched on optionally in the output side of the components or the input side of the components.
  • a voltage level converter is provided on the output side or input side when a transition from the low to the high voltage level is to take place.
  • the voltage level translator may be provided between the component and an output interface or upstream of one or more input interfaces.
  • the problem underlying the invention is also solved by a method for configuring a digital circuit having at least two components, each for performing different operations, with the following steps: splitting operations to be performed into sub-operations to be performed and creating associated data flow paths, in particular creating a data flow graph, Assigning the sub-operations to the components of the digital circuit and determining which component performs which sub-operation in which timing step, and setting a voltage level for the components for each timing step depending on the operations to be performed in that timing step and / or other constraints.
  • a digital circuit can be configured so that on the one hand, a reduced power consumption is achieved, but on the other hand, the performance of the digital circuit is not affected by a constant supply voltage.
  • an operation to be performed into sub-operations and then, for example, depending on an expected execution time for the sub-operations, defining a voltage level for the sub-operation to be performed and assigning that voltage level to the functional unit that is to perform the sub-operation, significant energy savings can be realized , Since time-critical sub-operations are assigned a supply voltage which ensures their timely execution within one clock step or the predetermined number of clock steps, the overall performance of the digital circuit is not impaired. According to the allocations made by Sub-operations and the setting of the voltage levels can then be generated control commands for the control unit.
  • development of the invention is selected when setting a voltage level between at least two voltage levels.
  • the storage of the allocations and definitions in a memory of a control unit of the digital circuit is provided.
  • the temporal and spatial dynamic voltage adjustment according to the invention can then be retrieved during the runtime of a program by retrieving the corresponding control commands from the memory and processed.
  • a digital circuit can always be reconfigured with the method according to the invention in principle.
  • the execution times required for partial operations are determined at different voltage levels, and voltage levels for the functional units are determined as a function of the determined execution times.
  • the comparison of the execution times for different sub-operations leads to a determination of the slip time that exists in certain sub-operations. Depending on the determined slip time can then, for example, the voltage level for such sub-operations are lowered.
  • the determination of a slip time is particularly advantageous if a slip time between simultaneously executed partial operations is determined and then a voltage level is determined depending on the determined slip times.
  • the problem underlying the invention is also solved by a digital storage medium with electronically executable control signals, in the execution of which on a computer system the method according to the invention is carried out.
  • a digital storage medium or a computer program product can be used within the scope of a development tool for the configuration of digital circuits, and by means of the computer program product, the method according to the invention can be implemented in the design of the digital circuit. In this way, reduced power consumption with undiminished performance of digital circuits can already be considered at the design stage.
  • FIG. 3 is a more detailed representation of a processing unit of the digital circuit of FIG. 2,
  • FIG. 4 shows a schematic representation of a further digital circuit according to the invention with the detailed illustration of a processing unit
  • FIG. 5 shows an illustration for explaining the method according to the invention for configuring a digital circuit on the basis of an exemplary operation to be carried out
  • FIG. 6 shows an illustration of the method according to the invention for configuring a digital circuit based on a further example of an operation to be carried out
  • FIG. 7 is an illustration of a processing unit of a digital circuit according to an alternative embodiment.
  • FIG. 1a shows a so-called data flow graph in which an operation to be performed is performed by sub-operations to be performed and data-flow paths linking the individual sub-operations is shown.
  • three multiplications and one subtraction are provided as partial operations.
  • the operation to be performed is processed in the illustration of FIG. 1a from top to bottom and processes a total of five input variables.
  • Two first input variables are processed in a first multiplication 10.
  • two further input variables are processed.
  • the result of the first multiplication 10 is fed to a third multiplication 14 and a subtraction 16.
  • the result from the first multiplication 10 is linked to a further input variable.
  • the result of the multiplication 12 is fed to the subtraction 16.
  • Fig. 1b shows a table listing the execution time required for multiplication and subtraction at voltage levels 1, 0 volts and 1.2 volts. Fig. 1b further introduces the energy required at different supply voltages to perform the multiplication and the subtraction.
  • a subtraction within 2.68 nanoseconds can be performed versus 4.06 nanoseconds for a multiplication when the supply voltage is 1.2 volts.
  • the subtraction can still be performed much faster than multiplication within 3.48 nanoseconds versus 5.45 nanoseconds.
  • energy savings of 1.1 milliwatts can be achieved by choosing a 1.0 volts supply voltage instead of 1.2 volts.
  • FIGS. 1c, 1d and 1e respectively show diagrams to which the assignment of the individual sub-operations 10, 12, 14, 16 to respectively one of two processing units PE1, PE2 can be taken in different clock steps T1, T2, T3.
  • the first multiplication 10 is executed in the first processing unit PE1 during the first time step T1.
  • the second multiplication 12 is also carried out in the first processing unit PE1 during the second time step T2.
  • the third multiplication 14 is also executed in the first processing unit PE1 during the third time step T3.
  • the subtraction 16 is then also executed in the second processing unit PE2.
  • the first processing unit PE1 is operated with a supply voltage of 1.2 volts.
  • the second processing unit PE2 is operated with a supply voltage of 1.0 volts, which is represented by the black-framed symbol.
  • a multiplication at 1.2 volts supply voltage is carried out within 4.06 nanoseconds.
  • a subtraction at 1.0 volt supply voltage requires 3.48 nanoseconds. It is thus possible in the time step T3 of FIG. 1c to operate the second processing unit PE2 with the lower supply voltage and nevertheless to finish the result of the third multiplication 14 and the subtraction 16 within the third time step T3.
  • the representation of FIG. 1c thus shows a purely spatial assignment of supply voltages, in that the first processing unit PE1 is operated at 1.2 volts and the second processing unit PE2 at 1.0 volts. It should be noted that the execution of the intended operation according to FIG. 1c can take place within three time steps.
  • Fig. 1d shows the realization of a purely temporal voltage adjustment.
  • Both processing PE1 and PE2 can be set according to Fig. 1d together to a higher supply voltage of 1, 2 volts or a lower supply voltage of 1, 0 volts.
  • the first multiplication 10 and 10 are used in this approach the second multiplication 12 is performed simultaneously during the first time step T1.
  • the higher supply voltage of 1.2 volts is still applied to both processing units PE1 and PE2, and the third multiplication 14 is executed.
  • the supply voltage of both processing units PE1 and PE2 is then lowered to 1, 0 volts and the subtraction 16 is executed. It can be seen on the basis of FIG.
  • FIG. 1e shows the combination according to the invention of a spatial and temporal voltage adaptation.
  • Each processing unit PE1 and PE2 can be acted upon individually during any clock steps with the higher supply voltage of 1, 2 volts or the lower supply voltage of 1, 0 volts.
  • the first multiplication 10 and the second multiplication 12 are executed during the first time step T1.
  • the first processing unit PE 1 executes the third multiplication 14 and is supplied with a supply voltage of 1.2 volts.
  • the second processing unit PE2 executes the subtraction 16 and is however supplied with the lower supply voltage of 1.0 volt.
  • FIG. 2 shows a schematic representation of a digital circuit 20 according to the invention.
  • the digital circuit 20 has four processing units PE1, PE2, PE3 and PE4.
  • the processing units PE1, PE2, PE3 and PE4 are interconnected for data exchange, which is symbolized by two double arrows between the individual processing units PE1, PE2, PE3 and PE4. All processing units PE1, PE2, PE3 and PE4 are synchronized in time by means of a common clock T.
  • the processing units PE1, PE2, PE3 and PE4 are constructed identically, so that only the processing unit PE1 will be described in more detail below.
  • the processing unit PE1 has a control unit 22, by means of which a data path and a supply voltage are selected. In the selection of the data path, registers (not shown) and interfaces of the processing unit PE1 are actuated in order to retrieve the desired data in accordance with the control commands present to the control unit 22 and to pass on the calculated results to their respective destination.
  • the actual calculations are performed in a circuit 24, which in addition to a functional unit, which will be explained below and can perform various operations, still has a voltage converter and an output interface.
  • the circuit 24 represents as a hardware component a closed voltage range that can be operated with different supply voltages.
  • the circuit 24 can be operated with a first supply voltage V1 and a second supply voltage V2, which are selectively applied to the circuit 24 by means of a voltage switch 26.
  • the control of the voltage switch 26 takes place by means of the control unit 22 and that in accordance with control commands which are present in a memory of the control unit 22 and are retrieved at runtime.
  • the selection of an operation takes place via a control line 25 between the control unit 22 and the circuit 24.
  • both a temporal voltage adaptation can be provided, namely that a supply voltage of the circuits 24 is changed for each clock or for a few clock cycles.
  • a spatial voltage adjustment can be made such that the circuits 24 of different processing units PE1, PE2, PE3, PE4 operate at different supply voltages during the same clock cycle.
  • control commands for voltage adjustment by means of the control unit 22 and for example by means of control commands, which are stored in a memory carried out to reconfigure the voltage adjustment, a reprogramming of the control unit.
  • the control unit 22 has a context memory 28 and logic gates 30. Further components of the control unit 22 are not shown in FIG. 3 for the sake of clarity.
  • a functional unit 32 in the circuit 24 is driven in order to execute desired operations in the functional unit 32 in accordance with the control commands.
  • the functional unit 32 may perform different operations, such as multiplications, additions, subtractions, and comparisons.
  • a supply voltage for the functional unit 32 is likewise selected from the context memory 28 by means of control commands, for example such that a specific supply voltage is assigned to a specific operation. For example, a multiplier tion always be associated with the higher supply voltage V2 as a time-critical operation and an addition or subtraction is always associated with the lower supply voltage V1.
  • the voltage changeover switch 26 has two transistors 34 and 36 which respectively block or enable a connection between the supply voltage rail V1 or the supply voltage rail V2 with the functional unit 32.
  • the functional unit 32 is surrounded by a dashed line. This is to symbolize that the functional unit 32 within the processing unit PE1 forms a voltage island which can be operated with different supply voltages V1, V2.
  • a calculation result of the functional unit 32 is output to an output interface 38 and can be output therefrom to the processing unit PE1.
  • a voltage level converter 40 can be switched on between the functional unit 32 and the output interface 38. The turning on of the voltage level converter 40 is required whenever the functional unit 32 is operated at the low voltage level V1. In order not to have to work with different signal levels in the communication of the processing units PE1, PE2, PE3, PE4 with each other, the output signal of the functional unit 32 when it is operated with the low supply voltage V1, set by the voltage level converter 40 back to the higher voltage level. The optional switching of the voltage level converter 40 in the signal path is determined by the control unit 22.
  • FIG. 4 shows in its left-hand section a schematic representation of a digital circuit 20 having a plurality of processing units PE1, PE2, PE3, PE4 and PE5.
  • the processing units communicate with each other via bidirectional data lines, which is indicated by oppositely directed arrows.
  • the processing unit PE5 is shown in more detail in the right part of FIG.
  • the processing unit PE5 has a context memory 42, which is divided into a context memory 44 for the voltage configuration and a context memory 46 for the selection of the operations control commands.
  • the control unit also has a finite state machine (FSM 48).
  • FSM 48 finite state machine
  • a memory 50 is provided in which a basic configuration is stored and accessed during booting. Furthermore, a register set 52 and numerous interfaces 54 for inputting and outputting data and status data are provided.
  • the voltage changeover switch 26 selectively supplies the functional unit 32 with one of a plurality of supply voltages, optionally including a voltage of zero volts, corresponding to a complete deactivation of the functional unit 32, and the voltage level converter 40 is provided at the output of the functional unit 32.
  • FIG. 5 shows the configuration of a digital circuit according to the method according to the invention for a trilinear interpolation.
  • a data flow graph of the operation to be carried out is created, corresponding to a breakdown. ment of the operation to be performed in sub-operations and creation of data flow paths, ie which data at which time step must be further processed by which sub-operations.
  • the temporal division takes place in accordance with steps of a predetermined circuit clock, which is plotted in the illustration of FIG. 5 rightmost and clock steps T1, T2, ... to T15 contains.
  • the operation represented by the data flow graph 60 can thus be completed in fifteen time steps T1 to T15.
  • the temporal arrangement of the sub-operations is also referred to as scheduling.
  • a second step the assignment of the individual sub-operations to the processing units PE1, PE2, PE3 and PE4 then takes place.
  • This process is also called binding.
  • FIG. 5 it is plotted over time which sub-operations are carried out in the individual processing units PE1, PE2, PE3 and PE4.
  • the symbols for the individual sub-operations are either only outlined in black or filled in black.
  • the black-rimmed sub-operations are carried out at a supply voltage of 1, 0 volts, whereas the completed partial operations shown executed at a supply voltage of 1, 2 volts. It can be seen from the illustration of FIG. 5 that only the multiplications with a supply voltage of 1.2 volts are carried out, all other operations can be completed within one clock even with a supply voltage of 1.0 volts.
  • this is Configuration process according to the invention completed in principle.
  • the accruals Instructions and definitions can then be stored in the form of control commands in a memory of the digital circuit.
  • the described configuration method may be applied during the development of a digital circuit, such as an ASIC circuit, and may be used in configuring a reconfigurable circuit such that the control instructions resulting from the assignments and determinations into a plurality of similar digital circuits may be simplified Way can be stored.
  • the data required for the processing are loaded into the processing units PE1, PE2, PE3, PE4 by means of a memory access.
  • twenty-one out of twenty-eight sub-operations of the trilinear interpolation can be performed at a supply voltage of 1.0 volts without violating the temporal boundary condition set at a maximum of 4.5 nanoseconds per clock.
  • only multiplications at the high supply voltage have to be carried out.
  • a 22.8% reduction in power consumption is achieved compared to performing a trilinear operation with the same circuit but with a constant supply voltage of 1.2 volts.
  • FIG. 6 shows a further example of the method according to the invention for configuring a digital circuit, using the example of the so-called "voxel fetch operation.”
  • a data flow graph 62 is created and the individual sub-operations then become the individual processing units
  • FIG. 7 shows a processing unit PE6 of a further embodiment of a digital circuit.
  • the processing unit PE6 is constructed similarly to the processing unit PE1 of FIG. 3 and functionally identical components will not be explained again.
  • the processing unit PE6 has two voltage level converters 70, 72 which are provided on an input side of the functional unit 32.
  • the voltage level converter 70 is turned on in a supply line which is in communication with a first input of the functional unit 32.
  • the voltage level converter 72 is turned on in a supply line which is in communication with a second input of the functional unit 32.
  • the communication between processing units can therefore take place, for example, at a low voltage level, and the inputs of the functional unit 32 are set to a high voltage level by means of the voltage level converters 70, 72.
  • the inputs of the functional unit 32 are therefore always at a high voltage level, regardless of whether the functional unit 32 is operated with a high or low voltage level. This is necessary when the functional unit 32 is operated at a high voltage level and is harmless when the functional unit 32 is operated at a low voltage level. It is thereby possible to dispense with a special control of the voltage level converter 70, 72.

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Abstract

La présente invention concerne un procédé pour commander un circuit numérique comprenant au moins deux éléments destinés à l'exécution d'opérations différentes, et au moins une unité de commande pour commander les éléments en fonction d'une opération à exécuter. Selon l'invention, une phase qui correspond à la sélection d'un niveau de tension pour l'unité fonctionnelle, se déroule au moyen de la/des unité(s) de commande en fonction de l'opération à exécuter et/ou d'autres conditions marginales. L'invention peut être utilisée par ex. pour des applications mobiles de circuits numériques pour limiter la consommation d'énergie.
PCT/EP2006/009760 2005-10-19 2006-10-10 Procede pour commander un circuit numerique, et circuit numerique correspondant WO2007045377A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06806137A EP1941339A1 (fr) 2005-10-19 2006-10-10 Procede pour commander un circuit numerique, et circuit numerique correspondant

Applications Claiming Priority (2)

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DE102005051451.0 2005-10-19
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