WO2006109214A1

WO2006109214A1 - Broadband amplifier

Info

Publication number: WO2006109214A1
Application number: PCT/IB2006/051033
Authority: WO
Inventors: Mihai A. T. Sanduleanu; Eduard F. Stikvoort
Original assignee: Nxp B.V.
Priority date: 2005-04-13
Filing date: 2006-04-04
Publication date: 2006-10-19

Abstract

A broadband amplifier (2) for receiving radio frequency signals from an antenna (4) is disclosed. The amplifier comprises a first amplifier stage (6) for receiving an input voltage signal, and a first feedback stage (12) for providing a feedback link between an input and an output of the first amplifier stage (6). A second amplifier stage (10) is connected to an output of the first amplifier stage (6) and a second feedback stage (16) provides a feedback link from an output of the second amplifier stage to an input of the first amplifier stage. An output voltage signal is provided at an output terminal (22) of an output stage (20).

Description

Broadband amplifier

The present invention relates to a broadband amplifier, and relates particularly, but not exclusively, to a broadband amplifier for use in amplifying radio frequency (RF) signals from an antenna. The invention also relates to an integrated amplifier and unbalanced/balanced transformer (BALUN) circuit incorporating such an amplifier. Broadband low noise amplifiers (LNAs) for use in radio frequency applications generally use feedback in order to provide the correct termination impedance and necessary noise and linearity performance. However, as supply voltages decrease in order to permit portable applications, existing designs of low noise amplifier prove to be inadequate.

A known low noise amplifier for low power applications in shown in Fig. 1. This amplifier may operate at supplies well under IV because the only required DC voltage drop is across transistor Ql. Matching of the input impedance is achieved by means of the coil Lg and capacitor network C₁, and the integrated transformer T₁ serves the dual purposes of improving the linearity of the circuit, and tuning out the Miller capacitance of the transistor Ql. The amplifier of Fig. 1 allows the design of fully integratable, stable and low- voltage low noise amplifiers (LNAs). However, it suffers from the drawback of possible resonant frequencies of the transformer, and a small bandwidth due to parasitic elements in the transformer.

Another approach, used generally in broadband amplifiers for use in optical communications, is a broadband low noise amplifier with transimpedance stage, as shown in Fig. 2. To aid in explaining the operation of the amplifier, impedances are replaced by resistances, and the condition when the input impedance Rj_n is equal to the output impedance R_0Ut, both of which are equal to R₃, is considered. It can be shown that the dual port matching condition, i.e. when Rj_n==R_out=Ra, occurs when:

R_F = g_mR_a A broadband 50Ω-matched LNA based on this design requires moderately large currents to achieve gains of the magnitude necessary for many purposes of the amplifier. For example, a bias current of about 3mA is needed for a 14dB gain. For this value, a noise Fig. of about 2dB is expected for a reasonable current gain β of the transistor Ql of about 10. This noise Fig. can be reduced below IdB, but at the expense of using impracticably large bias currents exceeding 7 to 8 mA. When the output impedance of the amplifier is not matched to R₃, the required value of the feedback resistor to achieve an input match can be shown to be:

R_F = R_L(g_mR. -l) + R.

For a load of, for example, 200Ω and bias current of 3mA, the noise Fig. is about 0.7dB with a power gain exceeding 2OdB. The required value of the feedback resistor can also be stated in terms of the numerical gain G. The feedback resistor RF and the gain G of the transistor Ql with active load current I_DC determine the input impedance as follows:

R,

IL = ^■

(G ₊ I)

The input capacitance C_m and the feedback R_F limit the bandwidth BW of the amplifier stage as follows:

BW ≡

2%R_FC_lt

The transimpedance gain is given by:

R_τ = - (G ₊ I)

However, larger bandwidths and higher gains are difficult to achieve because of the gain-bandwidth trade-off: R_F *BW ≡

2πC,

The selection of a larger transimpedance gain by means of R_F will reduce the required bandwidth, whereas the choice of a larger gain G leads to instability. The linearity performance of the amplifier stage, measured in terms of the third order intercept point IIP3, as will be familiar to persons skilled in the art, will not exceed OdBm with a reasonably large bias current above 7mA.

It is an object of the present invention to provide a low voltage broadband amplifier in which one or more of the above drawbacks is alleviated.

According to an aspect of the present invention, there is provided an amplifier comprising: a first amplifier stage for receiving a first voltage signal at an input thereof and amplifying said first voltage signal to provide a second voltage signal, dependent upon said first voltage signal, at an output thereof; a first feedback stage for providing a feedback link from an output of said first amplifier stage to an input thereof; a second amplifier stage for receiving said second voltage signal at an input thereof and amplifying said second voltage signal to provide a first current signal, dependent upon said second voltage signal, at an output thereof; a second feedback stage for providing a feedback link from an output of said second amplifier stage to an input of said first amplifier stage; and an output stage for providing a third voltage signal dependent upon said first current signal.

By providing a first feedback stage for providing a feedback link from an output of the first amplifier stage to an input thereof, and a second feedback stage for providing a feedback link from an output of the second amplifier stage to an input of the first amplifier stage, this provides the advantage of providing improved bandwidth and linearity, and providing active broadband impedance matching with an antenna from which an rf input signal is received. Such broadband operation is particularly advantageous for multi-standard, multi-band architectures. The first amplifier stage may include a first transistor and said first feedback stage may include at least one impedance connected between an input and an output of said first transistor.

Said second amplifier stage may include a second transistor for receiving said second voltage signal at an input thereof, and voltage to current conversion means for generating said first current signal.

Said voltage to current conversion means may include at least one impedance and a third transistor connected to said second transistor.

This provides the advantage of enabling the voltage to current conversion means to be constructed in a simple manner by driving a substantially constant current through said second transistor to cause a variable current to flow through said third transistor.

The output stage may include a fourth transistor for receiving a fourth voltage signal from an output of said second amplifier stage and amplifying said fourth voltage signal to provide said third voltage signal. The amplifier may further comprise a gain control stage for adjusting the amplitude of said third voltage signal.

The gain control stage may be adapted to be adjusted by means of a digital signal.

This provides the advantage of enabling more accurate adjustment of the gain control stage.

According to another aspect of the present invention, there is provided an integrated amplifier and unbalanced/balanced transformer circuit, the circuit comprising an amplifier as defined above and an unbalanced/balanced transformer stage for receiving said third electrical voltage signal at an input terminal thereof and providing a fifth electrical signal, dependent upon said fourth electrical signal, between two output terminals thereof.

Preferred embodiments of the present invention will now be described, by way of example only and not in any limitative sense, with reference to the accompanying drawings, in which:

Fig. 1 is a schematic diagram of a known design of low voltage low noise amplifier;

Fig. 2 is a circuit diagram of a known design of broadband low noise amplifier with transimpedance stage; Fig. 3 is a circuit diagram of a broadband low noise amplifier embodying the present invention;

Fig. 4 is a circuit diagram of a digitally controlled current generating circuit for use in the amplifier of Fig. 3; Fig. 5 is a circuit diagram of an integrated low noise amplifier and unbalanced/balanced transformer circuit incorporating the amplifier of Fig. 3;

Fig. 6 is a circuit diagram of the BALUN circuit of the circuit of Fig. 5; and Fig. 7 is an alternative embodiment of the BALUN circuit of Fig. 6.

Fig. 3 is a circuit diagram of a broadband low noise amplifier embodying the present invention comprising a broadband low noise amplifier 2 for use in amplifying radio frequency (RF) signals from an antenna 4, the amplifier having a first amplifier stage 6 including a transistor Ql for receiving an input signal from the antenna 4 and providing an output signal at an output terminal 8. The transistor Ql is biased by means of current I_DC, which ensures a temperature compensated biasing, and a resistor Rl provides a DC level shift in order to accommodate a second amplifier stage 10, which will be described in greater detail below, when using a 1.6V voltage supply. A capacitor C₁ provides a short circuit within the desired frequency band. A first feedback stage 12 is provided by a resistor R_F1 connected between the collector and base of transistor Ql . This improves the linearity of operation of the first amplifier stage 6. The second amplifier stage 10 comprises an emitter follower including a second transistor Q2, the base of which is connected to the output terminal 8 of the first amplifier stage 6, and a third transistor Q3, the collector of which is connected to the emitter of transistor Q2. An output terminal 14 of the second amplifier stage 10 is connected to the negative supply terminal via a resistor R₂ and capacitor C₂, and a second feedback stage 16 is provided by a resistor R_F and capacitor C_F connected in series between the output terminal 14 of the second amplifier stage 10 and the base of transistor Ql. The second feedback stage 16 serves to further improve the linearity of the combined first and second amplifier stages 6, 10. As a result of the second feedback stage 16, the base- emitter voltage of transistor Q2 is constant, as a result of which the voltage Vx appearing at the output terminal 14 of the second amplifier stage 10 tracks the voltage at the output terminal 8 of the first amplifier stage 6. A current source 18 drives a constant current of magnitude 2I_Dc through transistor Q2, as a result of which the voltage signal Vx at the output terminal 14 of the second amplifier stage 10 is converted to a current on the series combination of resistor R₂ and capacitor C_2, and through transistor Q3.

As a result of the additional feedback provided by the second feedback stage 16, the voltage to current conversation from the input of first amplifier stage 6 to the output terminal 14 of second amplifier stage 10 is substantially distortionless. The capacitor C_F is provided for low voltage operation and for decoupling the DC conditions of the first amplifier stage 6 from the second amplifier stage 10. It is generally preferred that the current on transistor Q3 is supplied via feedback resistor R_F, and the voltage Vx at the output terminal 14 of the second amplifier stage 10 is an amplified version of the input voltage received from the antenna 4, i.e.

D

V ^r X - ^~ -- „JLv ^r IN - ^~ G *-* * V ^r IN

where R₃ represents the series resistance of the antenna 4. The amplifier 2 further includes an output stage 20 including transistor Q4 and a load resistor RL. A single ended output voltage signal V₀ is provided at output terminal 22. The bases of transistors Q3 and Q4 are connected together, as a result of which the current I₀ through transistor Q4 is dependent upon the current flowing through transistor Q3. In this way, the output voltage signal V₀ at the output terminal 22 of the output stage 20 is an amplified version of voltage signal Vx output by the second amplifier stage 10.

A gain control circuit 24 includes transistors Q5, Q6 and Q7 and is provided to adjust the current gain from transistor Q3 to transistor Q4. The gain control circuit 24 is provided in order to reduce an input signal of very large dynamic range to one of generally constant amplitude. Linear IF amplifiers always have to provide variable gain, with a range of up to 8OdB. Using a detector cell at the output of the last IF stage, the control bias may be generated within a simple autonomous loop, of the sort used for decades in radio receivers. When the loop has settled in response to a change in signal amplitude this bias provides a measure of the signal strength, the so-called Received Signal Strength Indication or RSSI. If the gain function is linear- in-dB, the RSSI voltage is a logarithmic measure of signal power. A preferred gain-control iunction is one in which an increasing RSSI voltage reduces the gain; thus the RSSI output increases with signal power. Some part of the gain control can be done in the LNA part to reduce the DR requirements for the IF part. If the AGC control is present, on the resistor R3 a PTAT voltage drop appears as a consequence of the difference between the two currents Il and 12:

V_PTAT = V_T

The equal current condition 11-12 equates to the unitary gain condition. In general:

By choosing the ratio of the two currents such that:

we get a linear in dB gain of the current Io:

The voltage ΔV is a voltage drop on a resistor or a reference voltage. In order to generate the two currents, the circuit of Fig. 4 is used. The current 12 flows in the transistor Q20. The difference between the V_BE voltages of the transistors Q20 and Q21 is found on the resistor Rx. A current I_DAC provided by a digital-to-analog converter (DAC) generates a voltage drop I_DACRX dependent on the digital DAC code. This allows accurate digital setting of the gain control circuit 24. A buffer transistor Q22 delivers the current I_DAC and forces the current 12 in the transistor Q20. The two currents are related as:

_I2 =_I1 I_eJ-LvA. Therefore, the linear-in-dB law becomes:

Referring now to Fig. 5, in which parts common to the embodiment of Fig. 3 are denoted by like reference numerals, an integrated low noise amplifier and broadband active unbalanced/balanced transformer incorporating the amplifier 2 of Fig. 3 and an unbalanced/balanced transformer (BALUN) 28 is shown.

The BALUN circuit 28 of Fig. 5 is shown in more detail in Fig. 6 and receives a single ended output signal from the low noise amplifier (LNA) 2 in the form of current signal IO flowing in output stage 20. The BALUN circuit 28 has a first branch formed by output stage 20 of amplifier 2 having a resistor Rl 30 connected to the emitter of a bipolar transistor Q9. The collector of transistor Q9 is connected via an output terminal OUT+ and resistor RL to the positive voltage supply rail VCC. A second branch of the BALUN circuit 28 has a transistor QlO, the collector of which is connected to the supply rail Vcc via an output terminal OUT- and resistance RL, and the emitter of which is connected to the collector of a transistor Q8. The emitter of transistor Q8 is connected via resistor R3 32 to ground.

The voltages at the output terminals OUT+, OUT- are sensed by the inputs of an operational amplifier 34, the output signal of which is applied via resistors Rb to the bases of transistors Q9, QlO and via a voltage divider network R4, R5 to the base of transistor Q8. An input capacitor Q_N decouples the bias voltage of the base of transistor Q8 from input terminal 36. The base of transistor Q9 is connected to the emitter of transistor QlO via capacitor C2, and the base of transistor QlO is connected via variable capacitor Cl to the emitter of transistor Q9.

The operation of the BALUN circuit 28 of Fig. 6 will now be described. The current source Io provides a current through transistor Q9 and biases transistor Q9 at a current necessary for broadband operation and low distortion. The operational amplifier 34 senses the offset voltage between the two branches, which is dependent upon the offset current between the two branches, and applies its output to the base of transistor Q8, as a result of which the current flowing through transistors Q8 and QlO matches current I₀. Once current I₀ is chosen, the total circuit is self-biased, ensuring zero offset at the output. As a result, DC blocking capacitors between the BALUN 28 and the following mixer stage (not shown) can be avoided, as a result of which the introduction of additional losses and phase errors in the signal path is avoided.

A single ended RF input signal applied to the input terminal 36 from the LNA 2 creates a current signal at resistor Rl 30, as a result of which a matching current signal is provided through transistors Q8 and QlO, to cause a balanced voltage signal to be provided at the output terminals OUT+, OUT-. The sum of the base-emitter voltages of transistors Q9 and Q8 is constant, giving a constant product of the currents of Q9 and Q8.

The resistor Rl 30 provides the correct input resistance for maximum power transfer from the low noise amplifier 2 to the BALUN 28. At the same time, it assists the matching of transistors Q9 and Q8. Transistor QlO decreases the Miller capacitance observed at the base of transistor Q8, and enhances the isolation between the mixer (not shown) and low noise amplifier 2. Transistor QlO also provides better symmetry between the two branches of the circuit and provides equal branch impedances at the emitters of transistors Q9 and QlO. Capacitors Cl, C2 provide a means for adjusting the phase error of the two anti-phase outputs. If Cl is adjusted, the anti-phase operation can be extended to a larger frequency range, at the cost of a (usually acceptable) phase error at the output. A CMOS operational amplifier 34 with PMOS inputs is a suitable amplifier for this purpose.

Referring to Fig. 7, in which parts common to the embodiment of Fig. 6 are denoted by like reference numerals but increased by 100, an MOS version of the BALUN circuit of Fig. 6 is shown. In the case of the MOS BALUN 128, no equivalent to the input capacitor Cin between the input terminal 136 and the base of transistor Q8 of Fig. 6 is necessary.

With reference again to Fig. 5, amplifier 34 at the output of the BALUN 28 senses the DC imbalance between the two outputs OUT+ and OUT-, generating a current in transistors Q8 to QlO that equals the DC current of the LNA output transistor Q4. The gain control circuit 24 controls the gain of the LNA 2 in a "linear in dB" manner, which prevents the overloading effect of the BALUN 28 and can help in the accommodation of a large range of input voltages. It will be appreciated by persons skilled in the art that the above embodiments have been described by way of example only, and not in any limitative sense, and that various alternations and modifications are possible without departure from the scope of the invention as defined by the appended claims.

Claims

CLAIMS:

1. An amplifier comprising: a first amplifier stage (6) for receiving a first voltage signal at an input thereof and amplifying said first voltage signal to provide a second voltage signal, dependent upon said first voltage signal, at an output thereof; - a first feedback stage (12) for providing a feedback link from an output of said first amplifier stage to an input thereof; a second amplifier stage (10) for receiving said second voltage signal at an input thereof and amplifying said second voltage signal to provide a first current signal, dependent upon said second voltage signal, at an output thereof; - a second feedback stage (16) for providing a feedback link from an output of said second amplifier stage to an input of said first amplifier stage; and an output stage (20) for providing a third voltage signal dependent upon said first current signal.

2. An amplifier according to claim 1, wherein said first amplifier stage includes a first transistor (Ql) and said first feedback stage includes at least one impedance (RFl) connected between an input and an output of said first transistor.

3. An amplifier according to claim 1, wherein said second amplifier stage includes a second transistor (Q2) for receiving said second voltage signal at an input thereof, and voltage to current conversion means (R2, Q3) for generating said first current signal.

4. An amplifier according to claim 4, wherein said voltage to current conversion means includes at least one impedance (R2) and a third transistor (Q3) connected to said second transistor.

5. An amplifier according to claim 1, wherein said output stage includes a fourth transistor (Q4) for receiving a fourth voltage signal from an output of said second amplifier stage and amplifying said fourth voltage signal to provide said third voltage signal.

6. An amplifier according to claim 1, further comprising a gain control stage (24) for adjusting the amplitude of said third voltage signal.

7. An amplifier according to claim 6, wherein the gain control stage is adapted to be adjusted by means of a digital signal.

8. An integrated amplifier and unbalanced/balanced transformer circuit, the circuit comprising an amplifier (2) according to claim 1 and an unbalanced/balanced transformer stage (28) for receiving said third electrical voltage signal at an input terminal thereof and providing a fifth electrical signal, dependent upon said fourth electrical signal, between two output terminals (OUT+, OUT-) thereof.