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WO2006022152A1 - Driving circuit board, method for manufacturing the same, liquid crystal display panel and liquid crystal display device - Google Patents

Driving circuit board, method for manufacturing the same, liquid crystal display panel and liquid crystal display device Download PDF

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Publication number
WO2006022152A1
WO2006022152A1 PCT/JP2005/014762 JP2005014762W WO2006022152A1 WO 2006022152 A1 WO2006022152 A1 WO 2006022152A1 JP 2005014762 W JP2005014762 W JP 2005014762W WO 2006022152 A1 WO2006022152 A1 WO 2006022152A1
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WO
WIPO (PCT)
Prior art keywords
drive circuit
circuit board
wiring
liquid crystal
crystal display
Prior art date
Application number
PCT/JP2005/014762
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroyuki Moriwaki
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2006022152A1 publication Critical patent/WO2006022152A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to a drive circuit board, a manufacturing method thereof, a liquid crystal display panel, and a liquid crystal display device. More specifically, the present invention relates to a drive circuit board suitable as a system liquid crystal panel substrate, a manufacturing method thereof, and a liquid crystal display panel and a liquid crystal display device including the drive circuit board.
  • Liquid crystal display devices are used in a wide range of fields by taking advantage of thin, lightweight, and low power consumption.
  • an active matrix liquid crystal display device in which an active element such as a thin film transistor (TFT) is provided for each pixel as a circuit element for driving a pixel can realize a clear image display with little crosstalk.
  • TFT thin film transistor
  • It is widely used as a computer (PC), a mobile information device such as a mobile phone and a personal digital assistant (PDA), and a display device such as a car navigation system.
  • PC computer
  • PDA personal digital assistant
  • display device such as a car navigation system.
  • ESD electrostatic discharge destruction
  • the gate wiring is formed by performing dry etching on a metal thin film formed by sputtering or vacuum evaporation.
  • Dry etching here refers to reactive ion etching (RIE) performed in the gas phase, and ions (or radicals) generated by plasma collide with the metal thin film in the region to be etched. And a metal atom, and the reaction product is removed to the outside by a vacuum exhaust system.
  • RIE reactive ion etching
  • ions (or radicals) collide with the thin metal film electric charges are accumulated in the gate wiring, and the accumulated electric charges cause circuit elements such as transistors provided in the pixels to be static. It causes electric breakdown.
  • FIG. 4 is a schematic front view showing a configuration in the middle of manufacturing a conventional active matrix substrate.
  • the active matrix substrate shown in FIG. 4 includes a pixel region and a frame portion.
  • pixel electrodes 50 and pixel drive circuit elements 51 are arranged in a matrix, and between each pixel, a gate wiring 52 extending in the row direction and a source wiring 53 extending in the column direction are provided. Each is arranged.
  • a guard ring 54 is disposed at the frame portion (non-display area) located at the end of the pixel area (the left end in FIG. 4), and each gate wiring 52 is connected to the guard ring 54.
  • the gate wiring 52 and the guard ring 54 are formed by a process such as dry etching. In the etching process of this wiring, the charge is stored in the gate wiring 52. According to the active matrix substrate in the form of FIG. 4, a part of the charge stored in the gate wiring 52 moves to the guard ring 54. For this reason, the gate wiring 52 does not accumulate electric charges large enough to cause electrostatic breakdown of the circuit element 51. Note that the frame portion including the guard ring 54 is cut out until the substrate is completed. Thus, conventionally, the circuit element 51 for driving the pixel is prevented from being electrostatically damaged during the manufacturing process.
  • the monolithic technology referred to here is a technology for forming peripheral circuits necessary for liquid crystal driving such as drivers on a glass substrate on which pixels are formed as shown in FIG. Fig. 6 (a) is a schematic front view showing the state of the gate driver formed on the frame portion of the liquid crystal panel substrate to which the monolithic technology is applied, and (b) is the frame of the liquid crystal panel substrate shown in (a). It is the schematic diagram which expanded the part enclosed by the circle among the parts. According to the liquid crystal display device to which the monolithic technology is applied, as shown in FIG. 6 (a), the drive circuit 55 is formed directly on the substrate of the frame portion of the liquid crystal panel substrate.
  • the number of members can be reduced, the fine pitch can be reduced, and the weight can be reduced.
  • the continuous wiring is divided by the drive circuit, it is impossible to release charges to the guard ring by forming a guard ring in the frame portion. Therefore, the liquid crystal display device to which the monolithic technology is applied.
  • development of a new technology for preventing electrostatic breakdown during the manufacture of the circuit element 51 for driving the pixel has been awaited.
  • a drive circuit such as a driver formed on a substrate also includes a large number of circuit elements such as transistors. Then, the wiring 52 that connects the circuit elements 51 of the drive circuit also accumulates charges as shown in FIG. 6B in which there is no escape path for charges accumulated during manufacture. Therefore, in a liquid crystal display device to which the monolithic technology is applied, circuit elements of a driver circuit such as a driver formed on the substrate may also be electrostatically damaged during manufacturing, and this can be prevented. Technology development was awaited.
  • Patent Document 1 Japanese Patent Laid-Open No. 10-268794 (Pages 1, 8 and 1)
  • the present invention has been made in view of the above situation, and in a liquid crystal display device to which a monolithic technique is applied, a circuit element generated due to accumulation of electric charges in wirings connecting the circuit elements to each other
  • An object of the present invention is to provide a drive circuit board and a method for manufacturing the same, and a liquid crystal display panel and a liquid crystal display device including the drive circuit board. It is.
  • the circuit elements are connected using only the wiring of the same level as the gate wiring. Therefore, the circuit elements are electrostatically destroyed by the charge accumulated in the wiring in the dry etching process. I found out. Therefore, the wiring formation process is divided into two or more, and at least one of the wirings connecting the circuit elements is divided into two or more wiring parts formed of a configuration in which paths are formed in two or more layers or different materials. In this configuration, the electric charge is once discharged during each formation process, and the maximum amount of charge accumulated in the wiring can be reduced.
  • the present invention is a drive circuit substrate having a laminated structure in which two or more layers are formed on a substrate and having a structure in which two or more circuit elements are connected by wiring. At least one of them is a drive circuit board having a constitutional force in which paths are formed in two or more layers.
  • the present invention also provides a driving circuit board having a structure in which two or more circuit elements are connected by wiring on the board, wherein at least one of the wirings is formed by two or more wiring parts formed of different materials. It is also a drive circuit board comprising a configuration including
  • the present invention further relates to a method for manufacturing a drive circuit board having two or more circuit elements and wirings on a substrate, wherein the method for manufacturing a drive circuit board includes at least one wiring for connecting circuit elements to each other.
  • This is also a method for manufacturing a drive circuit board formed by the above dry etching process.
  • the drive circuit board of the present invention has a laminated structure in which two or more layers are formed on the board, and has a structure in which two or more circuit elements are connected by wiring.
  • “above” and “below” include the numerical values.
  • the substrate is preferably a transparent glass substrate when used in a liquid crystal display panel or a liquid crystal display device.
  • the circuit elements are not particularly limited, but active elements such as transistors and diodes, and passive elements such as resistors, capacitors, inductances, and transformers are suitable for achieving the effects of the present invention.
  • a thin film transistor (TFT) is particularly suitable.
  • Examples of the wiring include single-layer wiring such as copper (Cu) wiring and aluminum (A1) wiring, tungsten (W) Z tantalum nitride (TaN), titanium (Ti) Z aluminum-caine (Al-Si) ) Series alloy Z-Ti (Ti) or other laminated wiring is preferably used.
  • a method for forming the wiring for example, a method in which a wiring material is formed by sputtering or vacuum vapor deposition and then dry etching is preferably used. Dry etching tends to cause charge accumulation compared to patterning methods such as wet etching.
  • the drive circuit board of the present invention is not particularly limited as long as such components are included as essential components, and other components may or may not be included. Not.
  • the drive circuit board of the present invention is preferably one used for a liquid crystal display device (drive circuit board for liquid crystal display device).
  • At least one of the wirings also has a constitutional force in which paths are formed in two or more layers.
  • the wiring forming process for connecting the circuit elements is divided into two or more, and it is possible to accumulate the charges accumulated in the conventional dry etching process in a plurality of times. Therefore, the electric charge is once discharged during each forming process, and the maximum amount of charge accumulated in the wiring connecting the circuit elements is reduced, so that the circuit elements are prevented from being electrostatically damaged during manufacturing. be able to.
  • the etching process in wiring formation may be a combination of a dry etching process and a wet etching process.
  • a more preferable embodiment of the present invention is an embodiment in which substantially all the wirings have a constitutional force in which paths are formed in two or more layers.
  • the configuration in which the path is formed in the two or more layers is a circuit in which a part of the wiring is formed (divided formation) in each of the two or more layers and the wiring formed in each layer is connected. It means a structure in which elements are connected.
  • the number of layers in which the wiring is dividedly formed is not particularly limited as long as it is two or more layers.
  • two layers are used. Is preferred. In the present invention, it is sufficient to have at least one part in the wiring that is divided into two or more layers! However, in order to effectively exhibit the operational effects of the present invention, a mode in which the wiring is divided into two or more layers is provided between each circuit element.
  • the material, shape, dimensions (thickness, width, etc.) and forming method of the wiring may be the same or different in each layer.
  • the drive circuit board of the present invention may have other drive circuits externally attached to the board as long as at least one drive circuit is formed on the board.
  • the driving circuit formed on the substrate is not particularly limited as long as it can be monolithically formed.
  • a circuit for driving liquid crystal such as a ZDC circuit (direct current Z direct current converter) and a serial interface (I / F) is suitable.
  • a drive circuit board in which a circuit for driving liquid crystal is formed on a substrate can be suitably used as a liquid crystal panel substrate.
  • the circuit element is a thin film transistor
  • at least one of the wirings has a configuration in which a path is formed in the gate electrode arrangement layer and the source electrode arrangement layer.
  • the form which becomes is mentioned.
  • the wiring for connecting the circuit elements can be formed by a combination of the existing wiring forming processes, electrostatic breakdown during the manufacture of the circuit elements can be prevented at a low cost.
  • TFT thin film transistor
  • CMOS-FET complementary field effect transistor
  • the semiconductor layer has a continuous grain boundary (CG) silicon film or a polysilicon film.
  • CG continuous grain boundary
  • TFTs using CG silicon films are particularly suitable for use as TFTs constituting drive circuits because CG silicon films have high electron mobility.
  • the present invention also provides a driving circuit board having a structure in which two or more circuit elements are connected by wiring on the board, wherein at least one of the wirings is formed of two or more different materials. It is also a drive circuit board having a component power including the wiring part. Even in such a case, since the wiring forming process for connecting the circuit elements is divided into two or more, it is possible to prevent the circuit element from being electrostatically damaged in the wiring forming process. it can.
  • At least one of the wirings is (1) a configuration in which a path is formed in two or more layers, and (2) a configuration including two or more wiring parts formed of different materials. Of these, either one or a combination of (1) and (2).
  • the substrate used for the drive circuit substrate of the present invention preferably has a glass material strength.
  • a glass substrate is more susceptible to electrostatic breakdown of a circuit element having higher insulation than a semiconductor Si substrate used in an IC or the like. Therefore, the present invention is applied to such a glass substrate. The effects of the invention can be sufficiently obtained.
  • the present invention is also a method for manufacturing a drive circuit board including two or more circuit elements and wirings on a substrate, and the method for manufacturing the drive circuit board includes at least one circuit element connected to each other. It is also a method for manufacturing a drive circuit board in which wiring is formed by two or more etching processes including a dry etching process.
  • the wiring etching process for connecting the circuit elements is divided into two or more.
  • the charge accumulated in one time by the dry etching process is increased to two or more. It is possible to accumulate separately. Therefore, the electric charge is discharged and discharged during each etching step, and the maximum amount of electric charge accumulated in the wiring connecting the circuit elements is reduced, so that the circuit elements are prevented from being electrostatically broken during manufacturing. As a result, a highly reliable drive circuit board can be manufactured.
  • the dry etching step is a step of sputtering a wiring material formed by sputtering or vacuum deposition, and reactive ion etching (RIE) or the like is preferably used.
  • RIE reactive ion etching
  • the reactive ion etching (RIE) described above is a reaction product of an ion and a metal atom caused to react chemically by causing ions (or radicals) generated by plasma to collide with a metal thin film in a region to be etched. Is removed to the outside by a vacuum exhaust system.
  • the wiring for connecting circuit elements is divided into two or more layers. Although it may be formed in the same layer, it may be formed in two or more layers, whereby the manufacturing process can be simplified. In the case where the wiring is divided into two or more layers, two layers are preferable as the number of layers in which the wiring is divided. In the case of forming the same layer, the wiring material film forming process may be performed once by sputtering or vacuum evaporation, and only the etching process may be performed twice or more. The film process and etching process may be repeated twice or more.
  • the wiring material film forming process is performed twice or more, the wiring material, film forming conditions, etc. can be changed.
  • the portion where the wiring is divided is formed between the circuit elements. Each is preferably provided.
  • the two or more etching steps preferably include a wet etching step.
  • the wiring etching process is divided into two or more, so the wiring forming process may be a combination of a dry etching process and a wet etching process. In this way, when a part of the wiring is formed by the wet etching process, charge accumulation is less likely to occur than when the wiring is formed by repeating the dry etching process. It is possible to prevent destruction.
  • the circuit element is a thin film transistor
  • the two or more etching processes preferably include a patterning process for a gate electrode and a patterning process for a source electrode.
  • the etching process includes the patterning process of the gate electrode and the patterning process of the source electrode, so that the wiring for connecting the circuit elements and the gate electrode and the source electrode can be collectively formed by the existing process. Therefore, it is possible to prevent the circuit element from being electrostatically damaged during manufacture by an inexpensive method.
  • the substrate used in the method for manufacturing a drive circuit board of the present invention preferably has a glass material strength. Since a glass substrate is more likely to cause electrostatic breakdown of a circuit element having higher insulation than a semiconductor Si substrate used for ICs and the like, the present invention is applied to such a glass substrate. It is possible to sufficiently obtain the operational effects.
  • the present invention is also a liquid crystal display panel and a liquid crystal display device including the drive circuit board or the drive circuit board manufactured by the method for manufacturing the drive circuit board.
  • the liquid crystal display panel and the liquid crystal display device of the present invention characteristics such as electrostatic breakdown in circuit elements can be obtained even on a glass substrate that has high insulation and is prone to electrostatic breakdown as compared with a semiconductor Si substrate used in an IC or the like. Since a highly reliable drive circuit board in which deterioration is prevented is provided, a highly reliable liquid crystal display panel and a liquid crystal display device can be provided.
  • a preferred form of the liquid crystal display panel of the present invention is a form in which the drive circuit board is used as a liquid crystal panel substrate constituting the liquid crystal display panel.
  • a liquid crystal display panel in which a drive circuit (peripheral circuit for driving liquid crystal) is formed on a liquid crystal panel substrate is also called a system liquid crystal panel, and the drive circuit substrate is external to the liquid crystal panel substrate.
  • the number of parts is reduced, the fine pitch and thin It is possible to reduce the weight of the mold.
  • At least one of the wirings has a configuration in which paths are formed in two or more layers or a configuration including two or more wiring parts formed of different materials.
  • the wiring formation process is divided into two or more, and the charge accumulated in the wiring by dry etching at the time of wiring pattern formation is discharged once during each layer forming process and accumulated in the wiring connecting circuit elements to each other The maximum amount of charge can be reduced, and circuit elements can be prevented from being electrostatically destroyed during manufacturing.
  • the wiring formation process is divided into two or more, it is possible to combine the etching process in wiring formation with a dry etching process and a wet etching process.
  • electrostatic charge breakdown can be prevented more effectively in the circuit element manufacturing process than the accumulation of electric charges.
  • FIG. 1 (a) is a schematic front view showing a circuit arrangement of a frame portion of a liquid crystal panel substrate (driving circuit substrate) to which the monolithic technology according to the embodiment of the present invention is applied
  • FIG. It is the schematic diagram which expanded the circuit arrangement
  • the wiring 13 at the same level as the source wiring is used as part of the wiring that connects the circuit elements 11 to each other.
  • the gate wiring is connected to the connection part with the circuit elements 11 (both ends of the wiring connecting the circuit elements).
  • Wiring 12 at the same level as the source wiring is used for the other parts (intermediate part of the wiring connecting the circuit elements).
  • two processes that is, a process of forming a wiring 12 at the same level as the gate wiring, A process of forming the wiring 13 at the same level as the wiring is required.
  • the wiring formation process is divided into two times, so that it is possible to accumulate charges that have been accumulated once by dry etching during wiring patterning in two. Since charges are once discharged during this formation process, the maximum amount of charge accumulated in the wiring connecting the circuit elements 11 is smaller than in the prior art. As a result, it is possible to prevent the circuit element 11 from being electrostatically damaged during manufacture. In addition, if the etching process in the formation process of the wiring 13 at the same level as the source wiring is performed by wet etching, it is more effective that circuit elements that are unlikely to accumulate electric charge in the wiring 13 are electrostatically destroyed during manufacturing. Can be prevented.
  • a top gate type thin film transistor is used as the circuit element 11.
  • FIG. 2 (a) is a schematic cross-sectional view showing the structure of the wiring portion of the drive circuit formed on the substrate in the drive circuit substrate of Embodiment 1
  • FIG. 2 (b) is the drive circuit substrate shown in (a).
  • FIG. 2 is a schematic cross-sectional view showing the structure of the TFT portion of the drive circuit formed on the substrate.
  • undercoat (SiO ZSiNO) 28 and amorphous silicon (a-Si) are formed on glass substrate 21 by plasma enhanced chemical vapor deposition (PECVD) using silane gas as the source gas.
  • PECVD plasma enhanced chemical vapor deposition
  • the undercoat 28 may be (SiNZSiO 2) or the like. Normal PECVD
  • a-Si formed by the above method contains about 10% hydrogen, if laser beam is performed as it is, there is a risk of hydrogen bumping and roughening the layer.
  • a Process to reduce the hydrogen concentration in the Si layer (dehydrogenation process).
  • dehydrogenation process raising the temperature up to about 500 ° C is particularly problematic in terms of the characteristics of the glass substrate, but if the time is extended, it can be carried out at a lower temperature, for example, about 430 ° C for about 2 hours. You may go.
  • Such a dehydrogenation process can reduce the hydrogen content to around 1%.
  • a metal catalyst may be applied and a pretreatment for CG-silicone may be performed.
  • channel doping was performed on the a-Si layer.
  • NMOS field In this case, a trivalent atom such as boron is implanted into the a-Si layer, and in the case of PMOS, a pentavalent atom such as phosphorus is implanted.
  • This channel doping can also be performed after the formation of the gate insulating film 23 shown below.
  • a pretreatment for laser annealing a heat treatment for solid phase crystallization may be performed.
  • dry etching using photolithography and carbon tetrafluoride (CF 3) gas is performed to produce a transistor.
  • the P—Si layer other than the portion was removed, and the thin film transistor region 24 was formed.
  • a gate insulating film 23 made of a silicon dioxide (SiO 2) film was formed by PECVD using tetraethylorthosilicate (TEOS) gas as a source gas.
  • TEOS tetraethylorthosilicate
  • SiNx, SiON, etc. can be used as the material.
  • phosphorus was channel-doped to Nch to control the threshold values of the Nch and Pch transistors.
  • a tungsten (W) film having a resistance of 1 ⁇ / port and a tantalum nitride (TaN) film having a resistance of 500 ⁇ / port were formed in this order by sputtering.
  • Other metals that can be used for the gate metal include low resistance metals such as MoW and A1, and high melting point metals that have a flat surface and stable characteristics.
  • a mix of Ar, SF, CF, O, C1, etc. as photolithography and source gas.
  • the gate metal (wiring) 22 is composed of a gate electrode pattern of the TFT portion and a part of the wiring pattern of the wiring portion.
  • ion implantation was performed in the source / drain regions of the transistor (ion doping).
  • boron or the like is implanted to make a P-type semiconductor
  • phosphorus or the like is implanted to make an N-type semiconductor.
  • an excimer laser was irradiated so that ions existing near the surface of the p-Si thin film could be taken into the p-Si layer and activated by ion implantation. The electrical conductivity can be improved by this activation treatment.
  • an activation treatment there is a method of baking at a high temperature.
  • an interlayer insulating film 27 was formed by PECVD. SiNx, SiON, etc. can be used as the interlayer insulating film material.
  • a contact hole (contact part) 26 was formed using a hydrofluoric acid-based wet etching solution. Since the p-Si is thin, the etching accuracy is inferior to that of dry etching, but a wet etching method with a high selectivity is used.
  • a metal thin film was formed in the order of a titanium (Ti) film, an aluminum-silicon (Al-Si) alloy film, and a Ti film by a sputtering method.
  • wet etching is performed using a hydrofluoric acid solution for Ti and a mixed solution of phosphoric acid, nitric acid, and acetic acid for A1, and a three-layer resistance 1 ⁇ well source (drain) metal ( Wiring) 25 was formed and contact part 26 was completed.
  • the source (drain) metal (wiring) 25 includes a wiring portion connected to the TFT source electrode, a wiring portion connected to the TFT drain electrode, and a contact portion 26 of the wiring portion.
  • a wiring portion connected to the gate metal 22 was formed. Then, by connecting a part of the pattern of the source (drain) metal 25 and the pattern of the gate metal 22, the TFT gate electrodes are connected to each other, and the drive circuit is completed. After the formation, the low-temperature P-Si manufacturing process was completed by forming a protective film (one kind of interlayer insulating film) by PECVD, applying a resin film, and forming a transparent electrode (ITO). [0032] According to the drive circuit substrate manufactured according to the present embodiment, the process of forming the wiring connecting the TFTs is divided into the process of forming the gate metal 22 and the process of forming the source metal 23. The etching process in the step of forming the source metal 23 was performed by wet etching. As a result, the maximum amount of charge accumulated in the wiring connecting the circuit elements can be reduced, so that the circuit elements can be effectively prevented from being electrostatically damaged during manufacture.
  • FIG. 3 (a) is a schematic cross-sectional view showing the structure of the wiring portion of the drive circuit formed on the substrate in the drive circuit substrate of Embodiment 2
  • FIG. 3 (b) is the drive circuit substrate shown in (a).
  • FIG. 2 is a schematic cross-sectional view showing the structure of the TFT portion of the drive circuit formed on the substrate.
  • the order of the manufacturing process is as follows: (4) gate metal formation, (2) gate insulating film formation, (1) Si layer formation, (5) ion doping, By changing the order of 7) hydrogen annealing treatment, (8) contact portion formation, and (9) source metal formation, a drive circuit board having a bottom gate type thin film transistor was manufactured. As the process order was changed, the dehydrogenation process temperature and other factors were changed as appropriate.
  • FIG. 1 (a) is a schematic front view showing a circuit arrangement of a frame portion of a liquid crystal panel substrate (driving circuit board) to which a monolithic technique according to an embodiment of the present invention is applied.
  • FIG. 2 (a) is a schematic cross-sectional view showing the structure of a wiring portion of a drive circuit formed on the substrate in the drive circuit board of Embodiment 1
  • FIG. 2 (b) is a drive diagram shown in FIG. 2 (a).
  • FIG. 3 is a schematic cross-sectional view showing a structure of a TFT portion of a drive circuit formed on a circuit board.
  • FIG. 3 (a) is a schematic cross-sectional view showing the structure of a wiring portion of a drive circuit formed on the substrate in the drive circuit board of Embodiment 2
  • FIG. 3 (b) is a drive diagram shown in FIG. 3 (a).
  • FIG. 3 is a schematic cross-sectional view showing a structure of a TFT portion of a drive circuit formed on a circuit board.
  • FIG. 4 is a schematic front view showing a structure in the process of manufacturing an active matrix substrate mounted on a conventional liquid crystal display device.
  • FIG. 5 is a schematic front view showing a configuration of a liquid crystal panel substrate (driving circuit substrate) to which the monolithic technology is applied.
  • FIG. 6 (a) is a schematic front view showing a state of a gate driver formed on a frame portion of a liquid crystal panel substrate (driving circuit substrate) to which a conventional monolithic technology is applied, and (b) is ( It is the schematic diagram which expanded the part enclosed with the circle
  • Vref Reference voltage
  • Vbias Bias voltage
  • TG Timing generation circuit
  • Vcom Counter electrode

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

A driving circuit board is provided with a stack structure wherein two or more layers are formed on a board, and a structure to which two or more circuit elements such as a thin film transistor are connected by wiring. At least one of the wiring has a path formed on two or more layers, such as a layer whereupon a gate electrode is arranged and a layer whereupon a source electrode is arranged.

Description

明 細 書  Specification

駆動回路基板、その製造方法、液晶表示パネル及び液晶表示装置 技術分野  DRIVE CIRCUIT BOARD, ITS MANUFACTURING METHOD, LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE TECHNICAL FIELD

[0001] 本発明は、駆動回路基板、その製造方法、液晶表示パネル及び液晶表示装置に関 する。より詳しくは、システム液晶パネル用基板として好適な駆動回路基板及びその 製造方法、並びに、上記駆動回路基板を備えてなる液晶表示パネル及び液晶表示 装置に関するものである。 背景技術  The present invention relates to a drive circuit board, a manufacturing method thereof, a liquid crystal display panel, and a liquid crystal display device. More specifically, the present invention relates to a drive circuit board suitable as a system liquid crystal panel substrate, a manufacturing method thereof, and a liquid crystal display panel and a liquid crystal display device including the drive circuit board. Background art

[0002] 液晶表示装置は、薄型 ·軽量 ·低消費電力といった特徴を活かし、幅広い分野で利 用されている。特に、画素駆動用の回路素子として薄膜トランジスタ (TFT)等の能動 素子を画素毎に設けたアクティブマトリクス駆動方式の液晶表示装置は、クロストーク が少ない鮮明な画像表示を実現することができることから、パーソナルコンピュータ（ PC)、携帯電話や携帯情報端末 (PDA)等のモパイル情報機器及びカーナビゲー シヨン等のディスプレイ装置として多用されて 、る。  [0002] Liquid crystal display devices are used in a wide range of fields by taking advantage of thin, lightweight, and low power consumption. In particular, an active matrix liquid crystal display device in which an active element such as a thin film transistor (TFT) is provided for each pixel as a circuit element for driving a pixel can realize a clear image display with little crosstalk. It is widely used as a computer (PC), a mobile information device such as a mobile phone and a personal digital assistant (PDA), and a display device such as a car navigation system.

[0003] アクティブマトリクス駆動方式の液晶表示装置の製造工程においては、ゲート配線に 電荷が蓄積され、静電気放電破壊 (ESD)によって画素駆動用の回路素子が破壊さ れてしまうことがあり、これを防止する手段が必要である。  In the manufacturing process of an active matrix liquid crystal display device, charges are accumulated in the gate wiring, and the circuit element for driving the pixel may be destroyed by electrostatic discharge destruction (ESD). A means to prevent is needed.

具体的には、ゲート配線は、スパッタ法ゃ真空蒸着法で形成された金属薄膜に対し 、ドライエッチングを施すことにより形成される。ここでいうドライエッチングとは、気相 中で行う反応性イオンエッチング (RIE)のことであり、プラズマにより生成させたィォ ン (又はラジカル)を被エッチング領域の金属薄膜に衝突させることによってイオンと 金属原子とを化学反応させ、反応生成物を真空排気系により外部に除去するという プロセスからなる。このエッチングプロセスにおいて、イオン（又はラジカル）が金属薄 膜に衝突するときに、ゲート配線に電荷が蓄積されてしまい、この蓄積された電荷が 、画素内に設けられたトランジスタ等の回路素子を静電破壊する原因となる。  Specifically, the gate wiring is formed by performing dry etching on a metal thin film formed by sputtering or vacuum evaporation. Dry etching here refers to reactive ion etching (RIE) performed in the gas phase, and ions (or radicals) generated by plasma collide with the metal thin film in the region to be etched. And a metal atom, and the reaction product is removed to the outside by a vacuum exhaust system. In this etching process, when ions (or radicals) collide with the thin metal film, electric charges are accumulated in the gate wiring, and the accumulated electric charges cause circuit elements such as transistors provided in the pixels to be static. It causes electric breakdown.

[0004] これに対し、従来では、ガードリング (短絡線）という配線を設けることにより、製造ェ 程における回路素子の静電破壊を防止していた (例えば、特許文献 1参照。 ) oこの 静電破壊防止方法について、図 4を参照しながら説明する。なお、図 4は、従来のァ クティブマトリクス基板の製造途中の構成を示す正面模式図である。 [0004] On the other hand, conventionally, by providing a wiring called a guard ring (short circuit line), electrostatic breakdown of a circuit element in a manufacturing process has been prevented (for example, refer to Patent Document 1). The electrostatic breakdown prevention method will be described with reference to FIG. FIG. 4 is a schematic front view showing a configuration in the middle of manufacturing a conventional active matrix substrate.

図 4に示すアクティブマトリクス基板は、画素領域と額縁部とを備える。画素領域には 、画素電極 50及び画素駆動用の回路素子 51がそれぞれマトリクス状に配置されて おり、各画素の間には、行方向に伸びるゲート配線 52及び列方向に伸びるソース配 線 53がそれぞれ配置されている。一方、画素領域の端（図 4では左端）に位置する 額縁部（非表示領域）には、ガードリング 54が配置されており、ガードリング 54には各 ゲート配線 52が接続されて 、る。  The active matrix substrate shown in FIG. 4 includes a pixel region and a frame portion. In the pixel region, pixel electrodes 50 and pixel drive circuit elements 51 are arranged in a matrix, and between each pixel, a gate wiring 52 extending in the row direction and a source wiring 53 extending in the column direction are provided. Each is arranged. On the other hand, a guard ring 54 is disposed at the frame portion (non-display area) located at the end of the pixel area (the left end in FIG. 4), and each gate wiring 52 is connected to the guard ring 54.

[0005] 図 4に示すアクティブマトリクス基板の製造においては、各画素内に画素駆動用の回 路素子 51を形成した後、ドライエッチング等の工程により、ゲート配線 52及びガード リング 54を形成する。この配線のエッチング工程において、ゲート配線 52には電荷 が蓄積される力 図 4の形態のアクティブマトリクス基板によれば、ゲート配線 52に蓄 積された電荷の一部は、ガードリング 54に移動するため、ゲート配線 52には、回路 素子 51を静電破壊するほどの大きな電荷が蓄積されなくなる。なお、ガードリング 54 を含む額縁部は、基板完成までに切り取られる。このようにして、従来では、画素駆 動用の回路素子 51が製造中に静電破壊されることを防止して 、た。  In the production of the active matrix substrate shown in FIG. 4, after the circuit element 51 for driving the pixel is formed in each pixel, the gate wiring 52 and the guard ring 54 are formed by a process such as dry etching. In the etching process of this wiring, the charge is stored in the gate wiring 52. According to the active matrix substrate in the form of FIG. 4, a part of the charge stored in the gate wiring 52 moves to the guard ring 54. For this reason, the gate wiring 52 does not accumulate electric charges large enough to cause electrostatic breakdown of the circuit element 51. Note that the frame portion including the guard ring 54 is cut out until the substrate is completed. Thus, conventionally, the circuit element 51 for driving the pixel is prevented from being electrostatically damaged during the manufacturing process.

[0006] ところで、近年、いわゆるモノリシック技術が適用された液晶表示装置が増加の傾向 にある。ここでいうモノリシック技術とは、図 5に示すような、画素を形成するガラス基 板上に、ドライバ等の液晶駆動に必要な周辺回路を形成する技術のことである。 図 6 (a)は、モノリシック技術が適用された液晶パネル基板の額縁部に形成されたゲ ートドライバの様子を示す正面模式図であり、（b)は、（a)に示す液晶パネル基板の 額縁部のうち、丸で囲まれた部分を拡大した模式図である。モノリシック技術が適用さ れた液晶表示装置によれば、図 6 (a)に示すように、液晶パネル基板の額縁部の基 板上に直接駆動回路 55が形成されるため、基板に対して駆動回路 55が外付けされ た形態の液晶表示装置に比べて、部材ゃ工程数の削減、ファインピッチ化、薄型軽 量化等が可能となる。し力しながら、このような液晶表示装置では、駆動回路で一続 きの配線が分断されるため、額縁部にガードリングを形成することで電荷をガードリン グへ逃がすことができない。従って、モノリシック技術が適用された液晶表示装置に おいては、画素駆動用の回路素子 51の製造中における静電破壊を防止するための 新たな技術の開発が待たれて 、た。 Meanwhile, in recent years, liquid crystal display devices to which so-called monolithic technology is applied have been increasing. The monolithic technology referred to here is a technology for forming peripheral circuits necessary for liquid crystal driving such as drivers on a glass substrate on which pixels are formed as shown in FIG. Fig. 6 (a) is a schematic front view showing the state of the gate driver formed on the frame portion of the liquid crystal panel substrate to which the monolithic technology is applied, and (b) is the frame of the liquid crystal panel substrate shown in (a). It is the schematic diagram which expanded the part enclosed by the circle among the parts. According to the liquid crystal display device to which the monolithic technology is applied, as shown in FIG. 6 (a), the drive circuit 55 is formed directly on the substrate of the frame portion of the liquid crystal panel substrate. Compared to a liquid crystal display device with an external circuit 55, the number of members can be reduced, the fine pitch can be reduced, and the weight can be reduced. However, in such a liquid crystal display device, since the continuous wiring is divided by the drive circuit, it is impossible to release charges to the guard ring by forming a guard ring in the frame portion. Therefore, the liquid crystal display device to which the monolithic technology is applied However, development of a new technology for preventing electrostatic breakdown during the manufacture of the circuit element 51 for driving the pixel has been awaited.

[0007] また、基板上に形成されるドライバ等の駆動回路にも、トランジスタ等の多数の回路 素子が含まれている。そして、駆動回路の回路素子 51同士を接続する配線 52もまた 、製造中に蓄積された電荷の逃げ道がなぐ図 6 (b)に示すように、電荷が蓄積され てしまう。従って、モノリシック技術が適用された液晶表示装置は、基板上に形成され たドライバ等の駆動回路の回路素子もまた、製造中に静電破壊されるおそれがあり、 これについても防止することができる技術の開発が待たれていた。 [0007] A drive circuit such as a driver formed on a substrate also includes a large number of circuit elements such as transistors. Then, the wiring 52 that connects the circuit elements 51 of the drive circuit also accumulates charges as shown in FIG. 6B in which there is no escape path for charges accumulated during manufacture. Therefore, in a liquid crystal display device to which the monolithic technology is applied, circuit elements of a driver circuit such as a driver formed on the substrate may also be electrostatically damaged during manufacturing, and this can be prevented. Technology development was awaited.

特許文献 1 :特開平 10— 268794号公報 (第 1, 8頁、第 1図）  Patent Document 1: Japanese Patent Laid-Open No. 10-268794 (Pages 1, 8 and 1)

発明の開示  Disclosure of the invention

発明が解決しょうとする課題  Problems to be solved by the invention

[0008] 本発明は、上記現状に鑑みてなされたものであり、モノリシック技術が適用された液 晶表示装置において、回路素子同士を接続する配線に電荷が蓄積されることを原因 として生じる回路素子の静電破壊等の特性劣化を防止することができる駆動回路基 板及びその製造方法、並びに、上記駆動回路基板を備えてなる液晶表示パネル及 び液晶表示装置を提供することを目的とするものである。 [0008] The present invention has been made in view of the above situation, and in a liquid crystal display device to which a monolithic technique is applied, a circuit element generated due to accumulation of electric charges in wirings connecting the circuit elements to each other An object of the present invention is to provide a drive circuit board and a method for manufacturing the same, and a liquid crystal display panel and a liquid crystal display device including the drive circuit board. It is.

課題を解決するための手段  Means for solving the problem

[0009] 本発明者は、 2以上の回路素子及び回路素子同士を接続する配線を備えてなる駆 動回路基板について種々検討したところ、回路素子同士を接続する配線の形成ェ 程に着目した。そして、従来の配線形成工程では、ゲート配線と同じ階層の配線の みを用いて、回路素子同士を接続していたため、ドライエッチング工程で配線に蓄積 された電荷により、回路素子が静電破壊されることを見出した。そこで、配線の形成 工程を 2以上に分割して、回路素子同士を接続する配線の少なくとも 1つを、 2以上 の層に経路が形成された構成や異なる材料により形成された 2以上の配線部位を含 む構成とすることにより、各形成工程の間に電荷が一旦放電されて当該配線に蓄積 される最大の電荷量を小さくすることができ、製造中の静電破壊等による回路素子の 特性劣化を防止することができることを見いだし、上記課題をみごとに解決することが できることに想到し、本発明に到達したものである。 [0010] すなわち、本発明は、基板上に 2以上の層が形成された積層構造を有するとともに、 2以上の回路素子が配線により接続された構造を有する駆動回路基板であって、上 記配線の少なくとも 1つは、 2以上の層に経路が形成された構成力もなる駆動回路基 板である。 [0009] The inventor conducted various studies on the drive circuit board including two or more circuit elements and wirings for connecting the circuit elements, and focused attention on the process of forming the wirings for connecting the circuit elements. In the conventional wiring formation process, the circuit elements are connected using only the wiring of the same level as the gate wiring. Therefore, the circuit elements are electrostatically destroyed by the charge accumulated in the wiring in the dry etching process. I found out. Therefore, the wiring formation process is divided into two or more, and at least one of the wirings connecting the circuit elements is divided into two or more wiring parts formed of a configuration in which paths are formed in two or more layers or different materials. In this configuration, the electric charge is once discharged during each formation process, and the maximum amount of charge accumulated in the wiring can be reduced. The inventors have found that it is possible to prevent deterioration and have come up with the present invention by conceiving that the above problems can be solved brilliantly. [0010] That is, the present invention is a drive circuit substrate having a laminated structure in which two or more layers are formed on a substrate and having a structure in which two or more circuit elements are connected by wiring. At least one of them is a drive circuit board having a constitutional force in which paths are formed in two or more layers.

本発明はまた、 2以上の回路素子が配線により接続された構造を基板上に有する駆 動回路基板であって、上記配線の少なくとも 1つは、異なる材料により形成された 2以 上の配線部位を含む構成カゝらなる駆動回路基板でもある。  The present invention also provides a driving circuit board having a structure in which two or more circuit elements are connected by wiring on the board, wherein at least one of the wirings is formed by two or more wiring parts formed of different materials. It is also a drive circuit board comprising a configuration including

本発明は更に、基板上に 2以上の回路素子及び配線を備える駆動回路基板の製造 方法であって、上記駆動回路基板の製造方法は、回路素子同士を接続する少なくと も 1つの配線を 2以上のドライエッチング工程により形成する駆動回路基板の製造方 法でもある。  The present invention further relates to a method for manufacturing a drive circuit board having two or more circuit elements and wirings on a substrate, wherein the method for manufacturing a drive circuit board includes at least one wiring for connecting circuit elements to each other. This is also a method for manufacturing a drive circuit board formed by the above dry etching process.

以下に本発明を詳述する。  The present invention is described in detail below.

[0011] 本発明の駆動回路基板は、基板上に 2以上の層が形成された積層構造を有するとと もに、 2以上の回路素子が配線により接続された構造を有するものである。なお、本 願明細書における「以上」、「以下」は、当該数値を含むものである。 [0011] The drive circuit board of the present invention has a laminated structure in which two or more layers are formed on the board, and has a structure in which two or more circuit elements are connected by wiring. In the specification of the present application, “above” and “below” include the numerical values.

上記基板としては、液晶表示パネル、液晶表示装置に用いられる場合、透明なガラ ス基板が好ましい。上記回路素子としては特に限定されないが、本発明の作用効果 を奏するためには、トランジスタ、ダイオード等の能動素子や、抵抗器、コンデンサ、 インダクタンス、変圧器等の受動素子等が好適であり、中でも、薄膜トランジスタ (TF T)が特に好適である。上記配線としては、例えば、銅 (Cu)配線、アルミニウム (A1) 配線等の単層配線や、タングステン (W) Z窒化タンタル (TaN)、チタン (Ti) Zアル ミニゥム—ケィ素 (Al— Si)系合金 Zチタン (Ti)等の積層配線等が好適に用いられる 。上記配線の形成方法としては、例えば、配線材料をスパッタ法ゃ真空蒸着法にて 成膜した後、ドライエッチングを施す方法が好適に用いられる。ドライエッチングによ れば、ウエットエッチング等のパター-ング方法に比べ、電荷の蓄積が生じやすいが The substrate is preferably a transparent glass substrate when used in a liquid crystal display panel or a liquid crystal display device. The circuit elements are not particularly limited, but active elements such as transistors and diodes, and passive elements such as resistors, capacitors, inductances, and transformers are suitable for achieving the effects of the present invention. A thin film transistor (TFT) is particularly suitable. Examples of the wiring include single-layer wiring such as copper (Cu) wiring and aluminum (A1) wiring, tungsten (W) Z tantalum nitride (TaN), titanium (Ti) Z aluminum-caine (Al-Si) ) Series alloy Z-Ti (Ti) or other laminated wiring is preferably used. As a method for forming the wiring, for example, a method in which a wiring material is formed by sputtering or vacuum vapor deposition and then dry etching is preferably used. Dry etching tends to cause charge accumulation compared to patterning methods such as wet etching.

、より高精細なパターユングが可能である。 Higher definition patterning is possible.

本発明の駆動回路基板としては、このような構成要素を必須として構成されるもので ある限り、その他の構成要素を含んでいても含んでいなくてもよぐ特に限定されるも のではない。なお、本発明の駆動回路基板は、液晶表示装置に用いられるもの (液 晶表示装置用駆動回路基板)であることが好ましい。 The drive circuit board of the present invention is not particularly limited as long as such components are included as essential components, and other components may or may not be included. Not. The drive circuit board of the present invention is preferably one used for a liquid crystal display device (drive circuit board for liquid crystal display device).

[0012] 上記配線の少なくとも 1つは、 2以上の層に経路が形成された構成力もなるものであ る。これにより、回路素子同士を接続する配線の形成工程が 2以上に分割され、従来 では 1度のドライエッチング工程により蓄積されていた電荷を複数回に分けて蓄積さ せることが可能となる。従って、各形成工程の間に電荷が一旦放電され、回路素子同 士を接続する配線に蓄積される最大の電荷量が小さくなるため、回路素子が製造中 に静電破壊されるのを防止することができる。また、配線の形成工程が 2以上に分割 されることから、配線形成におけるエッチング工程をドライエッチング工程とウエットェ ツチング工程との組み合わせにしてもよい。このようにウエットエッチング工程により配 線の一部を形成した場合、ドライエッチング工程を繰り返し行って配線形成する場合 に比べ、電荷の蓄積が生じにくぐより効果的に回路素子の製造工程における静電 破壊を防止することができる。本発明のより好ましい形態は、実質的に全ての配線が 、 2以上の層に経路が形成された構成力 なる形態である。なお、上記 2以上の層に 経路が形成された構成とは、 2以上の層にそれぞれ配線の一部が形成 (分割形成)さ れるとともに、各層に形成された配線が接続されることにより回路素子同士が接続さ れた構造を意味する。配線が分割形成される層の数としては、 2層以上であれば特 に限定されないが、本発明の作用効果を得るとともに、配線の形成工程を簡略なもの とするためには、 2層が好適である。また、本発明においては、配線が 2以上の層に 分割形成された部分を配線中に少なくとも 1箇所有して!/ヽればよ！ヽが、本発明の作 用効果を効果的に奏するためには、配線が 2以上の層に分割形成された部分を各 回路素子間にそれぞれ有する形態が好ましい。配線の材質、形状、寸法 (厚さ、幅等 )及び形成方法は、各層で同一であってもよいし、異なっていてもよい。  [0012] At least one of the wirings also has a constitutional force in which paths are formed in two or more layers. As a result, the wiring forming process for connecting the circuit elements is divided into two or more, and it is possible to accumulate the charges accumulated in the conventional dry etching process in a plurality of times. Therefore, the electric charge is once discharged during each forming process, and the maximum amount of charge accumulated in the wiring connecting the circuit elements is reduced, so that the circuit elements are prevented from being electrostatically damaged during manufacturing. be able to. In addition, since the wiring formation process is divided into two or more, the etching process in wiring formation may be a combination of a dry etching process and a wet etching process. In this way, when a part of the wiring is formed by the wet etching process, charge accumulation is less likely to occur than in the case of forming the wiring by repeatedly performing the dry etching process. Destruction can be prevented. A more preferable embodiment of the present invention is an embodiment in which substantially all the wirings have a constitutional force in which paths are formed in two or more layers. Note that the configuration in which the path is formed in the two or more layers is a circuit in which a part of the wiring is formed (divided formation) in each of the two or more layers and the wiring formed in each layer is connected. It means a structure in which elements are connected. The number of layers in which the wiring is dividedly formed is not particularly limited as long as it is two or more layers. However, in order to obtain the effects of the present invention and to simplify the wiring formation process, two layers are used. Is preferred. In the present invention, it is sufficient to have at least one part in the wiring that is divided into two or more layers! However, in order to effectively exhibit the operational effects of the present invention, a mode in which the wiring is divided into two or more layers is provided between each circuit element. The material, shape, dimensions (thickness, width, etc.) and forming method of the wiring may be the same or different in each layer.

[0013] 本発明の駆動回路基板は、少なくとも 1つの駆動回路が基板上に形成されたもので あればよぐその他の駆動回路が基板に対して外付けされていてもよい。基板上に形 成される駆動回路としては、モノリシック形成が可能な回路であれば特に限定されな いが、例えば、ソースドライノく、ゲートドライノく、タイミング発生回路 (TG)、対向電極（ Vcom)ドライバ、基準電圧 (Vref)発生回路、バイアス電圧 (Vbias)発生回路、 DC ZDC回路（直流 Z直流コンバータ）、シリアルインターフェイス (I/F)等の液晶駆動 用の回路等が好適である。液晶駆動用の回路が基板上に形成された駆動回路基板 は、液晶パネル基板として好適に用いることができる。 [0013] The drive circuit board of the present invention may have other drive circuits externally attached to the board as long as at least one drive circuit is formed on the board. The driving circuit formed on the substrate is not particularly limited as long as it can be monolithically formed. For example, a source dry gate, a gate dry gate, a timing generation circuit (TG), a counter electrode ( Vcom) driver, reference voltage (Vref) generation circuit, bias voltage (Vbias) generation circuit, DC A circuit for driving liquid crystal such as a ZDC circuit (direct current Z direct current converter) and a serial interface (I / F) is suitable. A drive circuit board in which a circuit for driving liquid crystal is formed on a substrate can be suitably used as a liquid crystal panel substrate.

[0014] 本発明の駆動回路基板の好ましい形態としては、上記回路素子は、薄膜トランジスタ であり、上記配線の少なくとも 1つは、ゲート電極配置層及びソース電極配置層に経 路が形成された構成からなる形態が挙げられる。これによれば、回路素子同士を接 続する配線を既存の配線の形成工程の組み合わせにより形成することができるため 、低コストで回路素子の製造中の静電破壊を防止することができる。上記薄膜トラン ジスタ (TFT)としては、信頼性向上の観点から、オフセットゲート構造や LDD構造を 有するものが好ましぐ回路の安定動作、低消費電力等の観点から、相補型電界効 果トランジスタ (CMOS— FET)であることが好ましい。また、融点が低いガラス基板 等に形成される TFTとしては、半導体層が連続粒界 (CG)シリコン膜やポリシリコン 膜等力もなるものが好ましい。中でも、 CGシリコン膜を用いた TFTは、 CGシリコン膜 が高い電子移動度を有することから、駆動回路を構成する TFTとして特に好適に用 いられる。  In a preferred embodiment of the drive circuit board of the present invention, the circuit element is a thin film transistor, and at least one of the wirings has a configuration in which a path is formed in the gate electrode arrangement layer and the source electrode arrangement layer. The form which becomes is mentioned. According to this, since the wiring for connecting the circuit elements can be formed by a combination of the existing wiring forming processes, electrostatic breakdown during the manufacture of the circuit elements can be prevented at a low cost. As the thin film transistor (TFT), a complementary field effect transistor (TFT) is preferred from the viewpoint of stable operation of a circuit, low power consumption, etc., which are preferable for those having an offset gate structure or LDD structure from the viewpoint of improving reliability. CMOS-FET) is preferable. Further, as a TFT formed on a glass substrate having a low melting point, it is preferable that the semiconductor layer has a continuous grain boundary (CG) silicon film or a polysilicon film. Among these, TFTs using CG silicon films are particularly suitable for use as TFTs constituting drive circuits because CG silicon films have high electron mobility.

[0015] 本発明はまた、 2以上の回路素子が配線により接続された構造を基板上に有する駆 動回路基板であって、上記配線の少なくとも 1つは、異なる材料により形成された 2以 上の配線部位を含む構成力もなる駆動回路基板でもある。このような場合にお 、ても 、回路素子同士を接続する配線の形成工程が 2以上に分割されることから、回路素 子が配線の形成工程において静電破壊されることを防止することができる。  [0015] The present invention also provides a driving circuit board having a structure in which two or more circuit elements are connected by wiring on the board, wherein at least one of the wirings is formed of two or more different materials. It is also a drive circuit board having a component power including the wiring part. Even in such a case, since the wiring forming process for connecting the circuit elements is divided into two or more, it is possible to prevent the circuit element from being electrostatically damaged in the wiring forming process. it can.

なお、本発明の駆動回路基板においては、配線の少なくとも 1つが、（1) 2以上の層 に経路が形成された構成、 (2)異なる材料により形成された 2以上の配線部位を含 む構成のうち、いずれか一方、又は、（1)及び（2)の組み合わせによって構成される ことになる。  In the drive circuit board of the present invention, at least one of the wirings is (1) a configuration in which a path is formed in two or more layers, and (2) a configuration including two or more wiring parts formed of different materials. Of these, either one or a combination of (1) and (2).

[0016] 本発明の駆動回路基板に用いられる基板は、ガラス材料力もなることが好ましい。ガ ラス基板は、 IC等に用いられる半導体の Si基板に比べ、絶縁性が高ぐ回路素子の 静電気破壊を起こしやすいことから、このようなガラス基板に対して本発明を適用する ことで、本発明の作用効果を充分に得ることができる。 [0017] 本発明はまた、基板上に 2以上の回路素子及び配線を備える駆動回路基板の製造 方法であって、上記駆動回路基板の製造方法は、回路素子同士を接続する少なくと も 1つの配線をドライエッチング工程を含む 2以上のエッチング工程により形成する駆 動回路基板の製造方法でもある。本発明の駆動回路基板の製造方法によれば、回 路素子同士を接続する配線のエッチング工程が 2以上に分割され、従来ではドライ エッチング工程により 1度に蓄積されて 、た電荷が 2以上に分けて蓄積させることが 可能となる。従って、各エッチング工程の間に電荷がー且放電され、回路素子同士 を接続する配線に蓄積される最大の電荷量が小さくなるため、回路素子が製造中に 静電破壊されるのを防止することができ、その結果、高信頼性の駆動回路基板を製 造することができる。 [0016] The substrate used for the drive circuit substrate of the present invention preferably has a glass material strength. A glass substrate is more susceptible to electrostatic breakdown of a circuit element having higher insulation than a semiconductor Si substrate used in an IC or the like. Therefore, the present invention is applied to such a glass substrate. The effects of the invention can be sufficiently obtained. [0017] The present invention is also a method for manufacturing a drive circuit board including two or more circuit elements and wirings on a substrate, and the method for manufacturing the drive circuit board includes at least one circuit element connected to each other. It is also a method for manufacturing a drive circuit board in which wiring is formed by two or more etching processes including a dry etching process. According to the method for manufacturing a drive circuit board of the present invention, the wiring etching process for connecting the circuit elements is divided into two or more. Conventionally, the charge accumulated in one time by the dry etching process is increased to two or more. It is possible to accumulate separately. Therefore, the electric charge is discharged and discharged during each etching step, and the maximum amount of electric charge accumulated in the wiring connecting the circuit elements is reduced, so that the circuit elements are prevented from being electrostatically broken during manufacturing. As a result, a highly reliable drive circuit board can be manufactured.

[0018] 上記ドライエッチング工程は、スパッタ法ゃ真空蒸着法で成膜された配線材料をバタ 一-ングする工程であり、反応性イオンエッチング (RIE)等が好適に用いられる。上 記反応性イオンエッチング (RIE)とは、プラズマにより生成させたイオン (又はラジカ ル)を被エッチング領域の金属薄膜に衝突させることによってイオンと金属原子とをィ匕 学反応させ、反応生成物を真空排気系により外部に除去するものである。  [0018] The dry etching step is a step of sputtering a wiring material formed by sputtering or vacuum deposition, and reactive ion etching (RIE) or the like is preferably used. The reactive ion etching (RIE) described above is a reaction product of an ion and a metal atom caused to react chemically by causing ions (or radicals) generated by plasma to collide with a metal thin film in a region to be etched. Is removed to the outside by a vacuum exhaust system.

[0019] 本発明の駆動回路基板の製造方法では、ドライエッチング工程を含む 2以上のエツ チング工程により配線のパターン形成を行えば、回路素子同士を接続する配線を 2 以上の層に分割して形成してもよぐ同一の層に形成してもよいが、 2以上の層に分 割して形成すれば、製造工程の簡略ィ匕を図ることができる。 2以上の層に分割して形 成する場合には、配線が分割形成される層の数としては、 2層が好適である。同一の 層に形成する場合には、配線材料の成膜工程をスパッタ法ゃ真空蒸着法にて 1回で 行ってエッチング工程のみを 2回以上に分けて行ってもよいし、配線材料の成膜ェ 程及びエッチング工程を 2回以上繰り返して行ってもよ ヽ。配線材料の成膜工程を 2 回以上に分けて行う場合には、配線材料、成膜条件等を変更することが可能である。 本発明では、配線が分割形成される部分を配線中に少なくとも 1箇所設ければよい 力 本発明の作用効果を効果的に奏するためには、配線が分割形成される部分を各 回路素子間にそれぞれ設けることが好ましい。  In the method for manufacturing a drive circuit board according to the present invention, if wiring patterns are formed by two or more etching processes including a dry etching process, the wiring for connecting circuit elements is divided into two or more layers. Although it may be formed in the same layer, it may be formed in two or more layers, whereby the manufacturing process can be simplified. In the case where the wiring is divided into two or more layers, two layers are preferable as the number of layers in which the wiring is divided. In the case of forming the same layer, the wiring material film forming process may be performed once by sputtering or vacuum evaporation, and only the etching process may be performed twice or more. The film process and etching process may be repeated twice or more. When the wiring material film forming process is performed twice or more, the wiring material, film forming conditions, etc. can be changed. In the present invention, it suffices to provide at least one portion where the wiring is divided and formed in the wiring. In order to effectively achieve the effect of the present invention, the portion where the wiring is divided is formed between the circuit elements. Each is preferably provided.

[0020] 上記 2以上のエッチング工程は、ウエットエッチング工程を含むことが好ましい。すな わち、本発明の駆動回路基板の製造方法では、配線のエッチング工程が 2以上に分 割されることから、配線の形成工程をドライエッチング工程とウエットエッチング工程と の組み合わせにしてもょ 、。このようにウエットエッチング工程により配線の一部を形 成した場合、ドライエッチング工程を繰り返し行って配線形成する場合に比べ、電荷 の蓄積が生じにくぐより効果的に回路素子の製造工程における静電破壊を防止す ることがでさる。 [0020] The two or more etching steps preferably include a wet etching step. sand That is, in the method for manufacturing a drive circuit board according to the present invention, the wiring etching process is divided into two or more, so the wiring forming process may be a combination of a dry etching process and a wet etching process. In this way, when a part of the wiring is formed by the wet etching process, charge accumulation is less likely to occur than when the wiring is formed by repeating the dry etching process. It is possible to prevent destruction.

[0021] 本発明の駆動回路基板の製造方法では、上記回路素子は、薄膜トランジスタであり、 上記 2以上のエッチング工程は、ゲート電極のパターユング工程及びソース電極の パター-ング工程を含むことが好まし 、。このようにエッチング工程がゲート電極のパ ターニング工程及びソース電極のパター-ング工程を含むことにより、回路素子同士 を接続する配線とゲート電極やソース電極とを既存の工程により一括して形成するこ とができるので、安価な方法で回路素子が製造中に静電破壊されるのを防止するこ とがでさる。  In the method for manufacturing a drive circuit board according to the present invention, the circuit element is a thin film transistor, and the two or more etching processes preferably include a patterning process for a gate electrode and a patterning process for a source electrode. Better ,. As described above, the etching process includes the patterning process of the gate electrode and the patterning process of the source electrode, so that the wiring for connecting the circuit elements and the gate electrode and the source electrode can be collectively formed by the existing process. Therefore, it is possible to prevent the circuit element from being electrostatically damaged during manufacture by an inexpensive method.

[0022] 本発明の駆動回路基板の製造方法で用いられる基板としては、ガラス材料力もなる ことが好ましい。ガラス基板は、 IC等に用いられる半導体の Si基板に比べ、絶縁性が 高ぐ回路素子の静電気破壊を起こしやすいことから、このようなガラス基板に対して 本発明を適用することで、本発明の作用効果を充分に得ることができる。  [0022] The substrate used in the method for manufacturing a drive circuit board of the present invention preferably has a glass material strength. Since a glass substrate is more likely to cause electrostatic breakdown of a circuit element having higher insulation than a semiconductor Si substrate used for ICs and the like, the present invention is applied to such a glass substrate. It is possible to sufficiently obtain the operational effects.

[0023] 本発明は更に、上記駆動回路基板、又は、上記駆動回路基板の製造方法により製 造されてなる駆動回路基板を備える液晶表示パネル及び液晶表示装置でもある。本 発明の液晶表示パネル及び液晶表示装置によれば、 IC等に用いられる半導体の Si 基板に比べ、絶縁性が高ぐ静電気破壊を起こしやすいガラス基板においても、回路 素子における静電破壊等の特性劣化が防止された高信頼性の駆動回路基板を備え ることから、高信頼性の液晶表示パネル及び液晶表示装置を提供することができる。 本発明の液晶表示パネルの好ま U、形態としては、上記駆動回路基板が液晶表示 パネルを構成する液晶パネル基板として用いられた形態が挙げられる。このように、 駆動回路 (液晶駆動用の周辺回路）が液晶パネル基板上に形成された形態の液晶 表示パネルは、別名システム液晶パネルとも呼ばれ、駆動回路基板が液晶パネル基 板に対して外付けされた形態と比べ、部材ゃ工程数の削減、ファインピッチ化及び薄 型軽量化等が可能となる。 The present invention is also a liquid crystal display panel and a liquid crystal display device including the drive circuit board or the drive circuit board manufactured by the method for manufacturing the drive circuit board. According to the liquid crystal display panel and the liquid crystal display device of the present invention, characteristics such as electrostatic breakdown in circuit elements can be obtained even on a glass substrate that has high insulation and is prone to electrostatic breakdown as compared with a semiconductor Si substrate used in an IC or the like. Since a highly reliable drive circuit board in which deterioration is prevented is provided, a highly reliable liquid crystal display panel and a liquid crystal display device can be provided. A preferred form of the liquid crystal display panel of the present invention is a form in which the drive circuit board is used as a liquid crystal panel substrate constituting the liquid crystal display panel. In this way, a liquid crystal display panel in which a drive circuit (peripheral circuit for driving liquid crystal) is formed on a liquid crystal panel substrate is also called a system liquid crystal panel, and the drive circuit substrate is external to the liquid crystal panel substrate. Compared to the attached form, the number of parts is reduced, the fine pitch and thin It is possible to reduce the weight of the mold.

発明の効果  The invention's effect

[0024] 本発明の駆動回路基板によれば、配線の少なくとも 1つが、 2以上の層に経路が形 成された構成や異なる材料により形成された 2以上の配線部位を含む構成を有する ことから、配線の形成工程が 2以上に分割されており、配線パターン形成時のドライ エッチングにより配線に蓄積された電荷が各層形成工程の間に一旦放電され、回路 素子同士を接続する配線に蓄積される最大の電荷量を小さくすることができ、回路素 子が製造中に静電破壊されるのを防止することができる。また、配線の形成工程が 2 以上に分割されることから、配線形成におけるエッチング工程をドライエッチング工程 とウエットエッチング工程との組み合わせにすることも可能であり、このような場合には [0024] According to the drive circuit board of the present invention, at least one of the wirings has a configuration in which paths are formed in two or more layers or a configuration including two or more wiring parts formed of different materials. The wiring formation process is divided into two or more, and the charge accumulated in the wiring by dry etching at the time of wiring pattern formation is discharged once during each layer forming process and accumulated in the wiring connecting circuit elements to each other The maximum amount of charge can be reduced, and circuit elements can be prevented from being electrostatically destroyed during manufacturing. In addition, since the wiring formation process is divided into two or more, it is possible to combine the etching process in wiring formation with a dry etching process and a wet etching process.

、ドライエッチング工程を繰り返し行って配線形成する場合に比べ、電荷の蓄積が生 じにくぐより効果的に回路素子の製造工程における静電破壊を防止することができ る。 As compared with the case where the wiring is formed by repeatedly performing the dry etching process, electrostatic charge breakdown can be prevented more effectively in the circuit element manufacturing process than the accumulation of electric charges.

発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION

[0025] 以下に実施形態を掲げ、本発明について図面を参照しながら更に詳細に説明する 力 本発明はこれらの実施形態のみに限定されるものではない。  [0025] Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. The present invention is not limited to only these embodiments.

[0026] (実施形態 1)  (Embodiment 1)

図 1 (a)は、本発明の実施形態であるモノリシック技術が適用された液晶パネル基板 ( 駆動回路基板)の額縁部の回路配置を示す正面模式図であり、（b)は、（a)に示す 液晶パネル基板の額縁部のうち、丸で囲まれた部分の回路配置を拡大した模式図 である。  FIG. 1 (a) is a schematic front view showing a circuit arrangement of a frame portion of a liquid crystal panel substrate (driving circuit substrate) to which the monolithic technology according to the embodiment of the present invention is applied, and FIG. It is the schematic diagram which expanded the circuit arrangement | positioning of the part enclosed with the circle | round | yen among the frame parts of a liquid crystal panel board | substrate shown in FIG.

本実施形態の液晶パネル基板 (駆動回路基板)では、回路素子 11同士を接続する 配線の一部にソース配線と同じ階層の配線 13を用いている。具体的には、図 1 (b) に示すように、回路素子 11同士を接続する配線のうち、回路素子 11との接続部分（ 回路素子同士を接続する配線の両端部分）には、ゲート配線と同じ階層の配線 12が 用いられ、それ以外の部分（回路素子同士を接続する配線の中間部分）には、ソー ス配線と同じ階層の配線 13が用いられている。このような構成の配線を形成するに は、 2つの工程、すなわちゲート配線と同じ階層の配線 12を形成する工程と、ソース 配線と同じ階層の配線 13を形成する工程とが必要となる。このように、配線の形成ェ 程が 2回に分けられることにより、従来、配線パターユング時のドライエッチングにより 1度に蓄積されていた電荷が 2度に分けて蓄積させることが可能となる。そして、この 形成工程の間に、電荷が一旦放電されるので、回路素子 11同士を接続する配線に 蓄積される最大の電荷量は、従来よりも小さくなる。その結果、回路素子 11が製造中 に静電破壊されるのを防止することができる。また、ソース配線と同じ階層の配線 13 の形成工程におけるエッチングプロセスをウエットエッチングで行えば、配線 13に電 荷の蓄積が起こりにくぐ回路素子が製造中に静電破壊されるのをより効果的に防止 することができる。 In the liquid crystal panel substrate (drive circuit substrate) of the present embodiment, the wiring 13 at the same level as the source wiring is used as part of the wiring that connects the circuit elements 11 to each other. Specifically, as shown in FIG. 1 (b), of the wirings connecting the circuit elements 11 to each other, the gate wiring is connected to the connection part with the circuit elements 11 (both ends of the wiring connecting the circuit elements). Wiring 12 at the same level as the source wiring is used for the other parts (intermediate part of the wiring connecting the circuit elements). In order to form a wiring having such a configuration, two processes, that is, a process of forming a wiring 12 at the same level as the gate wiring, A process of forming the wiring 13 at the same level as the wiring is required. As described above, the wiring formation process is divided into two times, so that it is possible to accumulate charges that have been accumulated once by dry etching during wiring patterning in two. Since charges are once discharged during this formation process, the maximum amount of charge accumulated in the wiring connecting the circuit elements 11 is smaller than in the prior art. As a result, it is possible to prevent the circuit element 11 from being electrostatically damaged during manufacture. In addition, if the etching process in the formation process of the wiring 13 at the same level as the source wiring is performed by wet etching, it is more effective that circuit elements that are unlikely to accumulate electric charge in the wiring 13 are electrostatically destroyed during manufacturing. Can be prevented.

[0027] 本実施形態においては、回路素子 11としてトップゲート型薄膜トランジスタを用いた。  In the present embodiment, a top gate type thin film transistor is used as the circuit element 11.

図 2 (a)は、実施形態 1の駆動回路基板において、基板上に形成された駆動回路の 配線部の構造を示す断面模式図であり、（b)は、（a)に示す駆動回路基板において 、基板上に形成された駆動回路の TFT部の構造を示す断面模式図である。  FIG. 2 (a) is a schematic cross-sectional view showing the structure of the wiring portion of the drive circuit formed on the substrate in the drive circuit substrate of Embodiment 1, and FIG. 2 (b) is the drive circuit substrate shown in (a). FIG. 2 is a schematic cross-sectional view showing the structure of the TFT portion of the drive circuit formed on the substrate.

以下、本実施形態のトップゲート型薄膜トランジスタを有する駆動回路基板の製造方 法について説明する。  Hereinafter, a method for manufacturing a drive circuit substrate having the top gate type thin film transistor of this embodiment will be described.

[0028] (1) Si層の形成  [0028] (1) Formation of Si layer

まず、原料ガスとしてシランガスを用いたプラズマ化学気相成長法 (PECVD)により、 ガラス基板 21上にアンダーコート（SiO ZSiNO) 28とアモルファスシリコン（a— Si)  First, undercoat (SiO ZSiNO) 28 and amorphous silicon (a-Si) are formed on glass substrate 21 by plasma enhanced chemical vapor deposition (PECVD) using silane gas as the source gas.

2  2

層を形成した。アンダーコート 28は、他に（SiNZSiO )等でもよい。通常の PECVD  A layer was formed. In addition, the undercoat 28 may be (SiNZSiO 2) or the like. Normal PECVD

2  2

により形成した a— Siには約 10%の水素が含まれることから、そのままレーザー'ァ- ールを行うと、水素が突沸して層が荒れるおそれがあるため、次いで、約 500°Cで a Si層中の水素濃度を低減する処理 (脱水素処理)を行う。脱水素処理に関し、 50 0°C程度までの昇温はガラス基板の特性上特に問題な 、が、時間を延長すればより 低温で行うことも可能であり、例えば、 430°Cで 2時間程度行ってもよい。このような脱 水素処理により水素含有率を 1%前後まで落とすことができると考えられる。  Since a-Si formed by the above method contains about 10% hydrogen, if laser beam is performed as it is, there is a risk of hydrogen bumping and roughening the layer. a Process to reduce the hydrogen concentration in the Si layer (dehydrogenation process). Regarding dehydrogenation, raising the temperature up to about 500 ° C is particularly problematic in terms of the characteristics of the glass substrate, but if the time is extended, it can be carried out at a lower temperature, for example, about 430 ° C for about 2 hours. You may go. Such a dehydrogenation process can reduce the hydrogen content to around 1%.

また、この後、金属触媒を塗布して、 CG—シリコンィ匕するための前処理を行ってもよ い。  After this, a metal catalyst may be applied and a pretreatment for CG-silicone may be performed.

次に、 a— Si層に対してチャネルドープを行った。チャネルドープでは、 NMOSの場 合には、 a— Si層に対してボロン等の 3価の原子、 PMOSの場合には、リン等の 5価 の原子を注入する。 Next, channel doping was performed on the a-Si layer. In channel dope, NMOS field In this case, a trivalent atom such as boron is implanted into the a-Si layer, and in the case of PMOS, a pentavalent atom such as phosphorus is implanted.

また、このチャネルドープは、下記に示すゲート絶縁膜 23の形成後に行うことも可能 である。  This channel doping can also be performed after the formation of the gate insulating film 23 shown below.

次に、レーザー'ァニールを行って、 a— Siを溶融、冷却、固化させることによりポリ（ 多結晶）シリコン (p— Si)にした。本実施形態では、出力 200W前後のエキシマレー ザを用いた。  Next, laser annealing was performed, and a-Si was melted, cooled, and solidified to obtain poly (polycrystalline) silicon (p-Si). In this embodiment, an excimer laser with an output of around 200 W was used.

また、レーザー'ァニールの前処理として、固相結晶化の熱処理を行ってもよい。 次に、フォトリソと四フッ化炭素（CF )ガスによるドライエッチングを行い、トランジスタ  Further, as a pretreatment for laser annealing, a heat treatment for solid phase crystallization may be performed. Next, dry etching using photolithography and carbon tetrafluoride (CF 3) gas is performed to produce a transistor.

4  Four

部分以外の P - Si層を除去し、薄膜トランジスタ領域 24を形成した。  The P—Si layer other than the portion was removed, and the thin film transistor region 24 was formed.

[0029] (2)ゲート絶縁膜の形成 [0029] (2) Formation of gate insulating film

続 、て、原料ガスとしてテトラエチルオルトシリケート（TEOS)ガスを用いた PECVD により二酸ィ匕ケィ素（SiO )膜からなるゲート絶縁膜 23を形成した。ゲート絶縁膜材  Subsequently, a gate insulating film 23 made of a silicon dioxide (SiO 2) film was formed by PECVD using tetraethylorthosilicate (TEOS) gas as a source gas. Gate insulation film material

2  2

料としては、その他、 SiNx、 SiON等を用いることができる。  In addition, SiNx, SiON, etc. can be used as the material.

(3)チャネルドープ  (3) Channel dope

次に、 Nch、 Pchのトランジスタのしきい値を制御するため、リンを Nchにチャネルド ープした。  Next, phosphorus was channel-doped to Nch to control the threshold values of the Nch and Pch transistors.

(4)ゲートメタルの形成  (4) Formation of gate metal

続いて、スパッタ法により抵抗 1 Ω /口のタングステン (W)膜、及び、抵抗 500 Ω / 口の窒化タンタル (TaN)膜をこの順で形成した。ゲートメタルに用いられる金属とし ては、その他、 MoW、 A1等の低抵抗金属、表面が平坦で特性の安定した高融点金 属等が用いられる。次に、フォトリソと原料ガスとして Ar、 SF、 CF、 O、 C1等の混  Subsequently, a tungsten (W) film having a resistance of 1 Ω / port and a tantalum nitride (TaN) film having a resistance of 500 Ω / port were formed in this order by sputtering. Other metals that can be used for the gate metal include low resistance metals such as MoW and A1, and high melting point metals that have a flat surface and stable characteristics. Next, a mix of Ar, SF, CF, O, C1, etc. as photolithography and source gas.

6 4 2 2 合ガス分量を調整したドライエッチングを行い、 2層構造のゲートメタル (配線） 22を 形成した。ゲートメタル (配線） 22は、 TFT部のゲート電極パターンと配線部の配線 パターンの一部とから構成されるものである。  6 4 2 2 Dry etching with the combined gas content adjusted was performed to form a two-layer gate metal (wiring) 22. The gate metal (wiring) 22 is composed of a gate electrode pattern of the TFT portion and a part of the wiring pattern of the wiring portion.

[0030] (5)イオンドーピング [0030] (5) Ion doping

続いて、イオン注入したくない場所をフォトレジストで覆って保護した (マスキング)。そ の後、トランジスタのソース ·ドレイン領域にイオン注入を行った (イオンドーピング)。 このとき、 P型半導体とするには、ボロン等が注入され、 N型半導体とするには、リン等 が注入される。次に、イオン注入により p— Si薄膜表面近傍に存在しているイオンを p — Si層内に取り込んで活性ィ匕させるために、エキシマレーザを照射した。この活性化 処理により電気伝導性を向上することができる。 Subsequently, the area where ion implantation was not desired was covered with a photoresist to protect it (masking). After that, ion implantation was performed in the source / drain regions of the transistor (ion doping). At this time, boron or the like is implanted to make a P-type semiconductor, and phosphorus or the like is implanted to make an N-type semiconductor. Next, an excimer laser was irradiated so that ions existing near the surface of the p-Si thin film could be taken into the p-Si layer and activated by ion implantation. The electrical conductivity can be improved by this activation treatment.

また、活性化処理としては、高温焼成する方法もある。 Further, as an activation treatment, there is a method of baking at a high temperature.

(6)層間絶縁膜の形成 (6) Formation of interlayer insulation film

続いて、 PECVDにより層間絶縁膜 27を形成した。層間絶縁膜材料としては、 SiNx 、 SiON等を用いることができる。 Subsequently, an interlayer insulating film 27 was formed by PECVD. SiNx, SiON, etc. can be used as the interlayer insulating film material.

(7)水素アニーリング処理 (7) Hydrogen annealing treatment

特性安定ィ匕のための水素アニーリング処理を行った。 Hydrogen annealing treatment was performed to stabilize the characteristics.

(8)コンタクト部の形成  (8) Formation of contact part

続いて、フォトリソ後、フッ酸系のウエットエッチング液を用いてコンタクトホール (コン タクト部） 26の穴開けを行った。 p— Siの厚さが薄いため、ドライエッチングよりもエツ チング精度は劣るが、選択比が高いウエットエッチング法を採用した。 Subsequently, after photolithography, a contact hole (contact part) 26 was formed using a hydrofluoric acid-based wet etching solution. Since the p-Si is thin, the etching accuracy is inferior to that of dry etching, but a wet etching method with a high selectivity is used.

(9)ソースメタルの形成  (9) Source metal formation

続いて、スパッタリング法でチタン (Ti)膜、アルミニウム—ケィ素 (Al— Si)系合金膜、 Ti膜の順で金属薄膜を形成した。次に、フォトリソ後、 Tiについては、フッ酸溶液、 A1 については、リン酸、硝酸、酢酸の混合溶液を用いたウエットエッチングを行い、 3層 構造の抵抗 1 ΩΖ口のソース（ドレイン)メタル (配線） 25を形成するとともに、コンタク ト部 26を完成させた。このとき、ソース（ドレイン)メタル (配線） 25としては、 TFTのソ ース電極に接続された配線部分と、 TFTのドレイン電極に接続された配線部分と、 配線部のコンタクト部 26を介してゲートメタル 22に接続された配線部分とが形成され た。そして、ソース（ドレイン)メタル 25のパターンの一部と、ゲートメタル 22のパターン とが接続されたことにより、 TFTのゲート電極同士が接続され、駆動回路が完成した 本実施形態では、ソースメタルの形成後、 PECVDによる保護膜 (層間絶縁膜の 1種 )の形成、榭脂膜塗布、透明電極 (ITO)の形成等を行って低温 P— Si製造工程を完 了した。 [0032] 本実施形態により製造された駆動回路基板によれば、 TFT同士を接続する配線の 形成工程がゲートメタル 22を形成する工程とソースメタル 23を形成する工程とに分 割されている。また、ソースメタル 23を形成する工程におけるエッチングプロセスは、 ウエットエッチングで行った。その結果、回路素子同士を接続する配線に蓄積される 最大の電荷量を小さくすることができため、回路素子が製造中に静電破壊されるのを 効果的に防止することができた。 Subsequently, a metal thin film was formed in the order of a titanium (Ti) film, an aluminum-silicon (Al-Si) alloy film, and a Ti film by a sputtering method. Next, after photolithography, wet etching is performed using a hydrofluoric acid solution for Ti and a mixed solution of phosphoric acid, nitric acid, and acetic acid for A1, and a three-layer resistance 1 Ω well source (drain) metal ( Wiring) 25 was formed and contact part 26 was completed. At this time, the source (drain) metal (wiring) 25 includes a wiring portion connected to the TFT source electrode, a wiring portion connected to the TFT drain electrode, and a contact portion 26 of the wiring portion. A wiring portion connected to the gate metal 22 was formed. Then, by connecting a part of the pattern of the source (drain) metal 25 and the pattern of the gate metal 22, the TFT gate electrodes are connected to each other, and the drive circuit is completed. After the formation, the low-temperature P-Si manufacturing process was completed by forming a protective film (one kind of interlayer insulating film) by PECVD, applying a resin film, and forming a transparent electrode (ITO). [0032] According to the drive circuit substrate manufactured according to the present embodiment, the process of forming the wiring connecting the TFTs is divided into the process of forming the gate metal 22 and the process of forming the source metal 23. The etching process in the step of forming the source metal 23 was performed by wet etching. As a result, the maximum amount of charge accumulated in the wiring connecting the circuit elements can be reduced, so that the circuit elements can be effectively prevented from being electrostatically damaged during manufacture.

[0033] (実施形態 2)  [0033] (Embodiment 2)

図 3 (a)は、実施形態 2の駆動回路基板において、基板上に形成された駆動回路の 配線部の構造を示す断面模式図であり、（b)は、（a)に示す駆動回路基板において 、基板上に形成された駆動回路の TFT部の構造を示す断面模式図である。  FIG. 3 (a) is a schematic cross-sectional view showing the structure of the wiring portion of the drive circuit formed on the substrate in the drive circuit substrate of Embodiment 2, and FIG. 3 (b) is the drive circuit substrate shown in (a). FIG. 2 is a schematic cross-sectional view showing the structure of the TFT portion of the drive circuit formed on the substrate.

本実施形態では、実施形態 1に対し、製造工程順を、（4)ゲートメタルの形成、（2)ゲ ート絶縁膜の形成、（1) Si層の形成、（5)イオンドーピング、（7)水素アニーリング処 理、（8)コンタクト部の形成、（9)ソースメタルの形成の順に変更することで、ボトムゲ ート型薄膜トランジスタを有する駆動回路基板の製造を行った。なお、工程順を変更 したことに伴 、、脱水素処理の処理温度等を適宜変更した。  In the present embodiment, the order of the manufacturing process is as follows: (4) gate metal formation, (2) gate insulating film formation, (1) Si layer formation, (5) ion doping, By changing the order of 7) hydrogen annealing treatment, (8) contact portion formation, and (9) source metal formation, a drive circuit board having a bottom gate type thin film transistor was manufactured. As the process order was changed, the dehydrogenation process temperature and other factors were changed as appropriate.

本実施形態により製造された駆動回路基板においても、実施形態 1と同様の作用効 果を得ることができた。  In the drive circuit board manufactured according to the present embodiment, the same effects as those of the first embodiment could be obtained.

[0034] なお、本願は、 2004年 8月 27曰に出願された曰本国特許出願第 2004— 249097 号を基礎として、（合衆国法典 35卷第 119条に基づく）優先権を主張するものである 。該出願の内容は、その全体が本願中に参照として組み込まれている。  [0034] This application claims priority (based on 35 USC 119), based on Japanese Patent Application No. 2004-249097, filed August 27, 2004. . The contents of the application are hereby incorporated by reference in their entirety.

図面の簡単な説明  Brief Description of Drawings

[0035] [図 1] (a)は、本発明の実施形態に係るモノリシック技術が適用された液晶パネル基 板 (駆動回路基板)の額縁部の回路配置を示す正面模式図であり、（b)は、（a)に示 す液晶パネル基板の額縁部のうち、丸で囲まれた部分の回路配置を拡大した模式 図である。  [0035] FIG. 1 (a) is a schematic front view showing a circuit arrangement of a frame portion of a liquid crystal panel substrate (driving circuit board) to which a monolithic technique according to an embodiment of the present invention is applied. ) Is an enlarged schematic diagram of the circuit arrangement of the circled portion of the frame portion of the liquid crystal panel substrate shown in (a).

[図 2] (a)は、実施形態 1の駆動回路基板において、基板上に形成された駆動回路の 配線部の構造を示す断面模式図であり、（b)は、（a)に示す駆動回路基板において 、基板上に形成された駆動回路の TFT部の構造を示す断面模式図である。 [図 3] (a)は、実施形態 2の駆動回路基板において、基板上に形成された駆動回路の 配線部の構造を示す断面模式図であり、（b)は、（a)に示す駆動回路基板において 、基板上に形成された駆動回路の TFT部の構造を示す断面模式図である。 FIG. 2 (a) is a schematic cross-sectional view showing the structure of a wiring portion of a drive circuit formed on the substrate in the drive circuit board of Embodiment 1, and FIG. 2 (b) is a drive diagram shown in FIG. 2 (a). FIG. 3 is a schematic cross-sectional view showing a structure of a TFT portion of a drive circuit formed on a circuit board. FIG. 3 (a) is a schematic cross-sectional view showing the structure of a wiring portion of a drive circuit formed on the substrate in the drive circuit board of Embodiment 2, and FIG. 3 (b) is a drive diagram shown in FIG. 3 (a). FIG. 3 is a schematic cross-sectional view showing a structure of a TFT portion of a drive circuit formed on a circuit board.

[図 4]従来の液晶表示装置に搭載されるアクティブマトリクス基板の製造途中の構成 を示す正面模式図である。 FIG. 4 is a schematic front view showing a structure in the process of manufacturing an active matrix substrate mounted on a conventional liquid crystal display device.

[図 5]モノリシック技術が適用された液晶パネル基板 (駆動回路基板)の構成を示す 正面模式図である。  FIG. 5 is a schematic front view showing a configuration of a liquid crystal panel substrate (driving circuit substrate) to which the monolithic technology is applied.

[図 6] (a)は、従来のモノリシック技術が適用された液晶パネル基板 (駆動回路基板） の額縁部に形成されたゲートドライバの様子を示す正面模式図であり、（b)は、（a)に 示す液晶パネル基板の額縁部のうち、丸で囲まれた部分を拡大した模式図である。 符号の説明  [FIG. 6] (a) is a schematic front view showing a state of a gate driver formed on a frame portion of a liquid crystal panel substrate (driving circuit substrate) to which a conventional monolithic technology is applied, and (b) is ( It is the schematic diagram which expanded the part enclosed with the circle | round | yen among the frame parts of the liquid crystal panel board | substrate shown to a). Explanation of symbols

5, 55:駆動回路 5, 55: Drive circuit

6, 56:配線 6, 56: Wiring

11, 51:薄膜トランジスタ（回路素子）  11, 51: Thin film transistor (circuit element)

12, 22, 52:ゲー卜メタル（配線）  12, 22, 52: Gate metal (wiring)

13, 25, 53:ソース（ドレイン)メタル（配線）  13, 25, 53: Source (drain) metal (wiring)

21:ガラス基板 21: Glass substrate

23:ゲート絶縁膜  23: Gate insulation film

24:チャネル領域  24: Channel area

26:コンタクト咅  26: Contact 咅

27:層間絶縁膜  27: Interlayer insulation film

28:アンダーコート  28: Undercoat

50:画素電極  50: Pixel electrode

54:ガードリング  54: Guard ring

61:画素領域  61: Pixel area

62:ゲートドライバ  62: Gate driver

63:ソースドライバ  63: Source driver

64：基準電圧 (Vref)発生回路 ：バイアス電圧（Vbias)発生回路:タイミング発生回路 (TG) ：対向電極 (Vcom)ドライバ: DC/DC回路 64: Reference voltage (Vref) generation circuit : Bias voltage (Vbias) generation circuit: Timing generation circuit (TG): Counter electrode (Vcom) driver: DC / DC circuit

Claims

請求の範囲 The scope of the claims [1] 基板上に 2以上の層が形成された積層構造を有するとともに、 2以上の回路素子が 配線により接続された構造を有する駆動回路基板であって、  [1] A drive circuit board having a laminated structure in which two or more layers are formed on a substrate and having a structure in which two or more circuit elements are connected by wiring, 該配線の少なくとも 1つは、 2以上の層に経路が形成された構成からなる  At least one of the wirings has a configuration in which paths are formed in two or more layers. ことを特徴とする駆動回路基板。  A drive circuit board characterized by that. [2] 前記回路素子は、薄膜トランジスタであり、 [2] The circuit element is a thin film transistor, 前記配線の少なくとも 1つは、ゲート電極配置層及びソース電極配置層に経路が形 成された構成からなる  At least one of the wirings has a configuration in which a path is formed in the gate electrode arrangement layer and the source electrode arrangement layer. ことを特徴とする請求項 1記載の駆動回路基板。  The drive circuit board according to claim 1, wherein: [3] 前記基板は、ガラス材料力 なることを特徴とする請求項 1記載の駆動回路基板。 3. The drive circuit board according to claim 1, wherein the substrate is made of a glass material. [4] 2以上の回路素子が配線により接続された構造を基板上に有する駆動回路基板であ つて、 [4] A drive circuit board having a structure in which two or more circuit elements are connected by wiring on the board, 該配線の少なくとも 1つは、異なる材料により形成された 2以上の配線部位を含む構 成からなる  At least one of the wirings has a configuration including two or more wiring parts formed of different materials. ことを特徴とする駆動回路基板。  A drive circuit board characterized by that. [5] 前記基板は、ガラス材料力もなることを特徴とする請求項 4記載の駆動回路基板。 5. The drive circuit board according to claim 4, wherein the board also has a glass material force. [6] 基板上に 2以上の回路素子及び配線を備える駆動回路基板の製造方法であって、 該駆動回路基板の製造方法は、回路素子同士を接続する少なくとも 1つの配線をド ライエッチング工程を含む 2以上のエッチング工程により形成する [6] A method for manufacturing a drive circuit board comprising two or more circuit elements and wirings on a substrate, wherein the drive circuit board manufacturing method comprises performing a dry etching process on at least one wiring for connecting circuit elements to each other. Including two or more etching processes ことを特徴とする駆動回路基板の製造方法。  A method of manufacturing a drive circuit board. [7] 前記 2以上のエッチング工程は、ウエットエッチング工程を含むことを特徴とする請求 項 6記載の駆動回路基板の製造方法。 7. The method for manufacturing a drive circuit board according to claim 6, wherein the two or more etching steps include a wet etching step. [8] 前記回路素子は、薄膜トランジスタであり、 [8] The circuit element is a thin film transistor, 前記 2以上のエッチング工程は、ゲート電極のパターユング工程及びソース電極の パターニング工程を含む  The two or more etching processes include a gate electrode patterning process and a source electrode patterning process. ことを特徴とする請求項 6記載の駆動回路基板の製造方法。  The method for manufacturing a drive circuit board according to claim 6. [9] 前記基板は、ガラス材料力 なることを特徴とする請求項 6記載の駆動回路基板の製 造方法。 9. The method for manufacturing a drive circuit board according to claim 6, wherein the substrate is made of glass material. [10] 請求項 1記載の駆動回路基板を備えることを特徴とする液晶表示パネル。 10. A liquid crystal display panel comprising the drive circuit board according to claim 1. [11] 請求項 4記載の駆動回路基板を備えることを特徴とする液晶表示パネル。 11. A liquid crystal display panel comprising the drive circuit board according to claim 4. [12] 請求項 6記載の駆動回路基板の製造方法により製造されてなる駆動回路基板を備 えることを特徴とする液晶表示パネル。 12. A liquid crystal display panel comprising a drive circuit board manufactured by the drive circuit board manufacturing method according to claim 6. [13] 請求項 1記載の駆動回路基板を備えることを特徴とする液晶表示装置。 13. A liquid crystal display device comprising the drive circuit board according to claim 1. [14] 請求項 4記載の駆動回路基板を備えることを特徴とする液晶表示装置。 14. A liquid crystal display device comprising the drive circuit board according to claim 4. [15] 請求項 6記載の駆動回路基板の製造方法により製造されてなる駆動回路基板を備 えることを特徴とする液晶表示装置。 15. A liquid crystal display device comprising a drive circuit board manufactured by the drive circuit board manufacturing method according to claim 6.
PCT/JP2005/014762 2004-08-27 2005-08-11 Driving circuit board, method for manufacturing the same, liquid crystal display panel and liquid crystal display device WO2006022152A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036604A (en) * 1998-07-21 2000-02-02 Matsushita Electric Ind Co Ltd Manufacture of thin-film transistor circuit and liquid crystal display device
JP2003107524A (en) * 2001-10-01 2003-04-09 Matsushita Electric Ind Co Ltd Liquid crystal display device
JP2004163493A (en) * 2002-11-11 2004-06-10 Sanyo Electric Co Ltd Display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036604A (en) * 1998-07-21 2000-02-02 Matsushita Electric Ind Co Ltd Manufacture of thin-film transistor circuit and liquid crystal display device
JP2003107524A (en) * 2001-10-01 2003-04-09 Matsushita Electric Ind Co Ltd Liquid crystal display device
JP2004163493A (en) * 2002-11-11 2004-06-10 Sanyo Electric Co Ltd Display device

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