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WO2006090445A1 - Semiconductor circuit device, and method for manufacturing the semiconductor circuit device - Google Patents

Semiconductor circuit device, and method for manufacturing the semiconductor circuit device Download PDF

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Publication number
WO2006090445A1
WO2006090445A1 PCT/JP2005/002908 JP2005002908W WO2006090445A1 WO 2006090445 A1 WO2006090445 A1 WO 2006090445A1 JP 2005002908 W JP2005002908 W JP 2005002908W WO 2006090445 A1 WO2006090445 A1 WO 2006090445A1
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WO
WIPO (PCT)
Prior art keywords
wiring
type fet
fin
carrier
substrate
Prior art date
Application number
PCT/JP2005/002908
Other languages
French (fr)
Japanese (ja)
Inventor
Hidenobu Fukutome
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2005/002908 priority Critical patent/WO2006090445A1/en
Priority to JP2007504580A priority patent/JP5018475B2/en
Publication of WO2006090445A1 publication Critical patent/WO2006090445A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor integrated circuit device having a fin-type FET formed on a support substrate as a constituent element, suitable for highly integrated LSIs, and a method for manufacturing the same.
  • the present invention relates to a semiconductor integrated circuit device using a wiring embedded in a groove in a support substrate and a manufacturing method thereof for connecting constituent elements.
  • the logic macrocell is a logic circuit such as a NOT circuit or a NAND circuit, and is formed into a cell as a result of patterning the circuit layout. Therefore, the reduction of the logic macrocell is a component of it.
  • Oxide Semiconductor Field-Effect-Transistor Device size is greatly reduced.
  • reducing the size of the MOSFET involves increasing the current between the source and drain when the MOSFET is cut off, and decreasing the drive current when active. It was difficult to maintain the improvement. Therefore, a three-dimensional silicon (Si) region (hereinafter referred to as ⁇ fin region '') is provided on the insulating support substrate as a region for the MOSFET, except for the surface of the Fin region that is in contact with the insulating support substrate.
  • MOSFET structures hereinafter referred to as “fin-type FETs” in which the gate electrode is arranged in a band state are being adopted. This is because the current between the source and the drain caused by the substrate can be reduced by isolating the MOSFET region.
  • Patent Document 1 describes a processor configured by a conventional logic circuit using an fm type FET.
  • the processor 1 of FIG. 1 includes at least one chip 2, which has a logic circuit 3 on its surface. These mouth circuit 3 include fm type FET4.
  • the processor 1 is configured by interconnecting logic circuits 3.
  • the logic circuit 3 used for the processor 1 in FIG. 1, the logic circuit 3 is reduced in size. In addition, high integration of the processor 1 in FIG. 1 is realized.
  • Patent Document 1 JP 2004-266274 A
  • the reduction in the layout area of the logic macro cell has a problem that it is greatly influenced not only by the reduction in the size of the MOSFET device but also by the structure and arrangement of the wirings connecting the circuit elements.
  • examples of the structure and arrangement of wirings connecting circuit elements hinder the reduction of the layout area of the logic macrocell include the following.
  • the pattern shape of the wiring connecting the circuit elements be a shape that can be easily resolved in the photolithography process. If the pattern shape of the wiring is difficult to resolve, there is a problem that it is necessary to widen the interval between the wiring patterns in consideration of this point, and the size of the logic macrocell cannot be reduced.
  • the first invention provides a support that is formed in a self-aligned manner with the fm type FET as a wiring for connecting a circuit element such as a fin type FET formed on a support substrate.
  • a semiconductor circuit device characterized by using a buried wiring carried in a groove in a substrate.
  • the first invention provides a MOS transistor element having a silicon three-dimensional isolated region formed on a support substrate and a gate electrode formed on the surface of the three-dimensional isolated region, and a groove in the support substrate.
  • a semiconductor device provided with embedded embedded wiring and on-substrate wiring on the support substrate.
  • the semiconductor device is characterized in that connection between the MOS transistor elements is performed using the embedded wiring and the wiring on the substrate.
  • the above-mentioned carrier wiring is formed in a self-aligned manner with the three-dimensional isolated region of the above-mentioned MOSFET element.
  • the second invention is the semiconductor device described in the first invention, wherein the carrier wiring is aligned in the first direction, and the wiring on the substrate is in the first direction.
  • a semiconductor circuit device is provided that is aligned in a second direction orthogonal to the first direction.
  • the second invention is the semiconductor circuit device according to the first invention, wherein the embedded wiring is arranged in the first direction, and the connection portion of the circuit element connected by the wiring on the substrate is Providing a semiconductor circuit device characterized by being arranged linearly in a second direction
  • the first direction and the second direction are preferably orthogonal to each other.
  • a third invention is a method for manufacturing the semiconductor circuit device according to the first invention or the second invention, and is embedded in a self-aligned manner with an fm type FET.
  • a method for manufacturing a semiconductor circuit device characterized in that a wiring groove is formed and a buried wiring is formed in a self-aligning manner.
  • a third invention is a method of manufacturing the semiconductor circuit device according to the first invention or the second invention, wherein the solid isolated region forming step of forming the solid isolated region of the MOS transistor element and the method A groove forming process for forming a buried wiring groove in a substrate in a self-aligned manner with a three-dimensional isolated region; and a filling process for loading silicon and an etching selective carrier material into the carrier wiring groove.
  • a method for manufacturing a semiconductor circuit device comprising: a buried wiring forming step for forming a wiring; and an on-substrate wiring forming step for forming the on-substrate wiring.
  • Silicon (GeGe) is the preferred material for etching with silicon.
  • the trench for the buried wiring is formed using the Fin type FET as an etching mask. Then, wiring between circuit elements can be performed using two wiring layers of the carrier wiring and the wiring on the board. Therefore, compared to connecting with the same wiring layer, the wirings belonging to the same wiring layer are crossed. Avoid wiring area for connecting circuit elements. In addition, since the positional relationship between the fin-type FET and the embedded wiring is determined in a self-aligning manner, it is not necessary to provide an area for positioning the fin-type FET and the embedded wiring.
  • the interlayer insulating film between the embedded wiring and the wiring on the substrate is thicker than the interlayer insulating film between the first wiring and the second wiring on the substrate, the inter-wiring capacitance is reduced. Then, the carrier wiring and the on-board wiring can be brought close to each other. Therefore, a reduced semiconductor circuit device can be provided.
  • the arrangement interval between the carrier wiring and the Fin-type FET can be set to the minimum interval.
  • the second direction orthogonal to the first direction Since the connection points of the circuit elements connected in the direction by the wiring on the substrate are aligned, the shape of the wiring on the substrate can be made linear. Further, when the wiring on the substrate is arranged in parallel, the wiring on the substrate can be arranged with a minimum interval. Furthermore, when the circuit pattern is formed by photolithography, the pattern is easily resolved if it is a linear pattern. Therefore, it is possible to provide a semiconductor circuit device that is further reduced in size than the semiconductor circuit device described in the first invention.
  • the trench for the buried wiring is formed in a self-aligned manner, and silicon 'genorenium (SiGe) is once loaded. Then, a process step to which heat treatment is applied after that, for example, the gate electrode of the fin-type FET can be formed of the poly-thincon layer. After the completion of the process step to which heat treatment is applied, the embedded wiring is formed by removing the silicon 'germanium (SiGe) from the buried wiring trench and placing the metal material in the buried wiring trench. I can do it. Therefore, after the embedded wiring is formed, no thermal stress is generated in the carrier wiring that is not subjected to heat treatment.
  • SiGe silicon 'genorenium
  • FIG. 1 is a diagram illustrating a processor configured by a conventional logic circuit.
  • FIG. 2 is a diagram showing a circuit layout of logic macrocells of a Not circuit, a Nand circuit, and a Nor circuit using the fin-type FET according to the first embodiment as circuit elements.
  • FIG. 3 is a diagram showing a circuit layout of an SRAM macro cell in which an SRAM memory circuit according to Embodiment 2 having a fin-type FET as a circuit element is arranged.
  • FIG. 4 shows the circuit layout of an SRAM macrocell that is a cell-type SRAM memory circuit according to the third embodiment, characterized by having a fin-type FET as a circuit element and using a shared contact.
  • FIG. 4 shows the circuit layout of an SRAM macrocell that is a cell-type SRAM memory circuit according to the third embodiment, characterized by having a fin-type FET as a circuit element and using a shared contact.
  • FIG. 5 shows a flowchart of the manufacturing process of the logic macro cell or SRAM macro cell.
  • FIG. 6 is a diagram showing the detailed manufacturing process of the fin-type region forming process, which includes FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, and FIG.
  • FIG. 7 is a diagram showing the details of the process for forming a trench for embedded wiring, which is composed of FIG. 7G, FIG. 7H, FIG. 71, FIG. 7], FIG. 7K, and FIG. is there.
  • FIG. 8 is composed of FIG. 8M, FIG. 8N, FIG. 80, FIG. 8P, FIG. 8Q, and FIG. 8R, and shows the details of the groove forming process for the loading wiring.
  • FIG. 9 is composed of FIG. 9R, FIG. 9S, FIG. 9T, FIG. 9U, FIG. 9V, and FIG. 9W.
  • the details of the loading wiring process and the on-board wiring formation process (part 1) FIG.
  • Fig. 10 is composed of Fig. 10R, Fig. 10SS, Fig. 10TT, Fig. 10UU, Fig. 10VV, and Fig. 10 stomach, and the loading wiring process and on-board wiring formation process (part 2) It is a diagram showing details.
  • FIG. 11 is composed of FIG. 11XX, FIG. 11YY, and FIG. 11ZZ, and shows the details of the loading wiring process and the on-board wiring formation process (part 2).
  • Example 1 Example 1, Example 2, Example 3, and Example 4 of the present invention will be described.
  • Example 1 Example 1
  • FIG. 2 shows a Not circuit having a fin type FET according to the first embodiment as a circuit element, a Nand circuit, and The circuit layout of the logic macrocell of the Nor circuit is shown.
  • fin means “fish carp”, and at the beginning, the fm region meant a three-dimensional region created by laying a triangular prism sideways. Today, however, the fm region is used to include an isolated three-dimensional region such as a rectangular parallelepiped.
  • the fm-type FET has a three-dimensional fin region of silicon (Si) for MOSFET that is isolated on an insulating support substrate, and strips the gate electrode except for the surface of the fin region that contacts the insulating support substrate. This is the MOSFET placed in
  • FIG. 2A The upper and lower stages of FIG. 2A are circuit pattern examples of logic macrocells of Not circuits that use embedded wiring and wiring on a substrate for connecting circuit elements.
  • 5 is the wiring on the board that connects to the positive power supply
  • 6 is the P-channel inductor fin type FET
  • 7 is the N-channel fm type FET
  • 8 is the wiring on the board that connects to the input terminal
  • 9 is Wiring on the board connected to the output terminal, 10 on the board connected to the ground power supply, 11 the carrier wiring, and 13 the contact Via.
  • the on-board wirings 5, 8, 9, and 10 do not necessarily have to belong to a single wiring layer.
  • the on-board wiring 10 connected to the ground power supply and the on-board wiring 5 connected to the positive power supply belong to the second wiring layer and are connected to the input terminals.
  • the subsequent on-board wiring 8 and the on-board wiring 9 connected to the output terminal may belong to the first wiring layer.
  • the drain of the P-channel fin-type FET 6 and the on-substrate wiring 5 connected to the positive power supply are connected via a contact vial 3.
  • the substrate 9 connected to the source of the P-channel fm type FET6, the drain of the N-channel fin-type FET7, and the output terminal is connected via the contact vial3.
  • the gate electrode of the P-channel fin-type FET 6 and the gate electrode of the N-channel fin-type FET 7 are connected via the buried wiring 11 and the contact vial 3.
  • the embedded wiring 11 and the on-board wiring 8 connected to the input terminal are connected via a contact vial 3.
  • the source of the N-channel fin-type FET 7 is connected to the substrate wiring 10 connected to the ground power supply via the contact Via23.
  • the P-channel fin-type FET 6 and the N-channel fm-type FET 7 are connected in series between the positive power supply and the ground power supply, forming a not circuit, that is, an inverter circuit.
  • the upper not circuit in Figure 2 outputs the logic signal received at the input terminal and the logic signal having inverted logic from the output terminal.
  • the interlayer insulation layer between the carrier wiring 11 and the board wiring 5, 8, 9, 10 includes circuit elements such as fm type FETs. It is thicker than the insulating layer between the wiring layers that form 8, 9, and 10. Accordingly, the wiring capacity between the embedded wiring 11 and the on-board wirings 5, 8, 9, 10 is smaller than the wiring capacity between the plurality of wiring layers forming the on-board wirings 5, 8, 9, 10.
  • 15 is the wiring on the board connected to the positive power supply
  • 16 is the P-channel fin type FET
  • 17 is the N-channel fm type FET
  • 18 is the wiring on the board connected to the input terminal
  • 19 is On-board wiring connected to the output terminal
  • 20 on-board wiring connected to the ground power supply
  • the on-board wirings 15, 18, 19, and 20 do not necessarily belong to the same wiring layer, but have the power S to belong to a plurality of wiring layers, as in the upper circuit layout of FIG. 2A.
  • connection relationship of each component is the same as that of the upper Not circuit in FIG. 2A.
  • the function of the lower Not circuit in FIG. 2A is the same as the function of the upper Not circuit in FIG. 2A.
  • the gate electrode of P-channel f ln type FET16 and the gate electrode of N-channel fm type FET17 are embedded. Force S connected via wiring 21 and contact via 23 are not connected, and embedded wiring 21 and the gate electrode of each fm type FET are connected directly via wiring connection area 24.
  • the embedded wiring 21, the source contact via23 of the P-channel fin-type FET16, and the drain contact v of the N-channel fin-type FET17 so that the embedded wiring 21 and the on-board wiring 19 intersect at right angles. It is also different in that ia23 is arranged.
  • FET 17 and P-channel fm type FET 16 and embedded wiring 21 are also different in that they are self-aligned. Therefore, it is possible to omit the area for alignment between the carrier wiring and the fm type FET gate electrode and the carrier wiring and the fin type FET fm area. Further, the carrier wiring 21 and the on-substrate wirings 15, 18, 19, and 20 are linear, and the pattern can be easily resolved when the pattern is formed by the photolithography technique. Furthermore, the embedded wiring 21 and the on-board wiring 19 can be arranged so as to overlap each other. Then, the layout area of the lower Not circuit in FIG. 2A is reduced compared to the layout area of the upper Not circuit in FIG. 2A.
  • Fig. 2B are examples of logic macrocell patterns of Nand circuits that use embedded wiring and wiring on the board to connect circuit elements.
  • 25 is the on-board wiring connected to the positive power supply
  • 26 and 33 are P-channel fm type FETs
  • 27 and 34 are N-channel fm type FETs
  • 28 is connected to input terminal 1.
  • Wiring on board, 36 is wiring on board connected to input terminal 2
  • 29 is wiring on board connecting to output terminal
  • 30 is wiring on board connecting to ground power supply
  • 31 and 35 are loading wiring
  • 38 is board
  • the upper wiring 39 indicates a contact Via.
  • the on-board wirings 25, 28, 36, 29, and 30 do not necessarily belong to the same wiring layer, and may belong to a plurality of wiring layers, similar to the upper circuit layout of FIG. 2A.
  • the drain of the P-channel fin-type FET 26 is connected to the on-substrate wiring 25 connected to the positive power supply via the contact Via 39.
  • the source of the P-channel fin-type FET 26 is connected to the drain of the N-channel fin-type FET 27 and the source of the P-channel f ln- type FET 33 via the contact Via 39 and the substrate wiring 29 connected to the output terminal.
  • the gate electrode of the P-channel fm type FET 26 is connected to the gate electrode of the N-channel fm type FET 27 and the on-substrate wiring 28 connected to the input terminal 1 through the carrier wiring 31 and the contact Via 39.
  • the gate electrode of the P-channel fin type FET33 is connected to the gate electrode of the N-channel fm type FET34 through the buried wiring 35 and the contact Via39. Connect to the board wiring 36 connected to the pole and input terminal 2.
  • the drain of the P-channel fin-type FET33 is connected to the substrate wiring 25 connected to the positive power supply via the contact Via39.
  • the drain of the N-channel fin-type FET 34 is connected to the source of the N-channel fin-type FET 27 via the substrate wiring 38 and the contact Via 39.
  • the source of the N-channel fm type FET 34 is connected to the on-board wiring 30 connected to the ground power supply via the contact Via 39.
  • the P-channel fin-type FETs 26 and 33 are connected in parallel between the on-board wiring 25 connected to the positive power supply and the drain of the N-channel fin-type FET 27, and the N-channel fin-type FET 27, 34 is connected in series between the source of the P-channel fm type FETs 26 and 33 and the on-board wiring 30 connected to the ground power source. Therefore, the P channel fm type FETs 26 and 33 and the N channel fin type FETs 27 and 34 constitute a so-called nand circuit.
  • the Nand circuit in the upper part of Fig. 2B sends a logical signal indicating the inversion of the logical product (i.e., nand) from the input terminal 1 and the logical signal input from the input terminal 2 from the output terminal. Output.
  • the gate electrode of the P-channel fm type FET 41 and the gate electrode of the N-channel fm type FET 42 are connected via the embedded wiring 21, they are connected to the embedded wiring 21 without using the contact Via54.
  • the gate electrode of P-channel fin-type FET48 and the gate electrode of N-channel fin-type FET49 are connected via carrier wiring 50, but without via Via54, carrier wire 50 and the gate of each fin-type FET It differs from the electrode in that it is connected directly in the wiring connection region 55.
  • FET42 drain contact Via54 and P channel fm type FET48 source contact Via54 is different in that it is placed.
  • the P-channel fin-type FET 41 and the N-channel fm-type FET 42 are different from the carrier wiring 46 in that they are self-aligned.
  • the P-channel fin-type FET 48 and N-channel fin-type FET 49 are different from the embedded wiring 50 in that they are self-aligned.
  • the carrier wirings 43 and 50 and the on-substrate wirings 40, 43, 44, 45, 53, and 56 are linear, and the pattern can be easily resolved when the pattern is formed by photolithography.
  • the embedded wiring 46 and the on-substrate wiring 44 can be arranged so as to overlap each other. As a result, the layout area of the lower Nand circuit in Figure 2B is reduced compared to the layout area of the upper Nand circuit in Figure 2B.
  • FIG. 2C The upper and lower stages of FIG. 2C are examples of Norma logic macrocell patterns using the carrier wiring and the wiring on the substrate for connecting circuit elements.
  • 57a is on-board wiring connected to the positive power supply
  • 57b and 63 are P-channel fin type FETs
  • 57c and 64 are N-channel fin type FETs
  • 58 is connected to input terminal 1 on the board Wiring
  • 66 on board wiring connected to input terminal 2 59 on board wiring connected to output terminal
  • 60 on board wiring connected to ground power supply 60 on board wiring connected to ground power supply
  • 61 and 65 embedded wiring 67 on board wiring 69 represents a contact Via.
  • the on-board wirings 57a, 58, 66, 59, 60, and 67 do not necessarily belong to the same wiring layer, and may belong to multiple wiring layers, as in the upper circuit layout of FIG. 2A. .
  • the drain of the P-channel fm type FET 57b is connected to the on-substrate wiring 57a connected to the positive power supply via the contact Via69.
  • the gate electrode of the P-channel fm type FET 57b is connected to the gate electrode of the N-channel fin type FET 57C and the substrate wiring 58 connected to the input terminal 2 through the embedded wiring 61 and the contact Via 69.
  • the source of the P-channel fin-type FET 57b is connected to the drain of the P-channel fin-type FET 63 via the substrate wiring 67 and the contact Via69.
  • the source of the P-channel fin type FET 63 is connected to the drain of the N-channel fm type FET 57c and the drain of the N-channel fm type FET 64 via the substrate wiring 59 connected to the output terminal and the contact Via69.
  • the gate electrode of the P-channel fin-type FET 63 is connected to the gate electrode of the N-channel fin-type FET 64 and the input terminal 2 through the buried wiring 65 and the contact Via 69.
  • the source of N-channel fin-type FET 57 and the source of N-channel fin-type FET 64 are connected to the on-board wiring 60 connected to the ground power supply.
  • the N-channel fin-type FET 57 and the N-channel fin-type FET 64 are connected in parallel between the substrate wiring 60 connected to the ground power supply and the source of the P-channel fin-type FET 63.
  • the P-channel fin type FET 56 and the P-channel fm type FET 63 are connected in series between the on-board wiring 55 connected to the positive power supply and the drains of the N-channel fin type FET 57 and the N-channel fin type FET 64. Therefore, the N-channel fm FET 57, the N-channel fin FET 64, the P-channel fm FET 56, and the P-channel fin FET 63 constitute a so-called nor circuit.
  • the upper NOT circuit in Fig. 2C outputs the inverted signal of the logical sum of the logical signals input from the on-board wiring 58 connected to the input terminal 1 and the on-board wiring 66 connected to the input terminal 2 from the output terminal. To do.
  • 70 is the on-board wiring connected to the positive power supply
  • 71 and 78 are P-channel fm type FETs
  • 72 and 79 are N-channel fm type FETs
  • 73 is connected to input terminal 1.
  • Wiring on board 81 is wiring on board connecting to input terminal 2
  • 74 is wiring on board connecting to output terminal
  • 75 is wiring on board connecting to ground power supply
  • 76 and 80 are embedded wiring
  • 77 is board
  • Upper wiring 82 represents a wiring connection region
  • 83 represents a contact Via. Note that the on-board wirings 70, 73, 81, 74, 75, and 77 do not necessarily belong to the same wiring layer, and may belong to a plurality of wiring layers, similar to the circuit layout in the upper stage of FIG. 2A.
  • connection relationship of each component is the same as the Nor circuit in the upper part of Fig. 2C.
  • the function of the lower Nor circuit in Fig. 2C is the same as that of the upper Nor circuit in Fig. 2C.
  • the gate electrode of the P-channel fin-type FET 71 and the gate electrode of the N-channel fm-type FET 72 are connected via the embedded wiring 76, they are connected to the embedded wiring 76 without using the contact Via 83, respectively.
  • the fin type FET gate electrode is directly connected in the wiring connection region 82.
  • the gate electrode of the P-channel fin-type FET78 and the gate electrode of the N-channel fin-type FET79 are connected via the carrier wire 80, but without the contact Via83, the carrier wire 80 and each fm type It is directly connected to the gate electrode of the FET in the wiring connection region 82.
  • the FET 79 and the carrier wiring 80 are self-aligning.
  • the embedded wirings 76 and 80 and the on-substrate wirings 70, 73, 74, 75, 77, and 81 are linear, and the pattern can be easily resolved when the pattern is formed by photolithography. Further, the embedded wiring 80 and the on-substrate wiring 74 can be arranged so as to overlap each other.
  • the interlayer insulating film between the carrier wiring and the wiring on the substrate is thick because it includes each fin type FET. Therefore, the capacity between the carrier wiring and the on-board wiring is smaller than the capacity between the wiring layers to which the on-board wiring belongs. In this case, it is not necessary to avoid the embedded wiring and the board-shaped wiring from being close to each other.
  • the carrier wiring is connected to the fin region of each fin-type FET (the silicon formed on the support substrate). It is not necessary to secure the alignment area between the fin area and the loading wiring because it is formed in a self-aligned manner.
  • the direction in which the carrier wiring is wired is aligned, and the contact via of each fm type FET is arranged so that the wiring on the board is straight. Therefore, in the formation of the wiring pattern on each substrate, the pattern can be easily resolved. Then, the interval between the wiring patterns on the substrate can be reduced.
  • the embedded wiring and the on-board wiring are arranged so that there is a portion where the wiring direction of the embedded wiring and the substrate wiring are orthogonal to each other and the embedded wiring and the on-board wiring intersect. Therefore, the wiring can be arranged in a superimposed manner.
  • the logic macrocell can be reduced.
  • FIG. 3 is a diagram showing a circuit layout of an SRAM macro cell in which the SRAM memory circuit according to the second embodiment having a fin-type FET as a circuit element is used. 3A, 3B, 3C, and 3D.
  • FIG. 3A is a circuit showing a part of the SRAM memory element.
  • 85 and 86 are inverters, 87 is an input terminal, and 88 is an output terminal.
  • One inverter inverts and amplifies the logic signal input from the input terminal 87 and outputs an output signal from the output terminal.
  • the other inverter further inverts and amplifies the logic signal having the inverted logic from the output terminal, and feeds feedback to the input terminal 87 side. That is, a part of the SRAM memory element has a function of storing the logic of the logic signal from the input terminal 87.
  • FIG. 3B is a diagram showing a circuit layout including a fin-type FET that constitutes a part of the SRAM memory element of FIG. 3A, and embedded wiring and on-substrate wiring connecting the fin-type FET.
  • 90 is on-board wiring connected to the positive power supply
  • 91 and 93 are P-channel fin type FETs
  • 92 and 94 are N-channel fin type FETs
  • 95 and 96 are carrying wirings
  • 97 is ground power supply.
  • On-board wiring to be connected 98 is on-board wiring to be connected to the input terminal
  • 99 is on-board wiring to be connected to the output terminal
  • 100 is a contact via.
  • the above-mentioned wirings 90, 97, 98, 99 on the substrate do not necessarily need to be composed of one wiring layer.
  • the board wiring 98 connected to the input terminal and the board wiring 99 connected to the output terminal are the first layer board wiring, the board wiring 90 connected to the positive power supply, and the board connected to the ground power supply.
  • the wiring 97 may have a plurality of wiring layer forces such as a second-layer wiring on the substrate.
  • the gate electrode of the P-channel fin type FET 91 is connected to the gate electrode of the N-channel fm type FET 92 via the buried wiring 95 and the contact vial OO, the carrier wiring 95, the on-board wiring 98 connected to the input terminal, and The contacts are connected to the source of P-channel fin-type FET93 and the drain of N-channel fin-type FET94 via vialOO.
  • the drain of the P-channel fin-type FET 91 is connected to the on-board wiring 90 connected to the positive power supply.
  • the source of the P-channel fin-type FET91 is N-channel via the substrate wiring 99 connected to the output terminal and the contact vialOO.
  • the source of FET94 is connected to the on-board wiring 97 connected to the ground power supply via the contact vialOO.
  • the source of the N-channel fm type FET92 is connected to the on-board wiring 97 that is connected to the ground power supply via the contact vialOO.
  • the P-channel fin type FET 91 and the N-channel fm type FET 92 are connected in series between the positive power source and the ground power source, and form a not circuit, that is, an inverter circuit.
  • the P-channel f ln type FET 93 and the N-channel fin type FET 94 are connected in series between the positive power supply and the ground power supply, and form a not circuit, that is, an inverter circuit. As a result, as explained in FIG. 3A, the entire circuit has the same function as a part of the SRAM memory element.
  • the interlayer insulation layer between the embedded wiring 95, 96 and the wiring 90, 97, 98, 99 on the board is It is thicker than the insulating layer between the plurality of wiring layers constituting the upper wiring 90, 97, 98, 99. Therefore, the wiring capacity between the embedded wiring 95, 96 and the on-board wiring 90, 97, 98, 99 is smaller than the wiring capacity between the plurality of wiring layers forming the on-board wiring 90, 97, 98, 99. .
  • FIG. 3C is a diagram showing a circuit layout including the fm type FET constituting a part of the SRAM memory element of FIG. 3A, and the embedded wiring and the wiring on the substrate for connecting the fm type FET.
  • the points are the same as in Fig. 3B.
  • Some patterns of force-carrying wiring are formed in a self-aligned manner with the fin region of the fin-type FET, and the connection between the gate electrode of the fm-type FET and the loading wiring
  • the circuit layout is different in that the connection is made without using the contact via.
  • 105 is a substrate wiring connected to a positive power source
  • 106 and 107 are P channel fm type FETs
  • 108 and 109 are N channel fin type FETs
  • 110 is a substrate wiring connected to a ground power source
  • 111 Is the on-board wiring connected to the output terminal
  • 112 is the on-board wiring connected to the input terminal
  • 113 is the contact Via
  • 114 is the wiring connection area
  • 115, 116, 117, and 118 are the carrier wiring.
  • the on-board wirings 105, 110, 111, and 112 belong to a plurality of on-board wiring layers. This is the same as the circuit layout in Fig. 3B.
  • the drain of the P-channel fin-type FET 106 is connected to the on-substrate wiring 105 connected to the positive power source via the contact vial 13.
  • the gate electrode of the P-channel fin type FET 106 is connected to one end of the gate electrode of the N-channel fm type FET 108 via the buried wiring 115.
  • the other end of the N-channel fin-type FET 108 is connected to the source of the P-channel fin-type FET 107 and the N-channel fin-type FET 109 via the embedded wiring 117, the on-board wiring 112 connected to the input terminal, and the contact vial 13. It is connected to the drain.
  • the source of the P-channel fm type FET 106 is connected to the drain of the N-channel fm type FET 108 via the substrate wiring 111 connected to the output terminal, and further, the substrate wiring 111 connected to the output terminal, the contact via, and Connected to one end of the gate electrode of P-channel fin-type FET 107 via buried wiring 116.
  • the other end of the gate electrode of the P-channel fin-type FET 107 is connected to the N-channel fm type via the carrier wiring 118.
  • the drain of the P-channel fm type FET 107 is connected to the on-board wiring 105 that is connected to the positive power supply via the contact via.
  • the source of the N-channel fm type FET 108 is connected to the on-board wiring 110 connected to the ground power supply via the contact via.
  • the source of the N-channel fin type FET 109 is connected to the on-board wiring 110 connected to the ground power supply via the contact via.
  • a part of the embedded wiring pattern is formed in a self-aligned manner with the fin region of the fm type FET, so that the interval between the fm type FET and the embedded wiring can be reduced.
  • the fin FET gate electrode and the carrier wiring were connected without a contact via, the positions of the fm FET gate electrode and the contact via and the buried wiring and the contact via in the alignment region.
  • the alignment area can be omitted.
  • the contact vias are aligned so that the embedded wiring and the fin region of the fin-type FET are aligned in one direction and the wiring on the substrate is linear.
  • the resolution increases. As a result, the interval between patterns can be reduced.
  • the layout area can be reduced as compared with the circuit layout of FIG. 3B.
  • FIG. 3D is a diagram showing a circuit layout including an fm type FET that constitutes a part of the SRAM memory element of FIG. 3A, and embedded wiring and wiring on the substrate that connect the fm type FET.
  • the carrier wiring pattern is formed in a self-aligned manner with the fin region of the fin-type FET, and via the contact via when connecting the gate electrode of the fm-type FET and the carrier wire.
  • the circuit layout is different in that they are connected.
  • the difference is that the entire pattern of the carrier wiring is formed in a self-aligned manner with the fin region of the fin-type FET.
  • 120 is the on-board wiring connected to the positive power supply
  • 121 and 122 are P-channel fin-type FETs
  • 123 and 124 are N-channel fin-type FETs
  • 125 is the on-board wiring connected to the ground power supply
  • 126 is the output terminal
  • 127 is a contact via
  • 129 is a wiring connection region
  • 130 and 131 are carrier wirings.
  • the on-board wirings 120, 125, 126, and 127 belong to a plurality of wiring layers on the substrate, which is the same as the circuit layout of FIG. 3B.
  • connection relationship between the embedded wiring and the wiring on the substrate that connects the gate electrode of each fm FET, the source of each fin FET, the drain, input terminal, and output terminal of each fin FET is This is the same as the connection relationship in FIG. 3B.
  • the connection between the gate electrode of each fm type FET 121, 122, 123, 124 and the carrier wiring 130, 131 is made by direct connection in the contact line connection region 129, not through the contact vial 28. It is different.
  • embedded wirings 130 and 131 are formed in a self-aligned manner in the fm region of each fm type FET.
  • the contact Vial 28 is also arranged so that the on-board wiring 126 connected to the output terminal and the on-board wiring 127 connected to the input terminal are linear.
  • the carrier wiring 130 and the on-board wiring 126 connected to the output terminal cross each other, and the carrier wiring 131 and the on-board wiring 127 connected to the input terminal cross each other. Is different.
  • the P channel fin type FET 121 and the N channel fm type FET 123 constitute an inverter
  • the P channel f ln type FET 122 and the N channel fin type FET 124 constitute an inverter as in FIG. 3B.
  • the FETs 123 and 124 constitute a part of the SRAM storage element.
  • the interlayer insulating film between the carrier wiring and the wiring on the substrate becomes thick because each fin type FET is included. Therefore, buried
  • the capacitance between the embedded wiring and the on-board wiring is smaller than the capacitance between the on-board wiring layers to which the on-board wiring belongs. In this case, it is not necessary to avoid the embedded wiring and the board-shaped wiring from being close to each other.
  • the embedded wiring is connected to the fm region of each fin-type FET (the three-dimensional independent region of silicon formed on the support substrate) and self Since it is formed in a consistent manner, it is not necessary to secure an alignment region between the fm region and the embedded wiring.
  • the wiring direction of the carrier wiring is aligned, and the contact via position of each fm type FET is arranged so that the wiring on the board is linear. Therefore, the pattern can be easily resolved in the formation of each pattern. Then, the interval between the wiring patterns on the substrate can be reduced.
  • the embedded wiring and the on-board wiring are arranged so that there is a portion where the wiring direction of the embedded wiring and the substrate wiring are orthogonal to each other and the embedded wiring and the on-board wiring intersect. Therefore, the wiring is arranged in a superimposed manner.
  • the logic macrocell can be reduced.
  • FIG. 4 is a diagram showing an SRAM macro cell circuit layout in which the SRAM memory circuit according to the third embodiment is made into a cell, which has an fm type FET as a circuit element and uses a squired contact. is there. 4A, 4B, 4C, and 4D.
  • FIG. 4A is a circuit showing a part of the SRAM memory element.
  • 130 and 131 are inverters, 132 is an input terminal, and 133 is a wiring on a substrate connected to an output terminal.
  • FIG. 4B is a circuit layout including an fm type FET constituting a part of the SRAM memory element of FIG. 4A, a buried wiring connecting the fin type FET, and a wiring on the substrate. Share the best It is the figure which showed the circuit layout characterized by using a contact.
  • part of the embedded wiring pattern was formed in a self-aligned manner with the fm region of the fm type FET, and when connecting the gate electrode of the fm type FET and the carrier wiring, the contact via was used.
  • the circuit layout is characterized in that it is connected to each other, and the circuit layout is characterized in that a shared contact is used.
  • 135 is a substrate wiring connected to a positive power source
  • 136 and 137 are P-channel fin type FETs
  • 138 and 139 are N channel fin type FETs
  • 140 is a substrate wiring connected to a ground power source
  • 141 Is the on-board wiring connected to the output terminal
  • 142 is the on-board wiring connected to the input terminal
  • 143 is the contact via
  • 144 is the wiring connection area
  • 145, 146, 147, 148 are embedded wiring
  • 149 is the shared contact Respectively.
  • the above-mentioned wirings 135, 140, 141, 142 on the substrate do not necessarily have to be configured with a single wiring layer force.
  • the board wiring 142 connected to the input terminal and the board wiring 141 connected to the output terminal are the first layer board wiring, the board wiring 135 connected to the positive power supply, and the board wiring connected to the ground power supply. 140 may have a plurality of wiring layer forces such as a second layer wiring on the substrate.
  • each fm type FET, each power source, and each terminal are connected by a buried wiring, a wiring on a substrate, and the like as in FIG. 3C.
  • the drain of the N-channel fm FET 138 and the carrier wiring 146 are connected via the on-board wiring 141 that connects to the output terminal, the carrier wiring 146 and the drain of the N-channel fm FET 138 are close to each other. Therefore, the difference is that the shared contact 149 is used to connect to the on-board wiring 141 connected to the output terminal.
  • the shared contact 149 is used to connect to the on-board wiring 142 connected to the input terminal.
  • the shared contact means that when two or more patterns are connected to the same wiring pattern, the same wiring pattern and the contact via position of one pattern and the contact of the same wiring pattern and the other pattern are used. A contact that is made close to and connected to a via position to form a single contact via. That is, the same wiring pattern and one pattern are connected to a part of the shared contact, and the same wiring and the other pattern are connected to the remaining shared contact part. It becomes the form where the screen connects.
  • FIG. 4C is a circuit showing an SRAM memory element.
  • SRAM memory element of Figure 4C In the SRAM memory element of Figure 4C,
  • 152 and 153 are signal lines
  • 154 and 155 are inverters
  • 156 and 157 are transfer gate transistors
  • 158 is an input terminal
  • 159 is an output terminal.
  • the SRAM storage element in FIG. 4C has a configuration in which transfer gate transistors 156 and 157 are added to a circuit showing a part of the SRAM storage element in FIG. 4A.
  • the parts of the inverters 154 and 155 having the same configuration as the circuit showing a part of the SRAM memory element in FIG. Has the same operations and functions as 4A.
  • the transfer gate transistor 156 of the circuit showing the SRAM storage element of FIG. 4C is a signal line indicating whether or not to receive the logic signal stored in the inverters 154 and 155 from the input terminal 158. It has a function to select according to the logic of 152. That is, when a potential of logical value “H” is applied to the gate electrode of the transfer gate transistor 156, the circuit showing the SRAM memory element in FIG. 4C accepts the input signal. In addition, when the potential of the logical value “L” is applied to the gate electrode of the transfer gate transistor 156, the circuit showing the SRAM memory element in FIG. 4C does not accept the input signal.
  • FIG. 4D is a circuit layout including a fin-type FET constituting the SRAM memory element of FIG. 4C and a carrier wiring and a wiring on the substrate for connecting the fm-type FET, and a shared contact is partly included in the circuit layout. It is the figure which showed the circuit layout characterized by using this.
  • 160 is on-board wiring connected to the positive power supply
  • 161 and 162 are P-channel fin type FETs
  • 163, 164, 165 and 166 are N-channel fm type FETs
  • 167 is on-board wiring connected to the ground power supply
  • 168 is the on-board wiring connected to the output terminal
  • 169 is the on-board wiring connected to the input terminal
  • 170 and 171 are the on-board wiring
  • 172 and 173 are the embedded wiring
  • 174 is the contact Via
  • 175 is the shared contact
  • 177 and 178 are the wirings on the board that are connected to the signal lines.
  • the on-board wiring 160, 167, 168, 169, 170, 171 need not be composed of one wiring layer, and may be composed of a plurality of wiring layers.
  • the drain of the P-channel fin-type FET 161 is connected to the on-substrate wiring 160 connected to the positive power source via the contact vial 74.
  • the source of the P-channel fm type FET 161 is connected to the drain of the N-channel fm type FET 164 through the substrate contact 170 at the shared contact 175.
  • the source of the P-channel fin type FET161 is the board wiring 170 through a contact v Ial74, connected to the drain of N-channel fm type FET 165.
  • the source of the P-channel fm type FET 161 is connected to the gate electrode of the P-channel fin type FET 162 and the N-channel via the on-board wiring 170 and the carrier wiring 173 via the shade contact 175, the contact vial 74, and the wiring connection region 176 It is connected to the gate electrode of fin type FET166.
  • the gate electrode of the P-channel fin type FET 161 is connected to the gate electrode of the N-channel fm type FET 165 through the wiring connection region 176 by the embedded wiring 172.
  • the gate electrode of the P-channel fm type FET161 is by Tankomi wiring 172 and the board wiring 171, the wiring connection area 176, is connected to the source of P-channel fin type FET162 through contact v ial74.
  • the gate electrode of the P-channel fin-type FET 161 is connected to the drain and N of the N-channel fin-type FET 166 via the buried wiring 172 and the on-substrate wiring 171 via the contact line connection region 176, the contact vial 74, and the shared contact 175. Connected to the source of channel fm type FET163.
  • the source of the N-channel fin-type FET 164 is connected to the input terminal 168 via a contact vial 74.
  • N channel fin type FET165, 166 source is grounded via contact vial74 Connected to on-board wiring 167 connected to
  • the drain of the P-channel fin-type FET 162 is connected via a contact vial 74 to a substrate wiring 160 that is connected to the positive power supply.
  • the drain of the N-channel fin type FET 163 is connected to the on-board wiring 168 connected to the output terminal via the contact vial 74.
  • the gate electrode of the N-channel fm type FET163 is connected to the on-substrate wiring 178 that is connected to the signal line.
  • the gate electrode of the N-channel fm type FET 164 is connected to the substrate wiring 177 connected to the signal line.
  • the shared contact 175 By using the shared contact 175, it is not necessary to provide a space for arranging two normal contact vials 74, so that the space between the N-channel fm type FET164 and the P-channel fin-type FET161 can be further reduced. Similarly, by using the shared contact 175, the distance between the N-channel fin-type FET 163 and the N-channel fm-type FET 166 can be further reduced. Therefore, the circuit layout of the SRAM memory element can be reduced by using the shared contact 175.
  • FIG. 5 FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, and FIG. 11, as the fourth embodiment, manufacturing the logic macro cell or SRAM macro cell shown in the first, second, and third embodiments A process is shown.
  • Figure 5 shows a flowchart of the manufacturing process of a logic macrocell or SRAM macrocell.
  • 180 is a fin region forming process
  • 181 is an fm region
  • 182 is an insulating support substrate
  • 183 is a groove forming step
  • 184 is a groove for buried wiring
  • 185 is silicon-germanium (SiGe) loaded Process
  • 186 is silicon, germanium (SiGe)
  • 187 is a gate electrode formation process
  • 188 is a polysilicon (P-Si) layer
  • 189 is a loading wiring process
  • 190 is a cavity
  • 191 is a metal (metal)
  • 192 is a substrate
  • Each upper wiring formation process is shown.
  • the flowchart of FIG. 5 shows that the manufacturing process of the logic macro cell or SRAM macro cell is the fm region forming process 180, the groove forming process 183, the silicon germanium (SiGe) embedding process 185, the gate electrode forming process 187, and the embedding process. It shows that it consists of a wiring process 189 and a wiring formation process 192 on the substrate.
  • the fm region forming step 180 is a three-dimensional region made of a semiconductor on the insulating support substrate 182. This is a process for forming the fin region 181.
  • the above semiconductor is preferably silicon (Si).
  • the insulating support substrate 182 preferably has a silicon oxide film at an insulating portion desired by SOI (Silicon on insulator).
  • the groove forming step 183 is a step of forming the groove 184 for the carrier wiring on the insulating support substrate 182.
  • the SiGe loading process 185 is a process in which silicon germanium (SiGe) 186 is embedded in the trench 184 for embedded wiring in the insulating support substrate 182.
  • the gate electrode forming step is a step of forming the gate electrode of the fm type FET by using, for example, polysilicon (P-SD188 or other conductive material.
  • the first procedure is as follows: First, an insulating film is deposited on the gate electrode, and then a contact via is formed on the silicon 'germanium trapped in the trench. Then, contact is made by depositing metal 191. Next, heat treatment is performed to form a buried wiring by utilizing the substitution phenomenon of silicon and metal by the heat treatment.
  • the metal used for metal replacement is preferably aluminum (A1)
  • the second step in the embedded wiring process is as follows: First, silicon germanium (SiGe) 186 is used for loading wiring. Selectively remove from groove 184. Next, groove 1 for buried wiring 84 is a cavity 190, and then metal (metal) 191 is embedded, and tungsten is preferred as the above metal.
  • the on-board wiring forming process 192 leaves the metal (metal) layer used for the replacement of the silicon and the metal as it is, and the metal (metal) layer A wiring pattern is formed on the resist pattern, and wiring is formed by etching.
  • the carrier wiring process 189 is performed by the second procedure
  • the on-substrate wiring forming process 192 first, an insulating layer is formed, a contact via is formed with respect to the embedded wiring, etc.
  • a wiring pattern is formed by a resist pattern, and wiring is formed by etching.
  • the wiring on the substrate is not always formed by only one wiring layer.
  • aluminum (Al), tungsten (W), etc. are desirable for the metal used for wiring on the substrate.
  • FIG. 6 is a diagram showing the detailed manufacturing process of the fin-type region forming process, which includes the force shown in FIGS. 6A, 6B, 6C, 6D, 6E, and 6F. .
  • FIG. 6 is a diagram showing a cross section between A and B in FIG. 2A. In FIG.
  • 195 is a silicon oxide film (Si02) layer
  • 196 is a single crystal layer of silicon
  • 197 is a silicon oxide film (Si02) layer
  • 198 is a polysilicon (P-Si) layer
  • 199 is a resist pattern
  • 200 Denotes an isolated region of polysilicon
  • 201 denotes an interlayer insulating film of a silicon oxide film (Si02)
  • 202 denotes a sidewall of the silicon oxide film
  • 203 denotes an isolated region of the silicon oxide layer.
  • FIG. 6A shows that a silicon oxide film 197 and a polysilicon (P_Si) layer 198 are formed on a S0I substrate including a silicon oxide film layer 195 and a silicon single crystal layer 196 by a chemical vapor deposition (CVD) method.
  • FIG. The SOI substrate was prepared by forming a silicon oxide layer on a silicon substrate and then sticking the silicon substrate on the silicon oxide layer. Therefore, a single crystal layer of silicon has a structure in which a silicon oxide film is sandwiched.
  • the silicon single crystal layer on the circuit element forming side is thinned by polishing or the like compared to the silicon single crystal side on the opposite side. That is, FIG.
  • the thickness of the silicon oxide film layer 195 in the SOI substrate is preferably 70 nm or more, and preferably about lOO nm.
  • the thickness of the silicon single crystal layer 196 is preferably about 30 nm.
  • it is desirable that the silicon oxide film 197 is about 10 nm, and the thickness of the polysilicon (P-Si) layer 198 is about 30 nm.
  • FIG. 6B is a diagram showing a resist pattern 199 formed by applying a resist on the polysilicon (P-Si) layer 198 and using a photolithography technique. Since the width of the resist pattern 199 determines the interval between the fm regions of the fm type FET, it is preferably about 80 nm to 150 nm.
  • FIG. 6C shows an isolated region 200 of polysilicon obtained by anisotropically etching the polysilicon (P_Si) layer 198 using the resist pattern 199 as an etching mask. Similar to the width of the resist pattern 199, the width of the polysilicon isolated region 200 is about 80 nm to 150 nm. The height of the isolated region 200 of polysilicon is preferably about 20 nm to 30 nm. This is because the width of the side wall 202 of the silicon oxide film formed on the side wall of the polysilicon isolated region 200 is set to about 20 nm to 30 nm.
  • FIG. 6D is a view showing a state where an interlayer insulating film 201 of a silicon oxide film (Si02) is deposited on the polysilicon isolated region 200 and the silicon oxide film 197 by the CVD method.
  • silicon The thickness of the interlayer insulating film 201 of the oxide film (Si02) is preferably about 50 nm to about lOO nm so that the width of the side wall 202 of the silicon oxide film is about 20 nm to 30 nm.
  • FIG. 6E is a diagram showing that the side wall 202 of the silicon oxide film is formed by anisotropically etching the interlayer insulating film 201 of the silicon oxide film (Si02).
  • the width of the side wall 202 of the silicon oxide film is determined to be about 20 nm to 30 nm because the width of the fin region of the fin-type FET will be determined later.
  • FIG. 6F shows that the isolated region 200 of polysilicon is removed by isotropic etching, and the silicon oxide film (Si02) layer 197 is anisotropically etched using the side wall 202 of the silicon oxide film as an etching mask. It is the figure which showed the place which formed the isolation region 203 of the silicon oxide layer. Thereafter, the silicon single crystal layer 196 is anisotropically etched using the isolated region 203 of the silicon oxide layer as an etching mask to form a fin region of the fin-type FET.
  • FIG. 7 is a diagram showing the details of the step of forming a trench for embedded wiring, which includes the forces of FIGS. 7G, 7H, 71, 7J, 7K, and 7L. .
  • FIG. 7 is a diagram showing a cross-section between ⁇ and ⁇ in FIG.
  • 195 is a silicon oxide film (Si02) layer
  • 202 is a sidewall of the silicon oxide film
  • 203 is an isolated region of the silicon oxide layer
  • 204 is a three-dimensional isolated region of silicon, that is, fm of the fm type FET
  • the region 205 is a silicon oxide film layer
  • 206 is a sidewall of the silicon oxide film
  • 207 is a resist pattern
  • 208 is a trench for buried wiring
  • 209 is a silicon germanium (SiGe) layer.
  • FIG. 7G shows that after the step of FIG. 6F is completed, the silicon single crystal layer is anisotropically etched using the sidewall 202 of the silicon oxide film and the isolated region 203 of the silicon oxide layer as an etching mask.
  • FIG. 6 is a diagram showing a place where the fm region 204 is obtained.
  • the width of the side wall 202 of the silicon oxide film is about 20 nm to 30 nm, so that the width of the fm region 204 is also about 20 nm to 30 nm.
  • the thickness of the silicon single crystal is about 30 nm, the height of the fm region 204 is about 30 nm.
  • FIG. 7H is a diagram showing a state where the sidewall 202 of the silicon oxide film is removed by isotropic etching after the step of FIG. 7 is completed.
  • FIG. 71 shows that the silicon oxide film 205 was deposited after the process of FIG. 7H was completed.
  • the width of the silicon oxide film 205 is desirably about 40 nm to 60 nm. This is because the width of the side wall 206 of the silicon oxide film to be formed later is about 20 nm to 30 nm.
  • FIG. 7J is a diagram showing a state where the silicon oxide film 205 is anisotropically etched to form the silicon oxide film sidewall 206 after the process of FIG. 71 is completed. Further, after forming the side wall 206 of the silicon oxide film, a resist is applied, and a resist pattern 207 is formed by a photolithography technique. The interval between the resist patterns 207, that is, the opening of the resist pattern 207 is wider than the interval between the fin regions 204, and the end of the resist pattern 207 is located above the fm region 204.
  • FIG. 7K after completing the step of FIG. 7J, anisotropic etching was performed to form a trench 208 for embedded wiring in the silicon oxide film layer 195 of the support substrate, and the resist pattern 207 was removed.
  • FIG. 7L shows silicon germanium in the trench 208 for the carrier wiring after the process of FIG. 7K is completed.
  • FIG. 6 is a view showing a state where a silicon-germanium (SiGe) layer 209 is deposited by a CVD method to embed (SiGe).
  • the thickness of the silicon 'germanium (SiGe) layer is preferably about 75 nm to lOOnm because the purpose is to contain silicon germanium (SiGe) in the trench 208 for the carrier wiring.
  • the silicon nitride film is deposited with an lnm force of about 5 nm. It is desirable to deposit a silicon 'germanium (SiGe) layer 209.
  • the deposition of the silicon nitride film can be omitted if the metal (metal) is not sufficiently heated so that the metal (metal) diffuses after the metal is placed in the groove. Since the silicon nitride film is thin, it is not shown below.
  • silicon 'germanium (SiGe) is used as an embedding material because when silicon' genorenium (SiGe) is isotropically etched, silicon (Si) or silicon constituting the fin region 204 or the gate electrode is used. This is because it has selectivity for polysilicon (P-Si).
  • P-Si polysilicon
  • the fm region 204 or the gate electrode must be covered with the silicon oxide (Si02) film side 206 or the silicon oxide film (Si02) film layer, etc.
  • the side wall of the silicon oxide (Si02) film This is because, due to the nature of the formation process such as 206, it does not necessarily cover all of the silicon (Si) part.
  • FIG. 8 includes FIG. 8M, FIG. 8N, FIG. 80, FIG. 8P, FIG. 8Q, and FIG. 8R, and is a diagram showing details of the groove formation process for the embedded wiring.
  • FIG. 8 is a diagram showing a cross section between A and B in FIG. 2A.
  • 195 is a silicon oxide film (Si02) layer
  • 203 is an isolated region of the silicon oxide layer
  • 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET
  • 206 is a side of the silicon oxide film.
  • Wall 209 is a silicon germanium (SiGe) layer
  • 210 is a polysilicon (P-Si) layer
  • 211 is a silicon oxide film
  • 212 is a resist pattern
  • 213 is a gate electrode of a fin-type FET.
  • FIG. 8M is a diagram showing the silicon germanium (SiGe) layer 209 of FIG. 7L flattened at the upper part of the fm region.
  • the planarization of the silicon 'germanium (SiGe) layer 209 can be achieved, for example, by performing a chemical mechanical polishing (CMP) process, that is, a chemical and mechanical polishing process. .
  • CMP chemical mechanical polishing
  • FIG. 8N is a diagram showing that isotropic etching is performed on the silicon / germanium (SiGe) layer 209 after the process of FIG. 8M is completed.
  • the silicon / germanium (SiGe) layer 209 other than the trench for the buried wiring can be removed.
  • a silicon nitride film is deposited as a diffusion prevention film in the process of FIG. 7L, the silicon 'germanium (SiGe) layer 209 is removed and isotropic etching is performed for the buried wiring.
  • the silicon nitride film other than the trench is removed.
  • FIG. 80 is a view showing a state where the sidewall 206 of the silicon oxide film and the isolated region 203 of the silicon oxide layer are removed after the process of FIG. 8M is completed. By performing isotropic etching on the silicon oxide film, the silicon oxide film can be removed.
  • FIG. 8P is a diagram in which a polysilicon (P-Si) layer 210 and a silicon oxide film 211 are deposited after the process of FIG.
  • a CVD method can be used for the deposition of the polysilicon (P-Si) layer 210 and the silicon oxide film 211 .
  • the polysilicon (P-Si) layer 210 and the buried wiring trench Silicon 'Germanium (SiGe) is in direct contact with no contact via.
  • the thickness of the polysilicon (P-Si) layer 210 is preferably about 30 nm to 50 nm.
  • the silicon oxide film 211 serves as an etching stopper, it is preferably about 10 nm.
  • FIG. 8Q is a diagram showing a state where a resist is applied after the process of FIG. 8P is completed, and a resist pattern 212 is formed by a photolithography technique.
  • FIG. 8R is a diagram showing the fm FET gate electrode 213 formed by etching the silicon oxide film 211 and the polysilicon (P_Si) layer 210 by anisotropic etching using the resist pattern 212 as an etching mask. It is.
  • FIG. 9 includes FIG. 9R, FIG. 9S, FIG. 9T, FIG. 9U, FIG. 9V, and FIG. 9W, and shows details of the embedded wiring process and the on-board wiring formation process (part 1). It is a figure.
  • FIG. 9 is a view showing a cross section between A and B in FIG. 2A.
  • the on-substrate wiring formation step (part 1) is a detailed description of the step described as the first procedure in the description of the flowchart of FIG.
  • 195 is a silicon oxide film (Si02) layer
  • 204 is a three-dimensional isolated region of silicon, that is, fin region of fin type FET
  • 209 is a silicon 'germanium (SiGe) layer
  • 213 is a gate of fin type FET.
  • Reference numeral 214 denotes an interlayer insulating film made of a silicon oxide film
  • 215 denotes a contact via
  • 216 denotes an aluminum (AL) layer
  • 217 denotes substituted aluminum (AL) after the silicon-germanium (SiGe) layer is replaced.
  • FIG. 9R is a diagram similar to FIG. 8R.
  • FIG. 9S is a diagram showing a state where the silicon oxide interlayer insulating film 214 is deposited by the CVD method after the process of FIG. 9R is completed.
  • the thickness of the interlayer insulating film 214 of silicon oxide film is preferably about lOOnm to 200nm. This is because a sufficient thickness is required to include the fin-type FET gate electrode 213 when the silicon oxide interlayer insulating film 214 is planarized.
  • FIG. 9T is a diagram showing a state where the interlayer insulating film 214 of the silicon oxide film has been flattened by polishing using the CMP method after completing the step of FIG. 9S.
  • the thickness of the interlayer insulating film 214 of the silicon oxide film is preferably about 80 nm to lOOnm from the surface of the silicon oxide film (Si02) layer 195.
  • the height force of the fm region 204 of the fm type FET is about 20 nm to 30 nm and the thickness of the gate electrode of the fin type FET is about 20 nm to 30 nm, the entire fin type FET is included. This is necessary.
  • the silicon oxide interlayer insulating film 214 The thickness is greater than the thickness of the interlayer insulation film between the wiring layers on the substrate.
  • FIG. 9U is a diagram showing a contact via 215 formed in the interlayer insulating film 214 of the silicon oxide film after the process of FIG. 9T is completed.
  • the contact via 215 is formed by the following procedure. First, a resist is applied on the upper surface of the interlayer insulating film 214 of the silicon oxide film. Next, an opening pattern for the contact via 215 is formed by photolithography. Next, using the resist pattern as a mask, the silicon oxide film is etched by anisotropic etching to form a through hole up to the silicon germanium (SiGe) layer 209, which is used as a contact via 215.
  • SiGe silicon germanium
  • a contact via 215 represents a contact vai24 that connects the embedded wiring 21 and the input terminal 18 in FIG. 2A. Therefore, since the contact via 215 is hidden behind the gate electrode of the fm type FET, the contact via 215 is represented by a dotted line.
  • FIG. 9V is a diagram showing a state where the aluminum (AL) layer 216 is deposited by the CVD method or the sputtering method after the process of FIG. 9U is completed.
  • the thickness of the aluminum (AL) layer 216 is preferably about lOOnm to 500nm. This is to ensure the wiring resistance of the wiring on the substrate.
  • the aluminum (AL) layer 216 is then replaced with silicon (germanium) (SiGe) 209 embedded in the groove for receiving wiring. It is necessary to remove the insulating layer at the connection point between 216 and silicon-germanium (SiGe) 209. This is because the substitution phenomenon does not occur when the insulating layer is sandwiched. Therefore, in order to deposit the aluminum (AL) layer 216, it is usual to perform pretreatment, for example, isotropic etching to remove the insulating layer.
  • FIG. 9W after finishing the process of FIG. 9W, replaces aluminum (AL) in the aluminum (AL) layer 216 with silicon 'germanium (SiGe) in the trench for the loading wiring.
  • FIG. 5 is a view showing a state where buried wiring is formed by embedding aluminum (AL) in a groove for a buried wiring.
  • SiGe substitution phenomenon with SiGe
  • it can be achieved by applying heat treatment.
  • the heat treatment should be at 450 ° C for about 60 minutes.
  • FIG. 2 is a detailed description of the step described as the second procedure in the description of the flowchart of FIG.
  • FIG. 10 is a diagram composed of FIG. 10R, FIG. 10SS, FIG. 10TT, FIG. 10UU, FIG. 10VV, and FIG. FIG. 10 is a view showing a cross section between A and B in FIG. 2A.
  • 195 is a silicon oxide (Si02) layer
  • 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET
  • 209 is a silicon 'germanium (SiGe) layer
  • 213 is a gate of a fin type FET.
  • Electrode, 218 is a hollow state
  • 219 is a tungsten (W) layer
  • 220 is a resist pattern
  • 221 is a silicon oxide film layer.
  • FIG. 10R is a diagram similar to FIG. 8R and FIG. 9R, and branches between the loading wiring process and the on-board wiring formation process (part 1) and the embedded wiring process and the on-board wiring formation process (part 2). Indicates that it is after the process of FIG. 10R is completed.
  • FIG. 10SS shows a state where the silicon-germanium (SiGe) layer 209 is removed by being etched into the trench for the carrier wiring by performing isotropic etching.
  • FIG. 10TT is a diagram showing a state in which a tungsten (W) layer is deposited by the CVD method, a resist is applied, and a resist pattern 220 covering the buried wiring region is formed by a photolithography technique.
  • the thickness of the tungsten (W) layer 219 is preferably about lOOnm to about 500nm. This is because tungsten (W) is sufficiently loaded in the trench for the embedded wiring.
  • FIG. 10UU is a diagram showing a state in which the resist pattern 220 is removed by performing anisotropic etching on the tungsten (W) layer using the resist pattern 220 as an etching mask.
  • the reason why the process shown in Fig. 10UU is necessary is as follows. First, when there is a tungsten (W) layer in a wide area, it is easy to control the isotropic etching so that tungsten (W) remains in the trench for the buried wiring by performing isotropic etching. Well then ... Therefore, if the process of FIG. 10UU is performed so that tungsten (W) remains only in the periphery of the trench for the carrier wiring, control of the subsequent isotropic etching becomes easy.
  • FIG. 10VV shows that tanning is performed by performing isotropic etching after the process of FIG.
  • FIG. 6 is a view showing a state where tungsten (W) of the dusten (W) layer 219 is left only in the groove for the loading wiring. As a result, a carrier wiring is formed.
  • FIG. 10WW is a diagram showing a silicon oxide film layer 221 deposited by the CVD method after the process of FIG. 10W is completed.
  • the thickness of the silicon oxide layer 221 is preferably from lOOnm to 200nm in consideration of planarization after that. This is because it is necessary to include the fm region 204 of the fm type FET and the gate electrode of the fm type FET. If a heat treatment that is expected to diffuse tungsten (W) is applied after this step, it is desirable to deposit a silicon nitride film as a diffusion preventive film before the silicon oxide film layer 221 is deposited.
  • the thickness of the silicon nitride film for the diffusion prevention film is preferably about 5 to 10 mm.
  • the silicon nitride film for the diffusion barrier film is a thin film and is not shown in Figure 10WW.
  • FIG. 11 is a diagram configured from FIG. 11XX, FIG. 11YY, and FIG. 11ZZ.
  • FIG. 11 is a diagram showing a cross-section between ⁇ and ⁇ in FIG.
  • 195 is a silicon oxide (Si02) layer
  • 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET
  • 209 is a silicon 'germanium (SiGe) layer
  • 213 is a gate of a fin type FET.
  • Electrode, 219 is a tungsten (W) layer
  • 221 is a silicon oxide film layer
  • 222 is a contact via
  • 223 is a tungsten (W) layer.
  • FIG. 11XX is a diagram showing a state where the silicon oxide film layer 221 is flattened by chemical and mechanical polishing by the CMP method after the process of FIG. 10WW is completed.
  • the thickness of the interlayer insulating film 221 of the silicon oxide film is desirably about 80 nm to lOO nm from the surface of the silicon oxide film (Si02) layer 195.
  • the height force of the fm region 204 of the fm type FET is about 20 nm to 30 nm
  • the thickness force S of the gate electrode of the fin type FET and about 20 nm to 30 nm, it is necessary to include the entire fin type FET It is.
  • the thickness of the interlayer insulating film between these wiring layers is about 30 nm to 50 nm
  • the thickness of the interlayer insulating film 214 of the silicon oxide film The thickness is larger than the thickness of the interlayer insulating film between the wiring layers on the substrate.
  • FIG. 11YY is a diagram showing a contact via 222 formed in the interlayer insulating film 221 of the silicon oxide film after the process of FIG. 11XX is completed.
  • Contact via222 is as follows To form. First, a resist is applied on the upper surface of the interlayer insulating film 221 of the silicon oxide film. Next, an opening pattern for the contact via 222 is formed by photolithography. Next, using the resist pattern as a mask, the silicon oxide film is etched by anisotropic etching to form a through hole up to the tungsten (W) layer 209 to be a contact via 222.
  • the contact via 222 is represented by a dotted line because the contact via 222 does not actually appear in the A-B cross section of FIG.
  • a contact via 222 represents a contact vai24 that connects the embedded wiring 21 and the input terminal 18 in FIG. 2A. Therefore, the contact via 222 is hidden behind the gate electrode of the fm type FET, and the contact via 222 is represented by a dotted line.
  • FIG. 11ZZ is a view showing a state where the tungsten (W) layer 223 is deposited by the CVD method or the sputtering method after the process of FIG. 11YY is completed.
  • the thickness of the tungsten (W) layer 223 is preferably about lOOnm to 500nm. This is to ensure the wiring resistance of the wiring on the substrate.
  • the present invention provides a semiconductor integrated circuit device having a Fin-type FET formed on a support substrate as a constituent element, suitable for highly integrated LSIs, and a method for manufacturing the same.

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Abstract

To provide a semiconductor integrated circuit device, which has components of a fin-type FET suited for a high integration LSI and formed on a supporting substrate and which uses wires buried in trenches of the supporting substrate for connecting the components, and a method for manufacturing the semiconductor integrated circuit device. The semiconductor integrated circuit device comprises a MOS transistor element or the fin-type FET having a stereoscopic isolation area of silicon formed on a supporting substrate and a gate electrode formed on the surface of the stereoscopic isolation area of silicon, buried wires buried in trenches formed in self-alignment in the stereoscopic isolation area of silicon of the supporting substrate, and on-substrate wires on the supporting substrate. The MOS transistor elements are connected by the buried wires and the on-subsrate wires.

Description

明 細 書  Specification
半導体回路装置及びその半導体回路装置の製造方法  Semiconductor circuit device and method of manufacturing the semiconductor circuit device
技術分野  Technical field
[0001] 本発明は、高集積 LSIに好適な、支持基板上に形成された fin型 FETを構成素子とし て有する半導体集積回路装置及びその製造方法に関する。特に、構成素子間を接 続するのに、支持基板中の溝に埋め込まれた配線を用いた半導体集積回路装置及 びその製造方法に関する。  TECHNICAL FIELD [0001] The present invention relates to a semiconductor integrated circuit device having a fin-type FET formed on a support substrate as a constituent element, suitable for highly integrated LSIs, and a method for manufacturing the same. In particular, the present invention relates to a semiconductor integrated circuit device using a wiring embedded in a groove in a support substrate and a manufacturing method thereof for connecting constituent elements.
背景技術  Background art
[0002] 今日の高集積 LSIは、膨大な数の論理マクロセルにより構成される。従って、 LSIの 機能向上のため、 LSIの高集積化が要求されている力 それは、そのまま論理マクロ セルへの縮小化の要求となる。ここで、論理マクロセルとは、 NOT回路、 NAND回路 等のロジック回路であって、その回路レイアウトがパターン化された結果、セル化され たものである。従って、論理マクロセルの縮小化は、その構成要素である  [0002] Today's highly integrated LSI is composed of a huge number of logic macrocells. Therefore, the power required to increase the integration density of LSIs for improving the functions of LSIs is directly demanded for downsizing to logic macro cells. Here, the logic macrocell is a logic circuit such as a NOT circuit or a NAND circuit, and is formed into a cell as a result of patterning the circuit layout. Therefore, the reduction of the logic macrocell is a component of it.
MOSFET(Metal  MOSFET (Metal
Oxide Semiconductor Field- Effect-Transistor)デバイスのサイズの縮小化によるとこ ろが大きい。  Oxide Semiconductor Field-Effect-Transistor) Device size is greatly reduced.
ところで、 MOSFETのサイズ縮小には、 MOSFETのカットオフ時におけるソースとドレ イン間の電流の増大、及び、アクティブ時の駆動電流の減少を伴レ、、サイズ縮小化と 次世代において期待される性能向上の維持との両立は困難であった。そのため、 MOSFET用の領域として、絶縁支持基板上に孤立した、シリコン (Si)の立体的な領域 ( 以下、「fin領域」という)を設け、絶縁支持基板と接する Fin領域の面を除いて、ゲート 電極を帯状態に配置する MOSFETの構造 (以下、「fin型 FET」という)が採用されつつ ある。 MOSFET用の領域を孤立させることで、基板に起因するソースとドレイン間の電 流を減少させることができるからである。また、ゲート電極を帯状態に配置することに より、 fm領域の表面におけるソースとドレイン間の電流経路を遮断できるからである。 さらに、立体的な Fin領域の側面も電流経路として利用できるため、 fm型 FETの駆動 電流は増大するからである。 [0003] そこで、ロジック回路のサイズの縮小と、性能向上の維持との両立を図るため、支持 基板上の Fin型 FETを用いたロジック回路により構成された LSIが提案されている。 例えば、特許文献 1には、 fm型 FETを用いた、従来のロジック回路により構成された プロセッサが記載されている。以下、図 1を用いて、 fin型 FETを用いた、従来のロジッ ク回路により構成されたプロセッサについて説明する。図 1のプロセッサ 1は少なくとも 1つのチップ 2を含み、そのチップ 2はその表面にロジック回路 3を有する。これらの口 ジック回路 3は、 fm型 FET4を含む。プロセッサ 1は、ロジック回路 3を相互接続するこ とによって構成されている。 By the way, reducing the size of the MOSFET involves increasing the current between the source and drain when the MOSFET is cut off, and decreasing the drive current when active. It was difficult to maintain the improvement. Therefore, a three-dimensional silicon (Si) region (hereinafter referred to as `` fin region '') is provided on the insulating support substrate as a region for the MOSFET, except for the surface of the Fin region that is in contact with the insulating support substrate. MOSFET structures (hereinafter referred to as “fin-type FETs”) in which the gate electrode is arranged in a band state are being adopted. This is because the current between the source and the drain caused by the substrate can be reduced by isolating the MOSFET region. In addition, the current path between the source and the drain on the surface of the fm region can be cut off by arranging the gate electrode in a band state. Furthermore, since the side of the three-dimensional Fin region can also be used as a current path, the drive current of the fm type FET increases. [0003] Therefore, in order to achieve both reduction in the size of the logic circuit and maintenance of performance improvement, an LSI configured with a logic circuit using a Fin-type FET on a support substrate has been proposed. For example, Patent Document 1 describes a processor configured by a conventional logic circuit using an fm type FET. In the following, we will explain the processor configured with a conventional logic circuit using fin-type FETs, using Fig. 1. The processor 1 of FIG. 1 includes at least one chip 2, which has a logic circuit 3 on its surface. These mouth circuit 3 include fm type FET4. The processor 1 is configured by interconnecting logic circuits 3.
従って、図 1のプロセッサ 1に使用されるロジック回路 3では、 fm型 FETを用いている ため、ロジック回路 3の縮小化が図られている。また、図 1のプロセッサ 1の高集積化 が実現されている。  Therefore, since the fm type FET is used in the logic circuit 3 used for the processor 1 in FIG. 1, the logic circuit 3 is reduced in size. In addition, high integration of the processor 1 in FIG. 1 is realized.
特許文献 1：特開 2004—266274  Patent Document 1: JP 2004-266274 A
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0004] し力、し、論理マクロセルのレイアウト面積の縮小化は、 MOSFETデバイスのサイズの 縮小だけではなぐ回路素子間を接続する配線の構造及び配置にも大きく左右され る問題がある。 However, the reduction in the layout area of the logic macro cell has a problem that it is greatly influenced not only by the reduction in the size of the MOSFET device but also by the structure and arrangement of the wirings connecting the circuit elements.
そこで、本発明は、支持基板中の溝に埋め込まれた配線を利用して、回路素子間 の接続を行うことにより、レイアウト面積の縮小化が図れる、半導体回路装置の提供を 目的とする。また、本発明は、上記の半導体集積回路装置を製造する方法を提供す ることを目的とする。  Therefore, an object of the present invention is to provide a semiconductor circuit device that can reduce the layout area by making connections between circuit elements using wiring embedded in a groove in a support substrate. Another object of the present invention is to provide a method for manufacturing the semiconductor integrated circuit device.
ここで、回路素子間を接続する配線の構造及び配置が論理マクロセルのレイアウト 面積の縮小化を妨げる例としては、以下がある。  Here, examples of the structure and arrangement of wirings connecting circuit elements hinder the reduction of the layout area of the logic macrocell include the following.
まず、 MOSFETデバイス同士を配線する場合、同一配線層に属する配線同士の交 差はできない。また、同一配線層において、最小の配線幅と配線間隔は維持される 必要もある。従って、論理マクロセルにおいて、同一配線層に属する配線同士の交 差を避けて、回路素子を接続するための配線領域の確保が必要となる問題がある。 一方、上記の問題を解決するため、 2層の配線層を利用することも考えられるが、回 路素子と各配線層の配線との接続、又は、第 1層配線と第 2層配線との接続のための 位置合わせ領域を確保する必要があり、必ずしも、論理マクロセルの縮小化とならな い問題がある。 First, when wiring MOSFET devices, wiring belonging to the same wiring layer cannot be crossed. It is also necessary to maintain the minimum wiring width and wiring spacing in the same wiring layer. Therefore, in the logic macrocell, there is a problem that it is necessary to secure a wiring area for connecting circuit elements while avoiding the crossing of wirings belonging to the same wiring layer. On the other hand, in order to solve the above problem, it may be possible to use two wiring layers. It is necessary to secure an alignment area for the connection between the path element and the wiring of each wiring layer, or the connection between the first layer wiring and the second layer wiring, and this does not necessarily reduce the size of the logic macro cell. There's a problem.
さらに、回路素子間を接続する配線のパターン形状が、フォトリソグラフィー工程に おいて、解像しやすい形状であることも必要である。配線のパターン形状が解像しに くい形状である場合には、その点を考慮して、配線パターンの間隔を広げなければ ならず、論理マクロセルの縮小化が図れない問題がある。  Furthermore, it is necessary that the pattern shape of the wiring connecting the circuit elements be a shape that can be easily resolved in the photolithography process. If the pattern shape of the wiring is difficult to resolve, there is a problem that it is necessary to widen the interval between the wiring patterns in consideration of this point, and the size of the logic macrocell cannot be reduced.
また、今日、基板上の配線の層間絶縁膜は薄くなる傾向にあり、第 1層配線と第 2層 配線の配線間容量が低減できない問題がある。そうすると、第 1層配線と第 2層配線 の近接をさけることになるため、論理マクロセルの縮小化が図れない問題がある。 課題を解決する手段  In addition, today, the interlayer insulating film of the wiring on the substrate tends to be thin, and there is a problem that the capacitance between wirings of the first layer wiring and the second layer wiring cannot be reduced. If this is done, the first layer wiring and the second layer wiring will be avoided, so there is a problem that the logic macrocell cannot be reduced. Means to solve the problem
[0005] 上記の課題を解決するため、第 1の発明は、支持基板上に形成された fin型 FET等 の回路素子を接続する配線として、その fm型 FETと自己整合的に形成された支持基 板内の溝に坦め込まれた坦込配線を用いることを特徴とする半導体回路装置を提供 する。 [0005] In order to solve the above-mentioned problem, the first invention provides a support that is formed in a self-aligned manner with the fm type FET as a wiring for connecting a circuit element such as a fin type FET formed on a support substrate. Provided is a semiconductor circuit device characterized by using a buried wiring carried in a groove in a substrate.
すなわち、第 1の発明は、支持基板上に形成されたシリコンの立体孤立領域と前記 立体孤立領域の表面に形成されたゲート電極とを有する MOSトランジスタ素子と、前 記支持基板中の溝に坦め込まれた坦込配線と、前記支持基板上の基板上配線とを 備える半導体装置を提供する。そして.その半導体装置は、前記坦込配線と前記基 板上配線とを用いて前記 MOSトランジスタ素子間の接続が行われることを特徴とする 。なお、上記の坦込配線は、上記の MOSFET素子の立体孤立領域と自己整合的に 形成されてレ、ることが望ましレ、。  That is, the first invention provides a MOS transistor element having a silicon three-dimensional isolated region formed on a support substrate and a gate electrode formed on the surface of the three-dimensional isolated region, and a groove in the support substrate. Provided is a semiconductor device provided with embedded embedded wiring and on-substrate wiring on the support substrate. The semiconductor device is characterized in that connection between the MOS transistor elements is performed using the embedded wiring and the wiring on the substrate. In addition, it is desirable that the above-mentioned carrier wiring is formed in a self-aligned manner with the three-dimensional isolated region of the above-mentioned MOSFET element.
[0006] 上記の課題を解決するため、第 2の発明は、第 1の発明に記載した半導体装置で あって、坦込配線を第 1の方向へそろえ、基板上配線は、第 1の方向に直交する第 2 の方向へそろえることを特徴とする半導体回路装置を提供する。 [0006] In order to solve the above-described problem, the second invention is the semiconductor device described in the first invention, wherein the carrier wiring is aligned in the first direction, and the wiring on the substrate is in the first direction. A semiconductor circuit device is provided that is aligned in a second direction orthogonal to the first direction.
すなわち、第 2の発明は、第 1の発明に記載した半導体回路装置であって、前記埋 込配線を第 1の方向に配置し、前記基板上配線により接続する前記回路素子の接続 箇所を、第 2の方向へ、直線的に配置したことを特徴とした半導体回路装置を提供す る。なお、上記の第 1の方向と第 2の方向は、直交することが望ましい。 That is, the second invention is the semiconductor circuit device according to the first invention, wherein the embedded wiring is arranged in the first direction, and the connection portion of the circuit element connected by the wiring on the substrate is Providing a semiconductor circuit device characterized by being arranged linearly in a second direction The Note that the first direction and the second direction are preferably orthogonal to each other.
[0007] 上記の課題を解決するため、第 3の発明は、第 1の発明又は第 2の発明に記載した 半導体回路装置を製造する方法であって、 fm型 FETと自己整合的に埋込配線用溝 を形成し、 自己整合的に坦込配線を形成することを特徴とする半導体回路装置の製 造方法を提供する。 [0007] In order to solve the above problems, a third invention is a method for manufacturing the semiconductor circuit device according to the first invention or the second invention, and is embedded in a self-aligned manner with an fm type FET. Provided is a method for manufacturing a semiconductor circuit device, characterized in that a wiring groove is formed and a buried wiring is formed in a self-aligning manner.
すなわち、第 3の発明は、第 1の発明又は第 2の発明に記載した半導体回路装置を 製造する方法であって、前記 MOSトランジスタ素子の前記立体孤立領域を形成する 立体孤立領域形成工程と前記立体孤立領域と自己整合的に埋込配線用溝を支持 基板中に形成する溝形成工程と、前記坦込配線用溝にシリコンとエッチング選択性 力ある坦込材料を坦め込む埋込工程と、前記 MOSトランジスタ素子のゲート電極を形 成するゲート電極形成工程と、前記坦込配線用溝内の埋込材料を除去し、前記坦込 配線用溝に金属材料を坦め込み、前記坦込配線を形成する坦込配線形成工程と、 前記基板上配線を形成する基板上配線形成工程とを備える半導体回路装置の製造 方法を提供する。なお、シリコンとエッチング選択性がある埋込材料には、シリコン'ゲ ノレマニウム（SiGe)が望ましレヽ。  That is, a third invention is a method of manufacturing the semiconductor circuit device according to the first invention or the second invention, wherein the solid isolated region forming step of forming the solid isolated region of the MOS transistor element and the method A groove forming process for forming a buried wiring groove in a substrate in a self-aligned manner with a three-dimensional isolated region; and a filling process for loading silicon and an etching selective carrier material into the carrier wiring groove. A gate electrode forming step for forming a gate electrode of the MOS transistor element; and a filling material in the groove for the carrier wiring is removed; a metal material is loaded in the groove for the carrier wiring; Provided is a method for manufacturing a semiconductor circuit device, comprising: a buried wiring forming step for forming a wiring; and an on-substrate wiring forming step for forming the on-substrate wiring. Silicon (GeGe) is the preferred material for etching with silicon.
(発明の効果）  (The invention's effect)
[0008] 第 1の発明では、支持基板上に形成された fin型 FETを形成した後、 Fin型 FETをェ ツチングマスクとして用いて、坦込配線用の溝が形成される。そうすると、坦込配線と 基板上配線の 2層の配線層を利用して回路素子間の配線ができるため、同一配線 層で接続を行うことに比較し、同一配線層に属する配線同士の交差を避けて、回路 素子を接続するための配線領域を確保する必要がない。また、自己整合的に、 fin型 FETと坦込配線の位置関係が決まるため、 fin型 FETと埋込配線との位置合わせのた めの領域をとる必要がない。また、埋込配線と基板上配線間の層間絶縁膜は、基板 上の 1番目の配線と 2番目の配線との層間絶縁膜よりも厚いため、配線間容量の低減 となる。そうすると、坦込配線と基板上配線を近接させることができる。従って、縮小化 した半導体回路装置の提供が図れる。  [0008] In the first invention, after the fin type FET formed on the support substrate is formed, the trench for the buried wiring is formed using the Fin type FET as an etching mask. Then, wiring between circuit elements can be performed using two wiring layers of the carrier wiring and the wiring on the board. Therefore, compared to connecting with the same wiring layer, the wirings belonging to the same wiring layer are crossed. Avoid wiring area for connecting circuit elements. In addition, since the positional relationship between the fin-type FET and the embedded wiring is determined in a self-aligning manner, it is not necessary to provide an area for positioning the fin-type FET and the embedded wiring. In addition, since the interlayer insulating film between the embedded wiring and the wiring on the substrate is thicker than the interlayer insulating film between the first wiring and the second wiring on the substrate, the inter-wiring capacitance is reduced. Then, the carrier wiring and the on-board wiring can be brought close to each other. Therefore, a reduced semiconductor circuit device can be provided.
[0009] また、第 2の発明では、坦込配線を第 1の方向に配置したため、坦込配線及び Fin 型 FETの配置間隔を最小間隔とすることができる。また、第 1の方向と直交する第 2の 方向へ基板上配線により接続する回路素子の接続箇所をそろえたため、基板上配 線の形状を直線的とすることができる。また、基板上配線を平行して配置する場合に 、基板上配線を最小間隔で配置可能となる。さらに、回路パターンをホトリソグラフィ 一により形成する場合に、直線的なパターンであると、パターンが解像されやすい。 従って、第 1の発明に記載した半導体回路装置よりもさらに、縮小化した半導体回路 装置の提供が図れる。 [0009] Further, in the second invention, since the carrier wiring is arranged in the first direction, the arrangement interval between the carrier wiring and the Fin-type FET can be set to the minimum interval. The second direction orthogonal to the first direction Since the connection points of the circuit elements connected in the direction by the wiring on the substrate are aligned, the shape of the wiring on the substrate can be made linear. Further, when the wiring on the substrate is arranged in parallel, the wiring on the substrate can be arranged with a minimum interval. Furthermore, when the circuit pattern is formed by photolithography, the pattern is easily resolved if it is a linear pattern. Therefore, it is possible to provide a semiconductor circuit device that is further reduced in size than the semiconductor circuit device described in the first invention.
[0010] また、第 3の発明では、坦込配線用溝を自己整合的に形成し、一旦、シリコン'ゲノレ マニウム（SiGe)を坦め込む。そうすると、その後に、熱処理が加わるプロセス工程、例 えば、 fin型 FETのゲート電極をポリシンコン層で形成することができる。熱処理が加わ るプロセス工程の終了の後、埋込配線用溝からシリコン 'ゲルマニウム（SiGe)を除去 して、金属材料を坦込配線用溝に坦め込むことにより、埋込配線を形成することがで きる。従って、埋込配線形成後には、熱処理が加わることがなぐ坦込配線に熱ストレ スが発生することはない。  [0010] Further, in the third invention, the trench for the buried wiring is formed in a self-aligned manner, and silicon 'genorenium (SiGe) is once loaded. Then, a process step to which heat treatment is applied after that, for example, the gate electrode of the fin-type FET can be formed of the poly-thincon layer. After the completion of the process step to which heat treatment is applied, the embedded wiring is formed by removing the silicon 'germanium (SiGe) from the buried wiring trench and placing the metal material in the buried wiring trench. I can do it. Therefore, after the embedded wiring is formed, no thermal stress is generated in the carrier wiring that is not subjected to heat treatment.
図面の簡単な説明  Brief Description of Drawings
[0011] [図 1]図 1は従来のロジック回路により構成されたプロセッサを示す図である。  FIG. 1 is a diagram illustrating a processor configured by a conventional logic circuit.
[図 2]図 2は実施例 1に係る fin型 FETを回路要素とした Not回路、 Nand回路、及び、 Nor回路の論理マクロセルの回路レイアウトを示す図である。  FIG. 2 is a diagram showing a circuit layout of logic macrocells of a Not circuit, a Nand circuit, and a Nor circuit using the fin-type FET according to the first embodiment as circuit elements.
[図 3]図 3は、 fin型 FETを回路要素に有する、実施例 2に係る SRAMの記憶回路をセ ノレイ匕した SRAMマクロセルの回路レイアウトを示す図である。  FIG. 3 is a diagram showing a circuit layout of an SRAM macro cell in which an SRAM memory circuit according to Embodiment 2 having a fin-type FET as a circuit element is arranged.
[図 4]図 4は、 fin型 FETを回路要素として有し、シェアードコンタクトを用いたことを特 徴とする、実施例 3に係る SRAMの記憶回路をセル化した SRAMマクロセルの回路レ ィアウトを示す図である。  [Fig. 4] Fig. 4 shows the circuit layout of an SRAM macrocell that is a cell-type SRAM memory circuit according to the third embodiment, characterized by having a fin-type FET as a circuit element and using a shared contact. FIG.
[図 5]図 5は、論理マクロセル又は SRAMマクロセルの製造工程のフローチャートを示 したものである。  [FIG. 5] FIG. 5 shows a flowchart of the manufacturing process of the logic macro cell or SRAM macro cell.
[図 6]図 6は、図 6A、図 6B、図 6C、図 6D、図 6E、及び、図 6Fから構成されており、 fin型領域形成工程の詳細な製造工程を示した図である。  FIG. 6 is a diagram showing the detailed manufacturing process of the fin-type region forming process, which includes FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, and FIG.
[図 7]図 7は、図 7G、図 7H、図 71、図 7】、図 7K、及び、図 7L力ら構成されており、埋 込配線用の溝形成工程の詳細を示した図である。 [図 8]図 8は、図 8M、図 8N、図 80、図 8P、図 8Q、及び、図 8Rから構成されており、 坦込配線用の溝形成工程の詳細を示した図である。 [FIG. 7] FIG. 7 is a diagram showing the details of the process for forming a trench for embedded wiring, which is composed of FIG. 7G, FIG. 7H, FIG. 71, FIG. 7], FIG. 7K, and FIG. is there. [FIG. 8] FIG. 8 is composed of FIG. 8M, FIG. 8N, FIG. 80, FIG. 8P, FIG. 8Q, and FIG. 8R, and shows the details of the groove forming process for the loading wiring.
[図 9]図 9は、図 9R、図 9S、図 9T、図 9U、図 9V、及び、図 9Wから構成されており、 坦込配線工程及び基板上配線形成工程 (その 1)の詳細を示した図である。  [FIG. 9] FIG. 9 is composed of FIG. 9R, FIG. 9S, FIG. 9T, FIG. 9U, FIG. 9V, and FIG. 9W. The details of the loading wiring process and the on-board wiring formation process (part 1) FIG.
[図 10]図 10は、図 10R、図 10SS、図 10TT、図 10UU、図 10VV、及び、図 10胃から構 成されており、坦込配線工程及び基板上配線形成工程 (その 2)の詳細を示した図で ある。  [Fig. 10] Fig. 10 is composed of Fig. 10R, Fig. 10SS, Fig. 10TT, Fig. 10UU, Fig. 10VV, and Fig. 10 stomach, and the loading wiring process and on-board wiring formation process (part 2) It is a diagram showing details.
[図 11]図 11は、図 11XX、図 11YY、及び、図 11ZZから構成されており、坦込配線工程 及び基板上配線形成工程 (その 2)の詳細を示した図である。  [FIG. 11] FIG. 11 is composed of FIG. 11XX, FIG. 11YY, and FIG. 11ZZ, and shows the details of the loading wiring process and the on-board wiring formation process (part 2).
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0012] 以下、本発明の実施例 1、実施例 2、実施例 3、及び、実施例 4について説明する 実施例 1  [0012] Hereinafter, Example 1, Example 2, Example 3, and Example 4 of the present invention will be described. Example 1
[0013] (Not回路、 Nand回路、及び、 Nor回路において、 fm型 FETを用いた論理マクロセノレ） 図 2に、実施例 1に係る fin型 FETを回路要素とした Not回路、 Nand回路、及び、 Nor 回路の論理マクロセルの回路レイアウトを示す。なお、 finは「魚の鰭」を意味し、当初 は、 fm領域は三角柱を横に倒してできる立体的な領域を意味していた。しかし、今日 では、 fm領域は直方体等の孤立した立体的な領域を含む意味で使用されている。ま た、 fm型 FETとは、絶縁支持基板上に孤立した、 MOSFET用のシリコン (Si)の立体的 な fin領域を設け、絶縁支持基板と接する fin領域の面を除いて、ゲート電極を帯状に 配置する MOSFETをいう。  (Logic macro sensing using fm type FET in Not circuit, Nand circuit, and Nor circuit) FIG. 2 shows a Not circuit having a fin type FET according to the first embodiment as a circuit element, a Nand circuit, and The circuit layout of the logic macrocell of the Nor circuit is shown. Note that fin means “fish carp”, and at the beginning, the fm region meant a three-dimensional region created by laying a triangular prism sideways. Today, however, the fm region is used to include an isolated three-dimensional region such as a rectangular parallelepiped. In addition, the fm-type FET has a three-dimensional fin region of silicon (Si) for MOSFET that is isolated on an insulating support substrate, and strips the gate electrode except for the surface of the fin region that contacts the insulating support substrate. This is the MOSFET placed in
[0014] 図 2Aの上段及び下段は、埋込配線と基板上の配線を回路要素の接続に使用した Not回路の論理マクロセルの回路パターン例である。  [0014] The upper and lower stages of FIG. 2A are circuit pattern examples of logic macrocells of Not circuits that use embedded wiring and wiring on a substrate for connecting circuit elements.
図 2Aの上段の Not回路において、 5は正電源に接続する基板上配線、 6は Pチヤネ ノレ fin型 FET、 7は Nチャネル fm型 FET、 8は入力端子に接続する基板上配線、 9は出 力端子に接続する基板上配線、 10は接地電源に接続する基板上配線、 11は坦込配 線、 13はコンタクト Viaをそれぞれ示す。なお、基板上配線 5、 8、 9、 10は、かならずし も、単一の配線層に属する配線でなくでもよい。例えば、接地電源に接続する基板 上配線 10及び正電源に接続する基板上配線 5は、第 2配線層に属し、入力端子に接 続する基板上配線 8及び出力端子に接続する基板上配線 9は、第 1配線層に属する ことであってもよレ、。 In the upper Not circuit in Fig. 2A, 5 is the wiring on the board that connects to the positive power supply, 6 is the P-channel inductor fin type FET, 7 is the N-channel fm type FET, 8 is the wiring on the board that connects to the input terminal, and 9 is Wiring on the board connected to the output terminal, 10 on the board connected to the ground power supply, 11 the carrier wiring, and 13 the contact Via. The on-board wirings 5, 8, 9, and 10 do not necessarily have to belong to a single wiring layer. For example, the on-board wiring 10 connected to the ground power supply and the on-board wiring 5 connected to the positive power supply belong to the second wiring layer and are connected to the input terminals. The subsequent on-board wiring 8 and the on-board wiring 9 connected to the output terminal may belong to the first wiring layer.
そして、 Pチャネル fin型 FET6のドレインと正電源に接続する基板上配線 5とがコン タクト vial3を介して接続されている。 Pチャネル fm型 FET6のソース、 Nチャネル fin型 FET7のドレイン、及び、出力端子に接続する基板上配線 9がコンタクト vial3を介して 接続されている。 Pチャネル fin型 FET6のゲート電極と Nチャネル fin型 FET7のゲート 電極とは、埋込配線 11とコンタクト vial3とを介して接続されている。埋込配線 11と入 力端子に接続する基板上配線 8とは、コンタクト vial3を介して接続されている。 Nチヤ ネル fin型 FET7のソースは、接地電源に接続する基板上配線 10と、コンタクト Via23を 介して、接続されている。  The drain of the P-channel fin-type FET 6 and the on-substrate wiring 5 connected to the positive power supply are connected via a contact vial 3. The substrate 9 connected to the source of the P-channel fm type FET6, the drain of the N-channel fin-type FET7, and the output terminal is connected via the contact vial3. The gate electrode of the P-channel fin-type FET 6 and the gate electrode of the N-channel fin-type FET 7 are connected via the buried wiring 11 and the contact vial 3. The embedded wiring 11 and the on-board wiring 8 connected to the input terminal are connected via a contact vial 3. The source of the N-channel fin-type FET 7 is connected to the substrate wiring 10 connected to the ground power supply via the contact Via23.
従って、 Pチャネル fin型 FET6と Nチャネル fm型 FET7とは、正電源と接地電源の間 に直列に接続されており、 not回路、すなわち、インバーター回路を形成している。図 2の上段の not回路は、入力端子で受けた論理信号と反転論理を有する論理信号を 出力端子より出力する。  Therefore, the P-channel fin-type FET 6 and the N-channel fm-type FET 7 are connected in series between the positive power supply and the ground power supply, forming a not circuit, that is, an inverter circuit. The upper not circuit in Figure 2 outputs the logic signal received at the input terminal and the logic signal having inverted logic from the output terminal.
図 2Aの上段の回路レイアウトでは、坦込配線 11と基板上配線 5、 8、 9、 10との層間 絶縁層は、 fm型 FET等の回路素子を含むこととなるため、基板上配線 5、 8、 9、 10を 形成する複数の配線層間の絶縁層よりも厚い。従って、埋込配線 11と基板上配線 5、 8、 9、 10間の配線容量は、基板上配線 5、 8、 9、 10を形成する複数の配線層間の配 線容量より、小さい。  In the upper circuit layout of Fig. 2A, the interlayer insulation layer between the carrier wiring 11 and the board wiring 5, 8, 9, 10 includes circuit elements such as fm type FETs. It is thicker than the insulating layer between the wiring layers that form 8, 9, and 10. Accordingly, the wiring capacity between the embedded wiring 11 and the on-board wirings 5, 8, 9, 10 is smaller than the wiring capacity between the plurality of wiring layers forming the on-board wirings 5, 8, 9, 10.
図 2Aの下段の Not回路レイアウトにおいて、 15は正電源に接続する基板上配線、 16 は Pチャネル fin型 FET、 17は Nチャネル fm型 FET、 18は入力端子に接続する基板上 配線、 19は出力端子に接続する基板上配線、 20は接地電源に接続する基板上配線 、 21は埋込配線、 23はコンタクト Via、 24は配線接続領域をそれぞれ示す。なお、基 板上配線 15、 18、 19、 20は同一配線層に属するとはかぎらず、複数の配線層に属す ること力 Sあるのは、図 2Aの上段の回路レイアウトと同様である。 In the Not circuit layout at the bottom of Figure 2A, 15 is the wiring on the board connected to the positive power supply, 16 is the P-channel fin type FET, 17 is the N-channel fm type FET, 18 is the wiring on the board connected to the input terminal, 19 is On-board wiring connected to the output terminal, 20 on-board wiring connected to the ground power supply, 21 embedded wiring, 23 contact Via, and 24 wiring connection area. The on-board wirings 15, 18, 19, and 20 do not necessarily belong to the same wiring layer, but have the power S to belong to a plurality of wiring layers, as in the upper circuit layout of FIG. 2A.
そして、各構成要素の接続関係は、図 2Aの上段の Not回路と同様である。また、図 2 Aの下段の Not回路の機能も、図 2Aの上段の Not回路の機能と同様である。ただし、 Pチャネル fln型 FET16のゲート電極と Nチャネル fm型 FET17のゲート電極とは、埋込 配線 21を介して接続されている力 S、コンタクト via23を介さず、埋込配線 21とそれぞれ の fm型 FETのゲート電極とは直接的に配線接続領域 24を介して接続している点で異 なる。また、埋込配線 21と基板上配線 19とが直交状態で交差するように、埋込配線 21 、 Pチャネル fin型 FET16のソースのコンタクト via23、及び、 Nチャネル fin型 FET17のド レインのコンタクト via23が配置されている点でも異なる。さらに、 Nチャネル fin型 The connection relationship of each component is the same as that of the upper Not circuit in FIG. 2A. The function of the lower Not circuit in FIG. 2A is the same as the function of the upper Not circuit in FIG. 2A. However, the gate electrode of P-channel f ln type FET16 and the gate electrode of N-channel fm type FET17 are embedded. Force S connected via wiring 21 and contact via 23 are not connected, and embedded wiring 21 and the gate electrode of each fm type FET are connected directly via wiring connection area 24. Become. Also, the embedded wiring 21, the source contact via23 of the P-channel fin-type FET16, and the drain contact v of the N-channel fin-type FET17 so that the embedded wiring 21 and the on-board wiring 19 intersect at right angles. It is also different in that ia23 is arranged. Furthermore, N channel fin type
FET17及び Pチャネル fm型 FET16と、埋込配線 21は自己整合的である点でも異なる 。従って、坦込配線と fm型 FETのゲート電極、及び、坦込配線と fin型 FETの fm領域と の位置合わせのための領域を省くことができる。また、坦込配線 21及び基板上配線 15、 18、 19、 20が直線的となり、ホトリソグラフィー技術によりパターンを形成する際に パターンの解像が容易となる。さらに、埋込配線 21と基板上配線 19が重なるように配 置が可能となる。そうすると、図 2Aの上段の Not回路のレイアウト面積に比較し、図 2 Aの下段の Not回路のレイアウト面積は縮小化される。 FET 17 and P-channel fm type FET 16 and embedded wiring 21 are also different in that they are self-aligned. Therefore, it is possible to omit the area for alignment between the carrier wiring and the fm type FET gate electrode and the carrier wiring and the fin type FET fm area. Further, the carrier wiring 21 and the on-substrate wirings 15, 18, 19, and 20 are linear, and the pattern can be easily resolved when the pattern is formed by the photolithography technique. Furthermore, the embedded wiring 21 and the on-board wiring 19 can be arranged so as to overlap each other. Then, the layout area of the lower Not circuit in FIG. 2A is reduced compared to the layout area of the upper Not circuit in FIG. 2A.
図 2Bの上段及び下段は、坦込配線と基板上の配線を回路要素の接続に使用した Nand回路の論理マクロセルのパターン例である。  The upper and lower parts of Fig. 2B are examples of logic macrocell patterns of Nand circuits that use embedded wiring and wiring on the board to connect circuit elements.
図 2Bの上段の Nand回路のレイアウトにおいて、 25は正電源に接続する基板上配線 、 26、 33は Pチャネル fm型 FET、 27、 34は Nチャネル fm型 FET、 28は入力端子 1に接 続する基板上配線、 36は入力端子 2に接続する基板上配線、 29は出力端子に接続 する基板上配線、 30は接地電源に接続する基板上配線、 31、 35は坦込配線、 38は 基板上配線、 39はコンタクト Viaをそれぞれ示す。なお、基板上配線 25、 28、 36、 29、 30が同一配線層に属するとは限らず、複数の配線層に属することがある点は図 2Aの 上段の回路レイアウトと同様である。 In the layout of the upper Nand circuit in Figure 2B, 25 is the on-board wiring connected to the positive power supply, 26 and 33 are P-channel fm type FETs, 27 and 34 are N-channel fm type FETs, and 28 is connected to input terminal 1. Wiring on board, 36 is wiring on board connected to input terminal 2, 29 is wiring on board connecting to output terminal, 30 is wiring on board connecting to ground power supply, 31 and 35 are loading wiring, 38 is board The upper wiring 39 indicates a contact Via. Note that the on-board wirings 25, 28, 36, 29, and 30 do not necessarily belong to the same wiring layer, and may belong to a plurality of wiring layers, similar to the upper circuit layout of FIG. 2A.
そして、 Pチャネル fin型 FET26のドレインは、コンタクト Via39を介して、正電源に接 続する基板上配線 25と接続する。 Pチャネル fin型 FET26のソースは、コンタクト Via39 と出力端子に接続する基板上配線 29とを介して、 Nチャネル fin型 FET27のドレイン、 Pチャネル fln型 FET33のソースとに接続する。 Pチャネル fm型 FET26のゲート電極は 、坦込配線 31とコンタクト Via39を介して、 Nチャネル fm型 FET27のゲート電極、及び、 入力端子 1に接続する基板上配線 28とに接続する。 Pチャネル fin型 FET33のゲート 電極は、埋込配線 35及びコンタクト Via39を通じて、 Nチャネル fm型 FET34のゲート電 極及び入力端子 2に接続する基板上配線 36と接続する。 Pチャネル fin型 FET33のド レインは正電源に接続する基板上配線 25とコンタクト Via39を介して接続する。 Nチヤ ネル fin型 FET34のドレインは基板上配線 38とコンタクト Via39を介して、 Nチャネル fin 型 FET27のソースと接続する。 Nチャネル fm型 FET34のソースはコンタクト Via39を介 して接地電源に接続する基板上配線 30と接続する。 The drain of the P-channel fin-type FET 26 is connected to the on-substrate wiring 25 connected to the positive power supply via the contact Via 39. The source of the P-channel fin-type FET 26 is connected to the drain of the N-channel fin-type FET 27 and the source of the P-channel f ln- type FET 33 via the contact Via 39 and the substrate wiring 29 connected to the output terminal. The gate electrode of the P-channel fm type FET 26 is connected to the gate electrode of the N-channel fm type FET 27 and the on-substrate wiring 28 connected to the input terminal 1 through the carrier wiring 31 and the contact Via 39. The gate electrode of the P-channel fin type FET33 is connected to the gate electrode of the N-channel fm type FET34 through the buried wiring 35 and the contact Via39. Connect to the board wiring 36 connected to the pole and input terminal 2. The drain of the P-channel fin-type FET33 is connected to the substrate wiring 25 connected to the positive power supply via the contact Via39. The drain of the N-channel fin-type FET 34 is connected to the source of the N-channel fin-type FET 27 via the substrate wiring 38 and the contact Via 39. The source of the N-channel fm type FET 34 is connected to the on-board wiring 30 connected to the ground power supply via the contact Via 39.
[0017] すなわち、 Pチャネル fin型 FET26、 33は、正電源に接続する基板上配線 25と Nチヤ ネル型 fin型 FET27のドレインとの間に並列に接続しており、 Nチャネル fin型 FET27、 34は、 Pチャネル fm型 FET26、 33のソースと接地電源に接続する基板上配線 30間に 直列に接続されている。従って、 Pチャネル fm型 FET26、 33と、 Nチャネル fin型 FET27 、 34は、いわゆる、 nand回路を構成する。また、図 2Bの上段の Nand回路は、入力端 子 1と、入力端子 2から入力された論理信号に対して、論理積の反転 (いわるゆ、 nand)を示す論理信号を、出力端子より出力する。  That is, the P-channel fin-type FETs 26 and 33 are connected in parallel between the on-board wiring 25 connected to the positive power supply and the drain of the N-channel fin-type FET 27, and the N-channel fin-type FET 27, 34 is connected in series between the source of the P-channel fm type FETs 26 and 33 and the on-board wiring 30 connected to the ground power source. Therefore, the P channel fm type FETs 26 and 33 and the N channel fin type FETs 27 and 34 constitute a so-called nand circuit. In addition, the Nand circuit in the upper part of Fig. 2B sends a logical signal indicating the inversion of the logical product (i.e., nand) from the input terminal 1 and the logical signal input from the input terminal 2 from the output terminal. Output.
[0018] 図 2Bの下段の Nand回路において、 40は正電源に接続する基板上配線、 41、 48は Pチャネル fin型 FET、 42、 49は Nチャネル fm型 FET、 43は入力端子 1に接続する基板 上配線、 56は入力端子 2に接続する基板上配線、 44は出力端子に接続する基板上 配線、 45は接地電源に接続する基板上配線、 46、 50は埋込配線、 53は基板上配線 、 54はコンタクト Via、 55は配線接続領域をそれぞれ示す。そして、各構成要素の接 続関係は、図 2Bの上段の Nand回路と同様である。また、図 2Bの下段の Nand回路の 機能も、図 2Bの上段の Nand回路の機能と同様である。  [0018] In the Nand circuit at the bottom of Figure 2B, 40 is on-board wiring connected to the positive power supply, 41 and 48 are P-channel fin FETs, 42 and 49 are N-channel fm FETs, and 43 is connected to input terminal 1. Wiring on the board to be connected, 56 is wiring on the board to be connected to the input terminal 2, 44 is wiring on the board to be connected to the output terminal, 45 is wiring on the board to be connected to the ground power supply, 46 and 50 are embedded wiring, 53 is the board Upper wiring 54 is a contact via, and 55 is a wiring connection region. The connection relationship of each component is the same as that of the upper Nand circuit in Fig. 2B. The function of the lower Nand circuit in Fig. 2B is the same as that of the upper Nand circuit in Fig. 2B.
[0019] ただし、 Pチャネル fm型 FET41のゲート電極と Nチャネル fm型 FET42のゲート電極と は、埋込配線 21を介して接続されているが、コンタクト Via54を介さず、埋込配線 21と それぞれの fin型 FETのゲート電極とは直接的に配線接続領域 55において接続して レ、る点で異なる。 Pチャネル fin型 FET48のゲート電極と Nチャネル fin型 FET49のゲー ト電極は、坦込配線 50を介して接続されていが、コンタクト Via54を介さず、坦込配線 50とそれぞれの fin型 FETのゲート電極とは直接的に配線接続領域 55において接続 している点で異なる。坦込配線 46と基板上層配線 47とが直交状態で交差するように、 坦込配線 46、 Pチャネル fin型 FET41のソースのコンタクト Via54、 Nチャネル fm型  [0019] However, although the gate electrode of the P-channel fm type FET 41 and the gate electrode of the N-channel fm type FET 42 are connected via the embedded wiring 21, they are connected to the embedded wiring 21 without using the contact Via54. This differs from the fin type FET gate electrode in that it is directly connected in the wiring connection region 55. The gate electrode of P-channel fin-type FET48 and the gate electrode of N-channel fin-type FET49 are connected via carrier wiring 50, but without via Via54, carrier wire 50 and the gate of each fin-type FET It differs from the electrode in that it is connected directly in the wiring connection region 55. Carrier wiring 46, P channel fin type FET41 source contact Via54, N channel fm type so that the carrier wiring 46 and the upper layer wiring 47 intersect at right angles
FET42のドレインのコンタクト Via54、及び、 Pチヤネノレ fm型 FET48のソースのコンタクト Via54は配置されてレ、る点で異なる。 FET42 drain contact Via54 and P channel fm type FET48 source contact Via54 is different in that it is placed.
さらに、 Pチャネル fin型 FET41及び Nチャネル fm型 FET42と、坦込配線 46は自己整合 的である点で異なる。また、 Pチャネル fin型 FET48及び Nチャネル fin型 FET49と、坦 込配線 50は自己整合的である点で異なる。  Furthermore, the P-channel fin-type FET 41 and the N-channel fm-type FET 42 are different from the carrier wiring 46 in that they are self-aligned. Also, the P-channel fin-type FET 48 and N-channel fin-type FET 49 are different from the embedded wiring 50 in that they are self-aligned.
[0020] 従って、坦込配線と fm型 FETのゲート電極、及び、坦込配線と fin型 FETの fm領域と の位置合わせのための領域を省くことができる。また、坦込配線 43、 50及び基板上配 線 40、 43、 44、 45、 53、 56が直線的となり、ホトリソグラフィー技術によりパターンを形 成する際にパターンの解像が容易となる。さらに、埋込配線 46と基板上配線 44が重 なるように配置が可能となる。そうすると、図 2Bの上段の Nand回路のレイアウト面積に 比較し、図 2Bの下段の Nand回路のレイアウト面積は縮小化されている。  [0020] Accordingly, it is possible to omit the area for alignment between the carrier wiring and the fm FET gate electrode, and between the carrier wiring and the fm area of the fin FET. In addition, the carrier wirings 43 and 50 and the on-substrate wirings 40, 43, 44, 45, 53, and 56 are linear, and the pattern can be easily resolved when the pattern is formed by photolithography. Further, the embedded wiring 46 and the on-substrate wiring 44 can be arranged so as to overlap each other. As a result, the layout area of the lower Nand circuit in Figure 2B is reduced compared to the layout area of the upper Nand circuit in Figure 2B.
[0021] 図 2Cの上段及び下段は、坦込配線と基板上の配線を回路要素の接続に使用した Nor回路の論理マクロセルのパターン例である。  [0021] The upper and lower stages of FIG. 2C are examples of Norma logic macrocell patterns using the carrier wiring and the wiring on the substrate for connecting circuit elements.
図 2Cの上段の Nor回路において、 57aは正電源に接続する基板上配線、 57b, 63 は Pチャネル fin型 FET、 57c、 64は Nチャネル fin型 FET、 58は入力端子 1に接続する 基板上配線、 66は入力端子 2に接続する基板上配線、 59は出力端子に接続する基 板上配線、 60は接地電源に接続する基板上配線、 61、 65は埋込配線、 67は基板上 配線、 69はコンタクト Viaをそれぞれ示す。なお、基板上配線 57a、 58、 66、 59、 60、 67 が同一配線層に属するとは限らず、複数の配線層に属することがある点は図 2Aの上 段の回路レイアウトと同様である。  In the upper Nor circuit of Fig. 2C, 57a is on-board wiring connected to the positive power supply, 57b and 63 are P-channel fin type FETs, 57c and 64 are N-channel fin type FETs, 58 is connected to input terminal 1 on the board Wiring, 66 on board wiring connected to input terminal 2, 59 on board wiring connected to output terminal, 60 on board wiring connected to ground power supply, 61 and 65 embedded wiring, 67 on board wiring 69 represents a contact Via. Note that the on-board wirings 57a, 58, 66, 59, 60, and 67 do not necessarily belong to the same wiring layer, and may belong to multiple wiring layers, as in the upper circuit layout of FIG. 2A. .
[0022] Pチャネル fm型 FET57bのドレインはコンタクト Via69を介して正電源に接続する基板 上配線 57aと接続されている。 Pチャネル fm型 FET57bのゲート電極は、埋込配線 61と コンタクト Via69を介して、 Nチャネル fin型 FET57Cのゲート電極及び入力端子 2に接 続する基板上配線 58と接続している。 Pチャネル fin型 FET57bのソースは、基板上配 線 67及びコンタクト Via69を介して、 Pチャネル fin型 FET63のドレインと接続されている 。 Pチャネル fin型 FET63のソースは、出力端子に接続する基板上配線 59及びコンタク ト Via69を介して Nチャネル fm型 FET57cのドレイン、及び、 Nチャネル fm型 FET64のド レインと接続している。 Pチャネル fin型 FET63のゲート電極は、埋込配線 65とコンタク ト Via69を介して、 Nチャネル fin型 FET64のゲート電極及び入力端子 2に接続する基 板上配線 66と接続してレ、る。 Nチャネル fin型 FET57のソース及び Nチャネル fin型 FET64のソースは接地電源に接続する基板上配線 60と接続している。すなわち、 N チャネル fin型 FET57及び Nチャネル fin型 FET64は、接地電源に接続する基板上配 線 60と Pチャネル fin型 FET63のソースの間に並列に接続している。また、 Pチャネル fin型 FET56及び Pチャネル fm型 FET63は、正電源に接続する基板上配線 55と Nチヤ ネル fin型 FET57及び Nチャネル fin型 FET64のドレインとの間に直列に接続している。 従って、 Nチャネル fm型 FET57、 Nチャネル fin型 FET64、 Pチャネル fm型 FET56、及 び、 Pチャネル fin型 FET63はいわゆる nor回路を構成している。そして、図 2Cの上段 の NOT回路は入力端子 1に接続する基板上配線 58と入力端子 2に接続する基板上配 線 66から入力された論理信号の論理和の反転信号を、出力端子より出力する。 [0022] The drain of the P-channel fm type FET 57b is connected to the on-substrate wiring 57a connected to the positive power supply via the contact Via69. The gate electrode of the P-channel fm type FET 57b is connected to the gate electrode of the N-channel fin type FET 57C and the substrate wiring 58 connected to the input terminal 2 through the embedded wiring 61 and the contact Via 69. The source of the P-channel fin-type FET 57b is connected to the drain of the P-channel fin-type FET 63 via the substrate wiring 67 and the contact Via69. The source of the P-channel fin type FET 63 is connected to the drain of the N-channel fm type FET 57c and the drain of the N-channel fm type FET 64 via the substrate wiring 59 connected to the output terminal and the contact Via69. The gate electrode of the P-channel fin-type FET 63 is connected to the gate electrode of the N-channel fin-type FET 64 and the input terminal 2 through the buried wiring 65 and the contact Via 69. Connect to on-board wiring 66. The source of N-channel fin-type FET 57 and the source of N-channel fin-type FET 64 are connected to the on-board wiring 60 connected to the ground power supply. That is, the N-channel fin-type FET 57 and the N-channel fin-type FET 64 are connected in parallel between the substrate wiring 60 connected to the ground power supply and the source of the P-channel fin-type FET 63. The P-channel fin type FET 56 and the P-channel fm type FET 63 are connected in series between the on-board wiring 55 connected to the positive power supply and the drains of the N-channel fin type FET 57 and the N-channel fin type FET 64. Therefore, the N-channel fm FET 57, the N-channel fin FET 64, the P-channel fm FET 56, and the P-channel fin FET 63 constitute a so-called nor circuit. The upper NOT circuit in Fig. 2C outputs the inverted signal of the logical sum of the logical signals input from the on-board wiring 58 connected to the input terminal 1 and the on-board wiring 66 connected to the input terminal 2 from the output terminal. To do.
[0023] 図 2Cの下段の Nor回路において、 70は正電源に接続する基板上配線、 71、 78は P チャネル fm型 FET、 72、 79は Nチャネル fm型 FET、 73は入力端子 1に接続する基板 上配線、 81は入力端子 2に接続する基板上配線、 74は出力端子に接続する基板上 配線、 75は接地電源に接続する基板上配線、 76、 80は埋込配線、 77は基板上配線 、 82は配線接続領域、 83はコンタクト Viaをそれぞれ示す。なお、基板上配線 70、 73、 81、 74、 75、 77が同一配線層に属するとは限らず、複数の配線層に属することがある 点は図 2Aの上段の回路レイアウトと同様である。  [0023] In the Nor circuit at the bottom of Figure 2C, 70 is the on-board wiring connected to the positive power supply, 71 and 78 are P-channel fm type FETs, 72 and 79 are N-channel fm type FETs, and 73 is connected to input terminal 1. Wiring on board, 81 is wiring on board connecting to input terminal 2, 74 is wiring on board connecting to output terminal, 75 is wiring on board connecting to ground power supply, 76 and 80 are embedded wiring, 77 is board Upper wiring 82 represents a wiring connection region, and 83 represents a contact Via. Note that the on-board wirings 70, 73, 81, 74, 75, and 77 do not necessarily belong to the same wiring layer, and may belong to a plurality of wiring layers, similar to the circuit layout in the upper stage of FIG. 2A.
そして、各構成要素の接続関係は、図 2Cの上段の Nor回路と同様である。また、図 2Cの下段の Nor回路の機能も、図 2Cの上段の Nor回路の機能と同様である。  The connection relationship of each component is the same as the Nor circuit in the upper part of Fig. 2C. The function of the lower Nor circuit in Fig. 2C is the same as that of the upper Nor circuit in Fig. 2C.
[0024] ただし、 Pチャネル fin型 FET71のゲート電極と Nチャネル fm型 FET72のゲート電極と は、埋込配線 76を介して接続されているが、コンタクト Via83を介さず、埋込配線 76と それぞれの fin型 FETのゲート電極とは直接的に配線接続領域 82において接続して いる。 Pチャネル fin型 FET78のゲート電極と Nチャネル fin型 FET79のゲート電極は、 坦込配線 80を介して接続されてレ、が、コンタクト Via83を介さず、坦込配線 80とそれぞ れの fm型 FETのゲート電極とは直接的に配線接続領域 82において接続している。埋 込配線 80と出力端子に接続する基板上配線 74とが直交状態で交差するように、坦込 配線 80、 Pチャネル fin型 FET78のソースのコンタクト Via83、 Nチャネル fm型 FET72の ドレインのコンタクト Via83、及び、 Nチャネル fin型 FET79のソースのコンタクト Via83は 配置されている。さらに、 Pチャネル fm型 FET71及び Nチャネル fin型 FET72と、埋込 配線 76は自己整合的である。また、 Pチャネル fin型 FET78及び Nチャネル fin型 [0024] However, although the gate electrode of the P-channel fin-type FET 71 and the gate electrode of the N-channel fm-type FET 72 are connected via the embedded wiring 76, they are connected to the embedded wiring 76 without using the contact Via 83, respectively. The fin type FET gate electrode is directly connected in the wiring connection region 82. The gate electrode of the P-channel fin-type FET78 and the gate electrode of the N-channel fin-type FET79 are connected via the carrier wire 80, but without the contact Via83, the carrier wire 80 and each fm type It is directly connected to the gate electrode of the FET in the wiring connection region 82. Embedded wiring 80, P-channel fin type FET78 source contact Via83, N-channel fm type FET72 drain contact Via83 so that embedded wiring 80 and on-board wiring 74 connected to the output terminal intersect at right angles And the source contact Via83 of the N-channel fin-type FET79 Has been placed. Furthermore, the P-channel fm type FET 71 and N-channel fin type FET 72 and the embedded wiring 76 are self-aligned. Also, P channel fin type FET78 and N channel fin type
FET79と、坦込配線 80は自己整合的である。 The FET 79 and the carrier wiring 80 are self-aligning.
従って、坦込配線と fin型 FETのゲート電極、及び、埋込配線と fin型 FETの fin領域との 位置合わせのための領域を省くことができる。また、埋込配線 76、 80及び基板上配線 70、 73、 74、 75、 77、 81が直線的となり、ホトリソグラフィー技術によりパターンを形成 する際にパターンの解像が容易となる。さらに、埋込配線 80と基板上配線 74が重なる ように配置が可能となる。 Therefore, it is possible to omit the area for alignment between the buried wiring and the fin FET gate electrode and the buried wiring and the fin area of the fin FET. In addition, the embedded wirings 76 and 80 and the on-substrate wirings 70, 73, 74, 75, 77, and 81 are linear, and the pattern can be easily resolved when the pattern is formed by photolithography. Further, the embedded wiring 80 and the on-substrate wiring 74 can be arranged so as to overlap each other.
従って、図 2Cの上段の Nor回路のレイアウト面積に比較し、図 2Cの下段の Nor回路 のレイアウト面積は縮小化されてレ、る。 Therefore, compared with the layout area of the Nor circuit in the upper part of FIG. 2C, the layout area of the Nor circuit in the lower part of FIG. 2C is reduced.
実施例 1に係る、図 2A、図 2B、及び、図 2Cの上段に示した回路パターンによると、 坦込配線と基板上配線間の層間絶縁膜は、各 fin型 FETを含むため厚くなる。従って 、坦込配線と基板上配線間の容量は、基板上配線が属する配線層間の容量より、減 少する。そうすると、埋込配線と基板状配線とが近接するのをさける必要はない。 また、実施例 1に係る、図 2A、図 2B、及び、図 2Cの下段に示した回路パターンに よると坦込配線が、各 fin型 FETの fin領域 (支持基板上に形成されたシリコンの立体独 立領域)と自己整合的に形成されているため、 fin領域と坦込配線との位置合わせ領 域の確保が不要である。  According to the circuit pattern shown in the upper part of FIGS. 2A, 2B, and 2C according to the first embodiment, the interlayer insulating film between the carrier wiring and the wiring on the substrate is thick because it includes each fin type FET. Therefore, the capacity between the carrier wiring and the on-board wiring is smaller than the capacity between the wiring layers to which the on-board wiring belongs. In this case, it is not necessary to avoid the embedded wiring and the board-shaped wiring from being close to each other. In addition, according to the circuit pattern shown in the lower part of FIGS. 2A, 2B, and 2C according to Example 1, the carrier wiring is connected to the fin region of each fin-type FET (the silicon formed on the support substrate). It is not necessary to secure the alignment area between the fin area and the loading wiring because it is formed in a self-aligned manner.
また、坦込配線が配線されている方向が揃えられており、基板上配線が直線的とな るように、各 fm型 FETのコンタクト viaが配置されている。従って、各基板上配線パター ンの形成において、パターンの解像が容易となる。そうすると、基板上配線パターン の間隔を狭めることができる。  In addition, the direction in which the carrier wiring is wired is aligned, and the contact via of each fm type FET is arranged so that the wiring on the board is straight. Therefore, in the formation of the wiring pattern on each substrate, the pattern can be easily resolved. Then, the interval between the wiring patterns on the substrate can be reduced.
さらに、埋込配線の配線方向と基板条配線とが直交し、かつ、埋込配線と基板上配 線が交差する部分があるように、坦込配線と基板上配線が配置されている。従って、 配線の重畳的な配置が可能となる。  Furthermore, the embedded wiring and the on-board wiring are arranged so that there is a portion where the wiring direction of the embedded wiring and the substrate wiring are orthogonal to each other and the embedded wiring and the on-board wiring intersect. Therefore, the wiring can be arranged in a superimposed manner.
以上のことより、実施例 1に係る、図 2A、図 2B、及び、図 2Cに示した回路パターン によれば、論理マクロセルの縮小化が図れる。  From the above, according to the circuit patterns shown in FIGS. 2A, 2B, and 2C according to the first embodiment, the logic macrocell can be reduced.
実施例 2 [0026] (Fin型 FETを用いた SRAMマクロセル） Example 2 [0026] (SRAM macrocell using Fin-type FET)
図 3は、 fin型 FETを回路要素に有する、実施例 2に係る SRAMの記憶回路をセルイ匕 した SRAMマクロセルの回路レイアウトを示す図である。そして、図 3A、図 3B、図 3C 、及び、図 3Dから構成されている。  FIG. 3 is a diagram showing a circuit layout of an SRAM macro cell in which the SRAM memory circuit according to the second embodiment having a fin-type FET as a circuit element is used. 3A, 3B, 3C, and 3D.
図 3Aは、 SRAM記憶素子の一部を示した回路である。図 3Aの SRAM記憶素子の一 部において、 85、 86はインバーター、 87は入力端子、 88は出力端子を、それぞれ示 す。そして、一方のインバーターは、入力端子 87から入力された論理信号を反転増 幅し、出力端子から出力信号を出力する。また、他方のインバーターは、出力端子か らの反転論理を有する論理信号を、さらに、反転増幅して、入力端子 87側へフィード バックを力ける。すなわち、入力端子 87からの論理信号の論理を、 SRAM記憶素子の 一部は記憶する機能を有する。  FIG. 3A is a circuit showing a part of the SRAM memory element. In some of the SRAM memory elements in Figure 3A, 85 and 86 are inverters, 87 is an input terminal, and 88 is an output terminal. One inverter inverts and amplifies the logic signal input from the input terminal 87 and outputs an output signal from the output terminal. The other inverter further inverts and amplifies the logic signal having the inverted logic from the output terminal, and feeds feedback to the input terminal 87 side. That is, a part of the SRAM memory element has a function of storing the logic of the logic signal from the input terminal 87.
[0027] 図 3Bは、図 3Aの SRAM記憶素子の一部を構成する fin型 FETと、その fin型 FETを接 続する埋込配線及び基板上配線とを含む回路レイアウトを示した図である。図 3Bに おいて、 90は正電源に接続する基板上配線、 91、 93は Pチャネル fin型 FET、 92、 94 は Nチャネル fin型 FET、 95、 96は坦込配線、 97は接地電源に接続する基板上配線、 98は入力端子に接続する基板上配線、 99は出力端子に接続する基板上配線、 100 はコンタクト Viaをそれぞれ示す。 FIG. 3B is a diagram showing a circuit layout including a fin-type FET that constitutes a part of the SRAM memory element of FIG. 3A, and embedded wiring and on-substrate wiring connecting the fin-type FET. . In Fig. 3B, 90 is on-board wiring connected to the positive power supply, 91 and 93 are P-channel fin type FETs, 92 and 94 are N-channel fin type FETs, 95 and 96 are carrying wirings, and 97 is ground power supply. On-board wiring to be connected, 98 is on-board wiring to be connected to the input terminal, 99 is on-board wiring to be connected to the output terminal, and 100 is a contact via.
なお、上記の基板上配線 90、 97、 98、 99はかならずしも、 1層の配線層から構成され ている必要はない。例えば、入力端子に接続する基板上配線 98及び出力端子に接 続する基板上配線 99は第 1層目の基板上配線、正電源に接続する基板上配線 90及 び接地電源に接続する基板上配線 97は第 2層目の基板上配線というように複数の配 線層力 構成されていてもよい。  Note that the above-mentioned wirings 90, 97, 98, 99 on the substrate do not necessarily need to be composed of one wiring layer. For example, the board wiring 98 connected to the input terminal and the board wiring 99 connected to the output terminal are the first layer board wiring, the board wiring 90 connected to the positive power supply, and the board connected to the ground power supply. The wiring 97 may have a plurality of wiring layer forces such as a second-layer wiring on the substrate.
そして、 Pチャネル fin型 FET91のゲート電極は、埋込配線 95とコンタクト vialOOを介し て Nチャネル fm型 FET92のゲート電極と接続し、坦込配線 95、入力端子に接続する 基板上配線 98、及び、コンタクト vialOOを介して、 Pチャネル fin型 FET93のソース、及 び、 Nチャネル fin型 FET94のドレインに接続している。 Pチャネル fin型 FET91のドレイ ンは正電源に接続する基板上配線 90と接続してレ、る。 Pチャネル fin型 FET91のソー スは、出力端子に接続する基板上配線 99及びコンタクト vialOOを介して、 Nチャネル fin型 FET92のドレインと接続し、出力端子に接続する基板上配線 99、埋込配線 96、 及び、コンタクト vialOOを介して、 Pチャネル fin型 FET93のゲート電極及び Nチャネル fin型 FET94のゲート電極と接続する。 Pチャネル fin型 FET93のドレインは、コンタクト vialOOを介して、正電源に接続する基板上配線 90と接続する。 Nチャネル fin型 Then, the gate electrode of the P-channel fin type FET 91 is connected to the gate electrode of the N-channel fm type FET 92 via the buried wiring 95 and the contact vial OO, the carrier wiring 95, the on-board wiring 98 connected to the input terminal, and The contacts are connected to the source of P-channel fin-type FET93 and the drain of N-channel fin-type FET94 via vialOO. The drain of the P-channel fin-type FET 91 is connected to the on-board wiring 90 connected to the positive power supply. The source of the P-channel fin-type FET91 is N-channel via the substrate wiring 99 connected to the output terminal and the contact vialOO. Connect to the drain of fin type FET 92 and connect to the output terminal on the board wiring 99, buried wiring 96, and contact vial OO, the gate electrode of P channel fin type FET 93 and the gate electrode of N channel fin type FET 94 Connecting. The drain of the P-channel fin-type FET 93 is connected to the on-substrate wiring 90 connected to the positive power supply via the contact vialOO. N channel fin type
FET94のソースはコンタクト vialOOを介して接地電源に接続する基板上配線 97と接続 する。 Nチャネル fm型 FET92のソースはコンタクト vialOOを介して接地電源に接続す る基板上配線 97と接続する。  The source of FET94 is connected to the on-board wiring 97 connected to the ground power supply via the contact vialOO. The source of the N-channel fm type FET92 is connected to the on-board wiring 97 that is connected to the ground power supply via the contact vialOO.
[0028] 従って、 Pチャネル fin型 FET91と Nチャネル fm型 FET92とは、正電源と接地電源の 間に直列に接続されており、 not回路、すなわち、インバーター回路を形成している。 Therefore, the P-channel fin type FET 91 and the N-channel fm type FET 92 are connected in series between the positive power source and the ground power source, and form a not circuit, that is, an inverter circuit.
Pチャネル fln型 FET93と Nチャネル fin型 FET94とは、正電源と接地電源の間に直列に 接続されており、 not回路、すなわち、インバーター回路を形成している。その結果、 図 3Aで説明したように、回路全体では、 SRAMの記憶素子の一部と同様な機能を有 する。 The P-channel f ln type FET 93 and the N-channel fin type FET 94 are connected in series between the positive power supply and the ground power supply, and form a not circuit, that is, an inverter circuit. As a result, as explained in FIG. 3A, the entire circuit has the same function as a part of the SRAM memory element.
ここで、図 3Bの回路レイアウトにおいて、 fin型 FET等の回路素子を含むこととなるた め、坦込配線 95、 96と基板上配線 90、 97、 98、 99との層間絶縁層は、基板上配線 90、 97、 98、 99を構成する複数の配線層間の絶縁層よりも厚い。従って、埋込配線 95、 96 と基板上配線 90、 97、 98、 99間の配線容量は、基板上配線 90、 97、 98、 99を形成する 複数の配線層間の配線容量より、小さレ、。  Here, in the circuit layout of FIG. 3B, since circuit elements such as fin-type FETs are included, the interlayer insulation layer between the embedded wiring 95, 96 and the wiring 90, 97, 98, 99 on the board is It is thicker than the insulating layer between the plurality of wiring layers constituting the upper wiring 90, 97, 98, 99. Therefore, the wiring capacity between the embedded wiring 95, 96 and the on-board wiring 90, 97, 98, 99 is smaller than the wiring capacity between the plurality of wiring layers forming the on-board wiring 90, 97, 98, 99. .
[0029] 図 3Cは、図 3Aの SRAM記憶素子の一部を構成する fm型 FETと、その fm型 FETを接 続する埋込配線及び基板上配線とを含む回路レイアウトを示した図である点は、図 3 Bと同様である力 坦込配線の一部のパターンを fin型 FETの fin領域と自己整合的に 形成した点、及び、 fm型 FETのゲート電極と坦込配線の接続をコンタクト viaを介さず 接続する点で異なる回路レイアウトである。  [0029] FIG. 3C is a diagram showing a circuit layout including the fm type FET constituting a part of the SRAM memory element of FIG. 3A, and the embedded wiring and the wiring on the substrate for connecting the fm type FET. The points are the same as in Fig. 3B. Some patterns of force-carrying wiring are formed in a self-aligned manner with the fin region of the fin-type FET, and the connection between the gate electrode of the fm-type FET and the loading wiring The circuit layout is different in that the connection is made without using the contact via.
[0030] 図 3Cにおいて、 105は正電源に接続する基板上配線、 106、 107は Pチャネル fm型 FET、 108、 109は Nチャネル fin型 FET、 110は接地電源に接続する基板上配線、 111 は出力端子に接続する基板上配線、 112は入力端子に接続する基板上配線、 113は コンタク Via、 114は配線接続領域、 115、 116、 117、 118は坦込配線をそれぞれ示す。 なお、基板上配線 105、 110、 111、 112は複数の基板上配線層に属するとする点は、 図 3Bの回路レイアウトと同様である。 [0030] In FIG. 3C, 105 is a substrate wiring connected to a positive power source, 106 and 107 are P channel fm type FETs, 108 and 109 are N channel fin type FETs, 110 is a substrate wiring connected to a ground power source, 111 Is the on-board wiring connected to the output terminal, 112 is the on-board wiring connected to the input terminal, 113 is the contact Via, 114 is the wiring connection area, and 115, 116, 117, and 118 are the carrier wiring. Note that the on-board wirings 105, 110, 111, and 112 belong to a plurality of on-board wiring layers. This is the same as the circuit layout in Fig. 3B.
そして、 Pチャネル fin型 FET106のドレインはコンタクト vial 13を介して正電源に接続 する基板上配線 105と接続している。 Pチャネル fin型 FET106のゲート電極は、埋込配 線 115を介して、 Nチャネル fm型 FET108のゲート電極の一方の端と接続している。 N チャネル fin型 FET108の他方の端は、埋込配線 117、入力端子に接続する基板上配 線 112、及び、コンタクト vial 13を介して、 Pチャネル fin型 FET107のソース及び Nチヤ ネル fin型 FET109のドレインと接続している。 Pチャネル fm型 FET106のソースは、出力 端子に接続する基板上配線 111を介して、 Nチャネル fm型 FET108のドレインと接続し 、さらに、出力端子に接続する基板上配線 111、コンタクト via、及び、埋込配線 116を 介して、 Pチャネル fin型 FET107のゲート電極の一方の端に接続する。 Pチャネル fin 型 FET107のゲート電極の他方の端は、坦込配線 118を介して、 Nチャネル fm型  The drain of the P-channel fin-type FET 106 is connected to the on-substrate wiring 105 connected to the positive power source via the contact vial 13. The gate electrode of the P-channel fin type FET 106 is connected to one end of the gate electrode of the N-channel fm type FET 108 via the buried wiring 115. The other end of the N-channel fin-type FET 108 is connected to the source of the P-channel fin-type FET 107 and the N-channel fin-type FET 109 via the embedded wiring 117, the on-board wiring 112 connected to the input terminal, and the contact vial 13. It is connected to the drain. The source of the P-channel fm type FET 106 is connected to the drain of the N-channel fm type FET 108 via the substrate wiring 111 connected to the output terminal, and further, the substrate wiring 111 connected to the output terminal, the contact via, and Connected to one end of the gate electrode of P-channel fin-type FET 107 via buried wiring 116. The other end of the gate electrode of the P-channel fin-type FET 107 is connected to the N-channel fm type via the carrier wiring 118.
FET109のゲート電極に接続する。 Pチャネル fm型 FET107のドレインはコンタクト viaを 介して正電源に接続する基板上配線 105と接続する。 Nチャネル fm型 FET108のソー スはコンタクト viaを介して、接地電源に接続する基板上配線 110と接続する。 Nチヤネ ノレ fin型 FET109のソースはコンタクト viaを介して、接地電源に接続する基板上配線 110と接続する。  Connect to the gate electrode of FET109. The drain of the P-channel fm type FET 107 is connected to the on-board wiring 105 that is connected to the positive power supply via the contact via. The source of the N-channel fm type FET 108 is connected to the on-board wiring 110 connected to the ground power supply via the contact via. The source of the N-channel fin type FET 109 is connected to the on-board wiring 110 connected to the ground power supply via the contact via.
[0031] 図 3Cの回路レイアウトでは、埋込配線の一部のパターンを fm型 FETの fin領域と自 己整合的に形成したため、 fm型 FETと埋込配線の間隔を縮小できる。  In the circuit layout of FIG. 3C, a part of the embedded wiring pattern is formed in a self-aligned manner with the fin region of the fm type FET, so that the interval between the fm type FET and the embedded wiring can be reduced.
また、 fin型 FETのゲート電極と坦込配線の接続に際して、コンタクト viaを介さず接続 したため、位置合わせ領域のうち、 fm型 FETのゲート電極とコンタクト via、及び、埋込 配線とコンタクト viaの位置合わせ領域を省略することができる。  In addition, since the fin FET gate electrode and the carrier wiring were connected without a contact via, the positions of the fm FET gate electrode and the contact via and the buried wiring and the contact via in the alignment region. The alignment area can be omitted.
さらに、埋込配線と fin型 FETの fin領域を一方向へ揃え、かつ、基板上配線が直線 的となるように、コンタクト viaを並べたため、ホトリソグラフィ一により、パターンを形成 する際に、パターンの解像度があがる。その結果、パターン間の間隔を縮小すること ができる。  Furthermore, the contact vias are aligned so that the embedded wiring and the fin region of the fin-type FET are aligned in one direction and the wiring on the substrate is linear. The resolution increases. As a result, the interval between patterns can be reduced.
従って、図 3Bの回路レイアウトに比較して、レイアウト面積を縮小することができる。  Therefore, the layout area can be reduced as compared with the circuit layout of FIG. 3B.
[0032] 図 3Dは、図 3Aの SRAM記憶素子の一部を構成する fm型 FETと、その fm型 FETを 接続する埋込配線及び基板上配線とを含む回路レイアウトを示した図である点は、 図 3Bと同様であるが、坦込配線のパターンを fin型 FETの fin領域と自己整合的に形 成した点、及び、 fm型 FETのゲート電極と坦込配線の接続するに際してコンタクト via を介さず接続する点で異なる回路レイアウトである。また、図 3Cの回路レイアウトを比 較した場合には、坦込配線のパターンの全部を fin型 FETの fin領域と自己整合的に 形成した点で異なる。 [0032] FIG. 3D is a diagram showing a circuit layout including an fm type FET that constitutes a part of the SRAM memory element of FIG. 3A, and embedded wiring and wiring on the substrate that connect the fm type FET. Is Similar to Fig. 3B, but the carrier wiring pattern is formed in a self-aligned manner with the fin region of the fin-type FET, and via the contact via when connecting the gate electrode of the fm-type FET and the carrier wire. The circuit layout is different in that they are connected. In addition, when comparing the circuit layout of Fig. 3C, the difference is that the entire pattern of the carrier wiring is formed in a self-aligned manner with the fin region of the fin-type FET.
図 3Dにおいて、 120は正電源に接続する基板上配線、 121、 122は Pチャネル fin型 FET、 123、 124は Nチャネル fin型 FET、 125は接地電源に接続する基板上配線、 126 は出力端子に接続する基板上配線、 127は入力端子に接続する基板上配線、 128は コンタクト Via、 129は配線接続領域、 130、 131は坦込配線をそれぞれ示す。なお、基 板上配線 120、 125、 126、 127は複数の基板上配線層に属するとする点は、図 3Bの 回路レイアウトと同様である。  In Fig. 3D, 120 is the on-board wiring connected to the positive power supply, 121 and 122 are P-channel fin-type FETs, 123 and 124 are N-channel fin-type FETs, 125 is the on-board wiring connected to the ground power supply, and 126 is the output terminal , 127 is a contact via, 129 is a wiring connection region, and 130 and 131 are carrier wirings. It is to be noted that the on-board wirings 120, 125, 126, and 127 belong to a plurality of wiring layers on the substrate, which is the same as the circuit layout of FIG. 3B.
そして、図 3Dにおいて、各 fm型 FETのゲート電極、各 fin型 FETのソース、各 fin型 FETのドレイン、入力端子、及び、出力端子を接続する、埋込配線及び基板上配線 の接続関係は、図 3Bにおける接続関係と同様である。ただし、各 fm型 FET121、 122 、 123、 124のゲート電極と坦込配線 130、 131の接続が、コンタクト vial28を介さず、酉己 線接続領域 129における直接的な接続で、行われている点で異なる。また、各 fm型 FETの fm領域に対して埋め込み配線 130、 131が自己整合的に形成されている点で 異なる。さらに、出力端子に接続する基板上配線 126及び入力端子に接続する基板 上配線 127が直線となるように、ンタクト Vial28は配置されている点でも異なる。加えて 、坦込配線 130と出力端子に接続する基板上配線 126とが交差するように配置されて おり、坦込配線 131と入力端子に接続する基板上配線 127が交差するように配置され ている点で異なる。  In Fig. 3D, the connection relationship between the embedded wiring and the wiring on the substrate that connects the gate electrode of each fm FET, the source of each fin FET, the drain, input terminal, and output terminal of each fin FET is This is the same as the connection relationship in FIG. 3B. However, the connection between the gate electrode of each fm type FET 121, 122, 123, 124 and the carrier wiring 130, 131 is made by direct connection in the contact line connection region 129, not through the contact vial 28. It is different. Another difference is that embedded wirings 130 and 131 are formed in a self-aligned manner in the fm region of each fm type FET. Further, the contact Vial 28 is also arranged so that the on-board wiring 126 connected to the output terminal and the on-board wiring 127 connected to the input terminal are linear. In addition, the carrier wiring 130 and the on-board wiring 126 connected to the output terminal cross each other, and the carrier wiring 131 and the on-board wiring 127 connected to the input terminal cross each other. Is different.
なお、 Pチャネル fin型 FET121と Nチャネル fm型 FET123とがインバーターを構成し、 Pチャネル fln型 FET122と Nチャネル fin型 FET124とがインバーターを構成することは 図 3Bと同様である。また、 Pチャネル fin型 FET121、 122、及び、 Nチャネル fin型 The P channel fin type FET 121 and the N channel fm type FET 123 constitute an inverter, and the P channel f ln type FET 122 and the N channel fin type FET 124 constitute an inverter as in FIG. 3B. Also, P channel fin type FET121, 122 and N channel fin type
FET123、 124が、 SRAM記憶素子の一部を構成する点も同様である。 Similarly, the FETs 123 and 124 constitute a part of the SRAM storage element.
実施例 2に係る、図 3B、図 3C、及び、図 3Dに示した回路パターンによると、坦込 配線と基板上配線間の層間絶縁膜は、各 fin型 FETを含むため厚くなる。従って、埋 込配線と基板上配線間の容量は、基板上配線が属する基板上配線層間の容量より 、減少する。そうすると、埋込配線と基板状配線とが近接するのをさける必要はない。 また、実施例 2に係る、図 3C、及び、図 3Dに示した回路パターンによると埋込配線 が、各 fin型 FETの fm領域 (支持基板上に形成されたシリコンの立体独立領域)と自己 整合的に形成されてレ、るため、 fm領域と埋込配線との位置合わせ領域の確保が不 要である。 According to the circuit patterns shown in FIG. 3B, FIG. 3C, and FIG. 3D according to the second embodiment, the interlayer insulating film between the carrier wiring and the wiring on the substrate becomes thick because each fin type FET is included. Therefore, buried The capacitance between the embedded wiring and the on-board wiring is smaller than the capacitance between the on-board wiring layers to which the on-board wiring belongs. In this case, it is not necessary to avoid the embedded wiring and the board-shaped wiring from being close to each other. In addition, according to the circuit patterns shown in FIG. 3C and FIG. 3D according to Example 2, the embedded wiring is connected to the fm region of each fin-type FET (the three-dimensional independent region of silicon formed on the support substrate) and self Since it is formed in a consistent manner, it is not necessary to secure an alignment region between the fm region and the embedded wiring.
また、坦込配線の配線されている方向が揃えられており、基板上配線が直線的とな るように、各 fm型 FETのコンタクト via位置が配置されている。従って、各パターンの形 成において、パターンの解像が容易となる。そうすると、基板上配線の配線パターン の間隔を狭めることができる。  In addition, the wiring direction of the carrier wiring is aligned, and the contact via position of each fm type FET is arranged so that the wiring on the board is linear. Therefore, the pattern can be easily resolved in the formation of each pattern. Then, the interval between the wiring patterns on the substrate can be reduced.
さらに、埋込配線の配線方向と基板条配線とが直交し、かつ、埋込配線と基板上配 線が交差する部分があるように、坦込配線と基板上配線が配置されている。従って、 配線が、重畳的に配置される。  Furthermore, the embedded wiring and the on-board wiring are arranged so that there is a portion where the wiring direction of the embedded wiring and the substrate wiring are orthogonal to each other and the embedded wiring and the on-board wiring intersect. Therefore, the wiring is arranged in a superimposed manner.
以上のことより、実施例 2に係る、図 3B、図 3C、及び、図 3Dに示した回路パターン によれば、論理マクロセルの縮小化が図れる。  From the above, according to the circuit patterns shown in FIGS. 3B, 3C, and 3D according to the second embodiment, the logic macrocell can be reduced.
実施例 3  Example 3
[0034] (fm型 FETを用レ、、かつ、コンタクト viaにシェアードコンタクトを用いた SRAMマクロセル )  [0034] (SRAM macrocell using fm type FET and using shared contact as contact)
図 4は、 fm型 FETを回路要素として有し、シュエアードコンタクトを用いたことを特徴 とする、実施例 3に係る SRAMの記憶回路をセル化した SRAMマクロセルの回路レイァ ゥトを示す図である。そして、図 4A、図 4B、図 4C、及び、図 4Dから構成されている。 図 4Aは、 SRAM記憶素子の一部を示した回路である。図 4Aの SRAM記憶素子の一 部において、 130、 131はインバーター、 132は入力端子、 133は出力端子に接続する 基板上配線をそれぞれ示す。  FIG. 4 is a diagram showing an SRAM macro cell circuit layout in which the SRAM memory circuit according to the third embodiment is made into a cell, which has an fm type FET as a circuit element and uses a squired contact. is there. 4A, 4B, 4C, and 4D. FIG. 4A is a circuit showing a part of the SRAM memory element. In a part of the SRAM memory element of FIG. 4A, 130 and 131 are inverters, 132 is an input terminal, and 133 is a wiring on a substrate connected to an output terminal.
そして、図 4Aの、 SRAM記憶素子の一部を示した回路の動作、及び、機能は図 3A の SRAM記憶素子の一部を示した回路と同様である。  The operation and function of the circuit showing part of the SRAM memory element in FIG. 4A are the same as those of the circuit showing part of the SRAM memory element in FIG. 3A.
[0035] 図 4Bは、図 4Aの SRAM記憶素子の一部を構成する fm型 FETと、その fin型 FETを接 続する埋込配線及び基板上配線とを含む回路レイアウトであり、その一部にシェア一 ドコンタクトを用いたことを特徴とする回路レイアウトを示した図である。 [0035] FIG. 4B is a circuit layout including an fm type FET constituting a part of the SRAM memory element of FIG. 4A, a buried wiring connecting the fin type FET, and a wiring on the substrate. Share the best It is the figure which showed the circuit layout characterized by using a contact.
図 3Cと同様、埋込配線の一部のパターンを fm型 FETの fm領域と自己整合的に形 成した点、及び、 fm型 FETのゲート電極と坦込配線の接続に際して、コンタクト viaを 介さず接続する点で特徴を有する回路レイアウトであり、さらに、シェアードコンタクト を用いたことを特徴とする回路レイアウトである。  As in Fig. 3C, part of the embedded wiring pattern was formed in a self-aligned manner with the fm region of the fm type FET, and when connecting the gate electrode of the fm type FET and the carrier wiring, the contact via was used. The circuit layout is characterized in that it is connected to each other, and the circuit layout is characterized in that a shared contact is used.
[0036] 図 4Bにおいて、 135は正電源に接続する基板上配線、 136、 137は Pチャネル fin型 FET、 138、 139は Nチャネル fin型 FET、 140は接地電源に接続する基板上配線、 141 は出力端子に接続する基板上配線、 142は入力端子に接続する基板上配線、 143は コンタクト Via、 144は配線接続領域、 145、 146、 147、 148は埋込配線、 149はシェア一 ドコンタクトをそれぞれ示す。なお、上記の基板上配線 135、 140、 141、 142はかならず しも、 1層の配線層力 構成されている必要はない。例えば、入力端子に接続する基 板上配線 142及び出力端子に接続する基板上配線 141は第 1層目の基板上配線、正 電源に接続する基板上配線 135及び接地電源に接続する基板上配線 140は第 2層目 の基板上配線というように複数の配線層力 構成されていてもよい。  [0036] In FIG. 4B, 135 is a substrate wiring connected to a positive power source, 136 and 137 are P-channel fin type FETs, 138 and 139 are N channel fin type FETs, 140 is a substrate wiring connected to a ground power source, 141 Is the on-board wiring connected to the output terminal, 142 is the on-board wiring connected to the input terminal, 143 is the contact via, 144 is the wiring connection area, 145, 146, 147, 148 are embedded wiring, 149 is the shared contact Respectively. Note that the above-mentioned wirings 135, 140, 141, 142 on the substrate do not necessarily have to be configured with a single wiring layer force. For example, the board wiring 142 connected to the input terminal and the board wiring 141 connected to the output terminal are the first layer board wiring, the board wiring 135 connected to the positive power supply, and the board wiring connected to the ground power supply. 140 may have a plurality of wiring layer forces such as a second layer wiring on the substrate.
[0037] 図 4Bにおレ、て、各 fm型 FET、各電源、及び、各端子を、埋込配線及び基板上配線 等で接続することは、図 3Cと同様である。ただし、 Nチャネル fm型 FET138のドレイン と坦込配線 146とを出力端子に接続する基板上配線 141を介して行う場合に、坦込配 線 146と Nチャネル fm型 FET138のドレインとが近接しているため、シェアードコンタクト 149を用いて、出力端子に接続する基板上配線 141との接続を図っている点で異なる 。また、 Pチャネル fm型 FET137のソースと埋込配線 147とを入力端子に接続する基板 上配線 142を介して行う場合に、坦込配線 147と Pチャネル fin型 FET137のドレインとが 近接しているため、シェアードコンタクト 149を用いて、入力端子に接続する基板上配 線 142との接続を図っている点でも異なる。ここで、シェアードコンタクトとは、同一の 配線パターンに対して 2以上のパターンが接続する場合に、同一の配線パターンと 一方のパターンのコンタクト via位置と、同一の配線パターンと他方のパターンのコン タクト via位置とを近接させ、連結させて、一つのコンタクト viaとしたものをいう。すなわ ち、シェアードコンタクトの一部において、同一の配線パターンと一方のパターンが接 続し、さらに、残りのシェアードコンタクトの部分において、同一の配線と他方のパタ ーンが接続する形態となる。 [0037] In FIG. 4B, each fm type FET, each power source, and each terminal are connected by a buried wiring, a wiring on a substrate, and the like as in FIG. 3C. However, if the drain of the N-channel fm FET 138 and the carrier wiring 146 are connected via the on-board wiring 141 that connects to the output terminal, the carrier wiring 146 and the drain of the N-channel fm FET 138 are close to each other. Therefore, the difference is that the shared contact 149 is used to connect to the on-board wiring 141 connected to the output terminal. Also, when the P-channel fm type FET137 source and embedded wiring 147 are connected via the on-board wiring 142 that connects to the input terminal, the carrier wiring 147 and the drain of the P-channel fin type FET137 are close to each other. Therefore, it is different in that the shared contact 149 is used to connect to the on-board wiring 142 connected to the input terminal. Here, the shared contact means that when two or more patterns are connected to the same wiring pattern, the same wiring pattern and the contact via position of one pattern and the contact of the same wiring pattern and the other pattern are used. A contact that is made close to and connected to a via position to form a single contact via. That is, the same wiring pattern and one pattern are connected to a part of the shared contact, and the same wiring and the other pattern are connected to the remaining shared contact part. It becomes the form where the screen connects.
[0038] 従って、コンタクト via間の最小間隔の取得のための領域を削減することができる。例 えば、図 4Bでは、通常では、坦込配線 146上のコンタクト viaと Nチャネル fm型 FET138 のドレイン上のコンタクト viaが必要である力 上記の 2つのコンタクト viaを連結してシヱ ァードコンタクトとすることにより、コンタクト via間に必要な領域を削減できるとともに、 Nチャネル fm型 FETのドレインと埋込配線 146との間隔も狭めることができる。従って、 図 3Cの回路レイアウトに比較して、さらに、回路レイアウト面積を縮小することができ る。 Accordingly, it is possible to reduce the area for obtaining the minimum interval between the contacts via. For example, in FIG. 4B, a force that normally requires a contact via on the carrier wiring 146 and a contact via on the drain of the N-channel fm FET 138 connects the above two contact vias to form a side contact. As a result, the necessary area between the contacts via can be reduced, and the distance between the drain of the N-channel fm type FET and the buried wiring 146 can be reduced. Therefore, the circuit layout area can be further reduced as compared with the circuit layout of FIG. 3C.
[0039] 図 4Cは、 SRAM記憶素子を示した回路である。図 4Cの SRAM記憶素子において、  [0039] FIG. 4C is a circuit showing an SRAM memory element. In the SRAM memory element of Figure 4C,
152、 153は信号線、 154、 155はインバーター、 156、 157は転送ゲートトランジスタ、 158は入力端子、 159は出力端子をそれぞれ示す。  152 and 153 are signal lines, 154 and 155 are inverters, 156 and 157 are transfer gate transistors, 158 is an input terminal, and 159 is an output terminal.
[0040] そして、図 4Cの SRAM記憶素子は、図 4Aの SRAM記憶素子の一部を示す回路に、 転送ゲートトランジスタ 156、 157が追加された構成となっている。また、図 4Cの、 SRAM記憶素子を示した回路の動作、及び、機能において、図 4Aの SRAM記憶素子 の一部を示した回路と同様な構成をとる、インバーター 154、 155の部分は、図 4Aと同 様な操作、機能を有する。  The SRAM storage element in FIG. 4C has a configuration in which transfer gate transistors 156 and 157 are added to a circuit showing a part of the SRAM storage element in FIG. 4A. In addition, in the operation and function of the circuit showing the SRAM memory element in FIG. 4C, the parts of the inverters 154 and 155 having the same configuration as the circuit showing a part of the SRAM memory element in FIG. Has the same operations and functions as 4A.
[0041] 一方、図 4Cの SRAM記憶素子を示した回路の転送ゲートトランジスタ 156は、インバ 一ター 154、 155の部分に記憶される論理信号を、入力端子 158から、受け取るか否か を信号線 152の論理により、選択する機能を有する。すなわち、転送ゲートトランジス タ 156のゲート電極に、論理値 'H'の電位が印加されると、図 4Cの SRAM記憶素子を 示した回路は、入力信号を、受け入れる。また、転送ゲートトランジスタ 156のゲート電 極に、論理値' L'の電位が印加されると、図 4Cの SRAM記憶素子を示した回路は、入 力信号を、受け入れなレ、。一方、図 4Cの SRAM記憶素子を示した回路の転送ゲート トランジスタ 157は、インバーター 154、 155の部分に記憶される論理信号を、出力する か否力、を信号 153の論理により、選択する。すなわち、転送ゲートトランジスタ 158のゲ ート電極に、論理値 'H'の電位が印加されると、図 4Cの SRAM記憶素子を示した回路 は、出力信号を、出力する。また、転送ゲートトランジスタ 157のゲート電極に、論理値 'L'の電位が印加されると、図 4Cの SRAM記憶素子を示した回路は、出力信号を、出 力しない。 On the other hand, the transfer gate transistor 156 of the circuit showing the SRAM storage element of FIG. 4C is a signal line indicating whether or not to receive the logic signal stored in the inverters 154 and 155 from the input terminal 158. It has a function to select according to the logic of 152. That is, when a potential of logical value “H” is applied to the gate electrode of the transfer gate transistor 156, the circuit showing the SRAM memory element in FIG. 4C accepts the input signal. In addition, when the potential of the logical value “L” is applied to the gate electrode of the transfer gate transistor 156, the circuit showing the SRAM memory element in FIG. 4C does not accept the input signal. On the other hand, the transfer gate transistor 157 in the circuit showing the SRAM memory element in FIG. 4C selects whether or not to output the logic signal stored in the inverters 154 and 155 by the logic of the signal 153. That is, when a potential of logical value “H” is applied to the gate electrode of the transfer gate transistor 158, the circuit showing the SRAM memory element in FIG. 4C outputs an output signal. When a potential of logical value 'L' is applied to the gate electrode of the transfer gate transistor 157, the circuit showing the SRAM memory element in FIG. 4C outputs an output signal. I do not power.
[0042] 図 4Dは、図 4Cの SRAM記憶素子を構成する fin型 FETと、その fm型 FETを接続する 坦込配線及び基板上配線とを含む回路レイアウトであり、その一部にシェアードコン タクトを用いたことを特徴とする回路レイアウトを示した図である。  [0042] FIG. 4D is a circuit layout including a fin-type FET constituting the SRAM memory element of FIG. 4C and a carrier wiring and a wiring on the substrate for connecting the fm-type FET, and a shared contact is partly included in the circuit layout. It is the figure which showed the circuit layout characterized by using this.
図 4Dにおいて、 160は正電源に接続する基板上配線、 161、 162は Pチャネル fin型 FET、 163、 164、 165、 166は Nチャネル fm型 FET、 167は接地電源に接続する基板上 配線、 168は出力端子に接続する基板上配線、 169は入力端子に接続する基板上配 線、 170、 171は基板上配線、 172、 173は埋込配線、 174はコンタクト Via、 175はシェア ードコンタクト、 176は配線接続領域、 177、 178は信号線に接続する基板上配線をそ れぞれ示す。なお、基板上配線 160、 167、 168、 169、 170、 171は、一の配線層から構 成されてレ、る必要はなく、複数の配線層により構成されてレ、てもよレ、。  In Figure 4D, 160 is on-board wiring connected to the positive power supply, 161 and 162 are P-channel fin type FETs, 163, 164, 165 and 166 are N-channel fm type FETs, 167 is on-board wiring connected to the ground power supply, 168 is the on-board wiring connected to the output terminal, 169 is the on-board wiring connected to the input terminal, 170 and 171 are the on-board wiring, 172 and 173 are the embedded wiring, 174 is the contact Via, 175 is the shared contact, 176 Is the wiring connection area, and 177 and 178 are the wirings on the board that are connected to the signal lines. The on-board wiring 160, 167, 168, 169, 170, 171 need not be composed of one wiring layer, and may be composed of a plurality of wiring layers.
[0043] そして、 Pチャネル fin型 FET161のドレインはコンタクト vial74を介して正電源に接続 する基板上配線 160と接続している。 Pチャネル fm型 FET161のソースは、シェアード コンタクト 175において、基板上配線 170によって、 Nチャネル fm型 FET164のドレイン と接続されている。また、 Pチャネル fin型 FET161のソースは、基板上配線 170によって 、コンタクト vial74を介して、 Nチャネル fm型 FET165のドレインと接続している。さらに 、 Pチャネル fm型 FET161のソースは、基板上配線 170及び坦込配線 173により、シェ ァードコンタクト 175、コンタクト vial74、及び、配線接続領域 176を介して、 Pチャネル fin型 FET162のゲート電極及び Nチャネル fin型 FET166のゲート電極と接続している。 [0043] The drain of the P-channel fin-type FET 161 is connected to the on-substrate wiring 160 connected to the positive power source via the contact vial 74. The source of the P-channel fm type FET 161 is connected to the drain of the N-channel fm type FET 164 through the substrate contact 170 at the shared contact 175. The source of the P-channel fin type FET161 is the board wiring 170 through a contact v Ial74, connected to the drain of N-channel fm type FET 165. Furthermore, the source of the P-channel fm type FET 161 is connected to the gate electrode of the P-channel fin type FET 162 and the N-channel via the on-board wiring 170 and the carrier wiring 173 via the shade contact 175, the contact vial 74, and the wiring connection region 176 It is connected to the gate electrode of fin type FET166.
Pチャネル fin型 FET161のゲート電極は、埋込配線 172により、配線接続領域 176を介 して Nチャネル fm型 FET165のゲート電極と接続されている。また、 Pチャネル fm型 FET161のゲート電極は、坦込配線 172及び基板上配線 171により、配線接続領域 176 、コンタクト vial74を介して Pチャネル fin型 FET162のソースと接続している。さらに、 P チャネル fin型 FET161のゲート電極は、埋込配線 172及び基板上配線 171により、酉己 線接続領域 176、コンタクト vial74、及び、シェアードコンタクト 175を介して Nチャネル fin型 FET166のドレイン及び Nチャネル fm型 FET163のソースと接続している。 The gate electrode of the P-channel fin type FET 161 is connected to the gate electrode of the N-channel fm type FET 165 through the wiring connection region 176 by the embedded wiring 172. The gate electrode of the P-channel fm type FET161 is by Tankomi wiring 172 and the board wiring 171, the wiring connection area 176, is connected to the source of P-channel fin type FET162 through contact v ial74. Furthermore, the gate electrode of the P-channel fin-type FET 161 is connected to the drain and N of the N-channel fin-type FET 166 via the buried wiring 172 and the on-substrate wiring 171 via the contact line connection region 176, the contact vial 74, and the shared contact 175. Connected to the source of channel fm type FET163.
[0044] Nチャネル fin型 FET164のソースは入力端子 168へコンタクト vial74を介して接続し ている。 Nチャネル fin型 FET165、 166のソースは、コンタクト vial74を介して接地電源 に接続する基板上配線 167と接続している。 Pチャネル fin型 FET162のドレインはコン タクト vial74を介して正電源に接続する基板上配線 160へ接続している。 Nチャネル fin型 FET163のドレインはコンタクト vial74を介して出力端子へ接続する基板上配線 168へ接続している。 Nチャネル fm型 FET163のゲート電極は信号線へ接続する基板 上配線 178へ接続している。また、 Nチャネル fm型 FET164のゲート電極は信号線へ 接続する基板上配線 177へ接続してレ、る。 [0044] The source of the N-channel fin-type FET 164 is connected to the input terminal 168 via a contact vial 74. N channel fin type FET165, 166 source is grounded via contact vial74 Connected to on-board wiring 167 connected to The drain of the P-channel fin-type FET 162 is connected via a contact vial 74 to a substrate wiring 160 that is connected to the positive power supply. The drain of the N-channel fin type FET 163 is connected to the on-board wiring 168 connected to the output terminal via the contact vial 74. The gate electrode of the N-channel fm type FET163 is connected to the on-substrate wiring 178 that is connected to the signal line. The gate electrode of the N-channel fm type FET 164 is connected to the substrate wiring 177 connected to the signal line.
シェアードコンタクト 175を使用することにより、通常のコンタクト vial74を 2つ並べるた めの間隔をとる必要はないため、 Nチャネル fm型 FET164と Pチャネル fin型 FET161の 間隔をさらに縮小することができる。また、同様に、シェアードコンタクト 175を使用する ことにより、 Nチャネル fin型 FET163と Nチャネル fm型 FET166との間隔もさらに縮小す ること力 Sできる。従って、シェアードコンタクト 175を使用することにより、 SRAM記憶素 子の回路レイアウトを縮小することができる。  By using the shared contact 175, it is not necessary to provide a space for arranging two normal contact vials 74, so that the space between the N-channel fm type FET164 and the P-channel fin-type FET161 can be further reduced. Similarly, by using the shared contact 175, the distance between the N-channel fin-type FET 163 and the N-channel fm-type FET 166 can be further reduced. Therefore, the circuit layout of the SRAM memory element can be reduced by using the shared contact 175.
実施例 4  Example 4
[0045] (Fin型 FETを用いた、論理マクロセル又は SRAMマクロセルの製造工程）  [0045] (Manufacturing process of logic macro cell or SRAM macro cell using Fin type FET)
図 5、図 6、図 7、図 8、図 9、図 10、及び、図 11を用いて、実施例 4として、実施例 1、 2、及び、 3に示した論理マクロセル又は SRAMマクロセルの製造工程を示す。  Using FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, and FIG. 11, as the fourth embodiment, manufacturing the logic macro cell or SRAM macro cell shown in the first, second, and third embodiments A process is shown.
図 5は、論理マクロセル又は SRAMマクロセルの製造工程のフローチャートを示した ものである。  Figure 5 shows a flowchart of the manufacturing process of a logic macrocell or SRAM macrocell.
[0046] 図 5において、 180は fin領域形成工程、 181は fm領域、 182は絶縁支持基板、 183は 溝形成工程、 184は埋込配線用の溝、 185はシリコン ·ゲルマニウム (SiGe)坦込工程、 186はシリコン.ゲルマニウム (SiGe)、 187はゲート電極形成工程、 188はポリシリコン (P-Si)層、 189は坦込配線工程、 190は空洞、 191はメタル (金属)、 192は基板上配線 形成工程をそれぞれ示す。  In FIG. 5, 180 is a fin region forming process, 181 is an fm region, 182 is an insulating support substrate, 183 is a groove forming step, 184 is a groove for buried wiring, and 185 is silicon-germanium (SiGe) loaded Process, 186 is silicon, germanium (SiGe), 187 is a gate electrode formation process, 188 is a polysilicon (P-Si) layer, 189 is a loading wiring process, 190 is a cavity, 191 is a metal (metal), 192 is a substrate Each upper wiring formation process is shown.
[0047] そして、図 5のフローチャートは、論理マクロセル又は SRAMマクロセルの製造工程 は fm領域形成工程 180、溝形成工程 183、シリコン.ゲルマニウム（SiGe)埋込工程 185 、ゲート電極形成工程 187、埋込配線工程 189、及び、基板上配線形成工程 192から なることを示す。  [0047] The flowchart of FIG. 5 shows that the manufacturing process of the logic macro cell or SRAM macro cell is the fm region forming process 180, the groove forming process 183, the silicon germanium (SiGe) embedding process 185, the gate electrode forming process 187, and the embedding process. It shows that it consists of a wiring process 189 and a wiring formation process 192 on the substrate.
[0048] fm領域形成工程 180は、絶縁支持基板 182の上に、半導体からなる立体領域である fin領域 181を形成する工程である。なお、上記の半導体は、シリコン (Si)であることが 望ましレ、。また、上記の絶縁支持基板 182は SOI(Silicon on insulator)が望ましぐ絶縁 部分はシリコン酸化膜であることが望ましい。溝形成工程 183は、絶縁支持基板 182に 坦込配線用の溝 184を形成する工程である。 SiGe坦込工程 185は、絶縁支持基板 182 中の埋込配線用の溝 184にシリコン 'ゲルマニウム (SiGe)186を埋め込む工程である。 [0048] The fm region forming step 180 is a three-dimensional region made of a semiconductor on the insulating support substrate 182. This is a process for forming the fin region 181. The above semiconductor is preferably silicon (Si). In addition, the insulating support substrate 182 preferably has a silicon oxide film at an insulating portion desired by SOI (Silicon on insulator). The groove forming step 183 is a step of forming the groove 184 for the carrier wiring on the insulating support substrate 182. The SiGe loading process 185 is a process in which silicon germanium (SiGe) 186 is embedded in the trench 184 for embedded wiring in the insulating support substrate 182.
[0049] ゲート電極形成工程は、例えば、ポリシリコン (P-SD188等の導電性の材料により、 fm 型 FETのゲート電極を形成する工程である。埋込配線工程を行うには、複数の種類 の手順が考えられるが、以下に第 1の手順を示す。まず、ゲート電極の上に絶縁膜を 堆積する。次に、溝に坦め込まれたシリコン 'ゲルマニウムに対して、コンタクト viaを形 成し、メタル (金属) 191を堆積させて、コンタクトをとる。次に、熱処理をして、熱処理に よる、シリコンと金属の置換現象を利用して埋込配線を形成する。なお、シリコンと金 属の置換に使用される金属には、アルミニウム (A1)が望ましい。また、埋込配線工程 の第 2の手順は以下である。まず、シリコン.ゲルマニウム (SiGe)186を坦込配線用の 溝 184から選択的に除去する。次に、埋込配線用の溝 184を空洞 190とし、その後、メ タル (金属) 191を埋め込むことによって行う。なお、上記の金属には、タングステンお) が望ましい。 [0049] The gate electrode forming step is a step of forming the gate electrode of the fm type FET by using, for example, polysilicon (P-SD188 or other conductive material. The first procedure is as follows: First, an insulating film is deposited on the gate electrode, and then a contact via is formed on the silicon 'germanium trapped in the trench. Then, contact is made by depositing metal 191. Next, heat treatment is performed to form a buried wiring by utilizing the substitution phenomenon of silicon and metal by the heat treatment. The metal used for metal replacement is preferably aluminum (A1), and the second step in the embedded wiring process is as follows: First, silicon germanium (SiGe) 186 is used for loading wiring. Selectively remove from groove 184. Next, groove 1 for buried wiring 84 is a cavity 190, and then metal (metal) 191 is embedded, and tungsten is preferred as the above metal.
[0050] 基板上配線形成工程 192は、埋込配線工程 189を第 1の手順で行った場合は、シリ コンと金属の置換に使用したメタル (金属)層をそのまま残し、メタル (金属)層上にレジ ストパターンにより配線パターンを形成し、エッチングにより配線を形成する。一方、 坦込配線工程 189を第 2の手順で行った場合は、基板上配線形成工程 192において 、まず、絶縁層を形成し、埋込配線等に対してコンタクト viaを形成し、その後、メタル（ 金属) 191を堆積した後、レジストパターンにより配線パターンを形成し、エッチングに より配線を形成する。なお、基板上配線は、一の配線層のみで形成されるとは限らな レ、。また、基板上配線に使用される金属には、アルミニウム (Al)、タングステン (W)等が 望ましい。  [0050] When the embedded wiring process 189 is performed in the first procedure, the on-board wiring forming process 192 leaves the metal (metal) layer used for the replacement of the silicon and the metal as it is, and the metal (metal) layer A wiring pattern is formed on the resist pattern, and wiring is formed by etching. On the other hand, when the carrier wiring process 189 is performed by the second procedure, in the on-substrate wiring forming process 192, first, an insulating layer is formed, a contact via is formed with respect to the embedded wiring, etc. (Metal) After depositing 191, a wiring pattern is formed by a resist pattern, and wiring is formed by etching. In addition, the wiring on the substrate is not always formed by only one wiring layer. Moreover, aluminum (Al), tungsten (W), etc. are desirable for the metal used for wiring on the substrate.
[0051] 図 6は、図 6A、図 6B、図 6C、図 6D、図 6E、及び、図 6F力、ら構成されており、 fin型 領域形成工程の詳細な製造工程を示した図である。また、図 6は、図 2Aの A— B間の 断面を示した図である。 図 6において、 195はシリコン酸化膜 (Si02)層、 196はシリコンの単結晶層、 197はシリ コン酸化膜 (Si02)層、 198はポリシリコン (P-Si)層、 199はレジストパターン、 200はポリ シリコンの孤立領域、 201はシリコン酸化膜 (Si02)の層間絶縁膜、 202はシリコン酸化 膜のサイドウォール、 203はシリコン酸化層の孤立領域をそれぞれ示す。 [0051] FIG. 6 is a diagram showing the detailed manufacturing process of the fin-type region forming process, which includes the force shown in FIGS. 6A, 6B, 6C, 6D, 6E, and 6F. . FIG. 6 is a diagram showing a cross section between A and B in FIG. 2A. In FIG. 6, 195 is a silicon oxide film (Si02) layer, 196 is a single crystal layer of silicon, 197 is a silicon oxide film (Si02) layer, 198 is a polysilicon (P-Si) layer, 199 is a resist pattern, 200 Denotes an isolated region of polysilicon, 201 denotes an interlayer insulating film of a silicon oxide film (Si02), 202 denotes a sidewall of the silicon oxide film, and 203 denotes an isolated region of the silicon oxide layer.
[0052] 図 6Aは、シリコン酸化膜層 195及びシリコンの単結晶層 196を含む S〇I基板の上に 、シリコン酸化膜 197及びポリシリコン (P_Si)層 198を、 CVD(chemical vapor deposition) 法により、堆積したところを示した図である。なお、 S〇I基板は、シリコン基板の上にシ リコン酸化層を形成し、さらに、シリコン酸化層上にシリコン基板を張り付けて作成し たものである。従って、シリコンの単結晶層が、シリコン酸化膜を挟んだ構造となって いる。また、 S〇I基板において、回路素子を形成する側のシリコンの単結晶層は、研 磨等により、その反対側のシリコン単結晶側と比較して、薄くなつている。すなわち、 図 6Aには、シリコンの単結晶層の内、回路素子を形成する側のシリコンの単結晶層 196及びシンリコン酸化膜 195が示されている。ここで、 SOI基板中のシリコン酸化膜層 195の厚さは、 70nm以上であって、 lOOnm程度が望ましい。また、シリコンの単結晶層 196の厚さは 30nm程度が望ましレ、。さらに、シリコン酸化膜 197は 10nm程度、ポリシリ コン (P-Si)層 198の厚さは 30nm程度が望ましい。  [0052] FIG. 6A shows that a silicon oxide film 197 and a polysilicon (P_Si) layer 198 are formed on a S0I substrate including a silicon oxide film layer 195 and a silicon single crystal layer 196 by a chemical vapor deposition (CVD) method. FIG. The SOI substrate was prepared by forming a silicon oxide layer on a silicon substrate and then sticking the silicon substrate on the silicon oxide layer. Therefore, a single crystal layer of silicon has a structure in which a silicon oxide film is sandwiched. In addition, in the SOI substrate, the silicon single crystal layer on the circuit element forming side is thinned by polishing or the like compared to the silicon single crystal side on the opposite side. That is, FIG. 6A shows a silicon single crystal layer 196 and a silicon oxide film 195 on the circuit element forming side of the silicon single crystal layer. Here, the thickness of the silicon oxide film layer 195 in the SOI substrate is preferably 70 nm or more, and preferably about lOO nm. The thickness of the silicon single crystal layer 196 is preferably about 30 nm. Further, it is desirable that the silicon oxide film 197 is about 10 nm, and the thickness of the polysilicon (P-Si) layer 198 is about 30 nm.
[0053] 図 6Bは、ポリシリコン (P-Si)層 198の上にレジストを塗布し、ホトリソグラフィー技術に より、レジストパターン 199を作成したところを示した図である。レジストパターン 199の 幅は、 fm型 FETの fm領域の間隔を決めることになるため、 80nmから 150nm程度である ことが望ましい。  FIG. 6B is a diagram showing a resist pattern 199 formed by applying a resist on the polysilicon (P-Si) layer 198 and using a photolithography technique. Since the width of the resist pattern 199 determines the interval between the fm regions of the fm type FET, it is preferably about 80 nm to 150 nm.
[0054] 図 6Cは、レジストパターン 199をエッチングマスクに、ポリシリコン (P_Si)層 198を異方 性のエッチングし、ポリシリコンの孤立領域 200が得られたところである。レジストパタ ーン 199の幅と同様、ポリシリコンの孤立領域 200の幅は、 80nmから 150nm程度である 。また、ポリシリコンの孤立領域 200の高さは 20nmから 30nm程度が望ましい。のちに、 ポリシリコンの孤立領域 200の側壁に作成する、シリコン酸化膜のサイドウォール 202 の幅を 20nmから 30nm程度とするためである。  FIG. 6C shows an isolated region 200 of polysilicon obtained by anisotropically etching the polysilicon (P_Si) layer 198 using the resist pattern 199 as an etching mask. Similar to the width of the resist pattern 199, the width of the polysilicon isolated region 200 is about 80 nm to 150 nm. The height of the isolated region 200 of polysilicon is preferably about 20 nm to 30 nm. This is because the width of the side wall 202 of the silicon oxide film formed on the side wall of the polysilicon isolated region 200 is set to about 20 nm to 30 nm.
[0055] 図 6Dは、ポリシリコンの孤立領域 200及びシリコン酸化膜 197の上にシリコン酸化膜 (Si02)の層間絶縁膜 201を、 CVD法により堆積したところを示した図である。シリコン 酸化膜 (Si02)の層間絶縁膜 201の厚さは、シリコン酸化膜のサイドウォール 202の幅 を 20nmから 30nm程度とするため、 50nmから lOOnm程度とすることが望ましい。 FIG. 6D is a view showing a state where an interlayer insulating film 201 of a silicon oxide film (Si02) is deposited on the polysilicon isolated region 200 and the silicon oxide film 197 by the CVD method. silicon The thickness of the interlayer insulating film 201 of the oxide film (Si02) is preferably about 50 nm to about lOO nm so that the width of the side wall 202 of the silicon oxide film is about 20 nm to 30 nm.
[0056] 図 6Eは、シリコン酸化膜 (Si02)の層間絶縁膜 201を異方性エッチングすることにより 、シリコン酸化膜のサイドウォール 202を作成したところを示した図である。シリコン酸 化膜のサイドウォール 202の幅は、後に、 fin型 FETの fin領域の幅を決定することとな るため、 20nmから 30nm程度とすることが望ましい。  FIG. 6E is a diagram showing that the side wall 202 of the silicon oxide film is formed by anisotropically etching the interlayer insulating film 201 of the silicon oxide film (Si02). The width of the side wall 202 of the silicon oxide film is determined to be about 20 nm to 30 nm because the width of the fin region of the fin-type FET will be determined later.
[0057] 図 6Fは、ポリシリコンの孤立領域 200を等方性のエッチングにより除去し、シリコン酸 化膜のサイドウォール 202をエッチングマスクにシリコン酸化膜 (Si02)層 197を異方性 エッチングにより、シリコン酸化層の孤立領域 203を形成したところを示した図である。 その後、シリコン酸化層の孤立領域 203をエッチングマスクに、シリコンの単結晶層 196を異方性エッチングし、 fin型 FETの fin領域を形成する。  FIG. 6F shows that the isolated region 200 of polysilicon is removed by isotropic etching, and the silicon oxide film (Si02) layer 197 is anisotropically etched using the side wall 202 of the silicon oxide film as an etching mask. It is the figure which showed the place which formed the isolation region 203 of the silicon oxide layer. Thereafter, the silicon single crystal layer 196 is anisotropically etched using the isolated region 203 of the silicon oxide layer as an etching mask to form a fin region of the fin-type FET.
[0058] 図 7は、図 7G、図 7H、図 71、図 7J、図 7K、及び、図 7L力、ら構成されており、埋込 配線用の溝形成工程の詳細を示した図である。また、図 7は、図 2Αの Α— Β間の断面 を示した図である。  FIG. 7 is a diagram showing the details of the step of forming a trench for embedded wiring, which includes the forces of FIGS. 7G, 7H, 71, 7J, 7K, and 7L. . FIG. 7 is a diagram showing a cross-section between Α and Α in FIG.
図 7において、 195はシリコン酸化膜 (Si02)層、 202はシリコン酸化膜のサイドウォー ノレ、 203はシリコン酸化層の孤立領域、 204はシリコンの立体的な孤立領域、すなわち 、 fm型 FETの fm領域、 205はシリコン酸化膜層、 206はシリコン酸化膜のサイドウォー ノレ、 207はレジストパターン、 208は埋込配線用の溝、 209はシリコン 'ゲルマニウム (SiGe)層をそれぞれ示す。  In FIG. 7, 195 is a silicon oxide film (Si02) layer, 202 is a sidewall of the silicon oxide film, 203 is an isolated region of the silicon oxide layer, 204 is a three-dimensional isolated region of silicon, that is, fm of the fm type FET The region, 205 is a silicon oxide film layer, 206 is a sidewall of the silicon oxide film, 207 is a resist pattern, 208 is a trench for buried wiring, and 209 is a silicon germanium (SiGe) layer.
[0059] 図 7Gは、図 6Fの工程を終了した後、シリコン酸化膜のサイドウォール 202、及び、 シリコン酸化層の孤立領域 203をエッチングマスクにシリコンの単結晶層を、異方性ェ ツチングして、 fm領域 204を得たところを示した図である。ここで、図 6Dおいて説明し たように、シリコン酸化膜のサイドウォール 202の幅を 20nmから 30nm程度としたこと力 ら、 fm領域 204の幅もほぼ 20nmから 30nm程度となる。また、シリコン単結晶の厚さが 30nm程度であったことから、 fm領域 204の高さは 30nm程度となる。  [0059] FIG. 7G shows that after the step of FIG. 6F is completed, the silicon single crystal layer is anisotropically etched using the sidewall 202 of the silicon oxide film and the isolated region 203 of the silicon oxide layer as an etching mask. FIG. 6 is a diagram showing a place where the fm region 204 is obtained. Here, as described with reference to FIG. 6D, the width of the side wall 202 of the silicon oxide film is about 20 nm to 30 nm, so that the width of the fm region 204 is also about 20 nm to 30 nm. In addition, since the thickness of the silicon single crystal is about 30 nm, the height of the fm region 204 is about 30 nm.
[0060] 図 7Hは、図 7の工程を終了した後、シリコン酸化膜のサイドウォール 202を等方性 エッチングにより、除去したところを示す図である。  FIG. 7H is a diagram showing a state where the sidewall 202 of the silicon oxide film is removed by isotropic etching after the step of FIG. 7 is completed.
[0061] 図 71は、図 7Hの工程を終了した後、シリコン酸化膜 205を堆積したところを示した 図である。そして、シリコン酸化膜 205の幅は 40nmから 60nm程度であることが望ましい 。後に形成するシリコン酸化膜のサイドウォール 206の幅を 20nmから 30nm程度とする ためである。 FIG. 71 shows that the silicon oxide film 205 was deposited after the process of FIG. 7H was completed. FIG. The width of the silicon oxide film 205 is desirably about 40 nm to 60 nm. This is because the width of the side wall 206 of the silicon oxide film to be formed later is about 20 nm to 30 nm.
[0062] 図 7Jは、図 71の工程を終了した後、シリコン酸化膜 205を異方性エッチングして、シ リコン酸化膜のサイドウォール 206を形成したところを示した図である。また、シリコン 酸化膜のサイドウォール 206を形成した後、レジストを塗布し、ホトリソグラフィー技術 により、レジストパターン 207を形成したところを示した図である。レジストパターン 207 間の間隔、すなわち、レジストパターン 207の開口は、 fin領域 204間の間隔よりは広く 、レジストパターン 207の端は、 fm領域 204の上部に位置する。  FIG. 7J is a diagram showing a state where the silicon oxide film 205 is anisotropically etched to form the silicon oxide film sidewall 206 after the process of FIG. 71 is completed. Further, after forming the side wall 206 of the silicon oxide film, a resist is applied, and a resist pattern 207 is formed by a photolithography technique. The interval between the resist patterns 207, that is, the opening of the resist pattern 207 is wider than the interval between the fin regions 204, and the end of the resist pattern 207 is located above the fm region 204.
[0063] 図 7Kは、図 7Jの工程を終了後において、異方性エッチングを行ない、支持基板の シリコン酸化膜層 195に埋込配線用の溝 208を形成し、レジストパターン 207を除去し たところを示す図である。 fin領域 204間隔は 80nmから 150nm程度であることから、シリ コン酸化膜のサイドウォール 206の幅が 20nmから 30nm程度であることを考慮すると、 坦込配線用の溝 208の幅は 40nmから 90nm程度となる。また、埋込配線用の溝 208は 坦込配線用のメタル (金属)を溝に坦め込むこと考慮して、 50nm以下が望ましい。  In FIG. 7K, after completing the step of FIG. 7J, anisotropic etching was performed to form a trench 208 for embedded wiring in the silicon oxide film layer 195 of the support substrate, and the resist pattern 207 was removed. FIG. Since the spacing between the fin regions 204 is about 80 nm to 150 nm, considering that the width of the sidewall 206 of the silicon oxide film is about 20 nm to 30 nm, the width of the groove 208 for the carrier wiring is about 40 nm to 90 nm. It becomes. Further, the groove 208 for embedded wiring is preferably 50 nm or less in consideration of loading the metal for carrying wiring into the groove.
[0064] 図 7Lは、図 7Kの工程終了後に、坦込配線用の溝 208にシリコン.ゲルマニウム [0064] FIG. 7L shows silicon germanium in the trench 208 for the carrier wiring after the process of FIG. 7K is completed.
(SiGe)を埋め込むため、シリコン ·ゲルマニウム (SiGe)層 209を CVD法により堆積したと ころを示した図である。シリコン 'ゲルマニウム (SiGe)層の厚さは、坦込配線用の溝 208 にシリコン.ゲルマニウム (SiGe)を坦め込むことを目的としているため、 75nmから lOOnm 程度であることが望ましい。なお、後に、埋込配線用の溝 208には、メタル (金属)を埋 め込むことになることから、メタル (金属)の拡散を防止するため、シリコン窒化膜を lnm 力 5nm程度堆積した後に、シリコン 'ゲルマニウム (SiGe)層 209を堆積することが望ま しい。ただし、メタル (金属)を溝に坦め込んだ後に、メタル (金属)の拡散がおこる程、 高い熱処理が加わらない場合には、シリコン窒化膜の堆積を省略することもできる。 なお、シリコン窒化膜は、薄いため、以下、図示はしない。 FIG. 6 is a view showing a state where a silicon-germanium (SiGe) layer 209 is deposited by a CVD method to embed (SiGe). The thickness of the silicon 'germanium (SiGe) layer is preferably about 75 nm to lOOnm because the purpose is to contain silicon germanium (SiGe) in the trench 208 for the carrier wiring. In addition, since the metal 208 is buried in the trench 208 for embedded wiring later, in order to prevent diffusion of the metal, the silicon nitride film is deposited with an lnm force of about 5 nm. It is desirable to deposit a silicon 'germanium (SiGe) layer 209. However, the deposition of the silicon nitride film can be omitted if the metal (metal) is not sufficiently heated so that the metal (metal) diffuses after the metal is placed in the groove. Since the silicon nitride film is thin, it is not shown below.
ところで、埋込材料としてシリコン 'ゲルマニウム (SiGe)を用いたのは、シリコン'ゲノレ マニウム (SiGe)が、等方性エッチングを行う場合に、 fin領域 204又はゲート電極を構成 するシリコン (Si)又はポリシリコン (P-Si)に対して、選択性を有するからである。なお、選 択性が必要なのは、 fm領域 204又はゲート電極は、シリコン酸化 (Si02)膜のサイドゥォ ール 206又はシリコン酸化膜 (Si02)膜層等により覆われている力 シリコン酸化 (Si02) 膜のサイドウォール 206等の形成工程の性質上、確実にシリコン (Si)部分のすべてを 覆っているとは限らないからである。 By the way, silicon 'germanium (SiGe) is used as an embedding material because when silicon' genorenium (SiGe) is isotropically etched, silicon (Si) or silicon constituting the fin region 204 or the gate electrode is used. This is because it has selectivity for polysilicon (P-Si). The selection The fm region 204 or the gate electrode must be covered with the silicon oxide (Si02) film side 206 or the silicon oxide film (Si02) film layer, etc.The side wall of the silicon oxide (Si02) film This is because, due to the nature of the formation process such as 206, it does not necessarily cover all of the silicon (Si) part.
[0065] 図 8は、図 8M、図 8N、図 80、図 8P、図 8Q、及び、図 8Rから構成されており、坦 込配線用の溝形成工程の詳細を示した図である。また、図 8は、図 2Aの A— B間の断 面を示した図である。 FIG. 8 includes FIG. 8M, FIG. 8N, FIG. 80, FIG. 8P, FIG. 8Q, and FIG. 8R, and is a diagram showing details of the groove formation process for the embedded wiring. FIG. 8 is a diagram showing a cross section between A and B in FIG. 2A.
図 8において、 195はシリコン酸化膜 (Si02)層、 203はシリコン酸化層の孤立領域、 204はシリコンの立体的な孤立領域、すなわち、 fm型 FETの fm領域、 206はシリコン酸 化膜のサイドウォール、 209はシリコン 'ゲルマニウム (SiGe)層、 210はポリシリコン (P-Si)層、 211はシリコン酸化膜、 212はレジストパターン、 213は fin型 FETのゲート電 極をそれぞれ示す。  In FIG. 8, 195 is a silicon oxide film (Si02) layer, 203 is an isolated region of the silicon oxide layer, 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET, and 206 is a side of the silicon oxide film. Wall 209 is a silicon germanium (SiGe) layer, 210 is a polysilicon (P-Si) layer, 211 is a silicon oxide film, 212 is a resist pattern, and 213 is a gate electrode of a fin-type FET.
[0066] 図 8Mは、図 7Lのシリコン.ゲルマニウム (SiGe)層 209を、 fm領域の上部のところで、 平坦化したところを示した図である。ここで、シリコン 'ゲルマニウム (SiGe)層 209の平 坦化を行うには、例えば、 CMP(chemical mechanical polishing)プロセス、すなわち、 化学的、及び、機械的研磨工程を行うことにより達成することができる。  [0066] FIG. 8M is a diagram showing the silicon germanium (SiGe) layer 209 of FIG. 7L flattened at the upper part of the fm region. Here, the planarization of the silicon 'germanium (SiGe) layer 209 can be achieved, for example, by performing a chemical mechanical polishing (CMP) process, that is, a chemical and mechanical polishing process. .
[0067] 図 8Nは、図 8Mの工程を終了した後、等方的なエッチングを、シリコン 'ゲルマニウ ム (SiGe)層 209に対して行ったところを示した図である。等方性のエッチングを一定時 間行うことにより、埋込配線用の溝以外の部分のシリコン 'ゲルマニウム (SiGe)層 209を 除去することができる。なお、図 7Lの工程で、拡散防止膜として、シリコン窒化膜を堆 積させた場合には、シリコン 'ゲルマニウム (SiGe)層 209の除去後に、等方性のエッチ ングにて、坦込配線用の溝以外のシリコン窒化膜を除去する。  FIG. 8N is a diagram showing that isotropic etching is performed on the silicon / germanium (SiGe) layer 209 after the process of FIG. 8M is completed. By performing isotropic etching for a certain period of time, the silicon / germanium (SiGe) layer 209 other than the trench for the buried wiring can be removed. When a silicon nitride film is deposited as a diffusion prevention film in the process of FIG. 7L, the silicon 'germanium (SiGe) layer 209 is removed and isotropic etching is performed for the buried wiring. The silicon nitride film other than the trench is removed.
図 80は、図 8Mの工程を終了した後、シリコン酸化膜のサイドウォール 206、シリコ ン酸化層の孤立領域 203を除去したところを示した図である。等方性のエッチングを、 シリコン酸化膜に対して行うことにより、シリコン酸化膜を除去することができる。  FIG. 80 is a view showing a state where the sidewall 206 of the silicon oxide film and the isolated region 203 of the silicon oxide layer are removed after the process of FIG. 8M is completed. By performing isotropic etching on the silicon oxide film, the silicon oxide film can be removed.
図 8Pは、図 8〇の工程終了後、ポリシリコン (P-Si)層 210及びシリコン酸化膜 211を堆 積した図である。ポリシリコン (P-Si)層 210及びシリコン酸化膜 211の堆積には、例えば 、 CVD法を用いることができる。なお、ポリシリコン (P-Si)層 210と埋込配線用の溝内の シリコン 'ゲルマニウム (SiGe)とはコンタクト viaを介さず、直接接触している。ここで、ポ リシリコン (P-Si)層 210の厚さは 30nmから 50nm程度が望ましレ、。また、シリコン酸化膜 211はエッチングストッパーとしての役目を果たすため、 10nm程度が望ましい。 FIG. 8P is a diagram in which a polysilicon (P-Si) layer 210 and a silicon oxide film 211 are deposited after the process of FIG. For the deposition of the polysilicon (P-Si) layer 210 and the silicon oxide film 211, for example, a CVD method can be used. Note that the polysilicon (P-Si) layer 210 and the buried wiring trench Silicon 'Germanium (SiGe) is in direct contact with no contact via. Here, the thickness of the polysilicon (P-Si) layer 210 is preferably about 30 nm to 50 nm. Further, since the silicon oxide film 211 serves as an etching stopper, it is preferably about 10 nm.
[0068] 図 8Qは、図 8Pの工程を終了した後、レジストを塗布し、ホトリソグラフィー技術によ り、レジストパターン 212を形成したところを示した図である。  FIG. 8Q is a diagram showing a state where a resist is applied after the process of FIG. 8P is completed, and a resist pattern 212 is formed by a photolithography technique.
図 8Rは、レジストパターン 212をエッチングマスクに異方性のエッチングにより、シリ コン酸化膜 211及びポリシリコン (P_Si)層 210をエッチングし、 fm型 FETのゲート電極 213を形成したところを示した図である。  FIG. 8R is a diagram showing the fm FET gate electrode 213 formed by etching the silicon oxide film 211 and the polysilicon (P_Si) layer 210 by anisotropic etching using the resist pattern 212 as an etching mask. It is.
[0069] 図 9は、図 9R、図 9S、図 9T、図 9U、図 9V、及び、図 9Wから構成されており、埋 込配線工程及び基板上配線形成工程 (その 1)の詳細を示した図である。また、図 9 は、図 2Aの A— B間の断面を示した図である。なお、基板上配線形成工程 (その 1) は、図 5のフローチャートの説明では、第 1の手順として説明した工程の詳細説明で ある。  [0069] FIG. 9 includes FIG. 9R, FIG. 9S, FIG. 9T, FIG. 9U, FIG. 9V, and FIG. 9W, and shows details of the embedded wiring process and the on-board wiring formation process (part 1). It is a figure. FIG. 9 is a view showing a cross section between A and B in FIG. 2A. The on-substrate wiring formation step (part 1) is a detailed description of the step described as the first procedure in the description of the flowchart of FIG.
図 9において、 195はシリコン酸化膜 (Si02)層、 204はシリコンの立体的な孤立領域、 すなわち、 fin型 FETの fin領域、 209はシリコン 'ゲルマニウム (SiGe)層、 213は fin型 FET のゲート電極、 214はシリコン酸化膜の層間絶縁膜、 215はコンタクト via、 216はアルミ ニゥ (AL)層、 217はシリコン ·ゲルマニウム (SiGe)層を置換した後の置換アルミニウム (AL)をそれぞれ示す。  In FIG. 9, 195 is a silicon oxide film (Si02) layer, 204 is a three-dimensional isolated region of silicon, that is, fin region of fin type FET, 209 is a silicon 'germanium (SiGe) layer, and 213 is a gate of fin type FET. Reference numeral 214 denotes an interlayer insulating film made of a silicon oxide film, 215 denotes a contact via, 216 denotes an aluminum (AL) layer, and 217 denotes substituted aluminum (AL) after the silicon-germanium (SiGe) layer is replaced.
[0070] 図 9Rは、図 8Rと同様な図である。  FIG. 9R is a diagram similar to FIG. 8R.
図 9Sは、図 9Rの工程を終了した後、シリコン酸化膜の層間絶縁膜 214を CVD法に より堆積したところを示した図である。シリコン酸化膜の層間絶縁膜 214の厚さは、 lOOnmから 200nm程度が望ましい。シリコン酸化膜の層間絶縁膜 214の平坦化を行う 場合に、 fin型 FETのゲート電極 213を含むような、充分な厚さが必要だからである。  FIG. 9S is a diagram showing a state where the silicon oxide interlayer insulating film 214 is deposited by the CVD method after the process of FIG. 9R is completed. The thickness of the interlayer insulating film 214 of silicon oxide film is preferably about lOOnm to 200nm. This is because a sufficient thickness is required to include the fin-type FET gate electrode 213 when the silicon oxide interlayer insulating film 214 is planarized.
[0071] 図 9Tは、図 9Sの工程を終了した後、 CMP法により、研磨を行って、シリコン酸化膜 の層間絶縁膜 214の平坦ィ匕したところを示した図である。ここで、シリコン酸化膜の層 間絶縁膜 214の厚さは、シリコン酸化膜 (Si02)層 195の表面から、 80nmから lOOnm程 度が望ましレ、。 fm型 FETの fm領域 204の高さ力 20nmから 30nm程度、 fin型 FETのゲ ート電極の厚さが、 20nmから 30nm程度であることを考慮すると、 fin型 FET全体を含む 必要があるためである。なお、基板上配線層が複数配線層であった場合に、それら の配線層間の層間絶縁膜の厚さが 30nmから 50醒程度であることを考慮すると、シリ コン酸化膜の層間絶縁膜 214の厚さは、基板上配線層間の層間絶縁膜の厚さより厚 レ、。 FIG. 9T is a diagram showing a state where the interlayer insulating film 214 of the silicon oxide film has been flattened by polishing using the CMP method after completing the step of FIG. 9S. Here, the thickness of the interlayer insulating film 214 of the silicon oxide film is preferably about 80 nm to lOOnm from the surface of the silicon oxide film (Si02) layer 195. Considering that the height force of the fm region 204 of the fm type FET is about 20 nm to 30 nm and the thickness of the gate electrode of the fin type FET is about 20 nm to 30 nm, the entire fin type FET is included. This is necessary. In addition, when there are multiple wiring layers on the substrate, considering that the thickness of the interlayer insulating film between these wiring layers is about 30 nm to 50 nm, the silicon oxide interlayer insulating film 214 The thickness is greater than the thickness of the interlayer insulation film between the wiring layers on the substrate.
[0072] 図 9Uは、図 9Tの工程を終了した後、シリコン酸化膜の層間絶縁膜 214にコンタクト via215を形成したところを示した図である。コンタクト via215は以下のような手順により 形成する。まず、シリコン酸化膜の層間絶縁膜 214の上面にレジストを塗布する。次に 、ホトリソグラフィー技術により、コンタクト via215用の開口パターンを形成する。次に、 レジストパターンをマスクに、異方性エッチングにより、シリコン酸化膜をエッチングし て、シリコン.ゲルマニウム (SiGe)層 209までの貫通孔を形成し、コンタクト via215とする 。なお、図 9Tにおいて、コンタクト via215を点線であらわしたのは、実際には、コンタク ト via215は、図 2Aの A— B断面には、あらわれてこないからである。そして、コンタクト via215は図 2Aにおいて、埋込配線 21と入力端子 18を接続するコンタクト vai24を表し たものである。従って、コンタクト via215は fm型 FETのゲート電極の裏に隠れることとな るため、コンタクト via215を点線であらわしたのである。  FIG. 9U is a diagram showing a contact via 215 formed in the interlayer insulating film 214 of the silicon oxide film after the process of FIG. 9T is completed. The contact via 215 is formed by the following procedure. First, a resist is applied on the upper surface of the interlayer insulating film 214 of the silicon oxide film. Next, an opening pattern for the contact via 215 is formed by photolithography. Next, using the resist pattern as a mask, the silicon oxide film is etched by anisotropic etching to form a through hole up to the silicon germanium (SiGe) layer 209, which is used as a contact via 215. In FIG. 9T, the reason why the contact via 215 is represented by a dotted line is that the contact via 215 does not actually appear in the A-B cross section of FIG. 2A. A contact via 215 represents a contact vai24 that connects the embedded wiring 21 and the input terminal 18 in FIG. 2A. Therefore, since the contact via 215 is hidden behind the gate electrode of the fm type FET, the contact via 215 is represented by a dotted line.
[0073] 図 9Vは、図 9Uの工程を終了した後、アルミニウム (AL)層 216を CVD法、或いは、ス パッタ法により堆積させたところを示した図である。アルミニウム (AL)層 216の厚さは、 lOOnmから 500nm程度が望ましい。基板上配線の配線抵抗を確保するためである。な お、この後、アルミニウム (AL)層 216のアルミニウム (AL)と坦込配線用の溝に埋め込ま れているシリコン 'ゲルマニウム (SiGe)209を置換する工程を行うには、アルミニウム (AL)層 216とシリコン ·ゲルマニウム (SiGe)209の接続点において、絶縁層を取り除く必 要がある。なぜなら、絶縁層が挟まれていては置換現象が起きないからである。そこ で、アルミニウム (AL)層 216を堆積させるためには、前処理、例えば、絶縁層を取り除 く等方性のエッチングを行うことが通常である。  FIG. 9V is a diagram showing a state where the aluminum (AL) layer 216 is deposited by the CVD method or the sputtering method after the process of FIG. 9U is completed. The thickness of the aluminum (AL) layer 216 is preferably about lOOnm to 500nm. This is to ensure the wiring resistance of the wiring on the substrate. The aluminum (AL) layer 216 is then replaced with silicon (germanium) (SiGe) 209 embedded in the groove for receiving wiring. It is necessary to remove the insulating layer at the connection point between 216 and silicon-germanium (SiGe) 209. This is because the substitution phenomenon does not occur when the insulating layer is sandwiched. Therefore, in order to deposit the aluminum (AL) layer 216, it is usual to perform pretreatment, for example, isotropic etching to remove the insulating layer.
[0074] 図 9Wは、図 9Wの工程を終了した後、アルミニウム (AL)層 216中のアルミニウム (AL) と坦込配線用の溝中のシリコン 'ゲルマニウム (SiGe)との置換を行レ、、坦込配線用の 溝にアルミニウム (AL)を埋め込み、埋込配線を形成したところを示した図である。アル ミニゥム (AL)層 216中のアルミニウム (AL)と坦込配線用の溝中のシリコン.ゲルマニウ ム (SiGe)との置換現象を起こさせるには、熱処理を加えることにより達成できる。ここで 、その熱処理は 450°Cで 60分間程度であることが望ましレ、。 [0074] FIG. 9W, after finishing the process of FIG. 9W, replaces aluminum (AL) in the aluminum (AL) layer 216 with silicon 'germanium (SiGe) in the trench for the loading wiring. FIG. 5 is a view showing a state where buried wiring is formed by embedding aluminum (AL) in a groove for a buried wiring. Aluminum (AL) in Alminum (AL) layer 216 and silicon in the groove for loading wiring. In order to cause a substitution phenomenon with SiGe (SiGe), it can be achieved by applying heat treatment. Here, the heat treatment should be at 450 ° C for about 60 minutes.
[0075] 次に、図 10と図 11を用いて、埋込配線工程及び基板上配線形成工程 (その 2)の詳 細を示す。なお、基板上配線形成工程 (その 2)は、図 5のフローチャートの説明では 、第 2の手順として説明した工程の詳細説明である。  Next, details of the embedded wiring process and the on-substrate wiring forming process (part 2) will be described with reference to FIGS. 10 and 11. FIG. The on-substrate wiring forming step (part 2) is a detailed description of the step described as the second procedure in the description of the flowchart of FIG.
図 10は、図 10R、図 10SS、図 10TT、図 10UU、図 10VV、及び、図 10胃から構成さ れている図である。また、図 10は、図 2Aの A— B間の断面を示した図である。  FIG. 10 is a diagram composed of FIG. 10R, FIG. 10SS, FIG. 10TT, FIG. 10UU, FIG. 10VV, and FIG. FIG. 10 is a view showing a cross section between A and B in FIG. 2A.
図 10において、 195はシリコン酸化膜 (Si02)層、 204はシリコンの立体的な孤立領域 、すなわち、 fm型 FETの fm領域、 209はシリコン 'ゲルマニウム (SiGe)層、 213は fin型 FETのゲート電極、 218は空洞状態、 219はタングステン (W)層、 220はレジストパター ン、 221はシリコン酸化膜層をそれぞれ示す。  In FIG. 10, 195 is a silicon oxide (Si02) layer, 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET, 209 is a silicon 'germanium (SiGe) layer, and 213 is a gate of a fin type FET. Electrode, 218 is a hollow state, 219 is a tungsten (W) layer, 220 is a resist pattern, and 221 is a silicon oxide film layer.
[0076] 図 10Rは、図 8R及び図 9Rと同様な図であり、坦込配線工程及び基板上配線形成 工程 (その 1)と埋込配線工程及び基板上配線形成工程 (その 2)の枝分かれが、図 10Rの工程を終了した後からであることを示す。  FIG. 10R is a diagram similar to FIG. 8R and FIG. 9R, and branches between the loading wiring process and the on-board wiring formation process (part 1) and the embedded wiring process and the on-board wiring formation process (part 2). Indicates that it is after the process of FIG. 10R is completed.
図 10SSは、等方性のエッチングを行うことにより、坦込配線用の溝に坦め込まれて レ、るシリコン.ゲルマニウム (SiGe)層 209を取り除いたところを示した図である。  FIG. 10SS shows a state where the silicon-germanium (SiGe) layer 209 is removed by being etched into the trench for the carrier wiring by performing isotropic etching.
図 10TTは、タングステン (W)層を CVD法により、堆積させた後、レジストを塗布し、ホ トリソグラフィー技術により、坦込配線領域を覆うレジストパターン 220を形成したところ を示す図である。タングステン (W)層 219の厚さは、 lOOnmから 500nm程度が望ましレ、。 充分に、埋込配線用の溝にタングステン (W)を坦め込むためである。  FIG. 10TT is a diagram showing a state in which a tungsten (W) layer is deposited by the CVD method, a resist is applied, and a resist pattern 220 covering the buried wiring region is formed by a photolithography technique. The thickness of the tungsten (W) layer 219 is preferably about lOOnm to about 500nm. This is because tungsten (W) is sufficiently loaded in the trench for the embedded wiring.
[0077] 図 10UUは、レジストパターン 220をエッチングマスクに、タングステン (W)層に対して 異方性エッチングを行レ、、レジストパターン 220を除去したところを示した図である。そ して、図 10UUの工程が必要な理由は以下である。まず、広い範囲にタングステン (W) 層が存在する場合、等方性エッチングを行うことにより、タングステン (W)を坦込配線 用の溝に残すように、等方性エッチングを制御することは容易ではなレ、。そこで、図 10UUの工程を行なレ、、タングステン (W)が坦込配線用の溝の周辺にのみ残るように すると、その後の等方性エッチングの制御が容易となるからである。  FIG. 10UU is a diagram showing a state in which the resist pattern 220 is removed by performing anisotropic etching on the tungsten (W) layer using the resist pattern 220 as an etching mask. The reason why the process shown in Fig. 10UU is necessary is as follows. First, when there is a tungsten (W) layer in a wide area, it is easy to control the isotropic etching so that tungsten (W) remains in the trench for the buried wiring by performing isotropic etching. Well then ... Therefore, if the process of FIG. 10UU is performed so that tungsten (W) remains only in the periphery of the trench for the carrier wiring, control of the subsequent isotropic etching becomes easy.
[0078] 図 10VVは、図 10UUの工程を終了後に、等方性のエッチングを行うことにより、タン ダステン (W)層 219のタングステン (W)を坦込配線用の溝内のみに残したところを示し た図である。その結果、坦込配線が形成される。 [0078] FIG. 10VV shows that tanning is performed by performing isotropic etching after the process of FIG. FIG. 6 is a view showing a state where tungsten (W) of the dusten (W) layer 219 is left only in the groove for the loading wiring. As a result, a carrier wiring is formed.
図 10WWは、図 10Wの工程を終了後に、シリコン酸化膜層 221を CVD法により堆積 させたところを示す図である。シリコン酸化膜層 221の厚さは、その後に、平坦化を行 うことを考慮すると lOOnmから 200nmが望ましレ、。 fm型 FETの fm領域 204、及び、 fm型 FETのゲート電極を含むようにする必要があるからである。なお、この工程の後に、タ ングステン (W)の拡散が予想されるような熱処理が加わる場合は、シリコン酸化膜層 221の堆積前に、拡散防止膜としてシリコン窒化膜を堆積させることが望ましい。また 、拡散防止膜用のシリコン窒化膜の厚さは、 5匪から 10匪程度が望ましい。ただし、 拡散防止膜用のシリコン窒化膜は薄い膜であるため、図 10WWには図示していない  FIG. 10WW is a diagram showing a silicon oxide film layer 221 deposited by the CVD method after the process of FIG. 10W is completed. The thickness of the silicon oxide layer 221 is preferably from lOOnm to 200nm in consideration of planarization after that. This is because it is necessary to include the fm region 204 of the fm type FET and the gate electrode of the fm type FET. If a heat treatment that is expected to diffuse tungsten (W) is applied after this step, it is desirable to deposit a silicon nitride film as a diffusion preventive film before the silicon oxide film layer 221 is deposited. In addition, the thickness of the silicon nitride film for the diffusion prevention film is preferably about 5 to 10 mm. However, the silicon nitride film for the diffusion barrier film is a thin film and is not shown in Figure 10WW.
[0079] 図 11は、図 11XX、図 11YY、及び、図 11ZZから構成されている図である。また、図 11 は、図 2Αの Α— Β間の断面を示した図である。 FIG. 11 is a diagram configured from FIG. 11XX, FIG. 11YY, and FIG. 11ZZ. FIG. 11 is a diagram showing a cross-section between Α and Α in FIG.
図 11において、 195はシリコン酸化膜 (Si02)層、 204はシリコンの立体的な孤立領域 、すなわち、 fm型 FETの fm領域、 209はシリコン 'ゲルマニウム (SiGe)層、 213は fin型 FETのゲート電極、 219はタングステン (W)層、 221はシリコン酸化膜層、 222はコンタク ト via、 223はタングステン (W)層をそれぞれ示す。  In FIG. 11, 195 is a silicon oxide (Si02) layer, 204 is a three-dimensional isolated region of silicon, that is, an fm region of an fm type FET, 209 is a silicon 'germanium (SiGe) layer, and 213 is a gate of a fin type FET. Electrode, 219 is a tungsten (W) layer, 221 is a silicon oxide film layer, 222 is a contact via, and 223 is a tungsten (W) layer.
図 11XXは、図 10WWの工程を終了後、シリコン酸化膜層 221を CMP法により、化学 的、機械的な研磨をおこなって平坦ィ匕したところを示す図である。ここで、シリコン酸 化膜の層間絶縁膜 221の厚さは、シリコン酸化膜 (Si02)層 195の表面から、 80nmから lOOnm程度が望ましい。 fm型 FETの fm領域 204の高さ力 20nmから 30nm程度、 fin型 FETのゲート電極の厚さ力 S、 20nmから 30nm程度であることを考慮すると、 fin型 FET全 体を含む必要があるためである。なお、基板上配線層が複数配線層であった場合に 、それらの配線層間の層間絶縁膜の厚さが 30nmから 50nm程度であることを考慮する と、シリコン酸化膜の層間絶縁膜 214の厚さは、基板上配線層間の層間絶縁膜の厚 さより厚い。  FIG. 11XX is a diagram showing a state where the silicon oxide film layer 221 is flattened by chemical and mechanical polishing by the CMP method after the process of FIG. 10WW is completed. Here, the thickness of the interlayer insulating film 221 of the silicon oxide film is desirably about 80 nm to lOO nm from the surface of the silicon oxide film (Si02) layer 195. Considering that the height force of the fm region 204 of the fm type FET is about 20 nm to 30 nm, the thickness force S of the gate electrode of the fin type FET, and about 20 nm to 30 nm, it is necessary to include the entire fin type FET It is. When the wiring layer on the substrate is a plurality of wiring layers, considering that the thickness of the interlayer insulating film between these wiring layers is about 30 nm to 50 nm, the thickness of the interlayer insulating film 214 of the silicon oxide film The thickness is larger than the thickness of the interlayer insulating film between the wiring layers on the substrate.
[0080] 図 11YYは、図 11XXの工程を終了した後、シリコン酸化膜の層間絶縁膜 221にコン タクト via222を形成したところを示した図である。コンタクト via222は以下のような手順 により形成する。まず、シリコン酸化膜の層間絶縁膜 221の上面にレジストを塗布する 。次に、ホトリソグラフィー技術により、コンタクト via222用の開口パターンを形成する。 次に、レジストパターンをマスクに、異方性エッチングにより、シリコン酸化膜をエッチ ングして、タングステン (W)層 209までの貫通孔を形成し、コンタクト via222とする。なお 、図 11YYにおいて、コンタクト via222を点線であらわしたのは、実際には、コンタクト via222は、図 2Aの A— B断面には、あらわれてこないからである。そして、コンタクト via222は図 2Aにおいて、埋込配線 21と入力端子 18を接続するコンタクト vai24を表し たものである。従って、コンタクト via222は fm型 FETのゲート電極の裏に隠れることとな るため、コンタクト via222を点線であらわしたのである。 FIG. 11YY is a diagram showing a contact via 222 formed in the interlayer insulating film 221 of the silicon oxide film after the process of FIG. 11XX is completed. Contact via222 is as follows To form. First, a resist is applied on the upper surface of the interlayer insulating film 221 of the silicon oxide film. Next, an opening pattern for the contact via 222 is formed by photolithography. Next, using the resist pattern as a mask, the silicon oxide film is etched by anisotropic etching to form a through hole up to the tungsten (W) layer 209 to be a contact via 222. In FIG. 11YY, the contact via 222 is represented by a dotted line because the contact via 222 does not actually appear in the A-B cross section of FIG. 2A. A contact via 222 represents a contact vai24 that connects the embedded wiring 21 and the input terminal 18 in FIG. 2A. Therefore, the contact via 222 is hidden behind the gate electrode of the fm type FET, and the contact via 222 is represented by a dotted line.
[0081] 図 11ZZは、図 11YYの工程を終了した後、タングステン (W)層 223を CVD法、或いは 、スパッタ法により堆積させたところを示した図である。タングステン (W)層 223の厚さは 、 lOOnmから 500nm程度が望ましい。基板上配線の配線抵抗を確保するためである。 産業上の利用可能性 FIG. 11ZZ is a view showing a state where the tungsten (W) layer 223 is deposited by the CVD method or the sputtering method after the process of FIG. 11YY is completed. The thickness of the tungsten (W) layer 223 is preferably about lOOnm to 500nm. This is to ensure the wiring resistance of the wiring on the substrate. Industrial applicability
[0082] 本発明は、高集積 LSIに好適な、支持基板上に形成された Fin型 FETを構成素子とし て有する半導体集積回路装置及びその製造方法を提供する。 The present invention provides a semiconductor integrated circuit device having a Fin-type FET formed on a support substrate as a constituent element, suitable for highly integrated LSIs, and a method for manufacturing the same.
符号の説明  Explanation of symbols
[0083] 1 プロセッサ [0083] 1 processor
2 チップ  2 chips
3 ロジック回路  3 Logic circuit
4 fm型 FET  4 fm type FET
5、 15、 25、 40、 57a, 70 正電源に接続する基板上配線  5, 15, 25, 40, 57a, 70 Wiring on board to connect to positive power supply
6、 16、 26、 33、 41、 48、 57b、 63、 71、 78 Pチャネル fin型 FET  6, 16, 26, 33, 41, 48, 57b, 63, 71, 78 P-channel fin type FET
7、 17、 27、 34、 42、 49、 57c、 64、 72、 79 Nチャネル fin型 FET  7, 17, 27, 34, 42, 49, 57c, 64, 72, 79 N-channel fin type FET
8、 18 入力端子に接続する基板上配線  8, 18 Wiring on board connected to input terminal
9、 19、 29、 44、 59、 74 出力端子に接続する基板上配線  9, 19, 29, 44, 59, 74 On-board wiring connected to output terminals
10、 20、 30、 45、 60、 75 接地電源に接続する基板上配線  10, 20, 30, 45, 60, 75 Wiring on board to connect to ground power supply
11、 21、 31、 35、 46、 50、 61、 65、 76、 80 坦込配線  11, 21, 31, 35, 46, 50, 61, 65, 76, 80
13、 23、 39、 54、 69、 83 コンタクト Via 、 55、 82 配線接続領域 13, 23, 39, 54, 69, 83 Contact Via , 55, 82 Wiring connection area
、 43、 58、 73 入力端子 1に接続する基板上配線 、 56、 66、 81 入力端子 2に接続する基板上配線 、 53、 67、 77 基板上配線 , 43, 58, 73 On-board wiring connected to input terminal 1, 56, 66, 81 On-board wiring connected to input terminal 2, 53, 67, 77 On-board wiring
、 86 インバーター , 86 inverter
入力端子  Input terminal
出力端子  Output terminal
、 105、 120 正電源に接続する基板上配線 、 93、 106、 107、 121、 122 Pチャネル fin型 FET 、 94、 108、 109、 123、 124 Nチャネル fin型 FET 、 96、 115、 116、 117、 118、 130、 131 埋込配線 、 110、 125 接地電源に接続する基板上配線 、 112、 127 入力端子に接続する基板上配線 、 111、 126 出力端子に接続する基板上配線0、 113、 128 コンタクト Via, 105, 120 On-board wiring connected to positive power supply, 93, 106, 107, 121, 122 P-channel fin type FET, 94, 108, 109, 123, 124 N-channel fin type FET, 96, 115, 116, 117 118, 130, 131 Embedded wiring 110, 125 On-board wiring connected to ground power supply 112, 127 On-board wiring connected to input terminal 111, 126 On-board wiring connected to output terminal 0, 113, 128 Contact Via
4、 129 配線接続領域4, 129 Wiring connection area
0、 131 インバーター0, 131 inverter
2 入力端子2 Input terminal
3 出力端子3 Output terminal
5、 160 正電源に接続する基板上配線5, 160 Wiring on board connected to positive power supply
6、 137、 161、 162 Pチャネル fm型 FET6, 137, 161, 162 P-channel fm type FET
8、 139、 163、 164、 165、 166 Nチャネル fm型 FET0、 167 接地電源に接続する基板上配線8, 139, 163, 164, 165, 166 N-channel fm type FET0, 167 On-board wiring connected to ground power supply
1、 168 出力端子に接続する基板上配線1, 168 Wiring on board connected to output terminal
2、 169 入力端子に接続する基板上配線2, 169 On-board wiring connected to input terminal
3、 174 コンタクト Via3, 174 contacts Via
4、 176 配線接続領域4, 176 Wiring connection area
5、 146、 147、 148、 172、 173 坦込配線 149、 175 シェアードコンタクト 5, 146, 147, 148, 172, 173 149, 175 Shared contact
152、 153 は信号線  152 and 153 are signal lines
154、 155 インノくーター  154, 155 Inno Coutor
156、 157 転送ゲートトランジスタ  156, 157 Transfer gate transistor
158 入力端子  158 input terminal
159 出力端子  159 Output terminal
170、 171 基板上配線  170, 171 On-board wiring
177、 178 信号線に接続する基板上配線 177, 178 On-board wiring connected to signal line
180 fin領域形成工程 180 fin region formation process
181 fin領域  181 fin region
182 絶縁支持基板  182 Insulation support substrate
183 溝形成工程  183 Groove formation process
184 坦込配線用の溝  184 Groove for loading wiring
185 シリコン 'ゲルマニウム (SiGe)坦込工程 185 Silicon 'Germanium (SiGe) loading process
186 シリコン'ゲルマニウム (SiGe)186 Silicon 'Germanium (SiGe)
187 ゲート電極形成工程 187 Gate electrode formation process
188 ポリシリコン (P-Si)  188 Polysilicon (P-Si)
189 坦込配線工程  189 Loading wiring process
190 空洞  190 cavity
191 メタル (金属）  191 Metal
192 基板上配線形成工程  192 On-board wiring formation process
195 シリコン酸化膜 (Si02)層  195 Silicon oxide (Si02) layer
196 シリコンの単結晶層  196 Single crystal layer of silicon
197 シリコン酸化膜 (Si02)層  197 Silicon oxide (Si02) layer
198 ポリシリコン (P-Si)層  198 Polysilicon (P-Si) layer
199 レジストパターン  199 resist pattern
200 ポリシリコンの孤立領域  200 Polysilicon isolated region
201 シリコン酸化膜 (Si〇2)の層間絶縁膜 202 シリコン酸化膜のサイドウォール 201 Interlayer insulation film of silicon oxide film (Si02) 202 Silicon oxide sidewall
203 シリコン酸化層の孤立領域  203 Isolated region of silicon oxide layer
204 fin型 FETの fm領域 (シリコンの立体孤立領域) 204 fin type fm region (three-dimensional isolated region of silicon)
205 シリコン酸化層 205 Silicon oxide layer
206 シリコン酸化膜のサイドウォール  206 Side wall of silicon oxide film
207 レジストパターン  207 resist pattern
208 坦込配線用の溝  208 Groove for lead-in wiring
209 シリコン 'ゲルマニウム (SiGe)層  209 Silicon 'Germanium (SiGe) layer
208 坦込配線用の溝  208 Groove for lead-in wiring
209 シリコン 'ゲルマニウム (SiGe)層  209 Silicon 'Germanium (SiGe) layer
210 ポリシリコン (P- Si)層  210 Polysilicon (P-Si) layer
211 シリコン酸化膜  211 Silicon oxide film
212 レジストパターン  212 resist pattern
213 fin型 FETのゲート電極  213 fin FET gate electrode
214 シリコン酸化膜の層間絶縁膜  214 Interlayer insulation film of silicon oxide film
215 コンタクト Via  215 Contact Via
216 アルミニウム (AL)  216 Aluminum (AL)
218 空洞状態  218 Hollow state
219 タングステン (W)  219 Tungsten (W)
220 レジストパターン  220 resist pattern
221 シリコン酸化膜層  221 Silicon oxide layer
222 コンタクト Via  222 Contact Via
223 タングステン (W)層  223 Tungsten (W) layer

Claims

請求の範囲 The scope of the claims
[1] 支持基板上に形成されたシリコンの立体孤立領域と前記シリコンの立体孤立領域 の表面に形成されたゲート電極とを有する MOSトランジスタ素子と、  [1] A MOS transistor element having a three-dimensionally isolated region of silicon formed on a support substrate and a gate electrode formed on the surface of the three-dimensionally isolated region of silicon.
前記支持基板中の溝に坦め込まれた坦込配線と、  A carrier wiring carried in a groove in the support substrate;
前記支持基板上の基板上配線とを備え、  A wiring on a substrate on the support substrate;
前記坦込配線と前記基板上配線とを用いて前記 MOSトランジスタ素子間の接続が行 われることを特徴とする半導体回路装置。  The semiconductor circuit device is characterized in that the connection between the MOS transistor elements is performed using the carrier wiring and the wiring on the substrate.
[2] 前記シリコンの立体孤立領域と前記坦込配線が自己整合的に形成されていること を特徴とする請求項 1に記載した半導体回路装置。 [2] The semiconductor circuit device according to [1], wherein the three-dimensional isolated region of silicon and the embedded wiring are formed in a self-aligning manner.
[3] 前記坦込配線は前記 MOSトランジスタ素子のゲート電極を接続してレ、ることを特徴 とする請求項 1に記載した半導体回路装置。 3. The semiconductor circuit device according to claim 1, wherein the carrier wiring is connected to a gate electrode of the MOS transistor element.
[4] 前記坦込配線は、アルミニウムを含む材料からなることを特徴とする請求項 1に記 載した半導体回路装置。 4. The semiconductor circuit device according to claim 1, wherein the carrier wiring is made of a material containing aluminum.
[5] 前記坦込配線は、タングステンを含む材料からなることを特徴とする請求項 1に記 載した半導体回路装置。  5. The semiconductor circuit device according to claim 1, wherein the carrier wiring is made of a material containing tungsten.
[6] 前記坦込配線を第 1の方向に配置し、  [6] Arrange the carrier wiring in the first direction,
前記基板上配線により接続する前記回路素子の接続箇所を、第 2の方向へ、直線的 に配置したことを特徴とした請求項 1に記載した半導体回路装置。  2. The semiconductor circuit device according to claim 1, wherein the connection portions of the circuit elements connected by the wiring on the substrate are linearly arranged in the second direction.
[7] 前記第 1の方向と前記第 2の方向が直交することを特徴とする請求項 6に記載した 半導体回路装置。  7. The semiconductor circuit device according to claim 6, wherein the first direction and the second direction are orthogonal to each other.
[8] 前記 MOSトランジスタ素子の前記立体孤立領域を形成する立体孤立領域形成ェ 程と  [8] A solid isolated region forming step for forming the solid isolated region of the MOS transistor element;
前記立体孤立領域と自己整合的に埋込配線用溝を支持基板中に形成する溝形成 工程と、  Forming a groove for embedded wiring in a support substrate in a self-aligned manner with the three-dimensional isolated region; and
前記坦込配線用溝にシリコンとエッチング選択性がある坦込材料を坦め込む埋込ェ 程と、  An embedding step of loading a carrier material having etching selectivity with silicon into the groove for the carrier wiring;
前記 MOSトランジスタ素子のゲート電極を形成するゲート電極形成工程と、 前記坦込配線を形成する坦込配線形成工程と、 前記基板上配線を形成する基板上配線形成工程とを備える請求項 1に記載した半 導体回路装置の製造方法。 A gate electrode forming step of forming a gate electrode of the MOS transistor element; a carrier wiring forming step of forming the carrier wire; 2. The method of manufacturing a semiconductor circuit device according to claim 1, further comprising: an on-substrate wiring forming step for forming the on-substrate wiring.
[9] 前記坦込材料はシリコンとゲルマニウムとを含む材料力 なることを特徴とする請求 項 8に記載した半導体回路装置の製造方法。  9. The method for manufacturing a semiconductor circuit device according to claim 8, wherein the loading material has a material force including silicon and germanium.
[10] 前記坦込配線形成工程は、 [10] The carrier wiring forming step includes:
前記坦込材料を除去する工程と、  Removing the carrier material;
前記坦込配線用溝に金属材料を坦め込む工程を備えることを特徴とする請求項 8に 記載した半導体回路装置の製造方法。  9. The method for manufacturing a semiconductor circuit device according to claim 8, further comprising a step of loading a metal material into the groove for the loading wiring.
[11] 前記金属材料はタングステン (W)であることを特徴とした請求項 10記載の半導体回 路装置の製造方法。 11. The method for manufacturing a semiconductor circuit device according to claim 10, wherein the metal material is tungsten (W).
[12] 前記坦込配線形成工程は、 [12] The carrier wiring forming step includes:
前記坦込配線用溝内の前記埋込材料上に絶縁層を形成する工程と、  Forming an insulating layer on the embedded material in the groove for the carrier wiring;
前記絶縁層中に前記埋込材料に対してコンタクト Viaを開口する工程と、  Opening a contact via for the embedded material in the insulating layer;
前記絶縁層上に金属材料を堆積する工程と、  Depositing a metal material on the insulating layer;
前記坦込配線用溝中の前記埋込材料と前記金属材料を接触させ、熱処理を加えて 前記金属材料と前記坦込材料を置換させる工程とを備えること特徴とする請求項 8に 記載した半導体回路装置の製造方法。  The semiconductor according to claim 8, further comprising a step of bringing the embedded material and the metal material in the groove for the carrier wiring into contact with each other and applying heat treatment to replace the metal material and the carrier material. A method of manufacturing a circuit device.
[13] 前記金属材料はアルミニウムを含むことを特徴とする請求項 12の半導体回路装置 の製造方法。 13. The method for manufacturing a semiconductor circuit device according to claim 12, wherein the metal material includes aluminum.
PCT/JP2005/002908 2005-02-23 2005-02-23 Semiconductor circuit device, and method for manufacturing the semiconductor circuit device WO2006090445A1 (en)

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