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WO2006075574A1 - Resistance change element and manufacturing method thereof - Google Patents

Resistance change element and manufacturing method thereof Download PDF

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Publication number
WO2006075574A1
WO2006075574A1 PCT/JP2006/300142 JP2006300142W WO2006075574A1 WO 2006075574 A1 WO2006075574 A1 WO 2006075574A1 JP 2006300142 W JP2006300142 W JP 2006300142W WO 2006075574 A1 WO2006075574 A1 WO 2006075574A1
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WO
WIPO (PCT)
Prior art keywords
layer
resistance change
lower electrode
variable resistance
oxygen deficient
Prior art date
Application number
PCT/JP2006/300142
Other languages
French (fr)
Japanese (ja)
Inventor
Akihiro Sakai
Hideaki Adachi
Akihiro Odagawa
Tsutomu Kanno
Yasunari Sugita
Kiyoshi Ohnaka
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2006075574A1 publication Critical patent/WO2006075574A1/en

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/021Formation of switching materials, e.g. deposition of layers
    • H10N70/026Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/041Modification of switching materials after formation, e.g. doping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/821Device geometry
    • H10N70/826Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/883Oxides or nitrides
    • H10N70/8836Complex metal oxides, e.g. perovskites, spinels

Definitions

  • the present invention relates to a resistance change element that changes its resistance value by applying an electric pulse, and a manufacturing method thereof.
  • Memory elements are used in a wide range of fields as important basic electronic components that support the information society.
  • DRAM Dynamic Random Access Memory
  • An element disclosed in US Pat. No. 6,204,139 has a structure in which a lower electrode 101, a PCMO layer 102, and an upper electrode 103 are sequentially laminated, as shown in FIG.
  • the resistance value of the PCMO layer 102 can be changed by applying a predetermined current or voltage between the upper electrode 103 and the lower electrode 101.
  • An element using such a change in resistance value is not easily affected by miniaturization, and can improve the recording speed and the erasing speed as compared with a flash memory widely used as a nonvolatile memory element in recent years. Therefore, practical application to next-generation memory devices is expected.
  • the element disclosed in US Pat. No. 6,204,139 has a problem that its resistance change characteristic deteriorates as the temperature rises.
  • the resistance change rate of an element having the same structure as that of the element disclosed in US Pat. No. 6,204,139 decreases near 100 ° C. I will report that.
  • an object of the present invention is to provide a resistance change element having excellent heat resistance in which deterioration of resistance change characteristics at the time of temperature rise is suppressed as compared with a conventional element, and a method for manufacturing the resistance change element. To do.
  • the resistance change element of the present invention includes a substrate and a multilayer structure disposed on the substrate, and the multilayer structure includes an upper electrode and a lower electrode, and between the upper electrode and the lower electrode. There are two or more states in which the electric resistance value between the upper electrode and the lower electrode is different, and a predetermined value is provided between the upper electrode and the lower electrode. It is an element that changes from one state selected from the two or more state forces to another state by applying an electric pulse.
  • variable resistance layer has a composition represented by the formula (Pr, Ca) MnO xl
  • the multilayer structure includes at least one electrode selected from the upper electrode and the lower electrode force, and the It further includes an oxygen-deficient layer having a composition represented by the formula (Pr, Ca) MnO and disposed between the resistance change layer.
  • oxygen-deficient layer having a composition represented by the formula (Pr, Ca) MnO and disposed between the resistance change layer.
  • x2 are numerical values satisfying 0 ⁇ xl ⁇ 3, 0 ⁇ x2 ⁇ 3, and x2 ⁇ xl.
  • the oxygen deficient layer can suppress deterioration of the resistance change characteristic of the element at the time of temperature rise, and is an element having higher heat resistance than the conventional resistance change element. be able to.
  • variable resistance element manufacturing method (first manufacturing method) of the present invention is the above variable resistance element manufacturing method of the present invention, comprising: a lower electrode forming step of forming a lower electrode on a substrate; A variable resistance layer having a composition represented by the formula (Pr, Ca) MnO is formed on the lower electrode.
  • a variable resistance layer Forming a variable resistance layer, forming an oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO on the variable resistance layer, and forming the variable resistance layer and the oxygen deficient layer.
  • xl and x2 are numerical values satisfying 0 ⁇ xl ⁇ 3, 0 ⁇ x2 ⁇ 3, and x2 ⁇ xl, respectively.
  • a variable resistance element manufacturing method (second manufacturing method) according to the present invention is the above variable resistance element manufacturing method according to the present invention, comprising: a lower electrode forming step of forming a lower electrode on a substrate; An oxygen deficient layer forming step for forming an oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO on the lower electrode, and a formula (Pr, Ca) MnO represented on the oxygen deficient layer.
  • variable resistance layer forming step for forming a variable resistance layer having a composition
  • an upper electrode forming step for forming an upper electrode for sandwiching the oxygen deficient layer and the variable resistance layer together with the lower electrode.
  • xl and ⁇ 2 are numerical values satisfying 0 ⁇ xl ⁇ 3, 0 ⁇ 2 ⁇ 3, and ⁇ 2 ⁇ xl, respectively.
  • FIG. 1 is a cross-sectional view schematically showing an example of a variable resistance element according to the present invention.
  • FIG. 2 is a cross-sectional view schematically showing another example of the variable resistance element of the present invention.
  • FIG. 3 is a cross-sectional view schematically showing another example of the variable resistance element of the present invention.
  • FIG. 4 is a schematic diagram showing an example of a resistance change type memory including the resistance change element of the present invention.
  • FIG. 5A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 5B is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 5C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 5D is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 5E is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 5F is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 6A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 6B is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 6C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 6D is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 6E is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 6F is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 6G is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 7A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 7B is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 7C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 7D is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 7E is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
  • FIG. 7F is a process chart schematically showing an example of the method of manufacturing a resistance change element according to the present invention.
  • FIG. 7G is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 7H is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
  • FIG. 8 is a cross-sectional view schematically showing an example of a conventional variable resistance element.
  • variable resistance layer is represented by the formula (Pr, Ca) MnO.
  • the oxygen deficient layer and the variable resistance layer may be in contact with each other, and the oxygen deficient layer and the at least one electrode may be in contact with each other.
  • the multilayer structure may include only the oxygen deficient layer and the variable resistance layer as an oxide layer containing Pr, Ca, and Mn.
  • the multilayer structure may include the oxygen deficient layer, the resistance change layer, the upper electrode, and the lower electrode.
  • the oxygen deficient layer is represented by the formula Pr Ca MnO and p 1-p x2
  • p is 0.6 or more and 0.8 or less.
  • p 1-p xl is expressed by the resistance change layer force formula Pr Ca MnO.
  • p is 0.6 or more and 0.8 or less.
  • the resistance change layer may be formed so as to be in contact with the lower electrode, and the upper electrode may be formed so as to be in contact with the oxygen deficient layer formed on the surface of the resistance change layer.
  • Oxy inert may be larger than the ratio (P / P) of the atmosphere in the oxygen deficient layer forming step.
  • variable resistance layer forming step the variable resistance layer is formed by sputtering, and in the oxygen deficient layer forming step, the oxygen deficient layer is formed by sputtering. Also good.
  • the partial pressure P (P / P) of the inert gas that the atmosphere in the variable resistance layer forming step has
  • Oxy inert may be larger than the ratio (P / P) of the atmosphere in the oxygen deficient layer forming step.
  • the oxygen deficient layer is formed by sputtering
  • the variable resistance layer is formed by sputtering. Also good.
  • a resistance change element 1 shown in FIG. 1 includes a substrate 12, a pair of electrodes having a lower electrode 2 and an upper electrode 4, and a resistance change layer 3 sandwiched between the lower electrode 2 and the upper electrode 4. Contains.
  • an oxide force including Pr (prasedium), Ca (calcium), and Mn (manganese) is provided between the upper electrode 4 and the resistance change layer 3 in the same manner as the resistance change layer 3.
  • An oxygen-deficient layer 5 having a composition different from that of 3 is arranged.
  • the lower electrode 2, the resistance change layer 3, the oxygen deficient layer 5, and the upper electrode 4 are arranged on the substrate 12 in the above order as a multilayer structure (laminated body) 11.
  • the resistance change layer 3 has a composition A represented by the formula (Pr, Ca) MnO, and the oxygen deficient layer 5
  • the yarn has the formula B expressed by the formula (Pr, Ca) MnO.
  • xl and x2 are values satisfying 0 ⁇ xl ⁇ 3, 0 ⁇ x2 ⁇ 3, x2 and xl, respectively, and the oxygen deficiency layer 5 has an oxygen deficiency rate higher than that of the resistance change layer 3.
  • the fractions of Pr and Ca in the yarn and composition A and the fraction in the yarn and composition B may be the same or different, but if they are the same, the oxygen deficient layer 5 It can be said that this is a layer in which the oxygen deficiency rate in the change layer 3 is increased.
  • element 1 there are two or more states in which the electric resistance value between lower electrode 2 and upper electrode 4 is different, and a predetermined electric pulse is applied to element 1, specifically, lower electrode 2 and upper electrode 4.
  • a predetermined electric pulse is applied to element 1, specifically, lower electrode 2 and upper electrode 4.
  • the element 1 changes to one state force selected from the above-described two or more state forces to another state. If element 1 has two states with different electrical resistance values (relatively high resistance state A and relatively low resistance state B), device 1 will be in the state by applying a predetermined electrical pulse. Change from A to state B, or from state B to state A.
  • the predetermined electric pulse is applied to the resistance change layer 3 and can be obtained.
  • the element 1 has better heat resistance than the conventional resistance change element, and the degree depends on the configuration of the element 1, but as shown in the examples described later, for example, even at 200 ° C., It can maintain a resistance change rate almost equal to (25 ° C).
  • the specific value of the resistance change rate of the element 1 is a force depending on the configuration of the element 1, for example, 600% or more.
  • the resistance change rate is a numerical value that serves as an index of the resistance change characteristic of the element. Specifically, the maximum electric resistance value indicated by the element is R
  • the oxygen deficient layer 5 and the resistance change layer 3 are not necessarily in contact.
  • an arbitrary layer may be disposed between the two, but as shown in FIG. It is preferable that they touch each other.
  • an arbitrary layer may be disposed between the two, but it is preferable that the two are in contact with each other.
  • Oxygen deficient layer 5 And the resistance change layer 3 are in contact with each other, the boundary between them may not necessarily be clear.
  • a laminated body 11 shown in FIG. 1 may include a force laminated body 11 including a lower electrode 2, an upper electrode 4, a resistance change layer 3, and an oxygen deficient layer 5, and may include any layer other than the above layers.
  • the laminate 11 includes only the resistance change layer 3 and the oxygen deficient layer 5 having the above-described composition A and composition B, respectively, as the oxide layer containing Pr, Ca, and Mn.
  • FIG. 2 shows another example of the resistance change element 1 of the present invention.
  • the oxygen deficient layer 5 is disposed between the lower electrode 2 and the resistance change layer 3, and the lower electrode 2, the oxygen deficient layer 5, the resistance change layer 3 and the upper electrode 4 are The laminated body 11 is arranged on the substrate 12 in the above order.
  • the oxygen deficient layer 5 and the lower electrode 2 are not necessarily in contact with each other.
  • an arbitrary layer may be disposed between the two, but as shown in FIG. It is preferable to touch.
  • FIG. 3 shows another example of the variable resistance element 1 of the present invention.
  • the two oxygen deficient layers 5a and 5b are disposed between the lower electrode 2 and the resistance change layer 3, and between the upper electrode 4 and the resistance change layer 3, respectively.
  • the lower electrode 2, the oxygen deficient layer 5a, the resistance change layer 3, the oxygen deficient layer 5b, and the upper electrode 4 are arranged on the substrate 12 as the stacked body 11 in the order described above.
  • the resistance change layer 3 only needs to satisfy the above composition A.
  • the oxygen-deficient layer 5 only needs to satisfy the above-mentioned yarn composition B.
  • the yarn formation of the resistance change layer 3 and the oxygen deficient layer 5 may be evaluated by an analytical method such as Auger electron spectroscopy.
  • the lower electrode 2 is typically metallic if it has electrical conductivity.
  • Pt platinum
  • Ir iridium
  • alloys thereof may be used.
  • the lower electrode 2 also has a material force capable of crystallizing the variable resistance layer 3 and the Z or oxygen deficient layer 5 on the surface thereof.
  • the resistance change layer 3 and the Z or oxygen deficient layer 5 having a stable crystal structure can be formed on the lower electrode 2, and the resistance change layer 3 and the Z or oxygen deficient layer 5 on the lower electrode 2 can be formed. Can be formed more easily.
  • a lower electrode 2 for example, from SrRuO, SrTiO, or Nb, Cr and La
  • An electrode made of a conductive oxide having a crystal structure can be mentioned.
  • the upper electrode 4 should basically have conductivity.
  • Au gold
  • Pt platinum
  • Ru ruthenium
  • Ir iridium
  • Ti titanium
  • A1 Al
  • Cu copper
  • Ta tantalum
  • their alloys eg, iridium-tantalum alloy (Ir—Ta)
  • oxides eg, tin-doped indium oxides (ITO )
  • Nitrides fluorides, carbides, borides and the like.
  • the substrate 12 is not particularly limited as long as the multilayer body 11 can be disposed on the substrate 12, and may be, for example, a silicon (Si) substrate or an MgO substrate.
  • the substrate 12 is a Si substrate, the combination of the resistance change element of the present invention and the semiconductor element becomes easy.
  • the surface of the substrate 12 in contact with the lower electrode 2 may be oxidized, that is, an oxide film may be formed on the surface of the substrate 12.
  • the structure of the resistance change element of the present invention is such that a laminate 11 including a lower electrode 2, a resistance change layer 3, an oxygen deficient layer 5 and an upper electrode 4 is formed on a substrate 12, and the resistance change layer 3 is The oxygen deficient layer 5 is sandwiched between the lower electrode 2 and the upper electrode 4, and is arranged between at least one electrode selected from the lower electrode 2 and the upper electrode 4 and the resistance change layer 3.
  • the stacked body 11 may include two or more oxygen-deficient layers 5, and although not illustrated, the stacked body 11 may include two or more resistance change layers 3.
  • the state force in element 1 changes, for example, from state A to state B, but the changed state B is maintained until a predetermined electric pulse is applied to element 1 again. Then, by applying the electric pulse, for example, state B force state A is changed again.
  • the predetermined electrical pulse applied to element 1 is when element 1 is in state A.
  • the size, polarity, pulse shape, and the like that do not necessarily have to be the same between the state B and the state B may differ depending on the state of the element 1. That is, the “predetermined electric pulse” in this specification is an electric pulse that can change to another state different from the state when the element 1 is in a certain state.
  • a nonvolatile resistance change memory can be constructed by combining a mechanism for detecting the electric resistance value of the element 1 and assigning a bit to each of the above states. For the bit assignment, for example, state A may be “0” and state B may be “1”.
  • the resistance change type memory includes a memory array in which two or more memory elements are arranged in addition to the memory elements. Also, by assigning ON or OFF to each of the above states, element 1 can be applied to a switching element.
  • the electric pulse to be applied may be a voltage (pulse voltage) or a current (current pulse).
  • the shape of the pulse is not particularly limited, and may be any shape as long as it is a sine wave shape, a rectangular wave shape, and a triangular wave force.
  • the width of the pulse is usually in the range of a few nanoseconds to a few milliseconds.
  • the element 1 can be miniaturized and the electronic device constructed using the element 1 can be more easily downsized.
  • a potential difference applying mechanism that generates a potential difference between the lower electrode 2 and the upper electrode 4 is connected to the element 1.
  • a bias voltage positive bias voltage
  • a negative voltage negative bias voltage
  • Device 1 may be changed from state B to state A by applying.
  • a pulse generator may be used as the potential difference applying mechanism.
  • the resistance change element according to the present invention is combined with a semiconductor element, for example, a transistor such as a diode or a MOS field effect transistor (MOS-FET) to change the resistance.
  • a semiconductor element for example, a transistor such as a diode or a MOS field effect transistor (MOS-FET) to change the resistance.
  • MOS-FET MOS field effect transistor
  • FIG. 4 shows an example of a resistance change memory (element) in which the resistance change element of the present invention and a MOS-FET are combined.
  • a resistance change type memory element 31 shown in FIG. 4 includes a resistance change element 1 and a transistor 21, and the element 1 is electrically connected to the transistor 21 and the bit line 32.
  • the gate electrode of the transistor 21 is electrically connected to the word line 33, and the remaining one electrode in the transistor 21 is grounded.
  • the transistor 21 can be used as a switching element to detect the above state in the element 1 (that is, to detect the electric resistance value of the element 1) and to apply a predetermined electrical noise to the element 1. It becomes.
  • the memory element 31 shown in FIG. 4 can be a 1-bit resistance change memory element.
  • Recording of information in the memory element 31 may be performed by applying a predetermined electric pulse to the resistance change element 1. Reading of information recorded in the element 1 may be performed by, for example, a pulse voltage applied to the element 1. Alternatively, the current pulse may be changed by changing the magnitude of the current pulse.
  • the element 1 has a pulsed positive bias voltage having a magnitude equal to or greater than a certain threshold value (V).
  • the electrical resistance value of element 1 can be detected as the current output of element 1.
  • a voltage applied to detect the electric resistance value of the element 1 is defined as a READ voltage (V).
  • the READ voltage is the same as the SET voltage and RESET voltage.
  • the pulse voltage to the element 1, information can be recorded and read from the memory element 31, and the magnitude of the output current of the element 1 obtained by the reading is as follows. Different depending on the state. Here, if the relatively large output current is “1” and the relatively small output current is “0”, the memory device 31 records information “1” by the SET voltage, and the RESET voltage. Thus, the memory device can record information “0” (delete information “1”).
  • the magnitude of the READ voltage is usually preferably about 1 Z4 to 1Z1000 with respect to the magnitude of the SET voltage and the RESET voltage.
  • Specific values of the SET voltage and the RESET voltage are forces depending on the configuration of the resistance change element 1.
  • the voltage is in the range of 0.1V to 20V, and the range of 1V to 12V is preferable.
  • variable resistance element of the present invention can be formed, for example, by the method for manufacturing a variable resistance element of the present invention, which will be described in detail below.
  • the resistance change layer 3 having the composition A and the oxygen deficiency having the composition B are formed on the formed lower electrode 2.
  • Layer 5 is formed.
  • the composition of the variable resistance layer 3 to be formed is expressed by the formula (Pr, Ca) MnO.
  • composition (xl 3), that is, a composition satisfying the stoichiometric ratio! / ⁇ .
  • the order of forming the resistance change layer 3 and the oxygen deficiency layer 5 on the lower electrode 2, the number of the resistance change layers 3 and the oxygen deficiency layers 5 formed on the lower electrode 2, and the like are as follows. What is necessary is just to set suitably according to a structure.
  • a step of forming a lower electrode on the substrate (lower electrode forming step), a step of forming a resistance change layer having the composition A on the lower electrode (resistance change layer forming step), and the resistance change layer A step of forming an oxygen deficient layer having the above composition B (oxygen deficient layer forming step), a step of forming an upper electrode sandwiching the resistance change layer and the oxygen deficient layer together with the lower electrode (upper electrode forming step), May be performed in order (first manufacturing method).
  • the step of forming (resistance change layer forming step) and the upper electrode forming step may be sequentially performed (second manufacturing method).
  • an optional step may be added between the above steps as necessary.
  • the lower electrode 2, the upper electrode 4, and the resistance change layer 3 apply a semiconductor manufacturing process, If it is formed by a general thin film formation process and microfabrication process.
  • a semiconductor manufacturing process If it is formed by a general thin film formation process and microfabrication process.
  • PLD pulsed laser deposition
  • IBD ion beam deposition
  • cluster ion beam and various types such as RF, DC, electron cyclotron resonance (ECR), helicon, inductively coupled plasma (ICP), and opposed target Sputtering, molecular beam epitaxy (MBE), ion plating, or the like may be used.
  • PVD Physical Vapor D eposition
  • CVD Chemical Vapor Deposition
  • MOCVD Metal Organ ic Chemical Vapor Deposition
  • message 3 r method Metal Organic Decomposition
  • MOD Metal Organic Decomposition
  • sol-gel method etc. May be used.
  • each layer includes, for example, ion milling, RIE (Reactive Ion Etching), FIB (Focused Ion Beam) used in semiconductor manufacturing processes and magnetic device (such as magnetoresistive elements such as GMR and TMR) manufacturing processes. ) Or the like, and a photolithography technique using a stepper for forming a fine pattern, an electron beam (EB) method, or the like may be used in combination.
  • RIE Reactive Ion Etching
  • FIB Fluorused Ion Beam
  • a photolithography technique using a stepper for forming a fine pattern, an electron beam (EB) method, or the like may be used in combination.
  • EB electron beam
  • planarization of the surface of each layer for example, CMP (Chemical Mechanical Polishing), cluster ⁇ —— ion beam etching or the like may be used.
  • an insulating layer deposition method a microfabrication method, and a planarization method, which will be described later, and an electronic device such as a memory element or a memory array including the resistance change element of the present invention can be formed by the same method.
  • the method for forming the oxygen deficient layer 5 is not particularly limited, but for example, the following method may be used.
  • the oxygen deficient layer 5 is formed by reverse sputtering the surface of 3.
  • the resistance change layer 3 and the oxygen deficient layer 5 that are in contact with each other can be formed.
  • FIG. Element 1 shown in Fig. 1 can be formed.
  • Inverse sputtering may be performed by using the resistance change layer 3 as a target based on a general method. At this time, among the elements constituting the resistance change layer 3, the oxygen desorption degree is particularly large, so that the oxygen deficiency layer 5 can be formed by increasing the oxygen loss rate of the reverse-sputtered portion of the resistance change layer 3. .
  • the reverse sputtering is preferably performed in a non-oxidizing atmosphere, for example, in an atmosphere containing a reducing gas such as hydrogen and an inert gas such as Z or nitrogen or argon. Further, in order to prevent the resistance change layer 3 from being etched excessively at the time of reverse sputtering, it is desirable not to excessively increase the sputtering power to be input.
  • the thickness of the oxygen-deficient layer 5 to be formed can be controlled by the time for performing reverse sputtering.
  • Method II In the first manufacturing method, after the variable resistance layer 3 is formed, the oxygen deficient layer 5 is formed by heat-treating the surface of the variable resistance layer 3 in a non-acidic atmosphere. .
  • the resistance change layer 3 and the oxygen deficient layer 5 that are in contact with each other can be formed.
  • FIG. Element 1 shown in Fig. 1 can be formed.
  • the heat treatment may be performed based on a general method except that the heat treatment is performed in a non-oxidizing atmosphere.
  • the non-oxidizing atmosphere may be an atmosphere containing a reducing gas such as hydrogen and an inert gas such as Z or nitrogen or argon.
  • a reducing gas such as hydrogen
  • an inert gas such as Z or nitrogen or argon.
  • the temperature of the heat treatment is, for example, about 500 ° C. to 600 ° C.
  • the time for the heat treatment may be about several minutes, although it depends on the thickness of the oxygen deficient layer 5 to be formed. In order to suppress an increase in the oxygen deficiency rate of the entire resistance change layer 3 due to heat being transferred to the entire resistance change layer 3, rapid temperature increase and temperature decrease after the heat treatment are desired during the heat treatment.
  • method m changes the partial pressure of oxygen in the atmosphere in which each layer is formed, so that the resistance change layer 3 having a relatively small oxygen deficiency rate and the oxygen deficiency rate is relatively large. It can be said that this is a method of forming the oxygen deficient layer 5.
  • the resistance change layer 3 is formed under a condition where the partial pressure of oxygen is relatively large, and the oxygen deficient layer 5 is formed under a condition where the partial pressure of oxygen is relatively small.
  • the method of forming the resistance change layer 3 and the oxygen deficient layer 5 is not particularly limited.
  • Any sputtering method may be used.
  • the partial pressure ratio between argon and oxygen (P / P oxy
  • variable resistance layer 3 When the variable resistance layer 3 is formed under the condition A, the oxygen deficient layer 5 can be formed in contact with the formed variable resistance layer 3 by changing to the condition B. Similarly, when the oxygen deficient layer 5 is formed under the condition B, the resistance change layer 3 can be formed in contact with the formed oxygen deficient layer 5 by changing to the condition A.
  • the change to condition A or condition B may be performed continuously, intermittently or stepwise.
  • variable resistance layer 3 to be formed has a composition represented by the formula (Pr, Ca) MnO,
  • Condition A is an oxide containing Pr, Ca, and Mn, and includes oxygen that is necessary and sufficient and not excessive to form the oxide satisfying the stoichiometric ratio.
  • Condition B is oxygen It can be said that this is a condition for forming the oxide having defects.
  • Conditions A and B can be said to be sputtering conditions for forming the resistance change layer 3 and the oxygen deficient layer 5, respectively.
  • FIGS. 5A to 5F An example of the production method of the present invention is shown in FIGS. 5A to 5F.
  • the lower electrode 2 is formed on the substrate 12 (FIG. 5A).
  • An oxide film is formed on the surface of the substrate 12 where the lower electrode 2 is formed, for example, an SiO film when the substrate 12 is a Si substrate.
  • an insulating layer 31 is deposited on the entire surface including the exposed surface of the lower electrode 2 (FIG. 5B), and a contact hole 32 leading to the lower electrode 2 is formed in a part of the insulating layer 31 (FIG. 5C). .
  • the resistance change layer 3 is further formed. (Figure 5D). As necessary, as shown in FIG. 5E, the surface of the formed resistance change layer 3 may be flattened and the resistance change layer 3 may be embedded.
  • the formation method of the oxygen deficient layer 5 and the resistance change layer 3 is not particularly limited.
  • the resistance change layer 3 is formed according to the condition A. do it.
  • an upper electrode 4 is formed on the resistance change layer 3 so as to ensure electrical connection with the resistance change layer 3 (FIG. 5F), and resistance change as shown in FIG.
  • the resistance change element 1 in which the oxygen deficient layer 5 is disposed so as to be in contact with both layers is formed.
  • the insulating layer 31 plays a role as an interlayer insulating layer in the element 1 and may be made of an insulating material such as SiO, Al 2 O, or the like.
  • the insulating layer 31 may be a resist material.
  • the insulating layer 31 can be easily formed by the spin coating method, and the insulating layer 31 having a flat surface can be easily formed on the surface having the undulations.
  • FIGS. 6A to 6G Another example of the production method of the present invention is shown in FIGS. 6A to 6G.
  • the lower electrode 2 is formed on the substrate 12 (Fig. 6A), and the insulating layer 31 is deposited on the entire surface including the exposed surface of the formed lower electrode 2 (Fig. 6B). In part, a contact hole 32 leading to the lower electrode 2 is formed (FIG. 6C).
  • the resistance change layer 3 is formed on the exposed surface of the lower electrode 2 in the contact hole 32 so as to ensure electrical connection with the lower electrode 2 (FIG. 6D). If necessary, as shown in FIG. 6E, the surface of the formed resistance change layer 3 may be flattened, and the resistance change layer 3 may be embedded.
  • the oxygen deficient layer 5 is formed on the surface of the resistance change layer 3 (FIG. 6F).
  • the formation method of the oxygen deficient layer 5 is not particularly limited, and for example, the surface of the resistance change layer 3 may be subjected to reverse sputtering or heat treatment in a non-oxidizing atmosphere.
  • Electrode 4 is formed (FIG. 6G), and resistance change element 1 in which oxygen deficient layer 5 is disposed between resistance change layer 3 and upper electrode 4 so as to be in contact with both layers as shown in FIG. It is formed.
  • FIGS. 7A to 7H Another example of the production method of the present invention is shown in FIGS. 7A to 7H.
  • the lower electrode 2 is formed on the substrate 12 (FIG. 7A), and the resistance change layer 3 and the oxygen deficient layer 5 are sequentially formed on the formed lower electrode 2 (FIGS. 7B to 7C).
  • the formation method of the resistance change layer 3 and the oxygen deficiency layer 5 is not particularly limited. For example, after forming the resistance change layer 3 according to the condition A and using the sputtering method, the oxygen deficiency layer 5 may be formed according to the condition B. . Further, for example, the oxygen deficient layer 5 may be formed by forming the resistance change layer 3 and then subjecting the surface of the resistance change layer 3 to reverse sputtering or heat treatment in a non-oxidizing atmosphere.
  • the upper electrode 4 is formed on the oxygen deficient layer 5 so as to ensure electrical connection with the oxygen deficient layer 5 to form a laminate 11 (FIG. 7D).
  • a resist 33 is arranged on the upper electrode 4 in a region where the element 1 is to be formed (FIG. 7E), and is covered with the resist 33 in the laminate 11 by a fine processing means such as ion milling. Remove the part ( Figure 7F).
  • US Patent No. 6972238 (same content as JP-A-2004-349690) includes PrCaMnO.
  • variable resistance element one area is always PrCaMnO (yl is greater than 3) yl
  • Example 1 a resistance change element 1 as shown in FIG. 1 was produced by the method shown in FIGS. 6A to 6G, and the temperature dependence of the resistance change characteristics was evaluated.
  • a Pt layer (thickness: 200 nm) was laminated on the surface of the MgO substrate 12 as the lower electrode 2.
  • the Pt layer was laminated by RF magnetron sputtering in an argon atmosphere at a pressure of 1 Pa, with the substrate temperature set to room temperature (25 ° C) and the input power set to 80W.
  • the SiO layer is deposited by RF magnetron sputtering with argon at a pressure of 0.1 lPa.
  • the temperature of the substrate was set to 100 ° C., and the input power was set to 100 W.
  • a contact hole 32 (diameter 0.5 ⁇ m) leading to the Pt layer was formed in part of the SiO layer by RIE.
  • Pr Ca is formed as the resistance change layer 3.
  • PCMO layer thickness 300 nm
  • Lamination of the PCMO layer has the formula Pr Ca
  • the substrate temperature was set to 700 ° C and the input power was set to 80W.
  • the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, it was confirmed to be a polycrystalline film.
  • the oxygen deficiency layer 5 was formed by reverse sputtering the surface of the PCMO layer to increase the oxygen deficiency rate of a part of the PCMO layer including the surface.
  • Reverse sputtering was performed by RF magnetron sputtering with the PCMO layer as the target, the substrate temperature at 300 ° C, and the input power at 40 W in a hydrogen atmosphere at a pressure of 5 Pa.
  • the frequency of reverse sputtering voltage to be applied is 100 MHz, and reverse sputtering 200 seconds.
  • the Ag layer was laminated by RF magnetron sputtering in an argon atmosphere at a pressure of 1 Pa, with the substrate temperature set at room temperature and the input power set at 80W.
  • the resistance change element 1 in which the thickness of the oxygen deficient layer 5 is different from that of Sample 1-1, except that the time for reverse sputtering the surface of the PCMO layer was set to 100 seconds was made in the same way as Sample 1-1 (Sample 1-2). Since the reverse sputtering time is shorter than that of Sample 1-1, the thickness of oxygen deficient layer 5 in Sample 12 is considered to be smaller than that of Sample 1-1! /.
  • a pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this way via the lower electrode (Pt layer) and the upper electrode (Ag layer), and the resistance change rate
  • the temperature dependence of was evaluated.
  • the temperature dependency was evaluated as follows, and the same was applied to Examples 2 to 4 below.
  • the SET voltage is 5V (positive bias voltage)
  • the RESET voltage is 5V (negative bias voltage, magnitude 5V)
  • the READ voltage is 0. IV.
  • Positive bias voltage was applied randomly (pulse width of each voltage was 250ns). After applying the SET voltage and RESET voltage, calculate the electrical resistance value of the element from the current value read by applying the READ voltage. The maximum value of the calculated electrical resistance value is R and the minimum value is R. (R -R) / RX 100 (%)
  • the resistance change rate was determined.
  • each sample is held at room temperature (25 ° C), 100 ° C and 200 ° C until the temperature of each sample is approximately equal to the ambient temperature, the resistance of each sample is The anti-change rate was measured.
  • the reverse sputtering conditions for forming the oxygen deficient layer 5 are as follows: the substrate temperature is in the range of room temperature to 300 ° C, the gas pressure of the hydrogen atmosphere is in the range of lPa to: LOPa, and the input power is 40 to 80 W. When the range was changed, almost the same results as Samples 1-1 and 1-2 were obtained.
  • Example 2 a resistance change element 1 as shown in FIG. 1 was manufactured by the method shown in FIGS. 7A to 7H, and the temperature dependence of the resistance change characteristics was evaluated.
  • a Pt layer (thickness: 2 OOnm) was stacked as the lower electrode 2 on the surface of the Si substrate 12 in the same manner as in Example 1.
  • the substrate temperature was set to 700 ° C and the input power was set to 80W.
  • PCMO The partial pressure of oxygen in the stacking atmosphere was changed between when the layers were stacked and when the oxygen deficient layer 5 was stacked. Specifically, in a mixed atmosphere of oxygen and argon at a pressure of 3 Pa, the partial pressure ratio O
  • An oxygen deficient layer 5 was laminated with 2 being 0.08.
  • the total thickness of the PCMO layer and the oxygen deficient layer 5 was 300 nm.
  • the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, and was confirmed to be a polycrystalline film.
  • a resist 33 is arranged in a rectangular shape on the surface of the laminated Ag layer, and then the force that is not covered with the resist 33 in the Pt layer, the PCMO layer, the oxygen deficient layer 5 and the Ag layer by ion milling. One part was removed.
  • SiO layer was deposited as the insulating layer 31 on the entire exposed surface of each layer. Deposition of SiO layer
  • RF magnetron sputtering was performed at an input power of 100 W in an argon atmosphere with a substrate temperature of 100 ° C and a pressure of 0.1 IPa.
  • a sample was prepared in the same manner as Sample 2-1 except that Ar was changed to 0.1 (Sample 2-2). Since the above partial pressure ratio is larger than that of Sample 2-1, the oxygen deficiency rate in the oxygen deficient layer of Sample 2-2 is considered to be smaller than that of Sample 2-1.
  • a resistance change element that does not include the oxygen-deficient layer 5 is the same as Sample 2-1 except that the oxygen-deficient layer 5 is not stacked. (Sample B-1 as a comparative example).
  • a resistance change element including a PCMO layer and an oxygen excess layer containing excess oxygen exceeding the stoichiometric ratio between the Pt layer and the Ag layer, instead of stacking the oxygen-deficient layer 5, the partial pressure ratio O ZAr in the stacking atmosphere is set to about 0.6.
  • the sample was prepared in the same manner as Sample 1-1 except that an oxygen-excess layer was laminated (Comparison An example is Sample B-2. Sample B-2 does not have an oxygen deficient layer 5). It can be said that the oxygen-excess layer is a layer having a composition represented by the formula Pr Ca MnO (yl> 3).
  • a pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this manner via the lower electrode (Pt layer) and the upper electrode (Ag layer). Similarly, the temperature dependence of the resistance change rate of each sample was evaluated.
  • Example 3 a resistance change element 1 as shown in FIG. 2 was produced by the method shown in FIGS. 5A to 5F, and the temperature dependence of the resistance change characteristics was evaluated.
  • a Pt layer (thickness: 200 nm) was laminated as the lower electrode 2 on the surface of the MgO substrate 12 in the same manner as in Example 1.
  • the insulating layer 31 is formed on the entire surface including the exposed surface of the laminated Pt layer in the same manner as in Example 2. A SiO layer was deposited.
  • the portion where the variable resistance element 1 in the deposited SiO layer is to be formed is formed by RIE.
  • a contact hole 32 (diameter 0.5 m) was formed.
  • an oxygen deficient layer 5 was deposited on the exposed surface of the Pt layer in the formed contact hole 32.
  • the stacking of the oxygen deficient layer 5 is performed by RF magnetron sputtering with the formula Pr Ca M
  • the target is an oxide having a composition represented by ⁇ .
  • the substrate temperature is set to 700 ° C
  • the power used was 80W.
  • a PCMO layer was laminated as the resistance change layer 3 on the surface of the laminated oxygen deficient layer 5.
  • Lamination of the PCMO layer is done by setting the partial pressure ratio O ZAr in the lamination atmosphere to about 0.25.
  • the outside was performed in the same manner as the stacking of the oxygen deficient layer 5.
  • the thickness of the laminated oxygen deficient layer 5 and PCMO layer was 300 nm in total.
  • variable resistance element 1 (sample 3) was produced.
  • a pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this manner via the lower electrode (Pt layer) and the upper electrode (Ag layer). Similarly, the temperature dependence of the resistance change rate of each sample was evaluated.
  • the resistance change rate at room temperature was almost the same (600% or more) in all samples, but at 100 ° C, the resistance change rate of sample C, which is a comparative example, was large. At 200 ° C, the resistance change characteristics of sample C almost disappeared (resistance change rate was less than 5%). In contrast, the resistance change rate of sample 3 hardly changed even at temperatures of 100 ° C or higher, and could maintain a resistance change rate almost equal to room temperature even at 200 ° C
  • Example 4 a resistance change element 1 as shown in FIG. 1 was produced by the method shown in FIGS. 7A to 7H, and the temperature dependence of the resistance change characteristics was evaluated.
  • a Pt layer (thickness 2) is formed on the surface of the Si substrate 12 as the lower electrode 2 in the same manner as in Example 1.
  • a PCMO layer (thickness: 300 nm) was laminated as the resistance change layer 3 in the same manner as in Example 1 on the surface of the laminated Pt layer.
  • the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, it was confirmed to be a polycrystalline film.
  • the oxygen deficiency layer 5 was formed by increasing the deficiency rate of a part of oxygen including the surface in the O layer. In the heat treatment, the entire substrate, including the substrate, is heated to 500 ° C in 1 minute.
  • a resist 33 is arranged in a rectangular shape on the surface of the laminated Ag layer, and then covered with the resist 33 in the Pt layer, the resistance change layer 3, the oxygen deficient layer 5, and the Ag layer by ion milling. The part which did not exist was removed.
  • an SiO layer as an insulating layer 31 is deposited on the entire exposed surface of each layer in the same manner as in Example 2.
  • the resistance change rate at room temperature was almost the same (600% or more) for all samples, but at 100 ° C, the resistance change rate of sample D, which is a comparative example, was large. At 200 ° C, the resistance change characteristics of sample D almost disappeared (resistance change rate was less than 5%). In contrast, the resistance change rate of sample 4 hardly changed even at temperatures of 100 ° C or higher, and the resistance change rate at 200 ° C was almost the same as that of room temperature.
  • the resistance change element of the present invention is superior in heat resistance compared to conventional resistance change elements, and can operate stably in a temperature environment of 200 ° C, for example.
  • the resistance change element of the present invention can hold information in an nonvolatile manner as an electric resistance value, and the element can be easily miniaturized as compared with a conventional charge storage type memory element.
  • a non-volatile memory used for an information communication terminal or the like , Switching elements, sensors, image display devices, and the like.

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Abstract

There are provided a resistance change element having an excellent heat resistance for suppressing degrading of resistance change characteristic upon temperature increase as compared to a conventional element and a manufacturing method of the element. The resistance change element includes a substrate and a multi-layered structure arranged on the substrate. The multi-layered structure has an upper electrode, a lower electrode, and a resistance change layer arranged between the upper electrode and the lower electrode. The resistance change element has at least two states when the electric resistance value of the upper electrode is different from that of the lower electrode. By applying a predetermined electric pulse between the upper electrode and the lower electrode, the state is changed from selected one of the at least two states to another state. The resistance change layer has a composition expressed by Expression (Pr, Ca)MnOx1 and the multi-layered structure further includes at least one electrode selected from the upper electrode and the lower electrode and an oxygen lacking layer having a composition expressed by Expression (Pr, Ca)MnOx2. Here, x1 and x2 satisfy the following: 0 < x1 ≤ 3, 0 < x2 < 3, and x2 < x1.

Description

明 細 書  Specification
抵抗変化素子とその製造方法  Resistance change element and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、電気パルスの印加により抵抗値が変化する抵抗変化素子と、その製造 方法とに関する。  The present invention relates to a resistance change element that changes its resistance value by applying an electric pulse, and a manufacturing method thereof.
背景技術  Background art
[0002] メモリ素子は、情報化社会を支える重要な基幹電子部品として、幅広い分野に用い られている。近年、情報携帯端末の普及に伴い、メモリ素子の微細化の要求が高ま つており、不揮発性メモリ素子においても例外ではない。しかし、素子の微細化がナ ノメーターの領域に及ぶにつれ、従来の電荷蓄積型のメモリ素子 (代表的には DRA M : Dynamic Random Access Memory)では、情報単位(ビット)あたりの電荷容量じの 低下が問題となりつつあり、この問題を回避するために様々な改善等がなされている ものの、将来的な技術的限界が懸念されている。  Memory elements are used in a wide range of fields as important basic electronic components that support the information society. In recent years, with the widespread use of portable information terminals, there has been an increasing demand for miniaturization of memory elements, and nonvolatile memory elements are no exception. However, as device miniaturization reaches the nanometer range, conventional charge storage type memory devices (typically DRAM: Dynamic Random Access Memory) have the same charge capacity per information unit (bit). The decline is becoming a problem, and various improvements have been made to avoid this problem, but there are concerns about future technological limitations.
[0003] 微細化の影響を受けにくいメモリ素子として、電荷容量 Cではなぐ電気抵抗 Rの変 化により情報を記録する不揮発性メモリ素子 (抵抗変化型メモリ素子)が注目されて いる。このような抵抗変化型メモリ素子として、米国特許第 6204139号には、ぺロブス カイト酸化物(Pr Ca MnO: PCMO)を用いた素子が開示されている。  [0003] As a memory element that is not easily affected by miniaturization, attention is focused on a nonvolatile memory element (resistance change type memory element) that records information by changing the electric resistance R that is not the charge capacity C. As such a resistance change type memory element, US Pat. No. 6,204,139 discloses an element using perovskite oxide (Pr Ca MnO: PCMO).
0.7 0.3 3  0.7 0.3 3
[0004] 米国特許第 6204139号に開示されている素子は、図 8に示すように、下部電極 101 、 PCMO層 102および上部電極 103が順に積層された構造を有しており、当該素子 では、上部電極 103と下部電極 101との間に所定の電流または電圧を印加すること により、 PCMO層 102の抵抗値を変化させることができる。  [0004] An element disclosed in US Pat. No. 6,204,139 has a structure in which a lower electrode 101, a PCMO layer 102, and an upper electrode 103 are sequentially laminated, as shown in FIG. The resistance value of the PCMO layer 102 can be changed by applying a predetermined current or voltage between the upper electrode 103 and the lower electrode 101.
[0005] このような抵抗値の変化を利用した素子は、微細化の影響を受けにくいとともに、近 年不揮発性メモリ素子として幅広く用いられているフラッシュメモリに比べ、記録速度 、消去速度を向上できると考えられ、次世代メモリ素子への実用化が期待される。  [0005] An element using such a change in resistance value is not easily affected by miniaturization, and can improve the recording speed and the erasing speed as compared with a flash memory widely used as a nonvolatile memory element in recent years. Therefore, practical application to next-generation memory devices is expected.
[0006] しかし、米国特許第 6204139号に開示されている素子は、温度の上昇に伴ってその 抵抗変化特性が劣化する課題を有している。例えば、当該特許における発明者の一 人で teる グナシェフ (Ignatievノ【 、 In Proceedings of 15th International bvmposium on Integrated Ferroelectronics (ISIF 2003), p.584— 585 (2003)において、米国特許第 6204139号に開示されて 、る素子と同様の構成を有する素子の抵抗変化率が、 100 °C付近で減少することを報告して 、る。 [0006] However, the element disclosed in US Pat. No. 6,204,139 has a problem that its resistance change characteristic deteriorates as the temperature rises. For example, one of the inventors in the patent, te Gunashev (Ignatiev [In Proceedings of 15th International bvmposium on Integrated Ferroelectronics (ISIF 2003), p. 584—585 (2003), the resistance change rate of an element having the same structure as that of the element disclosed in US Pat. No. 6,204,139 decreases near 100 ° C. I will report that.
[0007] メモリセルをはじめとする電子デバイスは幅広い用途における使用が想定されるた め、当該デバイスに組み込まれる素子には、デバイスが使用される環境温度の変化 に対応できることが求められる。例えば、電子デバイスの耐熱環境試験法を定める JI S (曰本工業規格)。60068— 2— 2 : 1995 (旧 JIS C0021: 1995)には、 200。Cの 耐熱性が規定されており、上述した、 100°C付近の温度領域で抵抗変化特性が劣化 する素子を市販のデバイスに用いることは困難である。  [0007] Since electronic devices such as memory cells are expected to be used in a wide range of applications, elements incorporated in the device are required to be able to cope with changes in environmental temperature in which the device is used. For example, JIS (Enomoto Industrial Standard) that defines the heat resistance environment test method for electronic devices. 60068— 2—2: 1995 (former JIS C0021: 1995), 200. The heat resistance of C is specified, and it is difficult to use the above-mentioned element whose resistance change characteristic deteriorates in the temperature range near 100 ° C as a commercially available device.
[0008] そこで本発明は、従来の素子に比べて、昇温時における抵抗変化特性の劣化が抑 制された、耐熱性に優れる抵抗変化素子と、その製造方法とを提供することを目的と する。  Accordingly, an object of the present invention is to provide a resistance change element having excellent heat resistance in which deterioration of resistance change characteristics at the time of temperature rise is suppressed as compared with a conventional element, and a method for manufacturing the resistance change element. To do.
[0009] なお、本願と密接に関連する文献として米国特許第 6972238号 (特開 2004-349690 号公報と同一内容)を挙げることができる。この文献に開示されている技術的内容と 本発明との差違は、発明を実施するための最良の形態の欄で述べる。  [0009] Note that US Pat. No. 6,972,238 (the same content as JP-A-2004-349690) can be cited as a document closely related to the present application. Differences between the technical contents disclosed in this document and the present invention will be described in the section of the best mode for carrying out the invention.
発明の開示  Disclosure of the invention
[0010] 本発明の抵抗変化素子は、基板と前記基板上に配置された多層構造体とを含み、 前記多層構造体が、上部電極および下部電極と、前記上部電極と前記下部電極と の間に配置された抵抗変化層とを含み、前記上部電極と前記下部電極との間の電 気抵抗値が異なる 2以上の状態が存在し、前記上部電極と前記下部電極との間に所 定の電気パルスを印加することにより、前記 2以上の状態力 選ばれる 1つの状態か ら他の状態へと変化する素子である。ここで、前記抵抗変化層が、式 (Pr, Ca) MnO xlにより示される組成を有し、前記多層構造体が、前記上部電極および前記下部電 極力ゝら選ばれる少なくとも 1つの電極と、前記抵抗変化層との間に配置された、式 (Pr , Ca) MnO により示される組成を有する酸素欠損層をさらに含む。ただし、 xlおよ x2  [0010] The resistance change element of the present invention includes a substrate and a multilayer structure disposed on the substrate, and the multilayer structure includes an upper electrode and a lower electrode, and between the upper electrode and the lower electrode. There are two or more states in which the electric resistance value between the upper electrode and the lower electrode is different, and a predetermined value is provided between the upper electrode and the lower electrode. It is an element that changes from one state selected from the two or more state forces to another state by applying an electric pulse. Here, the variable resistance layer has a composition represented by the formula (Pr, Ca) MnO xl, and the multilayer structure includes at least one electrode selected from the upper electrode and the lower electrode force, and the It further includes an oxygen-deficient layer having a composition represented by the formula (Pr, Ca) MnO and disposed between the resistance change layer. However, xl and x2
び x2は、それぞれ、 0く xl≤3、 0く x2く 3、および、 x2く xlを満たす数値である。  And x2 are numerical values satisfying 0 <xl≤3, 0 <x2 <3, and x2 <xl.
[0011] 本発明の抵抗変化素子では、上記酸素欠損層により、昇温時における素子の抵抗 変化特性の劣化を抑制でき、従来の抵抗変化素子よりも耐熱性に優れる素子とする ことができる。 In the resistance change element of the present invention, the oxygen deficient layer can suppress deterioration of the resistance change characteristic of the element at the time of temperature rise, and is an element having higher heat resistance than the conventional resistance change element. be able to.
[0012] 本発明の抵抗変化素子の製造方法 (第 1の製造方法)は、上記本発明の抵抗変化 素子の製造方法であって、基板上に下部電極を形成する下部電極形成工程と、前 記下部電極上に、式 (Pr, Ca) MnO により示される組成を有する抵抗変化層を形  The variable resistance element manufacturing method (first manufacturing method) of the present invention is the above variable resistance element manufacturing method of the present invention, comprising: a lower electrode forming step of forming a lower electrode on a substrate; A variable resistance layer having a composition represented by the formula (Pr, Ca) MnO is formed on the lower electrode.
xl  xl
成する抵抗変化層形成工程と、前記抵抗変化層上に、式 (Pr, Ca) MnO により示さ れる組成を有する酸素欠損層を形成する酸素欠損層形成工程と、前記抵抗変化層 および酸素欠損層を前記下部電極とともに狭持する上部電極を形成する上部電極 形成工程とを、順に有する製造方法である。ただし、 xlおよび x2は、それぞれ、 0< xl≤3、 0く x2く 3、および、 x2く xlを満たす数値である。  Forming a variable resistance layer, forming an oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO on the variable resistance layer, and forming the variable resistance layer and the oxygen deficient layer. And an upper electrode forming step of forming an upper electrode sandwiching the lower electrode together with the lower electrode. However, xl and x2 are numerical values satisfying 0 <xl≤3, 0 <x2 <3, and x2 <xl, respectively.
[0013] 本発明の抵抗変化素子の製造方法 (第 2の製造方法)は、上記本発明の抵抗変化 素子の製造方法であって、基板上に下部電極を形成する下部電極形成工程と、前 記下部電極上に、式 (Pr, Ca) MnO により示される組成を有する酸素欠損層を形 成する酸素欠損層形成工程と、前記酸素欠損層上に、式 (Pr, Ca) MnO により示さ [0013] A variable resistance element manufacturing method (second manufacturing method) according to the present invention is the above variable resistance element manufacturing method according to the present invention, comprising: a lower electrode forming step of forming a lower electrode on a substrate; An oxygen deficient layer forming step for forming an oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO on the lower electrode, and a formula (Pr, Ca) MnO represented on the oxygen deficient layer.
xl  xl
れる組成を有する抵抗変化層を形成する抵抗変化層形成工程と、前記酸素欠損層 および抵抗変化層を前記下部電極とともに狭持する上部電極を形成する上部電極 形成工程とを、順に有する製造方法である。ただし、 xlおよび χ2は、それぞれ、 0< xl≤3、 0く χ2く 3、および、 χ2く xlを満たす数値である。  A variable resistance layer forming step for forming a variable resistance layer having a composition, and an upper electrode forming step for forming an upper electrode for sandwiching the oxygen deficient layer and the variable resistance layer together with the lower electrode. is there. However, xl and χ2 are numerical values satisfying 0 <xl≤3, 0 <χ2 <3, and χ2 <xl, respectively.
図面の簡単な説明  Brief Description of Drawings
[0014] [図 1]図 1は、本発明の抵抗変化素子の一例を模式的に示す断面図である。 FIG. 1 is a cross-sectional view schematically showing an example of a variable resistance element according to the present invention.
[図 2]図 2は、本発明の抵抗変化素子の別の一例を模式的に示す断面図である。  FIG. 2 is a cross-sectional view schematically showing another example of the variable resistance element of the present invention.
[図 3]図 3は、本発明の抵抗変化素子のまた別の一例を模式的に示す断面図である  FIG. 3 is a cross-sectional view schematically showing another example of the variable resistance element of the present invention.
[図 4]図 4は、本発明の抵抗変化素子を備える抵抗変化型メモリの一例を示す模式図 である。 FIG. 4 is a schematic diagram showing an example of a resistance change type memory including the resistance change element of the present invention.
[図 5A]図 5Aは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 5A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 5B]図 5Bは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。 [図 5C]図 5Cは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。 FIG. 5B is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention. [FIG. 5C] FIG. 5C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 5D]図 5Dは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 5D is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 5E]図 5Eは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 5E is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 5F]図 5Fは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 5F] FIG. 5F is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 6A]図 6Aは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 6A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 6B]図 6Bは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 6B is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 6C]図 6Cは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 6C] FIG. 6C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 6D]図 6Dは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 6D] FIG. 6D is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 6E]図 6Eは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 6E] FIG. 6E is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 6F]図 6Fは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 6F] FIG. 6F is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 6G]図 6Gは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 6G] FIG. 6G is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 7A]図 7Aは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 7A is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 7B]図 7Bは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  FIG. 7B is a process diagram schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 7C]図 7Cは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。 [図 7D]図 7Dは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。 [FIG. 7C] FIG. 7C is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention. FIG. 7D is a process diagram schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 7E]図 7Eは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 7E] FIG. 7E is a process chart schematically showing an example of a method of manufacturing a variable resistance element according to the present invention.
[図 7F]図 7Fは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 7F] FIG. 7F is a process chart schematically showing an example of the method of manufacturing a resistance change element according to the present invention.
[図 7G]図 7Gは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 7G] FIG. 7G is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 7H]図 7Hは、本発明の抵抗変化素子の製造方法の一例を模式的に示す工程図 である。  [FIG. 7H] FIG. 7H is a process chart schematically showing an example of a method of manufacturing a resistance change element according to the present invention.
[図 8]図 8は、従来の抵抗変化素子の一例を模式的に示す断面図である。  FIG. 8 is a cross-sectional view schematically showing an example of a conventional variable resistance element.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0015] 本発明の抵抗変化素子では、前記抵抗変化層が、式 (Pr, Ca) MnOにより示され In the variable resistance element of the present invention, the variable resistance layer is represented by the formula (Pr, Ca) MnO.
3  Three
る組成を有していてもよい。  It may have a composition.
[0016] 本発明の抵抗変化素子では、前記酸素欠損層と前記抵抗変化層とが、互いに接し ていてもよぐ前記酸素欠損層と前記少なくとも 1つの電極とが、互いに接していても よい。 In the variable resistance element of the present invention, the oxygen deficient layer and the variable resistance layer may be in contact with each other, and the oxygen deficient layer and the at least one electrode may be in contact with each other.
[0017] 本発明の抵抗変化素子では、前記多層構造体が、 Pr、 Caおよび Mnを含む酸ィ匕 物層として、前記酸素欠損層および前記抵抗変化層のみを含んでいてもよい。  In the variable resistance element of the present invention, the multilayer structure may include only the oxygen deficient layer and the variable resistance layer as an oxide layer containing Pr, Ca, and Mn.
[0018] 本発明の抵抗変化素子では、前記多層構造体が、前記酸素欠損層、前記抵抗変 化層、前記上部電極および前記下部電極からなってもょ ヽ。  [0018] In the resistance change element of the present invention, the multilayer structure may include the oxygen deficient layer, the resistance change layer, the upper electrode, and the lower electrode.
[0019] 本発明の抵抗変化素子では、前記酸素欠損層が、式 Pr Ca MnO により示され p 1-p x2  In the resistance change element of the present invention, the oxygen deficient layer is represented by the formula Pr Ca MnO and p 1-p x2
る組成を有していてもよい。ただし、 pは、 0. 6以上 0. 8以下である。  It may have a composition. However, p is 0.6 or more and 0.8 or less.
[0020] 本発明の抵抗変化素子では、前記抵抗変化層力 式 Pr Ca MnO により示され p 1-p xl [0020] In the resistance change element of the present invention, p 1-p xl is expressed by the resistance change layer force formula Pr Ca MnO.
る組成を有していてもよい。ただし、 pは、 0. 6以上 0. 8以下である。  It may have a composition. However, p is 0.6 or more and 0.8 or less.
[0021] 本発明の第 1の製造方法では、 xl = 3であってもよい。 In the first manufacturing method of the present invention, xl = 3 may be satisfied.
[0022] 本発明の第 1の製造方法では、前記酸素欠損層形成工程において、前記酸素欠 損層が、前記抵抗変化層の表面を逆スパッタリングすることにより形成されてもよい。 このとき、 xl = 3であってもよい。また、前記下部電極に接するように前記抵抗変化層 を形成し、前記抵抗変化層の表面に形成した前記酸素欠損層に接するように、前記 上部電極を形成してもよい。 In the first manufacturing method of the present invention, in the oxygen deficient layer forming step, the oxygen deficient layer may be formed by reverse sputtering the surface of the variable resistance layer. At this time, xl = 3 may be satisfied. Further, the variable resistance layer may be formed in contact with the lower electrode, and the upper electrode may be formed in contact with the oxygen deficient layer formed on the surface of the variable resistance layer.
[0023] 本発明の第 1の製造方法では、前記酸素欠損層形成工程において、前記酸素欠 損層が、前記抵抗変化層の表面を非酸ィ匕性雰囲気下にて熱処理することにより形成 されてもよい。このとき、 xl = 3であってもよい。また、前記下部電極に接するように前 記抵抗変化層を形成し、前記抵抗変化層の表面に形成した前記酸素欠損層に接す るように、前記上部電極を形成してもよい。  In the first production method of the present invention, in the oxygen deficient layer forming step, the oxygen deficient layer is formed by heat-treating the surface of the variable resistance layer in a non-oxidizing atmosphere. May be. At this time, xl = 3 may be satisfied. The resistance change layer may be formed so as to be in contact with the lower electrode, and the upper electrode may be formed so as to be in contact with the oxygen deficient layer formed on the surface of the resistance change layer.
[0024] 本発明の第 1の製造方法では、前記抵抗変化層形成工程における雰囲気が有す る不活性ガスの分圧 P 比 (P  In the first manufacturing method of the present invention, the partial pressure P ratio (P
inertと酸素の分圧 P )  inert and partial pressure of oxygen P)
oxyとの /P  / P with oxy
oxy inert が、前記酸素欠損層 形成工程における雰囲気が有する当該比 (P /P )よりも大きくてもよい。  Oxy inert may be larger than the ratio (P / P) of the atmosphere in the oxygen deficient layer forming step.
oxy inert  oxy inert
[0025] 本発明の第 1の製造方法では、前記抵抗変化層形成工程において、前記抵抗変 化層がスパッタリングにより形成され、前記酸素欠損層形成工程において、前記酸素 欠損層がスパッタリングにより形成されてもよい。  [0025] In the first manufacturing method of the present invention, in the variable resistance layer forming step, the variable resistance layer is formed by sputtering, and in the oxygen deficient layer forming step, the oxygen deficient layer is formed by sputtering. Also good.
[0026] 本発明の第 2の製造方法では、前記抵抗変化層形成工程における雰囲気が有す る不活性ガスの分圧 P (P /P )  In the second production method of the present invention, the partial pressure P (P / P) of the inert gas that the atmosphere in the variable resistance layer forming step has
inertと酸素の分圧 P  inert and partial pressure of oxygen P
oxyとの比  Ratio with oxy
oxy inert が、前記酸素欠損層 形成工程における雰囲気が有する当該比 (P /P )よりも大きくてもよい。  Oxy inert may be larger than the ratio (P / P) of the atmosphere in the oxygen deficient layer forming step.
oxy inert  oxy inert
[0027] 本発明の第 2の製造方法では、前記酸素欠損層形成工程において、前記酸素欠 損層がスパッタリングにより形成され、前記抵抗変化層形成工程において、前記抵抗 変化層がスパッタリングにより形成されてもよい。  In the second production method of the present invention, in the oxygen deficient layer forming step, the oxygen deficient layer is formed by sputtering, and in the variable resistance layer forming step, the variable resistance layer is formed by sputtering. Also good.
[0028] 以下、図面を参照しながら、本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0029] 図 1に示す抵抗変化素子 1は、基板 12と、下部電極 2および上部電極 4力 なる一 対の電極と、下部電極 2および上部電極 4により狭持された抵抗変化層 3とを含んで いる。また素子 1では、上部電極 4と抵抗変化層 3との間に、抵抗変化層 3と同様に Pr (プラセォジゥム)、 Ca (カルシウム)および Mn (マンガン)を含む酸化物力もなるが、 抵抗変化層 3とはその組成が異なる酸素欠損層 5が配置されている。下部電極 2、抵 抗変化層 3、酸素欠損層 5および上部電極 4は、多層構造体 (積層体) 11として、上 記順に基板 12上に配置されている。 [0030] 抵抗変化層 3は、式 (Pr, Ca) MnO により示される組成 Aを有し、酸素欠損層 5は A resistance change element 1 shown in FIG. 1 includes a substrate 12, a pair of electrodes having a lower electrode 2 and an upper electrode 4, and a resistance change layer 3 sandwiched between the lower electrode 2 and the upper electrode 4. Contains. In addition, in the element 1, an oxide force including Pr (prasedium), Ca (calcium), and Mn (manganese) is provided between the upper electrode 4 and the resistance change layer 3 in the same manner as the resistance change layer 3. An oxygen-deficient layer 5 having a composition different from that of 3 is arranged. The lower electrode 2, the resistance change layer 3, the oxygen deficient layer 5, and the upper electrode 4 are arranged on the substrate 12 in the above order as a multilayer structure (laminated body) 11. The resistance change layer 3 has a composition A represented by the formula (Pr, Ca) MnO, and the oxygen deficient layer 5
xl  xl
、式(Pr, Ca) MnO により示される糸且成 Bを有する。ここで、 xlおよび x2は、それぞ れ、 0<xl≤3、 0<x2< 3、 x2く xlを満たす数値であり、酸素欠損層 5は、抵抗変 化層 3よりも酸素の欠損率が大きい層であるといえる。抵抗変化層 3は、式 (Pr, Ca) MnOにより示される組成 (xl = 3)を有していてもよぐこの場合、当該組成は化学  The yarn has the formula B expressed by the formula (Pr, Ca) MnO. Here, xl and x2 are values satisfying 0 <xl≤3, 0 <x2 <3, x2 and xl, respectively, and the oxygen deficiency layer 5 has an oxygen deficiency rate higher than that of the resistance change layer 3. Can be said to be a large layer. The resistance change layer 3 may have a composition represented by the formula (Pr, Ca) MnO (xl = 3).
3  Three
量論比を満たしている。  It meets the stoichiometric ratio.
[0031] 糸且成 Aにおける Prおよび Caの分率と、糸且成 Bにおける当該分率とは同一であって も異なっていてもよいが、同一である場合、酸素欠損層 5は、抵抗変化層 3における 酸素の欠損率を増大させた層であるともいえる。  [0031] The fractions of Pr and Ca in the yarn and composition A and the fraction in the yarn and composition B may be the same or different, but if they are the same, the oxygen deficient layer 5 It can be said that this is a layer in which the oxygen deficiency rate in the change layer 3 is increased.
[0032] 素子 1には、下部電極 2と上部電極 4との間の電気抵抗値が異なる 2以上の状態が 存在し、所定の電気パルスを素子 1に、具体的には下部電極 2と上部電極 4との間に 、印加することにより、素子 1は、上記 2以上の状態力 選ばれる 1つの状態力 他の 状態へ変化する。素子 1に電気抵抗値が異なる 2つの状態 (相対的に高抵抗の状態 A、および、相対的に低抵抗の状態 B)が存在する場合、所定の電気パルスの印加 により、素子 1は、状態 Aから状態 Bへ、あるいは、状態 Bから状態 Aへと変化する。所 定の電気パルスは、抵抗変化層 3へ印加して 、るとも 、える。  [0032] In element 1, there are two or more states in which the electric resistance value between lower electrode 2 and upper electrode 4 is different, and a predetermined electric pulse is applied to element 1, specifically, lower electrode 2 and upper electrode 4. By applying between the electrode 4 and the electrode 4, the element 1 changes to one state force selected from the above-described two or more state forces to another state. If element 1 has two states with different electrical resistance values (relatively high resistance state A and relatively low resistance state B), device 1 will be in the state by applying a predetermined electrical pulse. Change from A to state B, or from state B to state A. The predetermined electric pulse is applied to the resistance change layer 3 and can be obtained.
[0033] このような抵抗変化素子 1とすることにより、昇温時における素子の抵抗変化特性の 劣化を抑制できる。換言すれば、素子 1は従来の抵抗変化素子よりも耐熱性に優れ ており、その程度は素子 1の構成にもよるが、例えば後述する実施例に示すように、 2 00°Cにおいても室温(25°C)とほぼ同等の抵抗変化率を保持できる。素子 1の抵抗 変化率の具体的な値は、素子 1の構成にもよる力 例えば、 600%以上である。なお 、抵抗変化率とは、素子の抵抗変化特性の指標となる数値であり、具体的には、素 子が示す最大電気抵抗値を R  [0033] By adopting such a resistance change element 1, it is possible to suppress the deterioration of the resistance change characteristic of the element at the time of temperature rise. In other words, the element 1 has better heat resistance than the conventional resistance change element, and the degree depends on the configuration of the element 1, but as shown in the examples described later, for example, even at 200 ° C., It can maintain a resistance change rate almost equal to (25 ° C). The specific value of the resistance change rate of the element 1 is a force depending on the configuration of the element 1, for example, 600% or more. The resistance change rate is a numerical value that serves as an index of the resistance change characteristic of the element. Specifically, the maximum electric resistance value indicated by the element is R
MAX、最小電気抵抗値を R MAX, minimum electrical resistance R
INとしたときに、式 (R — R  When IN, the expression (R — R
MAX  MAX
) /R X 100 (%)により求められる値である。  ) / R X 100 (%).
[0034] 酸素欠損層 5と抵抗変化層 3とは、必ずしも接していなくてもよぐ例えば、両者の間 に任意の層が配置されていてもよいが、図 1に示すように、両者が互いに接すること が好ましい。酸素欠損層 5と上部電極 4との関係についても同様に、両者の間に任意 の層が配置されていてもよいが、両者が互いに接することが好ましい。酸素欠損層 5 と抵抗変化層 3とが互いに接する場合、両者の境界は必ずしも明瞭でなくてもよい。 [0034] The oxygen deficient layer 5 and the resistance change layer 3 are not necessarily in contact. For example, an arbitrary layer may be disposed between the two, but as shown in FIG. It is preferable that they touch each other. Similarly, regarding the relationship between the oxygen deficient layer 5 and the upper electrode 4, an arbitrary layer may be disposed between the two, but it is preferable that the two are in contact with each other. Oxygen deficient layer 5 And the resistance change layer 3 are in contact with each other, the boundary between them may not necessarily be clear.
[0035] 図 1に示す積層体 11は、下部電極 2、上部電極 4、抵抗変化層 3および酸素欠損 層 5からなる力 積層体 11は上記各層以外の任意の層を含んでいてもよい。このとき 、積層体 11が、 Pr、 Caおよび Mnを含む酸ィ匕物層として、上述した組成 Aおよび組 成 Bをそれぞれ有する、抵抗変化層 3および酸素欠損層 5のみを含むことが好ましい A laminated body 11 shown in FIG. 1 may include a force laminated body 11 including a lower electrode 2, an upper electrode 4, a resistance change layer 3, and an oxygen deficient layer 5, and may include any layer other than the above layers. At this time, it is preferable that the laminate 11 includes only the resistance change layer 3 and the oxygen deficient layer 5 having the above-described composition A and composition B, respectively, as the oxide layer containing Pr, Ca, and Mn.
[0036] 図 2に、本発明の抵抗変化素子 1の別の一例を示す。図 2に示す素子 1では、酸素 欠損層 5が、下部電極 2と抵抗変化層 3との間に配置されており、下部電極 2、酸素 欠損層 5、抵抗変化層 3および上部電極 4は、積層体 11として、上記順に基板 12上 に配置されている。このような抵抗変化素子 1とすることによつても、昇温時における 素子の抵抗変化特性の劣化を抑制できる。 FIG. 2 shows another example of the resistance change element 1 of the present invention. In the element 1 shown in FIG. 2, the oxygen deficient layer 5 is disposed between the lower electrode 2 and the resistance change layer 3, and the lower electrode 2, the oxygen deficient layer 5, the resistance change layer 3 and the upper electrode 4 are The laminated body 11 is arranged on the substrate 12 in the above order. By adopting such a resistance change element 1, it is possible to suppress the deterioration of the resistance change characteristic of the element at the time of temperature rise.
[0037] 酸素欠損層 5と下部電極 2とは、必ずしも接していなくてもよぐ例えば、両者の間に 任意の層が配置されていてもよいが、図 2に示すように、両者が互いに接することが 好ましい。  [0037] The oxygen deficient layer 5 and the lower electrode 2 are not necessarily in contact with each other. For example, an arbitrary layer may be disposed between the two, but as shown in FIG. It is preferable to touch.
[0038] 図 3に、本発明の抵抗変化素子 1のまた別の一例を示す。図 3に示す素子 1では、 2つの酸素欠損層 5a、 5b力 下部電極 2と抵抗変化層 3との間、および、上部電極 4 と抵抗変化層 3との間に、それぞれ配置されている。図 3に示す素子 1では、下部電 極 2、酸素欠損層 5a、抵抗変化層 3、酸素欠損層 5bおよび上部電極 4は、積層体 11 として、上記順に基板 12上に配置されている。このような抵抗変化素子 1とすることに よっても、昇温時における素子の抵抗変化特性の劣化を抑制できる。  FIG. 3 shows another example of the variable resistance element 1 of the present invention. In the element 1 shown in FIG. 3, the two oxygen deficient layers 5a and 5b are disposed between the lower electrode 2 and the resistance change layer 3, and between the upper electrode 4 and the resistance change layer 3, respectively. In the element 1 shown in FIG. 3, the lower electrode 2, the oxygen deficient layer 5a, the resistance change layer 3, the oxygen deficient layer 5b, and the upper electrode 4 are arranged on the substrate 12 as the stacked body 11 in the order described above. By adopting such a resistance change element 1, it is possible to suppress the deterioration of the resistance change characteristic of the element at the time of temperature rise.
[0039] 抵抗変化層 3は、上記組成 Aを満たしていればよぐ例えば、式 Pr Ca MnO (0 p 1-p xl The resistance change layer 3 only needs to satisfy the above composition A. For example, the formula Pr Ca MnO (0 p 1-p xl
. 6≤p≤0. 8)により示される糸且成を有していればよい。 6≤p≤0. 8) It is sufficient to have the thread and the condition indicated by 8).
[0040] 酸素欠損層 5は、上記糸且成 Bを満たしていればよぐ例えば、式 Pr Ca MnO (0 p 1-p x2[0040] The oxygen-deficient layer 5 only needs to satisfy the above-mentioned yarn composition B. For example, the formula Pr Ca MnO (0 p 1-p x2
. 6≤p≤0. 8)により示される糸且成を有していればよい。 6≤p≤0. 8) It is sufficient to have the thread and the condition indicated by 8).
[0041] 抵抗変化層 3および酸素欠損層 5の糸且成は、例えば、ォージェ電子分光法などの 分析手法により評価すればよい。 [0041] The yarn formation of the resistance change layer 3 and the oxygen deficient layer 5 may be evaluated by an analytical method such as Auger electron spectroscopy.
[0042] 下部電極 2は、導電性を有していればよぐ代表的には金属力 なり、例えば、 Pt ( プラチナ)、 Ir (イリジウム)や、これらの合金など力もなればよい。 [0043] 下部電極 2は、その表面に抵抗変化層 3および Zまたは酸素欠損層 5が結晶化成 長可能である材料力もなることが好ましい。この場合、安定した結晶構造を有する抵 抗変化層 3および Zまたは酸素欠損層 5を下部電極 2上へ形成でき、また、下部電 極 2上への抵抗変化層 3および Zまたは酸素欠損層 5の形成がより容易となる。この ような下部電極 2として、例えば、 SrRuO 、 SrTiO、あるいは、 Nb、 Crおよび Laから [0042] The lower electrode 2 is typically metallic if it has electrical conductivity. For example, Pt (platinum), Ir (iridium), and alloys thereof may be used. [0043] It is preferable that the lower electrode 2 also has a material force capable of crystallizing the variable resistance layer 3 and the Z or oxygen deficient layer 5 on the surface thereof. In this case, the resistance change layer 3 and the Z or oxygen deficient layer 5 having a stable crystal structure can be formed on the lower electrode 2, and the resistance change layer 3 and the Z or oxygen deficient layer 5 on the lower electrode 2 can be formed. Can be formed more easily. As such a lower electrode 2, for example, from SrRuO, SrTiO, or Nb, Cr and La
3 3  3 3
選ばれる少なくとも 1種の元素がドープされた SrTiOなど、(Pr, Ca) MnOと同様の  Similar to (Pr, Ca) MnO, such as SrTiO doped with at least one selected element
3 3 結晶構造を有する導電性酸化物からなる電極が挙げられる。  3 3 An electrode made of a conductive oxide having a crystal structure can be mentioned.
[0044] 上部電極 4は、基本的に導電性を有して ヽればよぐ例えば、 Au (金)、 Pt (白金)、 Ru (ルテニウム)、 Ir (イリジウム)、 Ti (チタン)、 A1 (アルミニウム)、 Cu (銅)、 Ta (タン タル)や、これらの合金(例えば、イリジウム一タンタル合金 (Ir— Ta) )、酸ィ匕物(例え ば、スズ添加インジウム酸ィ匕物 (ITO) )、窒化物、フッ化物、炭化物、ホウ化物などか らなればよい。  [0044] The upper electrode 4 should basically have conductivity. For example, Au (gold), Pt (platinum), Ru (ruthenium), Ir (iridium), Ti (titanium), A1 (Aluminum), Cu (copper), Ta (tantalum), their alloys (eg, iridium-tantalum alloy (Ir—Ta)), oxides (eg, tin-doped indium oxides (ITO )), Nitrides, fluorides, carbides, borides and the like.
[0045] 基板 12は、基板 12上に積層体 11を配置できる限り特に限定されず、例えば、シリ コン (Si)基板や MgO基板であればよい。基板 12が Si基板である場合、本発明の抵 抗変化素子と半導体素子との組み合わせが容易となる。このとき、基板 12における 下部電極 2に接する表面が酸化されていてもよい、即ち、基板 12の表面に酸ィ匕膜が 形成されていてもよい。  The substrate 12 is not particularly limited as long as the multilayer body 11 can be disposed on the substrate 12, and may be, for example, a silicon (Si) substrate or an MgO substrate. When the substrate 12 is a Si substrate, the combination of the resistance change element of the present invention and the semiconductor element becomes easy. At this time, the surface of the substrate 12 in contact with the lower electrode 2 may be oxidized, that is, an oxide film may be formed on the surface of the substrate 12.
[0046] 本発明の抵抗変化素子の構成は、下部電極 2、抵抗変化層 3、酸素欠損層 5およ び上部電極 4を含む積層体 11が基板 12上に形成され、抵抗変化層 3が下部電極 2 および上部電極 4により狭持されており、酸素欠損層 5が、下部電極 2および上部電 極 4カゝら選ばれる少なくとも 1つの電極と抵抗変化層 3との間に配置されている限り、 特に限定されない。例えば、図 3に示すように、積層体 11が 2以上の酸素欠損層 5を 含んでもよいし、図示はしないが、積層体 11が 2以上の抵抗変化層 3を含んでもよい  [0046] The structure of the resistance change element of the present invention is such that a laminate 11 including a lower electrode 2, a resistance change layer 3, an oxygen deficient layer 5 and an upper electrode 4 is formed on a substrate 12, and the resistance change layer 3 is The oxygen deficient layer 5 is sandwiched between the lower electrode 2 and the upper electrode 4, and is arranged between at least one electrode selected from the lower electrode 2 and the upper electrode 4 and the resistance change layer 3. As long as it is not particularly limited. For example, as shown in FIG. 3, the stacked body 11 may include two or more oxygen-deficient layers 5, and although not illustrated, the stacked body 11 may include two or more resistance change layers 3.
[0047] 所定の電気パルスの印加により、素子 1における上記状態力 例えば状態 Aから状 態 Bへ変化するが、変化後の状態 Bは、素子 1に所定の電気パルスが再び印加され るまで保持され、当該電気パルスの印加により、例えば状態 B力 状態 Aへ、再び変 化する。ただし、素子 1に印加される所定の電気パルスは、素子 1が状態 Aにあるとき と、状態 Bにあるときとの間で必ずしも同一でなくてもよぐその大きさ、極性、パルス 形状などは、素子 1の状態により異なっていてもよい。即ち、本明細書における「所定 の電気パルス」とは、素子 1がある状態にあるときに、当該状態とは異なる他の状態へ 変化できる電気パルスであればょ 、。 [0047] By the application of a predetermined electric pulse, the state force in element 1 changes, for example, from state A to state B, but the changed state B is maintained until a predetermined electric pulse is applied to element 1 again. Then, by applying the electric pulse, for example, state B force state A is changed again. However, the predetermined electrical pulse applied to element 1 is when element 1 is in state A. The size, polarity, pulse shape, and the like that do not necessarily have to be the same between the state B and the state B may differ depending on the state of the element 1. That is, the “predetermined electric pulse” in this specification is an electric pulse that can change to another state different from the state when the element 1 is in a certain state.
[0048] このように、抵抗変化素子 1では、その電気抵抗値を、素子 1に所定の電気パルス を印加するまで保持できるため、素子 1と、素子 1における上記状態を検出する機構 、即ち、素子 1の電気抵抗値を検出する機構、とを組み合わせ、上記各状態に対して ビットを割り当てることにより、不揮発性の抵抗変化型メモリを構築できる。ビットの割り 当ては、例えば、状態 Aを「0」、状態 Bを「1」とすればよい。抵抗変化型メモリには、メ モリ素子の他に、 2以上のメモリ素子が配列したメモリアレイが含まれる。また、上記各 状態に対して ONまたは OFFを割り当てることにより、素子 1をスイッチング素子へ応 用することも可能である。  Thus, in the resistance change element 1, since the electric resistance value can be held until a predetermined electric pulse is applied to the element 1, a mechanism for detecting the state of the element 1 and the element 1, that is, A nonvolatile resistance change memory can be constructed by combining a mechanism for detecting the electric resistance value of the element 1 and assigning a bit to each of the above states. For the bit assignment, for example, state A may be “0” and state B may be “1”. The resistance change type memory includes a memory array in which two or more memory elements are arranged in addition to the memory elements. Also, by assigning ON or OFF to each of the above states, element 1 can be applied to a switching element.
[0049] 印加する電気パルスは、電圧(パルス電圧)であっても、電流(電流パルス)であつ てもよい。パルスの形状は特に限定されず、例えば、正弦波状、矩形波状および三 角波状力も選ばれる少なくとも 1つの形状であればよい。パルスの幅は、通常、数ナ ノ秒〜数ミリ秒の範囲である。  [0049] The electric pulse to be applied may be a voltage (pulse voltage) or a current (current pulse). The shape of the pulse is not particularly limited, and may be any shape as long as it is a sine wave shape, a rectangular wave shape, and a triangular wave force. The width of the pulse is usually in the range of a few nanoseconds to a few milliseconds.
[0050] 電気ノルスとしてノ ルス電圧を印加することが好ましぐこの場合、素子 1の微細化 や、素子 1を用いて構築した電子デバイスの小型化がより容易となる。上記状態 Aお よび状態 Bの 2つの状態が存在する素子 1の場合、下部電極 2と上部電極 4との間に 電位差を発生させる電位差印加機構を素子 1に接続し、例えば、下部電極 2の電位 に対して上部電極 4の電位が正となるようなバイアス電圧 (正バイアス電圧)を素子 1 に印加することにより、素子 1を状態 Aから状態 Bへと変化させ、下部電極 2の電位に 対して上部電極 4の電位が負となるようなノ ィァス電圧 (負バイアス電圧)を素子 1に 印加すること〖こより(即ち、状態 Aから状態 Bへの変化時とは極性を反転させた電圧を 印加することにより)、素子 1を状態 Bから状態 Aへと変化させてもよい。電位差印加 機構としては、例えば、パルスジェネレータを用いればよい。  [0050] In this case, it is preferable to apply a Nors voltage as the electrical norse. In this case, the element 1 can be miniaturized and the electronic device constructed using the element 1 can be more easily downsized. In the case of the element 1 in which the above two states A and B exist, a potential difference applying mechanism that generates a potential difference between the lower electrode 2 and the upper electrode 4 is connected to the element 1. By applying a bias voltage (positive bias voltage) that makes the potential of the upper electrode 4 positive with respect to the potential, the device 1 is changed from the state A to the state B, and the potential of the lower electrode 2 is On the other hand, a negative voltage (negative bias voltage) that causes the potential of the upper electrode 4 to be negative is applied to the element 1 (that is, the voltage with the polarity reversed when changing from state A to state B). Device 1 may be changed from state B to state A by applying. For example, a pulse generator may be used as the potential difference applying mechanism.
[0051] 本発明の抵抗変化素子を、半導体素子、例えば、ダイオード、 MOS電界効果トラ ンジスタ (MOS— FET)などのトランジスタなど、と組み合わせることにより、抵抗変化 型メモリを構築できる。 [0051] The resistance change element according to the present invention is combined with a semiconductor element, for example, a transistor such as a diode or a MOS field effect transistor (MOS-FET) to change the resistance. A type memory can be constructed.
[0052] 本発明の抵抗変化素子と MOS— FETとを組み合わせた、抵抗変化型メモリ(素子 )の一例を図 4に示す。  FIG. 4 shows an example of a resistance change memory (element) in which the resistance change element of the present invention and a MOS-FET are combined.
[0053] 図 4に示す抵抗変化型メモリ素子 31は、抵抗変化素子 1とトランジスタ 21とを備え ており、素子 1は、トランジスタ 21およびビット線 32と電気的に接続されている。トラン ジスタ 21のゲート電極はワード線 33に電気的に接続されており、トランジスタ 21にお ける残る 1つの電極は接地されている。このようなメモリ素子 31では、トランジスタ 21を スイッチング素子として、素子 1における上記状態の検出(即ち、素子 1の電気抵抗値 の検出)、および、素子 1への所定の電気ノ ルスの印加が可能となる。例えば、素子 1が、電気抵抗値が異なる 2つの状態をとる場合、図 4に示すメモリ素子 31を、 1ビット の抵抗変化型メモリ素子とすることができる。  A resistance change type memory element 31 shown in FIG. 4 includes a resistance change element 1 and a transistor 21, and the element 1 is electrically connected to the transistor 21 and the bit line 32. The gate electrode of the transistor 21 is electrically connected to the word line 33, and the remaining one electrode in the transistor 21 is grounded. In such a memory element 31, the transistor 21 can be used as a switching element to detect the above state in the element 1 (that is, to detect the electric resistance value of the element 1) and to apply a predetermined electrical noise to the element 1. It becomes. For example, when the element 1 takes two states having different electric resistance values, the memory element 31 shown in FIG. 4 can be a 1-bit resistance change memory element.
[0054] メモリ素子 31への情報の記録は、抵抗変化素子 1への所定の電気パルスの印加に より行えばよぐ素子 1に記録した情報の読出は、例えば、素子 1へ印加するパルス 電圧あるいは電流パルスの大きさを、記録時とは変化させることにより行えばよい。  [0054] Recording of information in the memory element 31 may be performed by applying a predetermined electric pulse to the resistance change element 1. Reading of information recorded in the element 1 may be performed by, for example, a pulse voltage applied to the element 1. Alternatively, the current pulse may be changed by changing the magnitude of the current pulse.
[0055] 例えば、素子 1が、ある閾値 (V )以上の大きさを有するパルス状の正バイアス電圧  [0055] For example, the element 1 has a pulsed positive bias voltage having a magnitude equal to or greater than a certain threshold value (V).
0  0
(SET電圧 V: I V I ≥V )の印加により、状態 Aから状態 Bへと変化し、ある閾値( s S 0  Applying (SET voltage V: I V I ≥V) changes from state A to state B, and a certain threshold (s S 0
V )以上の大きさを有するパルス状の負ノ ィァス電圧 (RESET電圧 V : V  V) pulse-like negative noise voltage (RESET voltage V: V
0, RS I RS I≥ 0, RS I RS I≥
V )の印加により、状態 B力も状態 Aへと変化するとする。 It is assumed that the state B force changes to the state A by applying V).
0,  0,
[0056] ここで、大きさが V未満の正バイアス電圧、あるいは、大きさが V未満の負バイアス  [0056] Here, a positive bias voltage having a magnitude of less than V or a negative bias having a magnitude of less than V
0 0'  0 0 '
電圧を素子 1に印加することにより、素子 1が有する電気抵抗値を、素子 1の電流出 力として検出できる。これら、素子 1の電気抵抗値を検出するために印加する電圧を READ電圧(V )とする。 READ電圧は、 SET電圧および RESET電圧と同様にパ By applying a voltage to element 1, the electrical resistance value of element 1 can be detected as the current output of element 1. A voltage applied to detect the electric resistance value of the element 1 is defined as a READ voltage (V). The READ voltage is the same as the SET voltage and RESET voltage.
E  E
ルス状であってもよぐパルス状の READ電圧とすることにより、メモリ素子 31におけ る消費電力の低減やスィッチング効率の向上を図ることができる。 READ電圧の印 加では、素子 1の状態は変化しないため、複数回 READ電圧を印加した場合におい ても、同一の電気抵抗値を検出できる。  By using a pulse-like READ voltage even if it is in the form of a pulse, power consumption in the memory element 31 can be reduced and switching efficiency can be improved. When the READ voltage is applied, the state of the element 1 does not change, so even when the READ voltage is applied multiple times, the same electric resistance value can be detected.
[0057] このように素子 1へのパルス電圧の印加により、メモリ素子 31への情報の記録およ び読出を行うことができ、読出によって得られる素子 1の出力電流の大きさは、素子 1 の状態に対応して異なる。ここで、相対的に出力電流の大きい状態を「1」、相対的に 出力電流が小さい状態を「0」とすれば、メモリ素子 31を、 SET電圧により情報「1」を 記録し、 RESET電圧により情報「0」を記録する (情報「1」を消去する)メモリ素子とす ることがでさる。 [0057] As described above, by applying the pulse voltage to the element 1, information can be recorded and read from the memory element 31, and the magnitude of the output current of the element 1 obtained by the reading is as follows. Different depending on the state. Here, if the relatively large output current is “1” and the relatively small output current is “0”, the memory device 31 records information “1” by the SET voltage, and the RESET voltage. Thus, the memory device can record information “0” (delete information “1”).
[0058] READ電圧の大きさは、 SET電圧および RESET電圧の大きさに対して、通常、 1 Z4〜1Z1000程度が好ましい。 SET電圧および RESET電圧の具体的な値は、抵 抗変化素子 1の構成にもよる力 通常、 0. 1V〜20Vの範囲であり、 1V〜12Vの範 囲が好ましい。  [0058] The magnitude of the READ voltage is usually preferably about 1 Z4 to 1Z1000 with respect to the magnitude of the SET voltage and the RESET voltage. Specific values of the SET voltage and the RESET voltage are forces depending on the configuration of the resistance change element 1. Usually, the voltage is in the range of 0.1V to 20V, and the range of 1V to 12V is preferable.
[0059] 本発明の抵抗変化素子は、例えば、以下に詳細を示す本発明の抵抗変化素子の 製造方法により形成できる。  The variable resistance element of the present invention can be formed, for example, by the method for manufacturing a variable resistance element of the present invention, which will be described in detail below.
[0060] 本発明の製造方法では、基板 12上に下部電極 2を形成した後に、形成した当該下 部電極 2上に、上記組成 Aを有する抵抗変化層 3および上記組成 Bを有する酸素欠 損層 5を形成する。形成する抵抗変化層 3の組成は、式 (Pr, Ca) MnOにより示され  In the manufacturing method of the present invention, after forming the lower electrode 2 on the substrate 12, the resistance change layer 3 having the composition A and the oxygen deficiency having the composition B are formed on the formed lower electrode 2. Layer 5 is formed. The composition of the variable resistance layer 3 to be formed is expressed by the formula (Pr, Ca) MnO.
3 る組成 (xl = 3)、即ち化学量論比を満たす組成、であってもよ!/ヽ。  3 composition (xl = 3), that is, a composition satisfying the stoichiometric ratio! / ヽ.
[0061] 下部電極 2上に抵抗変化層 3および酸素欠損層 5を形成する順序、下部電極 2上 に形成する抵抗変化層 3および酸素欠損層 5の数などは、得たい抵抗変化素子 1の 構成に応じて適宜設定すればよい。例えば、基板上に下部電極を形成する工程 (下 部電極形成工程)と、当該下部電極上に上記組成 Aを有する抵抗変化層を形成する 工程 (抵抗変化層形成工程)と、当該抵抗変化層上に上記組成 Bを有する酸素欠損 層を形成する工程 (酸素欠損層形成工程)と、抵抗変化層および酸素欠損層を下部 電極とともに狭持する上部電極を形成する工程 (上部電極形成工程)とを順に行って もよい (第 1の製造方法)。また例えば、下部電極形成工程と、当該下部電極上に上 記組成 Bを有する酸素欠損層を形成する工程 (酸素欠損層形成工程)と、当該酸素 欠損層上に上記組成 Aを有する抵抗変化層を形成する工程 (抵抗変化層形成工程 )と、上部電極形成工程とを順に行ってもよい (第 2の製造方法)。本発明の第 1およ び第 2の製造方法では、必要に応じ、上記各工程間に任意の工程が加えられてもよ い。 [0061] The order of forming the resistance change layer 3 and the oxygen deficiency layer 5 on the lower electrode 2, the number of the resistance change layers 3 and the oxygen deficiency layers 5 formed on the lower electrode 2, and the like are as follows. What is necessary is just to set suitably according to a structure. For example, a step of forming a lower electrode on the substrate (lower electrode forming step), a step of forming a resistance change layer having the composition A on the lower electrode (resistance change layer forming step), and the resistance change layer A step of forming an oxygen deficient layer having the above composition B (oxygen deficient layer forming step), a step of forming an upper electrode sandwiching the resistance change layer and the oxygen deficient layer together with the lower electrode (upper electrode forming step), May be performed in order (first manufacturing method). Further, for example, a lower electrode forming step, a step of forming an oxygen deficient layer having the above composition B on the lower electrode (oxygen deficient layer forming step), and a resistance change layer having the above composition A on the oxygen deficient layer The step of forming (resistance change layer forming step) and the upper electrode forming step may be sequentially performed (second manufacturing method). In the first and second production methods of the present invention, an optional step may be added between the above steps as necessary.
[0062] 下部電極 2、上部電極 4および抵抗変化層 3は、半導体の製造プロセスを応用し、 一般的な薄膜形成プロセスおよび微細加工プロセスにより形成すればょ 、。例えば 、パルスレーザーデポジション(PLD)、イオンビームデポジション(IBD)、クラスター イオンビーム、および RF、 DC、電子サイクロトン共鳴 (ECR)、ヘリコン、誘導結合プ ラズマ (ICP)、対向ターゲットなどの各種スパッタリング法、分子線ェピタキシャル法( MBE)、イオンプレーティング法などを用いればよい。これら PVD (Physical Vapor D eposition)法の他に、 CVD (Chemical Vapor Deposition)法、 MOCVD (Metal Organ ic Chemical Vapor Deposition)法、メッ3 r法、 MOD (Metal Organic Decomposition) 法、あるいは、ゾルゲル法などを用いてもよい。 [0062] The lower electrode 2, the upper electrode 4, and the resistance change layer 3 apply a semiconductor manufacturing process, If it is formed by a general thin film formation process and microfabrication process. For example, pulsed laser deposition (PLD), ion beam deposition (IBD), cluster ion beam, and various types such as RF, DC, electron cyclotron resonance (ECR), helicon, inductively coupled plasma (ICP), and opposed target Sputtering, molecular beam epitaxy (MBE), ion plating, or the like may be used. In addition to these PVD (Physical Vapor D eposition) method, CVD (Chemical Vapor Deposition) method, MOCVD (Metal Organ ic Chemical Vapor Deposition) method, message 3 r method, MOD (Metal Organic Decomposition) method, or a sol-gel method, etc. May be used.
[0063] 各層の微細加工には、例えば、半導体製造プロセスや磁性デバイス (GMRや TM Rなどの磁気抵抗素子など)製造プロセスに用いられるイオンミリング、 RIE (Reactive Ion Etching)、 FIB (Focused Ion Beam)などの物理的あるいは化学的エッチング法、 および、微細パターン形成のためのステッパー、 EB (Electron Beam)法などを用いた フォトリソグラフィー技術を組み合わせて用いればよい。各層の表面の平坦化には、 例えば、 CMP (Chemical Mechanical Polishing) ,クラスタ^——イオンビームエツチン グなどを用いればよい。 [0063] The microfabrication of each layer includes, for example, ion milling, RIE (Reactive Ion Etching), FIB (Focused Ion Beam) used in semiconductor manufacturing processes and magnetic device (such as magnetoresistive elements such as GMR and TMR) manufacturing processes. ) Or the like, and a photolithography technique using a stepper for forming a fine pattern, an electron beam (EB) method, or the like may be used in combination. For the planarization of the surface of each layer, for example, CMP (Chemical Mechanical Polishing), cluster ^ —— ion beam etching or the like may be used.
[0064] 後述する絶縁層の堆積方法、微細加工方法および平坦化方法についても同様で あり、本発明の抵抗変化素子を備えるメモリ素子、メモリアレイなどの電子デバイスも 、同様の方法により形成できる。  The same applies to an insulating layer deposition method, a microfabrication method, and a planarization method, which will be described later, and an electronic device such as a memory element or a memory array including the resistance change element of the present invention can be formed by the same method.
[0065] 酸素欠損層 5の形成方法は特に限定されないが、例えば、以下に示す方法を用い ればよい。  [0065] The method for forming the oxygen deficient layer 5 is not particularly limited, but for example, the following method may be used.
[0066] 方法 I 第 1の製造方法において、抵抗変化層 3を形成した後に、当該抵抗変化層 [0066] Method I In the first manufacturing method, after forming the resistance change layer 3, the resistance change layer
3の表面を逆スパッタリングすることにより、酸素欠損層 5を形成する。 The oxygen deficient layer 5 is formed by reverse sputtering the surface of 3.
[0067] このとき、抵抗変化層 3の組成は、式(Pr, Ca) MnOにより示される組成(xl = 3) At this time, the composition of the resistance change layer 3 is a composition represented by the formula (Pr, Ca) MnO (xl = 3).
3  Three
であってもよい。  It may be.
[0068] 方法 Iでは、互 、に接する抵抗変化層 3および酸素欠損層 5を形成できる。  [0068] In Method I, the resistance change layer 3 and the oxygen deficient layer 5 that are in contact with each other can be formed.
[0069] 方法 Iにおいて、下部電極 2に接するように抵抗変化層 3を形成し、抵抗変化層 3の 表面に形成した酸素欠損層 5に接するように上部電極 4をさらに形成すれば、図 1に 示す素子 1を形成できる。 [0070] 逆スパッタリングは一般的な方法に基づけばよぐ抵抗変化層 3をターゲットとしてス ノ ッタリングを行えばよい。このとき、抵抗変化層 3を構成する元素のうち、特に酸素 の脱離度が大きいため、抵抗変化層 3における逆スパッタリングした部分の酸素の欠 損率を増大させて酸素欠損層 5を形成できる。 In Method I, if the resistance change layer 3 is formed so as to be in contact with the lower electrode 2 and the upper electrode 4 is further formed so as to be in contact with the oxygen deficient layer 5 formed on the surface of the resistance change layer 3, FIG. Element 1 shown in Fig. 1 can be formed. [0070] Inverse sputtering may be performed by using the resistance change layer 3 as a target based on a general method. At this time, among the elements constituting the resistance change layer 3, the oxygen desorption degree is particularly large, so that the oxygen deficiency layer 5 can be formed by increasing the oxygen loss rate of the reverse-sputtered portion of the resistance change layer 3. .
[0071] 逆スパッタリングは、非酸化性雰囲気下、例えば、水素などの還元性ガス、および Zまたは、窒素、アルゴンなどの不活性ガスを含む雰囲気下、で行うことが好ましい。 また、逆スパッタリング時に抵抗変化層 3が過度にエッチングされることを抑制するた めに、投入するスパッタ電力を過度に大きくしないことが望まれる。形成する酸素欠 損層 5の厚さは、逆スパッタリングを実施する時間により制御できる。  [0071] The reverse sputtering is preferably performed in a non-oxidizing atmosphere, for example, in an atmosphere containing a reducing gas such as hydrogen and an inert gas such as Z or nitrogen or argon. Further, in order to prevent the resistance change layer 3 from being etched excessively at the time of reverse sputtering, it is desirable not to excessively increase the sputtering power to be input. The thickness of the oxygen-deficient layer 5 to be formed can be controlled by the time for performing reverse sputtering.
[0072] 方法 II 第 1の製造方法において、抵抗変化層 3を形成した後に、当該抵抗変化層 3の表面を非酸ィ匕性雰囲気下にて熱処理することにより、酸素欠損層 5を形成する。  Method II In the first manufacturing method, after the variable resistance layer 3 is formed, the oxygen deficient layer 5 is formed by heat-treating the surface of the variable resistance layer 3 in a non-acidic atmosphere. .
[0073] このとき、抵抗変化層 3の組成は、式(Pr, Ca) MnOにより示される組成(xl = 3)  At this time, the composition of the resistance change layer 3 is a composition represented by the formula (Pr, Ca) MnO (xl = 3).
3  Three
であってもよい。  It may be.
[0074] 方法 IIでは、互 ヽに接する抵抗変化層 3および酸素欠損層 5を形成できる。  In Method II, the resistance change layer 3 and the oxygen deficient layer 5 that are in contact with each other can be formed.
[0075] 方法 IIにおいて、下部電極 2に接するように抵抗変化層 3を形成し、抵抗変化層 3の 表面に形成した酸素欠損層 5に接するように上部電極 4をさらに形成すれば、図 1に 示す素子 1を形成できる。  In Method II, if the resistance change layer 3 is formed in contact with the lower electrode 2 and the upper electrode 4 is further formed in contact with the oxygen deficient layer 5 formed on the surface of the resistance change layer 3, FIG. Element 1 shown in Fig. 1 can be formed.
[0076] 熱処理は、非酸化性雰囲気下にて行う以外は、一般的な方法に基づいて行えばよ い。非酸化性雰囲気は、水素などの還元性ガス、および Zまたは、窒素、アルゴンな どの不活性ガスを含む雰囲気であればよい。上記熱処理では、抵抗変化層 3を構成 する元素のうち、特に酸素の脱離が促進されるため、抵抗変化層 3における熱処理し た部分の酸素の欠損率を増大させて酸素欠損層 5を形成できる。  [0076] The heat treatment may be performed based on a general method except that the heat treatment is performed in a non-oxidizing atmosphere. The non-oxidizing atmosphere may be an atmosphere containing a reducing gas such as hydrogen and an inert gas such as Z or nitrogen or argon. In the above heat treatment, among the elements constituting the resistance change layer 3, the desorption of oxygen is particularly promoted, so the oxygen deficiency rate of the heat-treated portion in the resistance change layer 3 is increased to form the oxygen deficiency layer 5. it can.
[0077] 熱処理の温度は、例えば、 500°C〜600°C程度であればよぐ熱処理の時間は、 形成したい酸素欠損層 5の厚さによっても異なるが、数分程度であればよい。抵抗変 化層 3全体に熱が伝わることによる、抵抗変化層 3全体の酸素の欠損率の増大を抑 制するために、速やかな昇温、および、熱処理後の降温が熱処理時に望まれる。  The temperature of the heat treatment is, for example, about 500 ° C. to 600 ° C. The time for the heat treatment may be about several minutes, although it depends on the thickness of the oxygen deficient layer 5 to be formed. In order to suppress an increase in the oxygen deficiency rate of the entire resistance change layer 3 due to heat being transferred to the entire resistance change layer 3, rapid temperature increase and temperature decrease after the heat treatment are desired during the heat treatment.
[0078] 方法 III 第 1および第 2の製造方法において、抵抗変化層形成工程における雰囲 気が有する不活性ガスの分圧 P と酸素の分圧 P との比 (P /P )を、酸素欠損 層形成工程における雰囲気が有する当該分圧比 (P /P )よりも大きくする。換言 oxy inert Method III In the first and second manufacturing methods, the ratio (P / P) between the partial pressure P of the inert gas and the partial pressure P of oxygen in the atmosphere in the variable resistance layer forming step is expressed as oxygen Deficiency The partial pressure ratio (P 1 / P 2) of the atmosphere in the layer forming process is increased. Oxy inert
すれば、方法 mは、各層を形成する雰囲気における酸素の分圧を変化させること〖こ より、相対的に酸素の欠損率が小さい抵抗変化層 3と、相対的に酸素の欠損率が大 きい酸素欠損層 5とを形成する方法であるといえる。抵抗変化層 3は、相対的に酸素 の分圧が大きい条件下で形成され、酸素欠損層 5は、相対的に酸素の分圧が小さい 条件下で形成される。  In this case, method m changes the partial pressure of oxygen in the atmosphere in which each layer is formed, so that the resistance change layer 3 having a relatively small oxygen deficiency rate and the oxygen deficiency rate is relatively large. It can be said that this is a method of forming the oxygen deficient layer 5. The resistance change layer 3 is formed under a condition where the partial pressure of oxygen is relatively large, and the oxygen deficient layer 5 is formed under a condition where the partial pressure of oxygen is relatively small.
[0079] 抵抗変化層 3および酸素欠損層 5を形成する手法は特に限定されないが、例えば [0079] The method of forming the resistance change layer 3 and the oxygen deficient layer 5 is not particularly limited.
、スパッタリング法であればよい。 Any sputtering method may be used.
[0080] 例えば、 RFマグネトロンスパッタリングを用いて抵抗変化層 3および酸素欠損層 5を 形成する場合、抵抗変化層 3を形成する際には、アルゴンと酸素との分圧比 (P /P oxy[0080] For example, when the resistance change layer 3 and the oxygen deficient layer 5 are formed using RF magnetron sputtering, when the resistance change layer 3 is formed, the partial pressure ratio between argon and oxygen (P / P oxy
) )を 0. 2〜0. 5程度 (条件 とし、酸素欠損層 5を形成する際には、当該分圧比を)) To about 0.2 to 0.5 (conditions, when forming the oxygen deficient layer 5, the partial pressure ratio is
Ar Ar
0. 04-0. 1程度 (条件 B)とすればよい。なお、これ以降、上記アルゴンと酸素との 分圧比を、単に、「0 ZAr」とも記す。  It should be around 0. 04-0. 1 (Condition B). Hereinafter, the partial pressure ratio between argon and oxygen is also simply referred to as “0 ZAr”.
2  2
[0081] 条件 Aにより抵抗変化層 3を形成している際に、条件 Bへ変化させることにより、形 成していた抵抗変化層 3に接するように酸素欠損層 5を形成できる。同様に、条件 B により酸素欠損層 5を形成している際に、条件 Aへ変化させることにより、形成してい た酸素欠損層 5に接するように抵抗変化層 3を形成できる。条件 Aある 、は条件 Bへ の変化は、連続的に行っても、断続的あるいは段階的に行ってもよい。  When the variable resistance layer 3 is formed under the condition A, the oxygen deficient layer 5 can be formed in contact with the formed variable resistance layer 3 by changing to the condition B. Similarly, when the oxygen deficient layer 5 is formed under the condition B, the resistance change layer 3 can be formed in contact with the formed oxygen deficient layer 5 by changing to the condition A. The change to condition A or condition B may be performed continuously, intermittently or stepwise.
[0082] 形成する抵抗変化層 3が、式 (Pr, Ca) MnOにより示される組成を有する場合、条  [0082] When the variable resistance layer 3 to be formed has a composition represented by the formula (Pr, Ca) MnO,
3  Three
件 Aは、 Pr、 Caおよび Mnを含む酸ィ匕物であって、化学量論比を満たす当該酸化物 を形成するために必要十分かつ過剰でない酸素を含む条件であり、条件 Bは、酸素 欠損を有する当該酸化物を形成する条件であるといえる。  Condition A is an oxide containing Pr, Ca, and Mn, and includes oxygen that is necessary and sufficient and not excessive to form the oxide satisfying the stoichiometric ratio. Condition B is oxygen It can be said that this is a condition for forming the oxide having defects.
[0083] 条件 Aおよび Bは、それぞれ、抵抗変化層 3および酸素欠損層 5を形成するための スパッタリングの条件であるともいえる。 [0083] Conditions A and B can be said to be sputtering conditions for forming the resistance change layer 3 and the oxygen deficient layer 5, respectively.
[0084] 本発明の製造方法の一例を、図 5A〜図 5Fに示す。 An example of the production method of the present invention is shown in FIGS. 5A to 5F.
[0085] 最初に、基板 12上に下部電極 2を形成する(図 5A)。基板 12における下部電極 2 が形成される面に酸化膜、例えば、基板 12が Si基板である場合には SiO膜、が形  First, the lower electrode 2 is formed on the substrate 12 (FIG. 5A). An oxide film is formed on the surface of the substrate 12 where the lower electrode 2 is formed, for example, an SiO film when the substrate 12 is a Si substrate.
2 成されていてもよい。 [0086] 次に、下部電極 2の露出面を含む全体に絶縁層 31を堆積させ(図 5B)、絶縁層 31 の一部に、下部電極 2へ通じるコンタクトホール 32を形成する(図 5C)。 2 It may be made. Next, an insulating layer 31 is deposited on the entire surface including the exposed surface of the lower electrode 2 (FIG. 5B), and a contact hole 32 leading to the lower electrode 2 is formed in a part of the insulating layer 31 (FIG. 5C). .
[0087] 次に、コンタクトホール 32内における下部電極 2の露出面に、下部電極 2との電気 的な接続が確保されるように酸素欠損層 5を形成した後、さらに抵抗変化層 3を形成 する(図 5D)。必要に応じて、図 5Eに示すように、形成した抵抗変化層 3の表面を平 坦化処理して、抵抗変化層 3を埋め込み処理してもよい。  Next, after forming the oxygen deficient layer 5 on the exposed surface of the lower electrode 2 in the contact hole 32 so as to ensure electrical connection with the lower electrode 2, the resistance change layer 3 is further formed. (Figure 5D). As necessary, as shown in FIG. 5E, the surface of the formed resistance change layer 3 may be flattened and the resistance change layer 3 may be embedded.
[0088] 酸素欠損層 5および抵抗変化層 3の形成方法は特に限定されず、例えば、スパッタ リング法を用い、条件 Bにより酸素欠損層 5を形成した後に、条件 Aにより抵抗変化層 3を形成すればよい。  [0088] The formation method of the oxygen deficient layer 5 and the resistance change layer 3 is not particularly limited. For example, after forming the oxygen deficient layer 5 under the condition B using the sputtering method, the resistance change layer 3 is formed according to the condition A. do it.
[0089] 次に、抵抗変化層 3との電気的な接続が確保されるように、抵抗変化層 3上へ上部 電極 4を形成して(図 5F)、図 2に示すような、抵抗変化層 3と下部電極 2との間に、両 層と接するように酸素欠損層 5が配置された抵抗変化素子 1が形成される。  Next, an upper electrode 4 is formed on the resistance change layer 3 so as to ensure electrical connection with the resistance change layer 3 (FIG. 5F), and resistance change as shown in FIG. Between the layer 3 and the lower electrode 2, the resistance change element 1 in which the oxygen deficient layer 5 is disposed so as to be in contact with both layers is formed.
[0090] 絶縁層 31は、素子 1における層間絶縁層としての役割を担っており、絶縁性材料、 例えば、 SiO、 Al Oなど、からなればよい。絶縁層 31は、レジスト材料であってもよ  The insulating layer 31 plays a role as an interlayer insulating layer in the element 1 and may be made of an insulating material such as SiO, Al 2 O, or the like. The insulating layer 31 may be a resist material.
2 2 3  2 2 3
ぐこの場合、スピンコーティングの手法により簡便に絶縁層 31を形成でき、また、起 伏を有する表面上への、自らの表面が平坦な絶縁層 31の形成が容易となる。  In this case, the insulating layer 31 can be easily formed by the spin coating method, and the insulating layer 31 having a flat surface can be easily formed on the surface having the undulations.
[0091] 本発明の製造方法の別の一例を、図 6A〜図 6Gに示す。 [0091] Another example of the production method of the present invention is shown in FIGS. 6A to 6G.
[0092] 最初に、基板 12上に下部電極 2を形成し(図 6A)、形成した下部電極 2の露出面を 含む全体に絶縁層 31を堆積させた後に(図 6B)、絶縁層 31の一部に、下部電極 2 へ通じるコンタクトホール 32を形成する(図 6C)。  [0092] First, the lower electrode 2 is formed on the substrate 12 (Fig. 6A), and the insulating layer 31 is deposited on the entire surface including the exposed surface of the formed lower electrode 2 (Fig. 6B). In part, a contact hole 32 leading to the lower electrode 2 is formed (FIG. 6C).
[0093] 次に、コンタクトホール 32内における下部電極 2の露出面に、下部電極 2との電気 的な接続が確保されるように、抵抗変化層 3を形成する(図 6D)。必要に応じて、図 6 Eに示すように、形成した抵抗変化層 3の表面を平坦化処理して、抵抗変化層 3を埋 め込み処理してもよい。  Next, the resistance change layer 3 is formed on the exposed surface of the lower electrode 2 in the contact hole 32 so as to ensure electrical connection with the lower electrode 2 (FIG. 6D). If necessary, as shown in FIG. 6E, the surface of the formed resistance change layer 3 may be flattened, and the resistance change layer 3 may be embedded.
[0094] 次に、抵抗変化層 3の表面に酸素欠損層 5を形成する(図 6F)。酸素欠損層 5の形 成方法は特に限定されず、例えば、抵抗変化層 3の表面を逆スパッタリング、または 、非酸化性雰囲気下にて熱処理すればよい。  Next, the oxygen deficient layer 5 is formed on the surface of the resistance change layer 3 (FIG. 6F). The formation method of the oxygen deficient layer 5 is not particularly limited, and for example, the surface of the resistance change layer 3 may be subjected to reverse sputtering or heat treatment in a non-oxidizing atmosphere.
[0095] 次に、酸素欠損層 5との電気的な接続が確保されるように、酸素欠損層 5上へ上部 電極 4を形成して(図 6G)、図 1に示すような、抵抗変化層 3と上部電極 4との間に、 両層と接するように酸素欠損層 5が配置された抵抗変化素子 1が形成される。 [0095] Next, in order to ensure electrical connection with the oxygen-deficient layer 5, an upper portion is formed on the oxygen-deficient layer 5. Electrode 4 is formed (FIG. 6G), and resistance change element 1 in which oxygen deficient layer 5 is disposed between resistance change layer 3 and upper electrode 4 so as to be in contact with both layers as shown in FIG. It is formed.
[0096] 本発明の製造方法のまた別の一例を、図 7A〜図 7Hに示す。  [0096] Another example of the production method of the present invention is shown in FIGS. 7A to 7H.
[0097] 最初に、基板 12上に下部電極 2を形成し(図 7A)、形成した下部電極 2上に、抵抗 変化層 3および酸素欠損層 5を順に形成する(図 7B〜C)。抵抗変化層 3および酸素 欠損層 5の形成方法は特に限定されず、例えば、スパッタリング法を用い、条件 Aに より抵抗変化層 3を形成した後に、条件 Bにより酸素欠損層 5を形成すればよい。また 例えば、抵抗変化層 3を形成した後に、抵抗変化層 3の表面を逆スパッタリング、また は、非酸化性雰囲気下にて熱処理して、酸素欠損層 5を形成してもよい。  First, the lower electrode 2 is formed on the substrate 12 (FIG. 7A), and the resistance change layer 3 and the oxygen deficient layer 5 are sequentially formed on the formed lower electrode 2 (FIGS. 7B to 7C). The formation method of the resistance change layer 3 and the oxygen deficiency layer 5 is not particularly limited. For example, after forming the resistance change layer 3 according to the condition A and using the sputtering method, the oxygen deficiency layer 5 may be formed according to the condition B. . Further, for example, the oxygen deficient layer 5 may be formed by forming the resistance change layer 3 and then subjecting the surface of the resistance change layer 3 to reverse sputtering or heat treatment in a non-oxidizing atmosphere.
[0098] 次に、酸素欠損層 5上に、酸素欠損層 5との電気的な接続が確保されるように上部 電極 4を形成し、積層体 11とする(図 7D)。次に、上部電極 4上における素子 1を構 成したい領域にレジスト 33を配置し(図 7E)、イオンミリングなどの微細加工手段によ り、積層体 11におけるレジスト 33により被覆されて 、な 、部分を除去する(図 7F)。  Next, the upper electrode 4 is formed on the oxygen deficient layer 5 so as to ensure electrical connection with the oxygen deficient layer 5 to form a laminate 11 (FIG. 7D). Next, a resist 33 is arranged on the upper electrode 4 in a region where the element 1 is to be formed (FIG. 7E), and is covered with the resist 33 in the laminate 11 by a fine processing means such as ion milling. Remove the part (Figure 7F).
[0099] 次に、下部電極 2、抵抗変化層 3、酸素欠損層 5および上部電極 4の露出面全体に 、絶縁層 31を堆積させた(図 7G)後に、レジスト 33をリフトオフして、図 1に示すような 、抵抗変化層 3と上部電極 4との間に、両層と接するように酸素欠損層 5が配置された 抵抗変化素子 1が形成される(図 7H)。  [0099] Next, after depositing an insulating layer 31 on the entire exposed surface of the lower electrode 2, the resistance change layer 3, the oxygen deficient layer 5, and the upper electrode 4 (FIG. 7G), the resist 33 is lifted off. As shown in FIG. 1, a resistance change element 1 in which an oxygen deficient layer 5 is disposed so as to be in contact with both layers is formed between the resistance change layer 3 and the upper electrode 4 (FIG. 7H).
[0100] 米国特許第 6972238号(特開 2004-349690号公報と同一内容)には、 PrCaMnO  [0100] US Patent No. 6972238 (same content as JP-A-2004-349690) includes PrCaMnO.
3 層を有する抵抗変化素子をアニーリングすることにより、酸素が豊富な PrCaMnO ( yl ylは 3より大きい)からなる領域と、酸素が少ない PrCaMnO (y2は 3未満)からなる y2  By annealing a variable resistance element with three layers, a region consisting of PrCaMnO rich in oxygen (yl yl is greater than 3) and a PrCaMnO low in oxygen (y2 is less than 3) y2
領域とに、当該 PrCaMnO層を変化させる技術が開示されている。当該文献に開示  A technique for changing the PrCaMnO layer in a region is disclosed. Disclosure in this document
3  Three
されている抵抗変化素子では、一方の領域は必ず PrCaMnO (ylは 3より大きい) yl  In the variable resistance element, one area is always PrCaMnO (yl is greater than 3) yl
からなり、他方の領域は必ず PrCaMnO (y2は 3未満)からなるから、添え字「yl」お y2  And the other region is always composed of PrCaMnO (y2 is less than 3), so the subscript “yl” and y2
よび「y2」がいずれも 3以下となることはあり得ない。従って、本発明の抵抗変化素子 のように、添え字「xl」が 0より大きく 3以下、添え字「x2」が 0より大きく 3未満であるこ とは、当該文献に開示もされていないし、示唆もされていない。寧ろ、当該文献では、 本発明の抵抗変化素子のように、添え字「xl」が 0より大きく 3以下、添え字「x2」が 0 より大きく 3未満であることを暗に否定して 、る。 実施例 Both “y2” and “y2” cannot be less than 3. Therefore, as in the variable resistance element of the present invention, the fact that the subscript “xl” is greater than 0 and less than or equal to 3 and the subscript “x2” is greater than 0 and less than 3 is not disclosed or suggested in the document. It has not been done. On the contrary, this document implicitly denies that the subscript “xl” is greater than 0 and less than 3, and the subscript “x2” is greater than 0 and less than 3, as in the variable resistance element of the present invention. . Example
[0101] 以下、実施例により、本発明をより詳細に説明する。本発明は、以下に示す実施例 に限定されない。  [0101] Hereinafter, the present invention will be described in more detail by way of examples. The present invention is not limited to the following examples.
[0102] (実施例 1)  [0102] (Example 1)
実施例 1では、図 6A〜図 6Gに示す方法により、図 1に示すような抵抗変化素子 1 を作製し、その抵抗変化特性の温度依存性を評価した。  In Example 1, a resistance change element 1 as shown in FIG. 1 was produced by the method shown in FIGS. 6A to 6G, and the temperature dependence of the resistance change characteristics was evaluated.
[0103] 最初に、 MgO基板 12の表面に、下部電極 2として Pt層(厚さ 200nm)を積層した。  [0103] First, a Pt layer (thickness: 200 nm) was laminated on the surface of the MgO substrate 12 as the lower electrode 2.
Pt層の積層は、 RFマグネトロンスパッタリング法により、圧力 lPaのアルゴン雰囲気 下において、基板の温度を室温(25°C)とし、投入する電力を 80Wとして行った。  The Pt layer was laminated by RF magnetron sputtering in an argon atmosphere at a pressure of 1 Pa, with the substrate temperature set to room temperature (25 ° C) and the input power set to 80W.
[0104] 次に、形成した Pt層の露出面を含む全体に、絶縁層 31として SiO層を堆積させた  [0104] Next, a SiO layer was deposited as the insulating layer 31 on the entire surface including the exposed surface of the formed Pt layer.
2  2
。 SiO層の堆積は、 RFマグネトロンスパッタリング法により、圧力 0. lPaのアルゴン . The SiO layer is deposited by RF magnetron sputtering with argon at a pressure of 0.1 lPa.
2 2
雰囲気下において、基板の温度を 100°Cとし、投入する電力を 100Wとして行った。  Under the atmosphere, the temperature of the substrate was set to 100 ° C., and the input power was set to 100 W.
[0105] 次に、 RIEにより、 SiO層の一部に、 Pt層へ通じるコンタクトホール 32 (直径 0. 5 μ [0105] Next, a contact hole 32 (diameter 0.5 μm) leading to the Pt layer was formed in part of the SiO layer by RIE.
2  2
m)を形成した。  m) was formed.
[0106] 次に、コンタクトホール 32内における Pt層の露出面に、抵抗変化層 3として Pr Ca  [0106] Next, on the exposed surface of the Pt layer in the contact hole 32, Pr Ca is formed as the resistance change layer 3.
0.7 0 0.7 0
MnO層(PCMO層:厚さ 300nm)を積層した。 PCMO層の積層は、式 Pr CaAn MnO layer (PCMO layer: thickness 300 nm) was stacked. Lamination of the PCMO layer has the formula Pr Ca
.3 3 0.7 0.3.3 3 0.7 0.3
MnOにより示される組成を有する酸ィ匕物をターゲットとし、 RFマグネトロンスパッタリTargeting an oxide having the composition indicated by MnO, RF magnetron sputtering
3 Three
ングにより、圧力 3Paの酸素 アルゴン混合雰囲気下 (分圧比 O ZArがおよそ 0. 2  In a mixed atmosphere of oxygen and argon at a pressure of 3 Pa (partial pressure ratio O ZAr is about 0.2
2  2
5)において、基板の温度を 700°Cとし、投入する電力を 80Wとして行った。積層した PCMO層の構造を、別途 X線回折測定により評価したところ、多結晶膜であることが 確認された。  In 5), the substrate temperature was set to 700 ° C and the input power was set to 80W. When the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, it was confirmed to be a polycrystalline film.
[0107] 次に、積層した PCMO層の表面を CMPにより平坦ィ匕処理し、コンタクトホール 32 内に埋め込んだ状態とした。  Next, the surface of the laminated PCMO layer was flattened by CMP and buried in the contact hole 32.
[0108] 次に、 PCMO層の表面を逆スパッタリングすることにより、 PCMO層における当該 表面を含む一部の酸素の欠損率を増大させて、酸素欠損層 5を形成した。逆スパッ タリングは、 RFマグネトロンスパッタリング法により、 PCMO層をターゲットとして、圧 力 5Paの水素雰囲気下において、基板の温度を 300°Cとし、投入する電力を 40Wと して行った。また、投入する逆スパッタ電圧の周波数を 100MHzとし、逆スパッタリン グの時間を 200秒、とした。 [0108] Next, the oxygen deficiency layer 5 was formed by reverse sputtering the surface of the PCMO layer to increase the oxygen deficiency rate of a part of the PCMO layer including the surface. Reverse sputtering was performed by RF magnetron sputtering with the PCMO layer as the target, the substrate temperature at 300 ° C, and the input power at 40 W in a hydrogen atmosphere at a pressure of 5 Pa. Also, the frequency of reverse sputtering voltage to be applied is 100 MHz, and reverse sputtering 200 seconds.
[0109] 次に、逆スパッタリングにより形成した酸素欠損層 5の表面に、上部電極 4として Ag 層 (厚さ 50nm)を積層し、抵抗変化素子 1を作製した (サンプル 1 - 1)。  Next, an Ag layer (thickness: 50 nm) was laminated as the upper electrode 4 on the surface of the oxygen deficient layer 5 formed by reverse sputtering to produce a resistance change element 1 (Sample 1-1).
[0110] Ag層の積層は、 RFマグネトロンスパッタリング法により、圧力 lPaのアルゴン雰囲 気下において、基板の温度を室温とし、投入する電力を 80Wとして行った。  [0110] The Ag layer was laminated by RF magnetron sputtering in an argon atmosphere at a pressure of 1 Pa, with the substrate temperature set at room temperature and the input power set at 80W.
[0111] サンプル 1—1の作製とは別に、酸素欠損層 5の厚さがサンプル 1—1とは異なる抵 抗変化素子 1を、 PCMO層の表面を逆スパッタリングする時間を 100秒とした以外は サンプル 1—1と同様にして、作製した(サンプル 1— 2)。サンプル 1—1に比べて逆 スパッタリングの時間が短いため、サンプル 1 2における酸素欠損層 5の厚さは、サ ンプル 1 - 1に比べて小さ!/、と考えられる。  [0111] Apart from the fabrication of Sample 1-1, the resistance change element 1 in which the thickness of the oxygen deficient layer 5 is different from that of Sample 1-1, except that the time for reverse sputtering the surface of the PCMO layer was set to 100 seconds Was made in the same way as Sample 1-1 (Sample 1-2). Since the reverse sputtering time is shorter than that of Sample 1-1, the thickness of oxygen deficient layer 5 in Sample 12 is considered to be smaller than that of Sample 1-1! /.
[0112] また、サンプル 1—1および 1—2の作製とは別に、酸素欠損層 5を備えない抵抗変 化素子を、抵抗変化層 3である PCMO層の表面を逆スパッタリングしない以外はサン プル 1— 1と同様にして、作製した (比較例であるサンプル A)。  [0112] In addition to the preparation of Samples 1-1 and 1-2, a resistance variable element without the oxygen deficient layer 5 was sampled except that the surface of the PCMO layer that is the resistance change layer 3 was not reverse-sputtered. It was produced in the same manner as 1-1 (Sample A as a comparative example).
[0113] このようにして作製した各サンプルに対し、下部電極 (Pt層)および上部電極 (Ag層 )を介して、パルス状の SET電圧、 RESET電圧および READ電圧を印加し、抵抗変 化率の温度依存性を評価した。温度依存性の評価は以下のように行い、以降の実施 例 2〜4においても同様とした。  [0113] A pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this way via the lower electrode (Pt layer) and the upper electrode (Ag layer), and the resistance change rate The temperature dependence of was evaluated. The temperature dependency was evaluated as follows, and the same was applied to Examples 2 to 4 below.
[0114] (抵抗変化率の測定方法)  [0114] (Measurement method of resistance change rate)
各サンプルにおける Pt層と Ag層との間に、パルスジェネレータを用いて、 SET電 圧として 5V (正バイアス電圧)、 RESET電圧として 5V (負バイアス電圧、大きさ 5V )、 READ電圧として 0. IV (正バイアス電圧)をランダムに印加した (各電圧のパルス 幅は 250ns)。 SET電圧および RESET電圧を印加した後、 READ電圧の印加によ り読み出した電流値カゝら素子の電気抵抗値を算出し、算出した電気抵抗値の最大値 を R 、最小値を R として、(R -R ) /R X 100 (%)で示す式より、素子の抵 Using a pulse generator between the Pt layer and Ag layer in each sample, the SET voltage is 5V (positive bias voltage), the RESET voltage is 5V (negative bias voltage, magnitude 5V), and the READ voltage is 0. IV. (Positive bias voltage) was applied randomly (pulse width of each voltage was 250ns). After applying the SET voltage and RESET voltage, calculate the electrical resistance value of the element from the current value read by applying the READ voltage.The maximum value of the calculated electrical resistance value is R and the minimum value is R. (R -R) / RX 100 (%)
Max in Max in ιη Max in Max in ιη
抗変化率を求めた。  The resistance change rate was determined.
[0115] (温度依存性の評価方法) [0115] (Temperature dependence evaluation method)
各サンプルを、室温(25°C)、 100°Cおよび 200°Cの環境下に、各サンプルの温度 が環境温度とほぼ同等になるまで保持した後に、上記方法により、各サンプルの抵 抗変化率を測定した。 After each sample is held at room temperature (25 ° C), 100 ° C and 200 ° C until the temperature of each sample is approximately equal to the ambient temperature, the resistance of each sample is The anti-change rate was measured.
[0116] 評価結果を、以下の表 1に示す。  [0116] The evaluation results are shown in Table 1 below.
[0117] [表 1] [0117] [Table 1]
Figure imgf000022_0001
Figure imgf000022_0001
[0118] 表 1に示すように、室温における抵抗変化率は、全てのサンプルでほぼ同等(600 %以上)であったが、 100°Cでは、比較例であるサンプル Aの抵抗変化率が大きく減 少し、 200°Cでは、サンプル Aの抵抗変化特性がほとんど消失 (抵抗変化率にして 5 %未満)した。これに対してサンプル 1 1および 1 2の抵抗変化率は、 100°C以上 の温度においてもほとんど変化せず、 200°Cにおいても室温とほぼ同等の抵抗変化 率を保持できた。 [0118] As shown in Table 1, the rate of resistance change at room temperature was almost the same (600% or more) for all samples, but at 100 ° C, the rate of resistance change of sample A, which is a comparative example, was large. At 200 ° C, the resistance change characteristics of sample A almost disappeared (resistance change rate was less than 5%). On the other hand, the resistance change rate of Samples 11 and 12 hardly changed even at a temperature of 100 ° C or higher, and could maintain a resistance change rate almost equal to room temperature even at 200 ° C.
[0119] 酸素欠損層 5を形成するための逆スパッタリングの条件を、基板温度を室温〜 300 °Cの範囲、水素雰囲気のガス圧を lPa〜: LOPaの範囲、投入する電力を 40W〜80 Wの範囲で変化させたところ、サンプル 1—1および 1—2とほぼ同様の結果を得るこ とができた。  [0119] The reverse sputtering conditions for forming the oxygen deficient layer 5 are as follows: the substrate temperature is in the range of room temperature to 300 ° C, the gas pressure of the hydrogen atmosphere is in the range of lPa to: LOPa, and the input power is 40 to 80 W. When the range was changed, almost the same results as Samples 1-1 and 1-2 were obtained.
[0120] (実施例 2)  [0120] (Example 2)
実施例 2では、図 7A〜図 7Hに示す方法により、図 1に示すような抵抗変化素子 1 を作製し、その抵抗変化特性の温度依存性を評価した。  In Example 2, a resistance change element 1 as shown in FIG. 1 was manufactured by the method shown in FIGS. 7A to 7H, and the temperature dependence of the resistance change characteristics was evaluated.
[0121] 最初に、 Si基板 12の表面に、実施例 1と同様にして、下部電極 2として Pt層(厚さ 2 OOnm)を積層した。  [0121] First, a Pt layer (thickness: 2 OOnm) was stacked as the lower electrode 2 on the surface of the Si substrate 12 in the same manner as in Example 1.
[0122] 次に、積層した Pt層の表面に、抵抗変化層 3として PCMO層と、 PCMO層よりも酸 素の欠損率が大きい酸素欠損層 5とを、順に積層した。両層の積層は、式 Pr Ca  [0122] Next, on the surface of the laminated Pt layer, a PCMO layer as the resistance change layer 3 and an oxygen deficient layer 5 having a larger oxygen deficiency rate than the PCMO layer were sequentially laminated. The lamination of both layers is the formula Pr Ca
0.7 0.3 0.7 0.3
MnOにより示される組成を有する酸ィ匕物をターゲットとし、 RFマグネトロンスパッタリTargeting an oxide having the composition indicated by MnO, RF magnetron sputtering
3 Three
ングにより、基板の温度を 700°C、投入する電力を 80Wとして行った。また、 PCMO 層を積層する時と、酸素欠損層 5を積層する時との間で、積層雰囲気中の酸素の分 圧を変化させた。具体的には、圧力 3Paの酸素 アルゴン混合雰囲気下、分圧比 O As a result, the substrate temperature was set to 700 ° C and the input power was set to 80W. PCMO The partial pressure of oxygen in the stacking atmosphere was changed between when the layers were stacked and when the oxygen deficient layer 5 was stacked. Specifically, in a mixed atmosphere of oxygen and argon at a pressure of 3 Pa, the partial pressure ratio O
2 2
ZArをおよそ 0. 25として PCMO層を積層し、同じ雰囲気下、ただし分圧比 O ZAr Laminate PCMO layers with ZAr approximately 0.25, under the same atmosphere, but partial pressure ratio O ZAr
2 を 0. 08として酸素欠損層 5を積層した。 PCMO層および酸素欠損層 5の厚さは、両 層の合計で 300nmとした。  An oxygen deficient layer 5 was laminated with 2 being 0.08. The total thickness of the PCMO layer and the oxygen deficient layer 5 was 300 nm.
[0123] 積層した PCMO層の構造を、別途 X線回折測定により評価したところ、多結晶膜で あることが確認された。 [0123] The structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, and was confirmed to be a polycrystalline film.
[0124] 次に、積層した酸素欠損層 5の表面に、実施例 1と同様にして、上部電極 4として A g層 (厚さ 50nm)を積層した。  Next, an Ag layer (thickness: 50 nm) was laminated as the upper electrode 4 on the surface of the laminated oxygen deficient layer 5 in the same manner as in Example 1.
[0125] 次に、積層した Ag層の表面に、矩形状にレジスト 33を配置した後、イオンミリングに より、 Pt層、 PCMO層、酸素欠損層 5および Ag層におけるレジスト 33により被覆され な力つた部分を除去した。 [0125] Next, a resist 33 is arranged in a rectangular shape on the surface of the laminated Ag layer, and then the force that is not covered with the resist 33 in the Pt layer, the PCMO layer, the oxygen deficient layer 5 and the Ag layer by ion milling. One part was removed.
[0126] 次に、各層の露出面全体に、絶縁層 31として SiO層を堆積させた。 SiO層の堆積 Next, a SiO layer was deposited as the insulating layer 31 on the entire exposed surface of each layer. Deposition of SiO layer
2 2 は、 RFマグネトロンスパッタリングにより、基板の温度を 100°C、圧力 0. IPaのァルゴ ン雰囲気において、投入電力を 100Wとして行った。  In 2 2, RF magnetron sputtering was performed at an input power of 100 W in an argon atmosphere with a substrate temperature of 100 ° C and a pressure of 0.1 IPa.
[0127] 最後に、レジスト 33をリフトオフし、抵抗変化素子 1 (サンプル 2— 1)を作製した。 [0127] Finally, the resist 33 was lifted off, and a resistance change element 1 (Sample 2-1) was produced.
[0128] サンプル 2— 1の作製とは別に、酸素欠損層 5における酸素の欠損率がサンプル 2[0128] In addition to the preparation of Sample 2-1, the oxygen deficiency rate in oxygen deficient layer 5 is
—1とは異なる抵抗変化素子 1を、酸素欠損層 5の積層雰囲気における分圧比 O / — Variable resistance ratio O / 1 in the laminated atmosphere of oxygen deficient layer 5
2 2
Arを 0. 1とした以外はサンプル 2—1と同様にして、作製した (サンプル 2— 2)。サン プル 2— 1に比べて上記分圧比が大き 、ため、サンプル 2— 2の酸素欠損層における 酸素の欠損率は、サンプル 2— 1に比べて小さ 、と考えられる。 A sample was prepared in the same manner as Sample 2-1 except that Ar was changed to 0.1 (Sample 2-2). Since the above partial pressure ratio is larger than that of Sample 2-1, the oxygen deficiency rate in the oxygen deficient layer of Sample 2-2 is considered to be smaller than that of Sample 2-1.
[0129] また、サンプル 2— 1および 2— 2の作製とは別に、酸素欠損層 5を備えない抵抗変 化素子を、酸素欠損層 5を積層しな力 た以外はサンプル 2—1と同様にして、作製 した (比較例であるサンプル B— 1)。  [0129] In addition to the manufacture of Samples 2-1 and 2-2, a resistance change element that does not include the oxygen-deficient layer 5 is the same as Sample 2-1 except that the oxygen-deficient layer 5 is not stacked. (Sample B-1 as a comparative example).
[0130] また、上記各サンプルの作製とは別に、 Pt層と Ag層との間に、 PCMO層と、化学 量論比を超える過剰な酸素を含む酸素過剰層とを備える抵抗変化素子を、酸素欠 損層 5を積層する代わりに、積層雰囲気における分圧比 O ZArをおよそ 0. 6とする  [0130] Further, separately from the production of each sample, a resistance change element including a PCMO layer and an oxygen excess layer containing excess oxygen exceeding the stoichiometric ratio between the Pt layer and the Ag layer, Instead of stacking the oxygen-deficient layer 5, the partial pressure ratio O ZAr in the stacking atmosphere is set to about 0.6.
2  2
ことにより酸素過剰層を積層した以外はサンプル 1— 1と同様にして、作製した (比較 例であるサンプル B— 2。サンプル B— 2は、酸素欠損層 5を備えない)。酸素過剰層 は、式 Pr Ca MnO (yl > 3)により示される組成を有する層であるといえる。 The sample was prepared in the same manner as Sample 1-1 except that an oxygen-excess layer was laminated (Comparison An example is Sample B-2. Sample B-2 does not have an oxygen deficient layer 5). It can be said that the oxygen-excess layer is a layer having a composition represented by the formula Pr Ca MnO (yl> 3).
0.7 0.3 yl  0.7 0.3 yl
[0131] このようにして作製した各サンプルに対し、下部電極 (Pt層)および上部電極 (Ag層 )を介して、パルス状の SET電圧、 RESET電圧および READ電圧を印加し、実施例 1と同様にして、各サンプルの抵抗変化率の温度依存性を評価した。  [0131] A pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this manner via the lower electrode (Pt layer) and the upper electrode (Ag layer). Similarly, the temperature dependence of the resistance change rate of each sample was evaluated.
[0132] 評価結果を、以下の表 2に示す。  [0132] The evaluation results are shown in Table 2 below.
[0133] [表 2]  [0133] [Table 2]
Figure imgf000024_0001
Figure imgf000024_0001
[0134] 表 2に示すように、室温における抵抗変化率は、全てのサンプルでほぼ同等(600 %以上)であったが、 100°Cでは、比較例であるサンプル B— 1および B— 2、特に酸 素過剰層を備えるサンプル B— 2の抵抗変化率が大きく減少し、 200°Cでは、サンプ ル B— 1および B— 2の抵抗変化特性がほとんど消失 (抵抗変化率にして 5%未満)し た。これに対してサンプル 2— 1および 2— 2の抵抗変化率は、 100°C以上の温度に おいてもほとんど変化せず、 200°Cにおいても室温とほぼ同等の抵抗変化率を保持 できた。 [0134] As shown in Table 2, the rate of change in resistance at room temperature was almost the same (600% or more) for all samples, but at 100 ° C, samples B-1 and B-2, which were comparative examples, were used. In particular, the resistance change rate of sample B-2 with an oxygen excess layer was greatly reduced, and at 200 ° C, the resistance change characteristics of samples B-1 and B-2 almost disappeared (resistance change rate 5% Less). On the other hand, the resistance change rate of Samples 2-1 and 2-2 hardly changed even at a temperature of 100 ° C or higher, and could maintain a resistance change rate almost equal to room temperature even at 200 ° C. .
[0135] (実施例 3)  [0135] (Example 3)
実施例 3では、図 5A〜図 5Fに示す方法により、図 2に示すような抵抗変化素子 1を 作製し、その抵抗変化特性の温度依存性を評価した。  In Example 3, a resistance change element 1 as shown in FIG. 2 was produced by the method shown in FIGS. 5A to 5F, and the temperature dependence of the resistance change characteristics was evaluated.
[0136] 最初に、 MgO基板 12の表面に、実施例 1と同様にして、下部電極 2として Pt層(厚 さ 200nm)を積層した。  [0136] First, a Pt layer (thickness: 200 nm) was laminated as the lower electrode 2 on the surface of the MgO substrate 12 in the same manner as in Example 1.
[0137] 次に、積層した Pt層の露出面を含む全体に、実施例 2と同様にして、絶縁層 31とし て SiO層を堆積させた。 [0137] Next, the insulating layer 31 is formed on the entire surface including the exposed surface of the laminated Pt layer in the same manner as in Example 2. A SiO layer was deposited.
2  2
[0138] 次に、堆積させた SiO層における抵抗変化素子 1を形成したい部分に、 RIEにより  [0138] Next, the portion where the variable resistance element 1 in the deposited SiO layer is to be formed is formed by RIE.
2  2
、コンタクトホール 32 (直径 0. 5 m)を形成した。  A contact hole 32 (diameter 0.5 m) was formed.
[0139] 次に、形成したコンタクトホール 32内における Pt層の露出面に、酸素欠損層 5を積 層した。酸素欠損層 5の積層は、 RFマグネトロンスパッタリングにより、式 Pr Ca M Next, an oxygen deficient layer 5 was deposited on the exposed surface of the Pt layer in the formed contact hole 32. The stacking of the oxygen deficient layer 5 is performed by RF magnetron sputtering with the formula Pr Ca M
0.7 0.3 ηθにより示される組成を有する酸ィ匕物をターゲットとし、圧力 3Paの酸素一アルゴン 0.7 0.3 ηθ The target is an oxide having a composition represented by ηθ.
3 Three
混合雰囲気下 (分圧比 O ZArが 0. 1)において、基板の温度を 700°Cとし、投入す  In a mixed atmosphere (partial pressure ratio O ZAr is 0.1), the substrate temperature is set to 700 ° C
2  2
る電力を 80Wとして行った。  The power used was 80W.
[0140] 続いて、積層した酸素欠損層 5の表面に、抵抗変化層 3として PCMO層を積層した 。 PCMO層の積層は、積層雰囲気における分圧比 O ZArをおよそ 0. 25とした以 [0140] Subsequently, a PCMO layer was laminated as the resistance change layer 3 on the surface of the laminated oxygen deficient layer 5. Lamination of the PCMO layer is done by setting the partial pressure ratio O ZAr in the lamination atmosphere to about 0.25.
2  2
外は、酸素欠損層 5の積層と同様に行った。積層した酸素欠損層 5および PCMO層 の厚さは、両層の合計で 300nmとした。  The outside was performed in the same manner as the stacking of the oxygen deficient layer 5. The thickness of the laminated oxygen deficient layer 5 and PCMO layer was 300 nm in total.
[0141] 積層した PCMO層の構造を、別途 X線回折測定により評価したところ、多結晶膜で あることが確認された。 [0141] When the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, it was confirmed to be a polycrystalline film.
[0142] 次に、積層した PCMO層の表面を CMPにより平坦ィ匕処理し、処理後の PCMO層 の表面に、実施例 1と同様にして、上部電極 4として Ag層(厚さ 50nm)を積層させ、 抵抗変化素子 1 (サンプル 3)を作製した。  [0142] Next, the surface of the laminated PCMO layer was flattened by CMP, and an Ag layer (thickness 50 nm) was formed as the upper electrode 4 on the surface of the PCMO layer after the treatment in the same manner as in Example 1. By stacking, variable resistance element 1 (sample 3) was produced.
[0143] サンプル 3の作製とは別に、酸素欠損層 5を備えないサンプルを、コンタクトホール 32内における Pt層の露出面に直接 PCMO層を積層した以外はサンプル 3と同様に して、作製した (比較例であるサンプル C)。  [0143] Separately from the preparation of Sample 3, a sample without oxygen deficient layer 5 was prepared in the same manner as Sample 3, except that the PCMO layer was directly laminated on the exposed surface of the Pt layer in contact hole 32. (Comparative sample C).
[0144] このようにして作製した各サンプルに対し、下部電極 (Pt層)および上部電極 (Ag層 )を介して、パルス状の SET電圧、 RESET電圧および READ電圧を印加し、実施例 1と同様にして、各サンプルの抵抗変化率の温度依存性を評価した。  [0144] A pulsed SET voltage, RESET voltage, and READ voltage were applied to each sample fabricated in this manner via the lower electrode (Pt layer) and the upper electrode (Ag layer). Similarly, the temperature dependence of the resistance change rate of each sample was evaluated.
[0145] 評価結果を、以下の表 3に示す。  [0145] The evaluation results are shown in Table 3 below.
[0146] [表 3] m ( ) [0146] [Table 3] m ()
サンプル N o .  Sample No.
2 5 °C 1 0 0。C 2 0 0で  2 5 ° C 1 0 0. C 2 0 0
3 630 620 620 3 630 620 620
C (J;瞧) 650 200 C (J; 瞧) 650 200
[0147] 表 3に示すように、室温における抵抗変化率は、全てのサンプルでほぼ同等(600 %以上)であったが、 100°Cでは、比較例であるサンプル Cの抵抗変化率が大きく減 少し、 200°Cでは、サンプル Cの抵抗変化特性がほとんど消失 (抵抗変化率にして 5 %未満)した。これに対してサンプル 3の抵抗変化率は、 100°C以上の温度において もほとんど変化せず、 200°Cにおいても室温とほぼ同等の抵抗変化率を保持できた [0147] As shown in Table 3, the resistance change rate at room temperature was almost the same (600% or more) in all samples, but at 100 ° C, the resistance change rate of sample C, which is a comparative example, was large. At 200 ° C, the resistance change characteristics of sample C almost disappeared (resistance change rate was less than 5%). In contrast, the resistance change rate of sample 3 hardly changed even at temperatures of 100 ° C or higher, and could maintain a resistance change rate almost equal to room temperature even at 200 ° C
[0148] (実施例 4) [0148] (Example 4)
実施例 4では、図 7A〜図 7Hに示す方法により、図 1に示すような抵抗変化素子 1 を作製し、その抵抗変化特性の温度依存性を評価した。  In Example 4, a resistance change element 1 as shown in FIG. 1 was produced by the method shown in FIGS. 7A to 7H, and the temperature dependence of the resistance change characteristics was evaluated.
[0149] 最初に、 Si基板 12の表面に、実施例 1と同様にして、下部電極 2として Pt層(厚さ 2First, a Pt layer (thickness 2) is formed on the surface of the Si substrate 12 as the lower electrode 2 in the same manner as in Example 1.
OOnm)を積層した。 OOnm) was laminated.
[0150] 次に、積層した Pt層の表面に、実施例 1と同様にして、抵抗変化層 3として PCMO 層(厚さ: 300nm)を積層した。積層した PCMO層の構造を、別途、 X線回折測定に より評価したところ、多結晶膜であることが確認された。  [0150] Next, a PCMO layer (thickness: 300 nm) was laminated as the resistance change layer 3 in the same manner as in Example 1 on the surface of the laminated Pt layer. When the structure of the laminated PCMO layer was separately evaluated by X-ray diffraction measurement, it was confirmed to be a polycrystalline film.
[0151] 次に、積層した PCMO層の表面を窒素雰囲気下にて熱処理することにより、 PCM[0151] Next, the surface of the laminated PCMO layer was heat-treated in a nitrogen atmosphere, so that PCM
O層における当該表面を含む一部の酸素の欠損率を増大させて、酸素欠損層 5を形 成した。熱処理は、基板を含む全体を 500°Cにまで 1分間で昇温し、 500°CにおいてThe oxygen deficiency layer 5 was formed by increasing the deficiency rate of a part of oxygen including the surface in the O layer. In the heat treatment, the entire substrate, including the substrate, is heated to 500 ° C in 1 minute.
3分間保持した後、室温まで急冷することにより行った。 After holding for 3 minutes, it was performed by rapidly cooling to room temperature.
[0152] 次に、形成した酸素欠損層 5の表面に、実施例 1と同様にして、上部電極 4として A g層 (厚さ 50nm)を積層した。 Next, an Ag layer (thickness: 50 nm) was stacked as the upper electrode 4 on the surface of the formed oxygen deficient layer 5 in the same manner as in Example 1.
[0153] 次に、積層した Ag層の表面に、矩形状にレジスト 33を配置した後、イオンミリングに より、 Pt層、抵抗変化層 3、酸素欠損層 5および Ag層におけるレジスト 33により被覆 されなかった部分を除去した。 [0154] 次に、各層の露出面全体に、実施例 2と同様にして、絶縁層 31として SiO層を堆 [0153] Next, a resist 33 is arranged in a rectangular shape on the surface of the laminated Ag layer, and then covered with the resist 33 in the Pt layer, the resistance change layer 3, the oxygen deficient layer 5, and the Ag layer by ion milling. The part which did not exist was removed. [0154] Next, an SiO layer as an insulating layer 31 is deposited on the entire exposed surface of each layer in the same manner as in Example 2.
2 積させた。  2 stacked.
[0155] 最後に、レジスト 33をリフトオフし、抵抗変化素子 1 (サンプル 4)を作製した。  [0155] Finally, the resist 33 was lifted off, and a resistance change element 1 (sample 4) was produced.
[0156] サンプル 4の作製とは別に、酸素欠損層 5を備えない抵抗変化素子を、抵抗変化 層 3である PCMO層の表面を熱処理しなかった以外はサンプル 4と同様にして、作 製した (比較例であるサンプル D)。 [0156] Separately from the production of sample 4, a resistance change element without oxygen deficient layer 5 was produced in the same manner as sample 4 except that the surface of the PCMO layer that is resistance change layer 3 was not heat-treated. (Comparative sample D).
[0157] このようにして作製した各サンプルに対し、下部電極 (Pt層)および上部電極 (Ag層[0157] For each sample prepared in this way, the lower electrode (Pt layer) and the upper electrode (Ag layer)
)を介して、パルス状の SET電圧、 RESET電圧および READ電圧を印加し、実施例) To apply a pulsed SET voltage, RESET voltage, and READ voltage.
1と同様にして、各サンプルの抵抗変化率の温度依存性を評価した。 In the same manner as in 1, the temperature dependence of the resistance change rate of each sample was evaluated.
[0158] 評価結果を、以下の表 4に示す。 [0158] The evaluation results are shown in Table 4 below.
[0159] [表 4] [0159] [Table 4]
Figure imgf000027_0001
Figure imgf000027_0001
[0160] 表 4に示すように、室温における抵抗変化率は、全てのサンプルでほぼ同等(600 %以上)であったが、 100°Cでは、比較例であるサンプル Dの抵抗変化率が大きく減 少し、 200°Cでは、サンプル Dの抵抗変化特性がほとんど消失 (抵抗変化率にして 5 %未満)した。これに対してサンプル 4の抵抗変化率は、 100°C以上の温度において もほとんど変化せず、 200°Cにおいても室温とほぼ同等の抵抗変化率を保持できた 産業上の利用可能性 [0160] As shown in Table 4, the resistance change rate at room temperature was almost the same (600% or more) for all samples, but at 100 ° C, the resistance change rate of sample D, which is a comparative example, was large. At 200 ° C, the resistance change characteristics of sample D almost disappeared (resistance change rate was less than 5%). In contrast, the resistance change rate of sample 4 hardly changed even at temperatures of 100 ° C or higher, and the resistance change rate at 200 ° C was almost the same as that of room temperature.
[0161] 以上説明したように、本発明の抵抗変化素子は、従来の抵抗変化素子に比べて耐 熱性に優れており、例えば、 200°Cの温度環境下において安定して動作できる。本 発明の抵抗変化素子は、情報を電気抵抗値として不揮発に保持でき、従来の電荷 蓄積型メモリ素子に比べて素子の微細化も容易である。本発明の抵抗変化素子を用 いた電子デバイスとしては、例えば、情報通信端末などに使用される不揮発性メモリ 、スイッチング素子、センサ、画像表示装置などが挙げられる。 [0161] As described above, the resistance change element of the present invention is superior in heat resistance compared to conventional resistance change elements, and can operate stably in a temperature environment of 200 ° C, for example. The resistance change element of the present invention can hold information in an nonvolatile manner as an electric resistance value, and the element can be easily miniaturized as compared with a conventional charge storage type memory element. As an electronic device using the variable resistance element of the present invention, for example, a non-volatile memory used for an information communication terminal or the like , Switching elements, sensors, image display devices, and the like.

Claims

請求の範囲 The scope of the claims
[1] 基板と、前記基板上に配置された多層構造体とを含み、  [1] including a substrate and a multilayer structure disposed on the substrate,
前記多層構造体が、上部電極および下部電極と、前記上部電極と前記下部電極と の間に配置された抵抗変化層と、を含み、  The multilayer structure includes an upper electrode and a lower electrode, and a resistance change layer disposed between the upper electrode and the lower electrode,
前記上部電極と前記下部電極との間の電気抵抗値が異なる 2以上の状態が存在し 前記上部電極と前記下部電極との間に所定の電気パルスを印加することにより、前 記 2以上の状態から選ばれる 1つの状態から他の状態へと変化する抵抗変化素子で あって、  There are two or more states where the electric resistance value between the upper electrode and the lower electrode is different, and by applying a predetermined electric pulse between the upper electrode and the lower electrode, two or more states A variable resistance element that changes from one state to another selected from:
前記抵抗変化層が、式 (Pr, Ca) MnO により示される組成を有し、  The variable resistance layer has a composition represented by the formula (Pr, Ca) MnO;
xl  xl
前記多層構造体が、前記上部電極および前記下部電極力 選ばれる少なくとも 1 つの電極と、前記抵抗変化層との間に配置された、式 (Pr, Ca) MnO により示され る糸且成を有する酸素欠損層をさらに含む抵抗変化素子。  The multilayer structure has a thread structure represented by the formula (Pr, Ca) MnO, disposed between at least one electrode selected from the upper electrode and the lower electrode force and the resistance change layer. A resistance change element further including an oxygen deficient layer.
ただし、 xlおよび x2は、それぞれ以下の式を満たす数値である。  However, xl and x2 are numerical values that satisfy the following expressions, respectively.
0< xl≤3  0 <xl≤3
0< x2< 3  0 <x2 <3
x2< xl  x2 <xl
[2] 前記抵抗変化層が、式 (Pr, Ca) MnOにより示される組成を有する請求項 1に記  [2] The variable resistance layer according to claim 1, wherein the variable resistance layer has a composition represented by a formula (Pr, Ca) MnO.
3  Three
載の抵抗変化素子。  The variable resistance element listed.
[3] 前記酸素欠損層と前記抵抗変化層とが、互いに接する請求項 1に記載の抵抗変化 素子。  [3] The resistance change element according to [1], wherein the oxygen deficient layer and the resistance change layer are in contact with each other.
[4] 前記酸素欠損層と前記少なくとも 1つの電極とが、互いに接する請求項 1に記載の 抵抗変化素子。  [4] The resistance change element according to [1], wherein the oxygen deficient layer and the at least one electrode are in contact with each other.
[5] 前記多層構造体が、 Pr、 Caおよび Mnを含む酸ィ匕物層として、前記酸素欠損層お よび前記抵抗変化層のみを含む請求項 1に記載の抵抗変化素子。  5. The resistance change element according to claim 1, wherein the multilayer structure includes only the oxygen deficient layer and the resistance change layer as an oxide layer containing Pr, Ca, and Mn.
[6] 前記多層構造体が、前記酸素欠損層、前記抵抗変化層、前記上部電極および前 記下部電極からなる請求項 1に記載の抵抗変化素子。  6. The variable resistance element according to claim 1, wherein the multilayer structure includes the oxygen deficient layer, the variable resistance layer, the upper electrode, and the lower electrode.
[7] 前記酸素欠損層が、式 Pr Ca MnO により示される組成を有する請求項 1に記載 p 1-p x2 の抵抗変化素子。 7. The p 1-p x2 according to claim 1, wherein the oxygen-deficient layer has a composition represented by the formula Pr Ca MnO. Resistance change element.
ただし、 pは、 0. 6以上 0. 8以下である。  However, p is 0.6 or more and 0.8 or less.
[8] 前記抵抗変化層が、式 Pr Ca MnO により示される組成を有する請求項 1に記載 p 1-p xl  [8] The p 1-p xl according to claim 1, wherein the variable resistance layer has a composition represented by a formula Pr Ca MnO.
の抵抗変化素子。  Resistance change element.
ただし、 pは、 0. 6以上 0. 8以下である。  However, p is 0.6 or more and 0.8 or less.
[9] 基板と、前記基板上に配置された多層構造体とを含み、 [9] including a substrate and a multilayer structure disposed on the substrate,
前記多層構造体が、上部電極および下部電極と、前記上部電極と前記下部電極と の間に配置された抵抗変化層と、を含み、  The multilayer structure includes an upper electrode and a lower electrode, and a resistance change layer disposed between the upper electrode and the lower electrode,
前記上部電極と前記下部電極との間の電気抵抗値が異なる 2以上の状態が存在し 前記上部電極と前記下部電極との間に所定の電気パルスを印加することにより、前 記 2以上の状態から選ばれる 1つの状態から他の状態へと変化する抵抗変化素子の 製造方法であって、  There are two or more states where the electric resistance value between the upper electrode and the lower electrode is different, and by applying a predetermined electric pulse between the upper electrode and the lower electrode, two or more states A method of manufacturing a resistance change element that changes from one state to another state selected from:
基板上に下部電極を形成する下部電極形成工程と、  A lower electrode forming step of forming a lower electrode on the substrate;
前記下部電極上に、式 (Pr, Ca) MnO により示される組成を有する抵抗変化層を xl  A variable resistance layer having a composition represented by the formula (Pr, Ca) MnO is formed on the lower electrode.
形成する抵抗変化層形成工程と、  A variable resistance layer forming step to be formed;
前記抵抗変化層上に、式 (Pr, Ca) MnO により示される組成を有する酸素欠損層 を形成する酸素欠損層形成工程と、  Forming an oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO on the variable resistance layer; and
前記抵抗変化層および酸素欠損層を前記下部電極とともに狭持する上部電極を 形成する上部電極形成工程と、を順に有する抵抗変化素子の製造方法。  An upper electrode forming step of forming an upper electrode for sandwiching the variable resistance layer and the oxygen deficient layer together with the lower electrode, in order.
ただし、 xlおよび x2は、それぞれ以下の式を満たす数値である。  However, xl and x2 are numerical values that satisfy the following expressions, respectively.
0<xl≤3  0 <xl≤3
0<x2< 3  0 <x2 <3
x2<xl  x2 <xl
[10] xl = 3である請求項 9に記載の抵抗変化素子の製造方法。  [10] The method for manufacturing a variable resistance element according to claim 9, wherein xl = 3.
[11] 前記酸素欠損層形成工程において、前記酸素欠損層は、前記抵抗変化層の表面 を逆スパッタリングすることにより形成される請求項 9に記載の抵抗変化素子の製造 方法。 11. The variable resistance element manufacturing method according to claim 9, wherein in the oxygen deficient layer forming step, the oxygen deficient layer is formed by reverse sputtering the surface of the variable resistance layer.
[12] xl = 3である請求項 11に記載の抵抗変化素子の製造方法。 12. The method for manufacturing a variable resistance element according to claim 11, wherein xl = 3.
[13] 前記下部電極に接するように前記抵抗変化層を形成し、 [13] forming the variable resistance layer in contact with the lower electrode;
前記抵抗変化層の表面に形成した前記酸素欠損層に接するように、前記上部電 極を形成する請求項 11に記載の抵抗変化素子の製造方法。  12. The method of manufacturing a variable resistance element according to claim 11, wherein the upper electrode is formed so as to be in contact with the oxygen deficient layer formed on the surface of the variable resistance layer.
[14] 前記酸素欠損層形成工程において、前記酸素欠損層は、前記抵抗変化層の表面 を非酸化性雰囲気下にて熱処理することにより形成される請求項 9に記載の抵抗変 化素子の製造方法。 14. The resistance variable element manufacturing method according to claim 9, wherein in the oxygen deficient layer forming step, the oxygen deficient layer is formed by heat-treating a surface of the variable resistance layer in a non-oxidizing atmosphere. Method.
[15] xl = 3である請求項 14に記載の抵抗変化素子の製造方法。 15. The method for manufacturing a variable resistance element according to claim 14, wherein xl = 3.
[16] 前記下部電極に接するように前記抵抗変化層を形成し、 [16] forming the variable resistance layer in contact with the lower electrode,
前記抵抗変化層の表面に形成した前記酸素欠損層に接するように、前記上部電 極を形成する請求項 14に記載の抵抗変化素子の製造方法。  15. The method of manufacturing a variable resistance element according to claim 14, wherein the upper electrode is formed so as to be in contact with the oxygen deficient layer formed on a surface of the variable resistance layer.
[17] 前記抵抗変化層形成工程における雰囲気が有する不活性ガスの分圧 P [17] Partial pressure of the inert gas in the atmosphere in the variable resistance layer forming step P
inertと酸素 の分圧 P との比 (P /P )が、前記酸素欠損層形成工程における雰囲気が有す oxy oxy inert  The ratio of inert to oxygen partial pressure P (P / P) is determined by the atmosphere in the oxygen deficient layer formation process.
る前記比よりも大きい、請求項 9に記載の抵抗変化素子の製造方法。  10. The method for manufacturing a resistance change element according to claim 9, wherein the ratio is greater than the ratio.
[18] 前記抵抗変化層形成工程において、前記抵抗変化層がスパッタリングにより形成さ れ、 [18] In the variable resistance layer forming step, the variable resistance layer is formed by sputtering,
前記酸素欠損層形成工程において、前記酸素欠損層がスパッタリングにより形成さ れる請求項 17に記載の抵抗変化素子の製造方法。  18. The method of manufacturing a resistance change element according to claim 17, wherein in the oxygen deficient layer forming step, the oxygen deficient layer is formed by sputtering.
[19] 基板と、前記基板上に配置された多層構造体とを含み、 [19] including a substrate and a multilayer structure disposed on the substrate,
前記多層構造体が、上部電極および下部電極と、前記上部電極と前記下部電極と の間に配置された抵抗変化層と、を含み、  The multilayer structure includes an upper electrode and a lower electrode, and a resistance change layer disposed between the upper electrode and the lower electrode,
前記上部電極と前記下部電極との間の電気抵抗値が異なる 2以上の状態が存在し 前記上部電極と前記下部電極との間に所定の電気パルスを印加することにより、前 記 2以上の状態から選ばれる 1つの状態から他の状態へと変化する抵抗変化素子の 製造方法であって、  There are two or more states where the electric resistance value between the upper electrode and the lower electrode is different, and by applying a predetermined electric pulse between the upper electrode and the lower electrode, two or more states A method of manufacturing a resistance change element that changes from one state to another state selected from:
基板上に下部電極を形成する下部電極形成工程と、  A lower electrode forming step of forming a lower electrode on the substrate;
前記下部電極上に、式 (Pr, Ca) MnO により示される組成を有する酸素欠損層を 形成する酸素欠損層形成工程と、 An oxygen deficient layer having a composition represented by the formula (Pr, Ca) MnO is formed on the lower electrode. An oxygen deficient layer forming step to be formed;
前記酸素欠損層上に、式 (Pr, Ca) MnO により示される組成を有する抵抗変化層  A variable resistance layer having a composition represented by the formula (Pr, Ca) MnO on the oxygen deficient layer
xl  xl
を形成する抵抗変化層形成工程と、  Forming a resistance change layer,
前記酸素欠損層および抵抗変化層を前記下部電極とともに狭持する上部電極を 形成する上部電極形成工程と、を順に有する抵抗変化素子の製造方法。  An upper electrode forming step of sequentially forming an upper electrode that sandwiches the oxygen deficient layer and the resistance change layer together with the lower electrode.
ただし、 xlおよび χ2は、それぞれ以下の式を満たす数値である。  However, xl and χ2 are numerical values that satisfy the following formulas.
0<xl≤3  0 <xl≤3
0<χ2< 3  0 <χ2 <3
x2<xl  x2 <xl
[20] 前記抵抗変化層形成工程における雰囲気が有する不活性ガスの分圧 Ρ と酸素  [20] Partial pressure of inert gas and oxygen in atmosphere in the resistance change layer forming step
inert の分圧 P との比 (P /P )が、前記酸素欠損層形成工程における雰囲気が有す oxy oxy inert  The ratio of inert partial pressure P (P / P) is the oxygen deficient layer formation process atmosphere.
る前記比よりも大きい、請求項 19に記載の抵抗変化素子の製造方法。  20. The method for manufacturing a resistance change element according to claim 19, wherein the ratio is greater than the ratio.
[21] 前記酸素欠損層形成工程において、前記酸素欠損層がスパッタリングにより形成さ れ、 [21] In the oxygen deficient layer forming step, the oxygen deficient layer is formed by sputtering,
前記抵抗変化層形成工程において、前記抵抗変化層がスパッタリングにより形成さ れる請求項 20に記載の抵抗変化素子の製造方法。  21. The variable resistance element manufacturing method according to claim 20, wherein in the variable resistance layer forming step, the variable resistance layer is formed by sputtering.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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WO2009072213A1 (en) * 2007-12-07 2009-06-11 Fujitsu Limited Resistance change-type memory device, nonvolatile memory device, and method for manufacturing them
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JP5007724B2 (en) * 2006-09-28 2012-08-22 富士通株式会社 Variable resistance element
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JP2013118386A (en) * 2006-10-03 2013-06-13 Hewlett-Packard Development Company L P Electrically actuated switch
US8913417B2 (en) 2007-06-29 2014-12-16 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US9018083B2 (en) 2011-05-04 2015-04-28 Hewlett-Packard Development Company, L.P. Electrically actuated device and method of controlling the formation of dopants therein

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4843259B2 (en) * 2005-06-10 2011-12-21 シャープ株式会社 Method for manufacturing variable resistance element
JP5423941B2 (en) * 2007-11-28 2014-02-19 ソニー株式会社 Storage element, manufacturing method thereof, and storage device
WO2010087000A1 (en) * 2009-01-30 2010-08-05 株式会社 東芝 Process for fabricating nonvolatile storage
US7785978B2 (en) 2009-02-04 2010-08-31 Micron Technology, Inc. Method of forming memory cell using gas cluster ion beams
JP2011165883A (en) * 2010-02-09 2011-08-25 Toshiba Corp Semiconductor memory device, and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004349690A (en) * 2003-05-21 2004-12-09 Sharp Corp Oxygen content system and method for controlling memory resistance properties
JP2004349689A (en) * 2003-05-21 2004-12-09 Sharp Corp Asymmetric crystalline structure memory cell
JP2005353662A (en) * 2004-06-08 2005-12-22 Sharp Corp Semiconductor apparatus and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004349690A (en) * 2003-05-21 2004-12-09 Sharp Corp Oxygen content system and method for controlling memory resistance properties
JP2004349689A (en) * 2003-05-21 2004-12-09 Sharp Corp Asymmetric crystalline structure memory cell
JP2005353662A (en) * 2004-06-08 2005-12-22 Sharp Corp Semiconductor apparatus and its manufacturing method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SAKAI ET AL.: "Observation of unrecoverable domains in two-dimensional-arrayed Pr0.5Ca0.5MnO3-y junctions", APPLIED SURFACE SCIENCE, vol. 220, no. 1 TO 4, 30 December 2003 (2003-12-30), pages 251 - 258, XP002999442 *

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