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WO2006068000A1 - Stacked body for cof substrate, method for manufacturing such stacked body for cof substrate, and cof film carrier tape formed by using such stacked body for cof substrate - Google Patents

Stacked body for cof substrate, method for manufacturing such stacked body for cof substrate, and cof film carrier tape formed by using such stacked body for cof substrate Download PDF

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Publication number
WO2006068000A1
WO2006068000A1 PCT/JP2005/022825 JP2005022825W WO2006068000A1 WO 2006068000 A1 WO2006068000 A1 WO 2006068000A1 JP 2005022825 W JP2005022825 W JP 2005022825W WO 2006068000 A1 WO2006068000 A1 WO 2006068000A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
conductor
cof
laminate
surface roughness
Prior art date
Application number
PCT/JP2005/022825
Other languages
French (fr)
Japanese (ja)
Inventor
Katsuya Kishida
Akira Shimada
Yuichi Tokuda
Taeko Takarabe
Original Assignee
Nippon Steel Chemical Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Chemical Co., Ltd. filed Critical Nippon Steel Chemical Co., Ltd.
Priority to JP2006548842A priority Critical patent/JP5064035B2/en
Priority to KR1020077016686A priority patent/KR101169829B1/en
Publication of WO2006068000A1 publication Critical patent/WO2006068000A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0108—Transparent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer

Definitions

  • COF substrate laminate method for producing the same, and COF film carrier tape formed using this COF substrate laminate
  • the present invention relates to a laminate for a flexible printed circuit board used as a CF application and a method for producing the same.
  • TAB method tape automated bonding in which a driver IC is mounted on a tape carrier is widely used in the electronics industry that uses liquid crystal display elements (LCD).
  • LCD liquid crystal display elements
  • COF chip 'on' film
  • COF chip 'on' film
  • the flexible printed circuit board (FPC) used in this COF does not have the device holes used in the TAB method, when measuring the relative position when mounting the chip, the driver IC chip is transmitted through the insulating layer. It is necessary to recognize the wiring. In particular, in the flexible printed circuit board (FPC) used in this COF, the wiring pitch is becoming narrower and it is necessary to be able to perform fine processing.
  • a laminate used for such an FPC for COF there is a laminate in which an adhesion reinforcing layer such as nickel is sputtered on an insulating film such as a polyimide film and then copper plating is applied.
  • the polyimide film is relatively transparent, so that it is easy to align when mounting ICs, and the adhesion between the conductor and the insulating layer is weakened. If the mouth migration is inferior, there is a problem.
  • a casting type in which a polyimide film is laminated on a copper foil by a coating method, or a thermoplastic resin or a thermosetting resin on the copper foil is used.
  • thermocompression bonding type in which an insulating film is thermocompression bonded.
  • Japanese Patent Application Laid-Open No. 2003-23046 has a structure in which a conductor layer and an insulating layer are laminated, and the surface roughness of the surface of the conductor layer in contact with the insulating layer is 0.1 to 1.8 xm.
  • the body is disclosed.
  • the above-mentioned laminated body can solve the problem of recognizing the wiring of the driver IC chip through the insulating layer to some extent, it can be used as a high-density substrate material that requires a pitch of 30 ⁇ m or less, for example. Is not always satisfactory.
  • JP 2004-142183 A describes a laminate in which the surface roughness of the surface in contact with the insulating layer is 1.0 zm or less and the surface roughness force of the back surface is 3 ⁇ 4.0 xm or less.
  • the surface roughness of the surface that is not in contact with the insulating layer is large, unevenness in thickness occurs during resist formation, and the subsequent linear circuit patterning process improves the linearity of the circuit. It was difficult.
  • the conductor even when the conductor is thick, it is difficult to ensure the linearity of the circuit, and in particular, fine processing with a pitch of 30 / im or less is difficult. That is, a laminate that can satisfy the requirements for fine processing with appropriate roughness on the insulating layer side and roughness on the resist surface side has been strong.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-23046
  • Patent Document 2 JP 2004-142183 A
  • An object of the present invention is to provide a laminate capable of being finely processed, for example, having a pitch of 30 / m or less, and a manufacturing method thereof.
  • the conductor forming the multilayer body has a predetermined thickness, and the surface of the surface of the conductor that is in direct contact with the insulating layer
  • the roughness Rz should be 1.0 ⁇ m or less, and the surface roughness Rz should be 1.0 ⁇ m or less in contact with the insulating layer.
  • the surface roughness Rz represents “10-point average roughness” and is measured according to JIS B 0601.
  • the present invention is a COF substrate laminate in which an insulating layer made of an insulating resin is formed on one surface of a conductor made of a conductive metal foil, wherein the conductor has a thickness of 1 to 8 ⁇ m. m, the surface roughness Rz of the surface in contact with the insulating layer of the conductor is 1.0 xm or less, and the surface roughness Rz of the surface not in contact with the insulating layer of the conductor is 1.0 ⁇ or less, C ⁇ It is a laminate for F substrates.
  • the present invention also provides a method for manufacturing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, and has a thickness of at least 10 zm and has one surface.
  • the thickness of the conductive metal foil is formed by forming an insulating layer on the surface of the conductive metal foil having a surface roughness Rz of 1.0 xm or less and chemically polishing the surface of the conductive metal foil not in contact with the insulating layer. 1 to 8 ⁇ m, and a conductor is formed with a surface roughness Rz of 1.0 ⁇ m or less.
  • the driver IC chip wiring can be recognized through the insulating layer. Further, when the surface roughness Rz of the conductor that is not in direct contact with the insulating layer is 1.0 ⁇ or less, when a high-density wiring is required, for example, processing of 30 ⁇ pitch or less is possible.
  • the surface roughness Rz of the conductor that is in direct contact with the insulating layer has a lower limit of 0.3 ⁇ m for ensuring the adhesion to the insulating layer, and the surface roughness of the conductor that is not in direct contact with the insulating layer.
  • Rz has a lower limit of 0.1 ⁇ m in order to ensure adhesion with an insulating protective film to be laminated later.
  • Examples of the conductor made of the conductive metal foil in the present invention include a copper foil made of copper or a copper alloy, as well as a metal foil made of gold, silver, etc., preferably a copper foil. Good.
  • Examples of the copper foil include rolled copper foil, electrolytic copper foil, and the like, and an electrolytic copper foil that can reduce the risk of mixing an oxide as an insulator as much as possible is more preferable.
  • the thickness of the conductor is 1 to 8 ⁇ m. If the thickness of the conductor is smaller than 1 ⁇ m, it is difficult to control the thickness during the chemical polishing process and sufficient reliability cannot be obtained. On the other hand, if it is larger than 8 xm, it becomes very difficult to obtain the linearity of the conductor, for example, when machining at 30 zm pitch. The invention's effect
  • the wiring of the driver IC chip can be recognized through the insulating layer, and the adhesive force between the conductor and the insulating layer is high.
  • the adhesive force between the conductor and the insulating layer is high.
  • the electrolytic copper foil having a surface roughness Rz of 1.0 zm or less on the surface on which an insulating layer is to be provided later is used. This is because, as described above, when the insulating layer is formed on this surface and the conductor is removed, the wiring of the driver IC chip can be recognized through the insulating layer.
  • Rz is preferably 0.3 zm or more.
  • the thickness of the conductor in the finally obtained laminate is l to 8 xm.
  • the thickness of this electrolytic copper foil is about 10 xm or more thick as the copper foil to be prepared because chemical polishing will be described later. It is preferable to use one having a thickness of 12 to 18 ⁇ m.
  • the insulating layer forming the laminate is formed from an insulating film having a thermosetting resin layer, which may be formed from an insulating film having a thermoplastic resin layer, for example. There may be. Alternatively, a polyimide precursor resin solution may be applied to the conductor, and the polyimide precursor resin solution may be dried and cured. Of these, the insulating layer is preferably formed by applying a polyimide precursor resin solution to the conductor and then drying and curing.
  • diamines used include 4,4'-diaminodiphenyl ether, 2'-methoxy 4,4'-diaminobenzanilide, 1,4 bis (4 aminophenoxy) benzene, 1 , 3 Bis (4 aminophenoxy) benzene, 2,2'-bis [4— (4 aminophenoxy) phenyl] pro Bread, 2,2′-dimethyl-4,4′-diaminobiphenyl, 3,3′-dihydroxy-4,4′-diaminobiphenyl, 4,4′-diaminobenzanilide and the like.
  • Examples of the acid anhydride include pyromellitic anhydride, 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-diphenylsulfonetetracarboxylic acid Examples include dianhydrides and water-free 4,4'-oxydiphthalic acid.
  • diamine and acid anhydride can be used alone or in combination of two or more.
  • Examples of the solvent include dimethylacetamide, n_methylpyrrolidinone, 2-butanone, diglyme, xylene, and the like, and they can be used alone or in combination of two or more.
  • the polyimide precursor resin solution preferably has a polymerized resin viscosity in the range of 500 cps to 35,000 cps, preferably applied directly to one side of the conductor in the precursor state.
  • the applied resin solution must be heat-treated. For this heat treatment, for example, heat treatment is performed at 100 ° C to 150 ° C for 2 to 4 minutes in the atmosphere, and then heated from room temperature to 340 ° C by vacuum heating. It's better to heat up and bring it back to room temperature for about 9 hours.
  • the insulating layer made of the polyimide resin thus formed may be formed of only a single layer of the polyimide resin layer or a plurality of layers.
  • the polyimide resin layer is formed from a plurality of layers, other polyimide resins made of different components may be sequentially applied on the polyimide resin layer.
  • the polyimide resin layer is composed of three or more layers, the polyimide resin composed of the same component may be used twice or more.
  • the thickness of the conductor is reduced to 1 to 8 ⁇ by chemically polishing the surface of the conductor that is not in direct contact with the insulating layer.
  • the surface roughness Rz of the surface should be 1.0 / im or less.
  • the surface roughness of the copper foil varies depending on the conditions of chemical polishing. In the present invention, the copper foil of the desired laminate is adjusted by adjusting the polishing conditions such as the known polishing temperature and polishing rate. The surface roughness can be adjusted.
  • the polishing liquid is a hydrogen peroxide Z sulfuric acid system containing hydrogen peroxide and sulfuric acid as main components.
  • the concentration of hydrogen peroxide is in the range of 70 to 85 g / L, and the concentration of sulfuric acid is in the range of 18 to 22 g / L. If the concentration range is not within the above range, precise control of the surface roughness tends to be difficult.
  • the polishing temperature is 20-50 Keep it constant at any temperature of ° C.
  • the insulating layer is formed by applying a polyimide resin on the electrolytic copper foil.
  • an insulating layer is formed by laminating one or more polyimide films on the electrolytic copper foil, Thereafter, chemical polishing as described above may be performed.
  • the laminate thus produced may be a single-sided copper-clad laminate having an electrolytic copper foil only on one side of the insulating layer, or a double-sided copper-clad laminate having an electrolytic copper foil on both sides of the insulating layer.
  • double-sided copper-clad laminates after forming a single-sided copper-clad laminate, a method of crimping electrolytic copper foil by hot pressing, a method of sandwiching a polyimide film between two electrolytic copper foils, and crimping by hot pressing, etc. Can be mentioned.
  • the surface roughness Rz of the surface of the electrolytic copper foil that is not in direct contact with the insulating layer is set to 1.0 zm or less, and the thickness of the electrolytic copper foil is in the range of 1 to 8 xm. So that chemical polishing is performed.
  • the surface roughness Rz of the electrolytic copper foil that is not in direct contact with the insulating layer is desirably 0.1 ⁇ m or more from the viewpoint of ensuring adhesion with the insulating protective film on which the rear force is also laminated.
  • Copper foil 1 Electrolytic copper foil Insulation layer side Rz0.7 ⁇ m, resist side Rz2.0 ⁇ m
  • Copper foil 2 Electrolytic copper foil Insulation layer side Rzl.6 ⁇ m, resist side Rzl.5 ⁇ m
  • Copper foil 3 Electrolytic copper foil Insulation layer side Rz2.5 ⁇ m, resist side Rzl.5 ⁇ m
  • Copper foil 4 Electrolytic copper foil Insulation layer side Rz0.8 ⁇ m, resist side Rzl.O ⁇ m
  • ⁇ -methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, pyromellitic anhydride (PMDA) was added to the reaction vessel, and then 4,4-diaminodiphenyl ether, (DAPE) and 2, -methoxy- 4,4,-Gaminobensanilide ( ⁇ ) was introduced.
  • the total amount of monomer input is At 15 wt%, the molar ratio of each diamine (MABA: DAPE) was 3 ⁇ 40: 40, and the molar ratio of acid anhydride to diamine was 0.98: 1.0.
  • N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, PMDA / 3, 3, 4, 4, 4-biphenyltetracarboxylic dianhydride (BTDA) is charged into the reaction vessel, and then 4, 4, -Diaminodiphenyl ether (DAPE) was added. The total amount of monomers charged was 15 wt%, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ⁇ 5 ° C. Stirring was continued for 3 hours at room temperature, and the resulting polyamic acid solution viscosity was 3,200 cps.
  • BTDA 4-biphenyltetracarboxylic dianhydride
  • DAPE -Diaminodiphenyl
  • N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, 3,3 '4,4'-diphenylsulfone tetracarboxylic dianhydride (DSDA) and PMDA were added to the reaction vessel, and then 1,3- Bis (4-aminophenoxy) benzene (TPE-R) was added. The total amount of monomers charged was 15 wt%, the molar ratio of each acid anhydride (DSDA: PMDA) was 3 ⁇ 40: 10, and the molar ratio of acid anhydride to diamine was 1.03: 1.0.
  • DSDA 3,3 '4,4'-diphenylsulfone tetracarboxylic dianhydride
  • TPE-R 1,3- Bis (4-aminophenoxy) benzene
  • a wiring pattern was formed on the COF substrate laminate obtained above to obtain a COF film carrier tape.
  • the linearity of the circuit is visually confirmed with a laser microscope with a magnification of 50 times, and the line width is uneven. If the condition was observed, it was determined as NG.
  • an IC with gold bumps was mounted on the inner lead of the COF film carrier tape.
  • Flip chip bonder “TFC_2100” manufactured by Shibaura Mechatronics Co., Ltd. is used for mounting. Bond head head temperature is 100 ° C, stage temperature is 420 ° C, and bonding pressure is 20gf per bump. It was done like that.
  • the polyamic acid solution of Synthesis Example 1 was dried by a roll coater to a thickness of 2.0 ⁇ m. And then dried at 150 ° C for 2 minutes, and the other surface is coated with the polyamic acid solution of Synthesis Example 2 using a roll coater so that the thickness force after drying is 3 ⁇ 4.0 xm. 70. 140 minutes after drying for 5 minutes at C and 5 minutes at 110 ° C. C2 minutes, 180.
  • the side coated with the polyamic acid solution of Synthesis Example 1 is a non-thermoplastic polyimide resin layer, and the polyamic acid solution of Synthesis Example 2 is applied A polyimide insulating film having a heat-resistant polyimide resin layer on the finished side was obtained.
  • a roll laminator covered with silicon rubber was used by superimposing the surface of the insulating film obtained above on the side of the thermoplastic polyimide resin layer and the surface of the copper foil 4 on the side of the insulating layer.
  • the copper foil 4 and the above insulating film were bonded together under the conditions of 240 ° C. and pressure 1.5 MPa.
  • annealing was performed in a batch type autoclave at a temperature of 340 ° C. for 4 hours under a nitrogen atmosphere to obtain a laminate.
  • the obtained laminate was chemically polished in the same manner as in Example 1.
  • COF substrate laminate consisting of a conductor and an insulating layer, with the conductor being formed with a copper foil thickness of 8.0 ⁇ and a copper foil surface roughness Rz of 0.6 / im that is not in contact with the insulating film Got.
  • This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
  • Example 2 Using the copper foil 2, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed.
  • the thickness of the conductor of the obtained laminate for COF substrate is 8.0 ⁇ m
  • the surface roughness Rz of the surface in contact with the insulating layer is 1.6 ⁇ m
  • the side not in contact with the insulating layer resist side
  • the surface roughness Rz was 1.2 zm.
  • This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after mounting the COF were evaluated. The results are shown in Table 1.
  • a laminate was formed in the same manner as in Example 1 using copper foil 4. This laminated body was not subjected to chemical polishing.
  • the thickness of the conductor of the obtained COF substrate laminate is 18 ⁇ m
  • the surface roughness Rz of the surface on the opposite side is 0.8 ⁇ m
  • the surface roughness Rz is in contact with the insulating layer
  • the surface roughness Rz on the side (resist surface side) was 1.0 xm.
  • This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
  • a laminate was produced in the same manner as in Example 1 until just before chemical polishing.
  • this laminate is subjected to chemical polishing using a polishing solution having a sulfuric acid concentration of 80 g / L, a hydrogen peroxide concentration of 20 g / L, and an additive concentration of 3% so that the thickness force of the copper foil becomes 0.0 / m.
  • a conductor was formed such that the surface roughness Rz of the copper foil not in contact with the polyimide resin layer was 1.6 ⁇ m, and a laminate for a COF substrate comprising a conductor and an insulating layer was obtained.
  • This COF substrate laminate was mounted in the same manner as in Example 1 and evaluated for image recognition during mounting, linearity of the inner leads, and reliability after COF mounting. The results are shown in Table 1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

A stacked body which permits wiring of a driver IC chip to be recognized through an insulating layer, has strong adhesion between a conductor and the insulating layer and excellent electromigration resistivity, and to which fine processing, for example, that of a pitch of 30μm or less, can be performed, and a method for manufacturing such stacked body. The stacked body for COF substrate is provided with the insulating layer composed of an insulating resin on one plane of the conductor composed of a conductive metal foil. In the stacked body, the conductor thickness is 1-8μm, the surface roughness Rz of a plane touching the insulating layer of the conductor is 1.0μm or less, and the surface roughness Rz of a plane not touching the insulating layer of the conductor is 1.0μm or less. In the method for manufacturing the stacked body for COF substrate, the insulating layer is formed on the one plane of the conductive metal foil, which has a thickness of at least 10μm and a surface roughness Rz of 1.0μm or less on the one plane, a plane of the conductive metal foil not touching the insulating layer is chemically polished to have a conductive metal foil thickness of 1-8μm and a surface roughness Rz of 1.0μm or less to form the conductor.

Description

明 細 書  Specification
COF基板用積層体及びその製造方法並びにこの COF基板用積層体を 用いて形成した COFフィルムキャリアテープ  COF substrate laminate, method for producing the same, and COF film carrier tape formed using this COF substrate laminate
技術分野  Technical field
[0001] 本発明は、 C〇F用途として使用するフレキシブルプリント基板用の積層体とその製 造方法に関するものである。  [0001] The present invention relates to a laminate for a flexible printed circuit board used as a CF application and a method for producing the same.
背景技術  Background art
[0002] テープキャリアにドライバ ICを実装する TAB方式 (テープ ·オートメイティッド'ボン デイング）は、液晶表示素子 (LCD)を使用するような電子産業において広く用レ、られ ている。  [0002] The TAB method (tape automated bonding) in which a driver IC is mounted on a tape carrier is widely used in the electronics industry that uses liquid crystal display elements (LCD).
[0003] また、近時では、より小さいスペースで、より高密度の実装を行う実装方法として、裸 の ICチップをフィルムキャリアテープ上に直接搭載する COF (チップ 'オン'フィルム） が開発されている。  [0003] Recently, COF (chip 'on' film), in which a bare IC chip is directly mounted on a film carrier tape, has been developed as a mounting method for mounting at higher density in a smaller space. Yes.
[0004] この COFに用いられるフレキシブルプリント基板（FPC)は、 TAB方式で用いられて きたデバイスホールを有しないため、チップ実装時の相対位置を測定する際、絶縁 層を透過してドライバ ICチップの配線を認識する必要がある。特に、この COFに用い られるフレキシブルプリント基板（FPC)においては、配線の狭ピッチ化が進み、微細 加工が可能である必要がある。  [0004] Since the flexible printed circuit board (FPC) used in this COF does not have the device holes used in the TAB method, when measuring the relative position when mounting the chip, the driver IC chip is transmitted through the insulating layer. It is necessary to recognize the wiring. In particular, in the flexible printed circuit board (FPC) used in this COF, the wiring pitch is becoming narrower and it is necessary to be able to perform fine processing.
[0005] このような COF用の FPCに用いられる積層体としては、ポリイミドフィルムなどの絶 縁フィルムにニッケルなどの密着強化層をスパッタした後、銅メツキを施した積層体が ある。このような銅メツキ積層体では、ポリイミドフィルムが比較的透明であるので、 IC 搭載の際の位置合わせが容易ではある力 s、導体と絶縁層との間の接着力が弱ぐま た、耐エレクト口マイグレーション性に劣るとレ、つた問題がある。  [0005] As a laminate used for such an FPC for COF, there is a laminate in which an adhesion reinforcing layer such as nickel is sputtered on an insulating film such as a polyimide film and then copper plating is applied. In such a copper-plated laminate, the polyimide film is relatively transparent, so that it is easy to align when mounting ICs, and the adhesion between the conductor and the insulating layer is weakened. If the mouth migration is inferior, there is a problem.
[0006] 上記のような課題を解決する積層体としては、銅箔にポリイミドフィルムを塗布法に より積層したキャスティングタイプのものや、銅箔に熱可塑性樹脂や熱硬化性樹脂な どを介して絶縁フィルムを熱圧着した熱圧着タイプのものなどがある。  [0006] As a laminate that solves the above problems, a casting type in which a polyimide film is laminated on a copper foil by a coating method, or a thermoplastic resin or a thermosetting resin on the copper foil is used. There is a thermocompression bonding type in which an insulating film is thermocompression bonded.
[0007] し力、しながら、キャスティングタイプの積層体や熱圧着タイプの積層体については、 導体と絶縁層との接着力の問題をある程度解消するものの、例えば銅箔をエツチン グで除去した領域にっレ、ては、銅箔の粗度（表面粗さ）が絶縁層側に転写されてしま レ、、絶縁層の表面が光を乱反射して絶縁層を透過して銅パターンが認識できないと いった問題がある。 [0007] However, for casting type laminates and thermocompression type laminates, Although the problem of adhesion between the conductor and the insulating layer is solved to some extent, the roughness (surface roughness) of the copper foil is transferred to the insulating layer side, for example, in the area where the copper foil is removed by etching. However, there is a problem that the copper pattern cannot be recognized because the surface of the insulating layer irregularly reflects light and passes through the insulating layer.
[0008] そこで、特開 2003— 23046号公報では、導体層と絶縁層とが積層された構造を有し 、この導体層の絶縁層と接する面の表面粗さが 0.1〜1.8 x mである積層体が開示さ れている。し力 ながら、上記積層体は、絶縁層を透過してドライバ ICチップの配線 を認識する問題についてはある程度解消はされるものの、例えば 30 μ mピッチ以下 を必要とするような高密度基板材料としては必ずしも満足出来るものではなレ、。一方 、特開 2004-142183号公報には絶縁層と接している面の表面粗さが 1.0 z m以下で 裏面の表面粗さ力 ¾.0 x m以下である積層体が記載されている。し力、しながら、絶縁 層と接していない面の表面粗さが大きい場合、レジスト形成時に厚みムラが生じ、そ の後の配線回路のパターユング工程で回路の直線性を良好にするのが困難であつ た。また、導体の厚さが厚い場合にも、同様に回路の直線性の確保が難しぐ特に、 3 0 /i mピッチ以下の微細加工が困難であった。すなわち、絶縁層側の粗度とレジスト 面側の粗度とが適切であって、微細加工の要求を満足できる積層体はな力つた。 特許文献 1：特開 2003— 23046号公報  [0008] In view of this, Japanese Patent Application Laid-Open No. 2003-23046 has a structure in which a conductor layer and an insulating layer are laminated, and the surface roughness of the surface of the conductor layer in contact with the insulating layer is 0.1 to 1.8 xm. The body is disclosed. However, although the above-mentioned laminated body can solve the problem of recognizing the wiring of the driver IC chip through the insulating layer to some extent, it can be used as a high-density substrate material that requires a pitch of 30 μm or less, for example. Is not always satisfactory. On the other hand, JP 2004-142183 A describes a laminate in which the surface roughness of the surface in contact with the insulating layer is 1.0 zm or less and the surface roughness force of the back surface is ¾.0 xm or less. However, if the surface roughness of the surface that is not in contact with the insulating layer is large, unevenness in thickness occurs during resist formation, and the subsequent linear circuit patterning process improves the linearity of the circuit. It was difficult. In addition, even when the conductor is thick, it is difficult to ensure the linearity of the circuit, and in particular, fine processing with a pitch of 30 / im or less is difficult. That is, a laminate that can satisfy the requirements for fine processing with appropriate roughness on the insulating layer side and roughness on the resist surface side has been strong. Patent Document 1: Japanese Patent Laid-Open No. 2003-23046
特許文献 2：特開 2004-142183号公報  Patent Document 2: JP 2004-142183 A
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0009] そこで、本発明では、絶縁層を透過してドライバ ICチップの配線を認識することが 可能であると共に、導体と絶縁層との間の接着力が高ぐ耐エレクト口マイグレーショ ン性に優れ、例えば 30 / mピッチ以下の微細加工可能な積層体とその製造方法を 提供することを目的とする。 [0009] Therefore, in the present invention, it is possible to recognize the wiring of the driver IC chip through the insulating layer, and at the same time, it is possible to recognize the anti-electral migration in which the adhesive force between the conductor and the insulating layer is high. An object of the present invention is to provide a laminate capable of being finely processed, for example, having a pitch of 30 / m or less, and a manufacturing method thereof.
課題を解決するための手段  Means for solving the problem
[0010] 上記問題点を解決するために、本発明者等が鋭意検討した結果、積層体を形成す る導体を所定の厚みにすると共に、この導体の絶縁層と直接接している面の表面粗 さ Rzを 1.0 μ m以下にし、かつ、絶縁層と接してレ、なレ、面の表面粗さ Rzを 1.0 μ m以 下にすることによって、上記課題を解決し得ることを見出し、本発明を完成した。なお[0010] As a result of intensive studies by the present inventors in order to solve the above-described problems, the conductor forming the multilayer body has a predetermined thickness, and the surface of the surface of the conductor that is in direct contact with the insulating layer The roughness Rz should be 1.0 μm or less, and the surface roughness Rz should be 1.0 μm or less in contact with the insulating layer. The present inventors have found that the above-mentioned problems can be solved by setting down, and completed the present invention. In addition
、表面粗さ Rzは「10点平均粗さ」を表し、 JIS B 0601に準じて測定される。 The surface roughness Rz represents “10-point average roughness” and is measured according to JIS B 0601.
[0011] したがって、本発明は、導電性金属箔よりなる導体の一方の面に絶縁性樹脂よりな る絶縁層が形成された COF基板用積層体であって、導体の厚みが 1〜8 μ mであり、 導体の絶縁層と接している面の表面粗さ Rzが 1.0 x m以下であり、かつ、導体の絶縁 層と接していない面の表面粗さ Rzが 1.0 μ πι以下である、 C〇F基板用積層体である。 また、本発明は、導体の一方の面に絶縁性樹脂よりなる絶縁層が形成された COF 基板用積層体の製造方法であって、少なくとも 10 z m以上の厚みを有し、かつ、一方 の面の表面粗さ Rzが 1.0 x m以下である導電性金属箔の当該面に絶縁層を形成し、 この絶縁層と接していない導電性金属箔の面を化学研摩してこの導電性金属箔の 厚みを 1〜8 μ mにすると共に、表面粗さ Rzを 1.0 μ m以下にして導体を形成する、 C OF基板用積層体の製造方法である。  [0011] Accordingly, the present invention is a COF substrate laminate in which an insulating layer made of an insulating resin is formed on one surface of a conductor made of a conductive metal foil, wherein the conductor has a thickness of 1 to 8 μm. m, the surface roughness Rz of the surface in contact with the insulating layer of the conductor is 1.0 xm or less, and the surface roughness Rz of the surface not in contact with the insulating layer of the conductor is 1.0 μπι or less, C ○ It is a laminate for F substrates. The present invention also provides a method for manufacturing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, and has a thickness of at least 10 zm and has one surface. The thickness of the conductive metal foil is formed by forming an insulating layer on the surface of the conductive metal foil having a surface roughness Rz of 1.0 xm or less and chemically polishing the surface of the conductive metal foil not in contact with the insulating layer. 1 to 8 μm, and a conductor is formed with a surface roughness Rz of 1.0 μm or less.
[0012] 本発明では、絶縁層と直接接している導体の表面粗さ Rzを 1.0 μ ΐη以下とすること により、仮に絶縁層との積層時に導体の粗度が絶縁層側に転写されても、絶縁層を 透過してドライバ ICチップの配線を認識することが可能となる。また、絶縁層と直接接 していない導体の表面粗度 Rzが 1.0 μ πι以下とすることにより、高密度配線を必要と する場合において例えば 30 μ ΐηピッチ以下の加工が可能である。なお、絶縁層と直 接接している導体の表面粗さ Rzは、絶縁層との密着性を確保するため Rzは 0.3 μ m が下限であり、絶縁層と直接接していない導体の表面粗度 Rzは、後に積層される絶 縁性保護膜との密着性を確保するため Rzは 0.1 μ mが下限である。  In the present invention, by setting the surface roughness Rz of the conductor directly in contact with the insulating layer to 1.0 μΐη or less, even if the roughness of the conductor is transferred to the insulating layer side during lamination with the insulating layer, The driver IC chip wiring can be recognized through the insulating layer. Further, when the surface roughness Rz of the conductor that is not in direct contact with the insulating layer is 1.0 μπι or less, when a high-density wiring is required, for example, processing of 30 μΐη pitch or less is possible. Note that the surface roughness Rz of the conductor that is in direct contact with the insulating layer has a lower limit of 0.3 μm for ensuring the adhesion to the insulating layer, and the surface roughness of the conductor that is not in direct contact with the insulating layer. Rz has a lower limit of 0.1 μm in order to ensure adhesion with an insulating protective film to be laminated later.
[0013] 本発明における導電性金属箔よりなる導体については、例えば銅又は銅合金から なる銅箔のほか、金、銀等からなる金属箔を挙げることができ、好ましくは銅箔である のがよい。銅箔については圧延銅箔、電解銅箔等を挙げることができるが、絶縁物で ある酸化物が混在するおそれを可及的に低減できる電解銅箔が更に好ましい。  [0013] Examples of the conductor made of the conductive metal foil in the present invention include a copper foil made of copper or a copper alloy, as well as a metal foil made of gold, silver, etc., preferably a copper foil. Good. Examples of the copper foil include rolled copper foil, electrolytic copper foil, and the like, and an electrolytic copper foil that can reduce the risk of mixing an oxide as an insulator as much as possible is more preferable.
[0014] また、本発明においては、導体の厚みを 1〜8 μ mとする。導体の厚みが 1 μ mより 小さいと化学研磨工程時に厚さ制御が困難であると共に信頼性を充分に得ることが 出来ない。反対に 8 x mより大きくなると例えば 30 z mピッチ加工時に、導体の直線 性を得る事が非常に難しくなる。 発明の効果 [0014] In the present invention, the thickness of the conductor is 1 to 8 μm. If the thickness of the conductor is smaller than 1 μm, it is difficult to control the thickness during the chemical polishing process and sufficient reliability cannot be obtained. On the other hand, if it is larger than 8 xm, it becomes very difficult to obtain the linearity of the conductor, for example, when machining at 30 zm pitch. The invention's effect
[0015] 本発明によれば、絶縁層を透過してドライバ ICチップの配線を認識することが可能 であり、導体と絶縁層との間の接着力が高ぐ耐エレクト口マイグレーション性に優れ、 例えば 30 μ mピッチ以下の微細加工が可能な積層体を得ることができる。  [0015] According to the present invention, the wiring of the driver IC chip can be recognized through the insulating layer, and the adhesive force between the conductor and the insulating layer is high. For example, it is possible to obtain a laminate that can be finely processed with a pitch of 30 μm or less.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0016] 以下、本発明を詳細に説明する。尚、以下では電解銅箔を用いて積層体を形成す る例を説明するが、本発明における積層体とこれを得るための方法については下記 の内容に限定されるものではない。  Hereinafter, the present invention will be described in detail. In the following, an example in which a laminate is formed using electrolytic copper foil will be described, but the laminate and the method for obtaining the laminate in the present invention are not limited to the following contents.
[0017] 導電性金属箔よりなる導体として電解銅箔を用いる場合、この電解銅箔については 、後に絶縁層を設ける側の面の表面粗さ Rzが 1.0 z m以下のものを使用する。これは 、既に述べたように、この面に絶縁層を形成して導体を除去した際、絶縁層を透過し てドライバ ICチップの配線の認識を可能とする為である。なお、絶縁層との密着性を 確保するためには Rzは 0.3 z m以上であることが好ましい。また、最終的に得られる 積層体における導体の厚みは l〜8 x mである力 この電解銅箔の厚みについては、 後述する化学研摩を行うことから、用意する銅箔としては厚さ 10 x m以上、好ましくは 12〜18 μ mの厚みのものを用いるようにするのがよレ、。  [0017] When an electrolytic copper foil is used as a conductor made of a conductive metal foil, the electrolytic copper foil having a surface roughness Rz of 1.0 zm or less on the surface on which an insulating layer is to be provided later is used. This is because, as described above, when the insulating layer is formed on this surface and the conductor is removed, the wiring of the driver IC chip can be recognized through the insulating layer. In order to secure adhesion with the insulating layer, Rz is preferably 0.3 zm or more. Moreover, the thickness of the conductor in the finally obtained laminate is l to 8 xm. The thickness of this electrolytic copper foil is about 10 xm or more thick as the copper foil to be prepared because chemical polishing will be described later. It is preferable to use one having a thickness of 12 to 18 μm.
[0018] 積層体を形成する絶縁層については、例えば熱可塑性樹脂層を有する絶縁フィル ムから形成されたものであってもよぐ熱硬化性樹脂層を有する絶縁フィルムから形 成されたものであってもよい。また、ポリイミド前駆体樹脂溶液が導体に塗布され、こ のポリイミド前駆体樹脂溶液を乾燥及び硬化させることにより形成してもよい。これら のうち、好ましくは導体にポリイミド前駆体樹脂溶液が塗布された後、乾燥及び硬化さ せることにより絶縁層を形成したものであるのがよい。  [0018] The insulating layer forming the laminate is formed from an insulating film having a thermosetting resin layer, which may be formed from an insulating film having a thermoplastic resin layer, for example. There may be. Alternatively, a polyimide precursor resin solution may be applied to the conductor, and the polyimide precursor resin solution may be dried and cured. Of these, the insulating layer is preferably formed by applying a polyimide precursor resin solution to the conductor and then drying and curing.
[0019] 上記絶縁層につレ、て、ポリイミド前駆体樹脂溶液を塗布した後、乾燥及び硬化する ことにより形成する場合には、公知のジァミンと酸無水物とを溶媒の存在下で重合し て製造すること力できる。  [0019] When the polyimide precursor resin solution is applied to the insulating layer and then formed by drying and curing, a known diamine and acid anhydride are polymerized in the presence of a solvent. Can be manufactured.
[0020] 用いられるジァミンとしては、例えば、 4,4'ージアミノジフエニルエーテル、 2'—メト キシ 4,4'ージァミノベンズァニリド、 1,4 ビス（4 アミノフエノキシ）ベンゼン、 1,3 ビ ス（4 アミノフエノキシ）ベンゼン、 2,2'—ビス [4— (4 アミノフエノキシ）フエニル]プロ パン、 2,2 '—ジメチルー 4,4'ージアミノビフエニル、 3,3 '—ジヒドロキシー4，4'ージアミ ノビフエニル、 4,4'ージァミノべンズァニリド等が挙げられる。また、酸無水物としては 、例えば、無水ピロメリット酸、 3，3 ' ,4,4'—ビフエニルテトラカルボン酸二無水物、 3,3 ' , 4,4'—ジフエニルスルフォンテトラカルボン酸二無水物、 4，4'—ォキシジフタル酸無 水物が挙げられる。ジァミン、酸無水物はそれぞれ、その 1種のみを使用してもよく 2 種以上を併用して使用することも出来る。 [0020] Examples of diamines used include 4,4'-diaminodiphenyl ether, 2'-methoxy 4,4'-diaminobenzanilide, 1,4 bis (4 aminophenoxy) benzene, 1 , 3 Bis (4 aminophenoxy) benzene, 2,2'-bis [4— (4 aminophenoxy) phenyl] pro Bread, 2,2′-dimethyl-4,4′-diaminobiphenyl, 3,3′-dihydroxy-4,4′-diaminobiphenyl, 4,4′-diaminobenzanilide and the like. Examples of the acid anhydride include pyromellitic anhydride, 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, 3,3 ′, 4,4′-diphenylsulfonetetracarboxylic acid Examples include dianhydrides and water-free 4,4'-oxydiphthalic acid. Each of diamine and acid anhydride can be used alone or in combination of two or more.
[0021] 溶媒については、ジメチルァセトアミド、 n_メチルピロリジノン、 2—ブタノン、ジグラ ィム、キシレン等が挙げられ、 1種若しくは 2種以上併用して使用することもできる。  [0021] Examples of the solvent include dimethylacetamide, n_methylpyrrolidinone, 2-butanone, diglyme, xylene, and the like, and they can be used alone or in combination of two or more.
[0022] 上記ポリイミド前駆体樹脂溶液については、前駆体状態で導体の一方の面に直接 塗布することが好ましぐ重合された樹脂粘度を 500cps〜35，000cpsの範囲とすること が好ましい。塗布された樹脂液については熱処理を行う必要がある力 この熱処理に ついては例えば 100°C〜150°Cを 2分〜 4分大気中で熱処理し、その後、真空加熱で 室温から 340°Cまで昇温させ再び室温まで戻すといった処理を 9時間程度行うのがよ レ、。このようにして形成するポリイミド樹脂からなる絶縁層は、ポリイミド樹脂層の単層 のみから形成してもよぐ複数層から形成してもよい。ポリイミド樹脂層を複数層から形 成する場合、ポリイミド樹脂層の上に異なる構成成分からなる他のポリイミド樹脂を順 次塗布して形成してもよい。ポリイミド樹脂層が 3層以上からなる場合、同一の構成成 分からなるポリイミド樹脂を 2回以上使用してもよい。  [0022] The polyimide precursor resin solution preferably has a polymerized resin viscosity in the range of 500 cps to 35,000 cps, preferably applied directly to one side of the conductor in the precursor state. The applied resin solution must be heat-treated. For this heat treatment, for example, heat treatment is performed at 100 ° C to 150 ° C for 2 to 4 minutes in the atmosphere, and then heated from room temperature to 340 ° C by vacuum heating. It's better to heat up and bring it back to room temperature for about 9 hours. The insulating layer made of the polyimide resin thus formed may be formed of only a single layer of the polyimide resin layer or a plurality of layers. When the polyimide resin layer is formed from a plurality of layers, other polyimide resins made of different components may be sequentially applied on the polyimide resin layer. When the polyimide resin layer is composed of three or more layers, the polyimide resin composed of the same component may be used twice or more.
[0023] 上記で得た絶縁層と導体との積層体については、絶縁層と直接接していない導体 の面を化学研摩することによって、この導体の厚みを 1〜8 μ ΐηにすると共に、この面 の表面粗さ Rzを 1.0 /i m以下にする。この銅箔の表面粗さは、化学研磨の条件によつ ても変化するが、本発明においては、公知の研磨温度や研磨速度などの研磨条件 を調整して、所望の積層体の銅箔表面粗さを調整することができる。但し、研磨液の 種類と組成は、銅箔の表面粗さとの関係で重要な因子となるため、その研磨液は、過 酸化水素と硫酸を主剤として含有する過酸化水素 Z硫酸系が好ましい。過酸化水素 /硫酸系の研磨液を使用する場合、過酸化水素の濃度については 70〜85g/L、硫 酸の濃度については 18〜22g/Lの範囲とすることが好ましい。濃度範囲が上記範囲 にないと表面粗さの精密な制御が困難となる傾向にある。また、研磨温度は、 20〜50 °cの任意の温度で一定に保つことがょレ、。 [0023] For the laminated body of the insulating layer and the conductor obtained above, the thickness of the conductor is reduced to 1 to 8 μΐη by chemically polishing the surface of the conductor that is not in direct contact with the insulating layer. The surface roughness Rz of the surface should be 1.0 / im or less. The surface roughness of the copper foil varies depending on the conditions of chemical polishing. In the present invention, the copper foil of the desired laminate is adjusted by adjusting the polishing conditions such as the known polishing temperature and polishing rate. The surface roughness can be adjusted. However, since the type and composition of the polishing liquid are important factors in relation to the surface roughness of the copper foil, it is preferable that the polishing liquid is a hydrogen peroxide Z sulfuric acid system containing hydrogen peroxide and sulfuric acid as main components. When using a hydrogen peroxide / sulfuric acid based polishing solution, it is preferable that the concentration of hydrogen peroxide is in the range of 70 to 85 g / L, and the concentration of sulfuric acid is in the range of 18 to 22 g / L. If the concentration range is not within the above range, precise control of the surface roughness tends to be difficult. The polishing temperature is 20-50 Keep it constant at any temperature of ° C.
[0024] なお、上記の説明では、電解銅箔上にポリイミド樹脂を塗布することによって絶縁層 を形成したが、例えば 1層以上のポリイミドフィルムを電解銅箔にラミネートして絶縁 層を形成し、その後、上記で説明したような化学研磨を行うようにしてもよい。 [0024] In the above description, the insulating layer is formed by applying a polyimide resin on the electrolytic copper foil. However, for example, an insulating layer is formed by laminating one or more polyimide films on the electrolytic copper foil, Thereafter, chemical polishing as described above may be performed.
[0025] このようにして製造した積層体は、絶縁層の片面のみに電解銅箔を有する片面銅 張り積層体としてもよぐまた、絶縁層の両面に電解銅箔を有する両面銅張り積層体 としてもよレ、。両面銅張り積層体については、片面銅張り積層体を形成した後、電解 銅箔を熱プレスにより圧着する方法や 2枚の電解銅箔の間にポリイミドフィルムを挟み 熱プレスにより圧着する方法等を挙げることができる。いずれの方法においても、圧 着後には、絶縁層と直接接していない電解銅箔の面の表面粗さ Rzを 1.0 z m以下に すると共にこの電解銅箔の厚みを l〜8 x mの範囲となるように化学研磨を行うように する。なお、絶縁層と直接接していない電解銅箔の表面粗さ Rzは後力も積層される 絶縁性保護膜との密着性を確保する観点から 0.1 μ m以上であることが望ましい。 [0025] The laminate thus produced may be a single-sided copper-clad laminate having an electrolytic copper foil only on one side of the insulating layer, or a double-sided copper-clad laminate having an electrolytic copper foil on both sides of the insulating layer. Anyway. For double-sided copper-clad laminates, after forming a single-sided copper-clad laminate, a method of crimping electrolytic copper foil by hot pressing, a method of sandwiching a polyimide film between two electrolytic copper foils, and crimping by hot pressing, etc. Can be mentioned. In any method, after the pressing, the surface roughness Rz of the surface of the electrolytic copper foil that is not in direct contact with the insulating layer is set to 1.0 zm or less, and the thickness of the electrolytic copper foil is in the range of 1 to 8 xm. So that chemical polishing is performed. Note that the surface roughness Rz of the electrolytic copper foil that is not in direct contact with the insulating layer is desirably 0.1 μm or more from the viewpoint of ensuring adhesion with the insulating protective film on which the rear force is also laminated.
[0026] 以下、本発明を実施例により更に詳細に説明する。  Hereinafter, the present invention will be described in more detail with reference to examples.
[0027] 積層体の作成にあたり、下記 4種類の銅箔を準備した。  [0027] In preparing the laminate, the following four types of copper foils were prepared.
1)銅箔 1：電解銅箔 絶縁層側 Rz0.7 μ m、レジスト面側 Rz2.0 μ m  1) Copper foil 1: Electrolytic copper foil Insulation layer side Rz0.7 μm, resist side Rz2.0 μm
三井金属鉱業 (株)製 NA— VLP箔 厚さ 15 / m  Mitsui Metal Mining Co., Ltd. NA— VLP foil thickness 15 / m
2)銅箔 2：電解銅箔 絶縁層側 Rzl.6 μ m、レジスト面側 Rzl.5 μ m  2) Copper foil 2: Electrolytic copper foil Insulation layer side Rzl.6 μm, resist side Rzl.5 μm
古河サーキットフオイル (株）製 F2— WS箔 厚さ 12 μ πι  F2— WS foil manufactured by Furukawa Circuit Oil Co., Ltd. Thickness 12 μ πι
3)銅箔 3：電解銅箔 絶縁層側 Rz2.5 μ m、レジスト面側 Rzl.5 μ m  3) Copper foil 3: Electrolytic copper foil Insulation layer side Rz2.5 μm, resist side Rzl.5 μm
三井金属鉱業 (株)製 SQ— VLP箔 厚さ 12 μ π:  Mitsui Mining & Smelting Co., Ltd. SQ— VLP foil thickness 12 μ π:
4)銅箔 4：電解銅箔 絶縁層側 Rz0.8 μ m、レジスト面側 Rzl.O μ m  4) Copper foil 4: Electrolytic copper foil Insulation layer side Rz0.8 μm, resist side Rzl.O μm
日本電解 (株)製 USLPS箔 厚さ 18 x m  USLPS foil manufactured by Nippon Electrolytic Co., Ltd.Thickness 18 x m
[0028] [合成例 1]  [0028] [Synthesis Example 1]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器に η-メチルピロリジ ノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器に無水ピロメ リット酸（PMDA)を投入し、その後、 4,4，-ジアミノジフヱニルエーテル、（DAPE)と 2 ， -メトキシ- 4,4， -ジァミノべンズァニリド（ΜΑΒΑ)を投入した。モノマーの投入総量が 15wt%で、各ジァミンのモル比率（MABA: DAPE)力 ¾0 : 40であり、酸無水物とジァ ミンのモル比が 0.98 : 1.0となるよう投入した。その後、更に攪拌を続け、反応容器内の 温度が、室温から ± 5°Cの範囲となった時に反応容器を氷水から外した。室温のまま 3時間攪拌を続け、得られたポリアミック酸の溶液粘度は 15,000cpsであった。 Η-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, pyromellitic anhydride (PMDA) was added to the reaction vessel, and then 4,4-diaminodiphenyl ether, (DAPE) and 2, -methoxy- 4,4,-Gaminobensanilide (ΜΑΒΑ) was introduced. The total amount of monomer input is At 15 wt%, the molar ratio of each diamine (MABA: DAPE) was ¾0: 40, and the molar ratio of acid anhydride to diamine was 0.98: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the solution viscosity of the resulting polyamic acid was 15,000 cps.
[0029] [合成例 2] [0029] [Synthesis Example 2]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器に n-メチルピロリジ ノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器に PMDA/3 ， 3，，4,4，-ビフエニルテトラカルボン酸二無水物（BTDA)を投入し、その後、 4，4，-ジ アミノジフエニルエーテル（DAPE)を投入した。モノマーの投入総量が 15wt%で、酸 無水物とジァミンのモル比が 1.03 : 1.0となるよう投入した。その後、更に攪拌を続け、 反応容器内の温度が、室温から ± 5°Cの範囲となった時に反応容器を氷水から外し た。室温のまま 3時間攪拌を続け、得られたポリアミック酸の溶液粘度は 3，200cpsであ つに。  N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, PMDA / 3, 3, 4, 4, 4-biphenyltetracarboxylic dianhydride (BTDA) is charged into the reaction vessel, and then 4, 4, -Diaminodiphenyl ether (DAPE) was added. The total amount of monomers charged was 15 wt%, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the resulting polyamic acid solution viscosity was 3,200 cps.
[0030] [合成例 3] [0030] [Synthesis Example 3]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器に n-メチルピロリジ ノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器に 3,3' 4,4' - ジフエニルスルフォンテトラカルボン酸二無水物（DSDA)、 PMDAを投入し、その後 、 1,3-ビス（4-アミノフエノキシ）ベンゼン (TPE-R)を投入した。モノマーの投入総量 が 15wt%で、各酸無水物のモル比率（DSDA: PMDA)力 ¾0 : 10であり、酸無水物と ジァミンのモル比が 1.03 : 1.0となるよう投入した。その後、更に攪拌を続け、反応容器 内の温度が、室温から ± 5°Cの範囲となった時に反応容器を氷水から外した。室温の まま 3時間攪拌を続け、得られたポリアミック酸の溶液粘度は 3，200cpsであった。  N-methylpyrrolidinone was placed in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, 3,3 '4,4'-diphenylsulfone tetracarboxylic dianhydride (DSDA) and PMDA were added to the reaction vessel, and then 1,3- Bis (4-aminophenoxy) benzene (TPE-R) was added. The total amount of monomers charged was 15 wt%, the molar ratio of each acid anhydride (DSDA: PMDA) was ¾0: 10, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the solution viscosity of the resulting polyamic acid was 3,200 cps.
実施例 1  Example 1
[0031] 上記銅箔 1の絶縁層側の面に合成例:!〜 3のポリアミック酸溶液を順次塗布し、乾 燥を繰り返し、銅箔上にポリイミド前駆体樹脂層を形成した積層体を得た。この積層 体を 340°Cで、 8時間かけて熱処理し、ポリィミド榭脂層の厚みが40 /1 111 (2 /1 111/36 /1 ηι/2 μ ΐη)の片面銅箔の積層体を得た。この積層体を硫酸濃度 20g/L、過酸化水素 濃度 80g/L、添加剤濃度 3%の研磨液で化学研磨し、銅箔の厚みが 8.0 μ ΐηになるよ うにすると共に、ポリイミド樹脂層と接していない銅箔の表面粗さ Rzが 0.8 / mとなるよ うにして導体を形成し、導体と絶縁層とからなる COF基板用積層体を得た。 [0031] A polyamic acid solution of Synthesis Examples:! To 3 is sequentially applied to the surface of the copper foil 1 on the insulating layer side, and drying is repeated to obtain a laminate in which a polyimide precursor resin layer is formed on the copper foil. It was. This laminate was heat-treated at 340 ° C for 8 hours, and a single-sided copper foil laminate with a polyimide resin layer thickness of 40/1 111 (2/1 111/36/1 ηι / 2 μ ΐη) was obtained. Obtained. This laminate is chemically polished with a polishing solution with a sulfuric acid concentration of 20 g / L, a hydrogen peroxide concentration of 80 g / L, and an additive concentration of 3%. The thickness of the copper foil becomes 8.0 μΐη. In addition, a conductor was formed so that the surface roughness Rz of the copper foil not in contact with the polyimide resin layer was 0.8 / m, and a COF substrate laminate comprising a conductor and an insulating layer was obtained.
[0032] 上記で得た COF基板用積層体に配線パターンを形成して COFフィルムキャリアテ ープとした。この時、インナーリード部の回路パターンを 30 μ πιピッチで作成し、錫メッ キを施した後、倍率 50倍のレーザー顕微鏡にて目視で回路の直線性の確認を行い ライン幅が不均一な状態が観察された場合を NGとした。その後、 COFフィルムキヤリ ァテープのインナーリード部へ金バンプを有する ICを実装した。実装には、フリップ チップボンダ一「TFC_2100」芝浦メカトロニクス (株)製を使用し、ボンディングヘッドッ ール温度は 100°C、ステージ温度は 420°C、接合圧力は 1バンプ当たりの荷重が 20gf になるようにして行った。この実装の際、 COFフィルムキャリアテープを通して ICを画 像認識して ICの位置合わせに用いられるァライメントマークが認識可能であるかどう かで視認性評価を行った。実装後、 HHBT試験機「ETAC HIFLEXj楠本化成（ 株)製にて (8 5°C、 85%RT、 150V, 1000時間）を行い、信頼性評価を行った。結果 を表 1に示す。 [0032] A wiring pattern was formed on the COF substrate laminate obtained above to obtain a COF film carrier tape. At this time, after creating the circuit pattern of the inner lead part with 30 μπι pitch and tin plating, the linearity of the circuit is visually confirmed with a laser microscope with a magnification of 50 times, and the line width is uneven. If the condition was observed, it was determined as NG. After that, an IC with gold bumps was mounted on the inner lead of the COF film carrier tape. Flip chip bonder “TFC_2100” manufactured by Shibaura Mechatronics Co., Ltd. is used for mounting. Bond head head temperature is 100 ° C, stage temperature is 420 ° C, and bonding pressure is 20gf per bump. It was done like that. During this mounting, the IC was image-recognized through a COF film carrier tape, and a visibility evaluation was performed to see if the alignment mark used for IC alignment could be recognized. After mounting, the HHBT tester “ETAC HIFLEXj Enomoto Kasei Co., Ltd.” (85 ° C, 85% RT, 150V, 1000 hours) was evaluated for reliability. The results are shown in Table 1.
実施例 2  Example 2
[0033] 市販のポリイミド樹脂フィルム (東レ 'デュポン (株)製、商品名：カプトン 150EN)を用 レ、、片面に合成例 1のポリアミック酸溶液をロールコーターにより乾燥後の厚さで 2.0 μ mになるように塗布して 150°Cで 2分間乾燥させた後、もう一方の面に合成例 2のポ リアミック酸溶液をロールコーターにより乾燥後の厚さ力 ¾.0 x mになるように塗布し、 70。Cで 5分、 110°Cで 5分乾燥後、 140。C2分、 180。C5分、 265°C2分、エアーフロ ート方式の加熱炉にて硬化を行い、合成例 1のポリアミック酸溶液を塗布した側が非 熱可塑性ポリイミド樹脂層であり、合成例 2のポリアミック酸溶液を塗布した側が熱可 塑性ポリイミド樹脂層であるポリイミドの絶縁フィルムを得た。  [0033] Using a commercially available polyimide resin film (product name: Kapton 150EN, manufactured by Toray 'Dupont Co., Ltd.), on the one side, the polyamic acid solution of Synthesis Example 1 was dried by a roll coater to a thickness of 2.0 μm. And then dried at 150 ° C for 2 minutes, and the other surface is coated with the polyamic acid solution of Synthesis Example 2 using a roll coater so that the thickness force after drying is ¾.0 xm. 70. 140 minutes after drying for 5 minutes at C and 5 minutes at 110 ° C. C2 minutes, 180. C5 minutes, 265 ° C for 2 minutes, curing in an air-float heating furnace, the side coated with the polyamic acid solution of Synthesis Example 1 is a non-thermoplastic polyimide resin layer, and the polyamic acid solution of Synthesis Example 2 is applied A polyimide insulating film having a heat-resistant polyimide resin layer on the finished side was obtained.
[0034] 次レ、で、上記で得られた絶縁フィルムの熱可塑性ポリイミド樹脂層側の面と上記銅 箔 4の絶縁層側の面とを重ね合わせ、シリコンゴムで覆われたロールラミネーターを 用いて 240°C、圧力 1. 5Mpaの条件で銅箔 4と上記絶縁フィルムとを貼り合わせた。 その後、バッチ式のオートクレーブにて温度 340°C4時間窒素雰囲気下でァニール を行って積層体を得た。この得られた積層体を実施例 1と同様にして化学研磨を行い 、銅箔の厚みを 8.0 μ ΐηとし、絶縁フィルムと接していない銅箔の表面粗さ Rzを 0.6 /i mとなるようにして導体を形成し、導体と絶縁層とからなる COF基板用積層体を得た。 この COF基板用積層体について、実施例 1と同様にして実装を行い、実装時の画像 認識、インナーリードの直線性及び COF実装後信頼性について評価した。結果を表 1に示す。 [0034] In the next step, a roll laminator covered with silicon rubber was used by superimposing the surface of the insulating film obtained above on the side of the thermoplastic polyimide resin layer and the surface of the copper foil 4 on the side of the insulating layer. The copper foil 4 and the above insulating film were bonded together under the conditions of 240 ° C. and pressure 1.5 MPa. Thereafter, annealing was performed in a batch type autoclave at a temperature of 340 ° C. for 4 hours under a nitrogen atmosphere to obtain a laminate. The obtained laminate was chemically polished in the same manner as in Example 1. COF substrate laminate consisting of a conductor and an insulating layer, with the conductor being formed with a copper foil thickness of 8.0 μΐη and a copper foil surface roughness Rz of 0.6 / im that is not in contact with the insulating film Got. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
[0035] [比較例 1] [0035] [Comparative Example 1]
上記銅箔 2を用い、実施例 1と同様にして積層体を形成して化学研摩を行った。得 られた COF基板用積層体の導体の厚みは 8.0 μ mであり、絶縁層と接している側の 面の表面粗さ Rzが 1.6 μ m、絶縁層と接していない側（レジスト面側）の表面粗さ Rzが 1.2 z mであった。この COF基板用積層体について、実施例 1と同様にして実装を行 レ、、実装時の画像認識、インナーリードの直線性及び COF実装後信頼性について 評価した。結果を表 1に示す。  Using the copper foil 2, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed. The thickness of the conductor of the obtained laminate for COF substrate is 8.0 μm, the surface roughness Rz of the surface in contact with the insulating layer is 1.6 μm, the side not in contact with the insulating layer (resist side) The surface roughness Rz was 1.2 zm. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after mounting the COF were evaluated. The results are shown in Table 1.
[0036] [比較例 2] [0036] [Comparative Example 2]
上記銅箔 3を用い、実施例 1と同様にして積層体を形成して化学研摩を行った。得 られた COF基板用積層体の導体の厚みは 8.0 /i mであり、絶縁層と接している側の 面の表面粗さ Rzが 2.5 /i m、絶縁層と接していない側（レジスト面側）の表面粗さ Rzが 0.9 / mであった。この COF基板用積層体について、実施例 1と同様にして実装を行 レ、、実装時の画像認識、インナーリードの直線性及び COF実装後信頼性について 評価した。結果を表 1に示す。  Using the copper foil 3, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed. The thickness of the conductor of the obtained COF substrate laminate is 8.0 / im, the surface roughness Rz of the surface in contact with the insulating layer is 2.5 / im, the side not in contact with the insulating layer (resist surface side) The surface roughness Rz was 0.9 / m. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after mounting the COF were evaluated. The results are shown in Table 1.
[0037] [比較例 3] [0037] [Comparative Example 3]
銅箔 4を用レ、、実施例 1と同様にして積層体を形成した。この積層体についてはィ匕 学研磨を行わなかった。得られた COF基板用積層体の導体の厚みは 18 μ mであり、 絶縁層と接してレ、る側の面の表面粗さ Rzが 0.8 μ m、絶縁層と接してレ、なレ、側（レジ スト面側）の表面粗さ Rzが 1.0 x mであった。この COF基板用積層体について、実施 例 1と同様にして実装を行レ、、実装時の画像認識、インナーリードの直線性及び CO F実装後信頼性について評価した。結果を表 1に示す。  A laminate was formed in the same manner as in Example 1 using copper foil 4. This laminated body was not subjected to chemical polishing. The thickness of the conductor of the obtained COF substrate laminate is 18 μm, the surface roughness Rz of the surface on the opposite side is 0.8 μm, the surface roughness Rz is in contact with the insulating layer, The surface roughness Rz on the side (resist surface side) was 1.0 xm. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.
[0038] [比較例 4] [0038] [Comparative Example 4]
銅箔 1を用いて、化学研摩を行う手前まで実施例 1と同様にして積層体を作成した。 次いで、この積層体を硫酸濃度 80g/L、過酸化水素濃度 20g/L、添加剤濃度 3%の 研磨液を用いて化学研磨を行い、銅箔の厚み力 .0 / mになるようにすると共に、ポリ イミド樹脂層と接していない銅箔の表面粗さ Rzが 1.6 μ mとなるようにして導体を形成 し、導体と絶縁層とからなる COF基板用積層体を得た。この COF基板用積層体につ いて、実施例 1と同様にして実装を行い、実装時の画像認識、インナーリードの直線 性及び COF実装後信頼性について評価した。結果を表 1に示す。 Using the copper foil 1, a laminate was produced in the same manner as in Example 1 until just before chemical polishing. Next, this laminate is subjected to chemical polishing using a polishing solution having a sulfuric acid concentration of 80 g / L, a hydrogen peroxide concentration of 20 g / L, and an additive concentration of 3% so that the thickness force of the copper foil becomes 0.0 / m. At the same time, a conductor was formed such that the surface roughness Rz of the copper foil not in contact with the polyimide resin layer was 1.6 μm, and a laminate for a COF substrate comprising a conductor and an insulating layer was obtained. This COF substrate laminate was mounted in the same manner as in Example 1 and evaluated for image recognition during mounting, linearity of the inner leads, and reliability after COF mounting. The results are shown in Table 1.
1] 実施例 実施例 比較例 比較例 比較例 比較例  1] Examples Examples Comparative Examples Comparative Examples Comparative Examples Comparative Examples
1 2 1 2 3 4 銅箔 化学 絶縁層側 0. 7 0. 8 1. 6 2. 5 0. 8 0. 7 の Rz 研摩前 レシ'スト面側 2. 0 1. 0 1. 5 1. 5 1. 0 2. 0. 1 2 1 2 3 4 Copper foil Chemical Insulating layer side 0. 7 0. 8 1. 6 2. 5 0. 8 0. 7 Rz Before polishing Resist side 2. 0 1. 0 1. 5 1. 5 1. 0 2. 0.
( i l) 化学 絶縁層側 0. 7 0. 8 1. 6 2. 5 ― 0. 7 (i l) Chemical Insulating layer side 0.7 7 0. 8 1. 6 2. 5 ― 0.7
研磨後 レシ'スト面側 0. 8 0. 6 1. 2 0. 9 ― 1. 6 導体の厚さ （ i m) 8 8 8 8 18 8 実装時の画像認識 〇 〇 X X 〇 X ィンナ一リードの直線性 〇 〇 X X X X  After polishing Resist side 0. 8 0. 6 1. 2 0. 9 ― 1. 6 Conductor thickness (im) 8 8 8 8 18 8 Image recognition when mounted 〇 〇 XX 〇 X Linearity ○ ○ XXXX
C0F実装後信頼性 〇 〇 X X Δ X  Reliability after mounting C0F 〇 〇 X X Δ X

Claims

請求の範囲 The scope of the claims
[1] 導電性金属箔よりなる導体の一方の面に絶縁性樹脂よりなる絶縁層が形成された COF基板用積層体であって、導体の厚みが l〜8 z mであり、導体の絶縁層と接して レ、る面の表面粗さ Rzが 1.0 z m以下であり、かつ、導体の絶縁層と接していない面の 表面粗さ Rzが 1.0 μ m以下であることを特徴とする C〇F基板用積層体。  [1] A laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one side of a conductor made of a conductive metal foil, wherein the conductor has a thickness of 1 to 8 zm, and the conductor insulating layer The surface roughness Rz of the contact surface is 1.0 zm or less, and the surface roughness Rz of the surface that is not in contact with the insulating layer of the conductor is 1.0 μm or less. Laminate for substrate.
[2] 絶縁層が、ポリイミド前駆体樹脂溶液を導体に直接塗布した後、乾燥及び硬化させ て形成したものであることを特徴とする請求項 1記載の COF基板用積層体。  2. The COF substrate laminate according to claim 1, wherein the insulating layer is formed by directly applying a polyimide precursor resin solution to a conductor, followed by drying and curing.
[3] 絶縁層が、熱可塑性樹脂層を有する絶縁フィルムを導体に熱圧着して形成したも のであることを特徴とする請求項 1又は 2記載の COF基板用積層体。  3. The COF substrate laminate according to claim 1 or 2, wherein the insulating layer is formed by thermocompression bonding an insulating film having a thermoplastic resin layer to a conductor.
[4] 少なくとも 10 μ ΐη以上の厚みを有し、かつ、一方の面の表面粗さ Rzが 1.0 /i m以下 である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接していない導電性 金属箔の面を化学研摩してこの導電性金属箔の厚みを 1〜8 μ mにすると共に、表面 粗さ Rzを 1.0 / m以下にして導体が形成されることを特徴とする請求項 1に記載の CO F基板用積層体。  [4] An insulating layer is formed on the surface of the conductive metal foil having a thickness of at least 10 μΐη and having a surface roughness Rz of 1.0 / im or less on one surface, and is in contact with the insulating layer. The conductive metal foil is chemically polished to a thickness of 1-8 μm and the conductor is formed with a surface roughness Rz of 1.0 / m or less. The laminate for a COF substrate according to claim 1.
[5] 請求項 1〜4のいずれかに記載の積層体を用いて形成したことを特徴とする COFフ イルムキャリアテープ。  [5] A COF film carrier tape formed by using the laminate according to any one of claims 1 to 4.
[6] 導体の一方の面に絶縁性樹脂よりなる絶縁層が形成された COF基板用積層体の 製造方法であって、少なくとも 10 x m以上の厚みを有し、かつ、一方の面の表面粗さ Rzが 1.0 μ m以下である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接 していない導電性金属箔の面を化学研摩してこの導電性金属箔の厚みを 1〜8 μ m にすると共に、表面粗さ Rzを 1.0 μ m以下にして導体を形成することを特徴とする CO F基板用積層体の製造方法。  [6] A method for manufacturing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, having a thickness of at least 10 xm and having a surface roughness on one surface An insulating layer is formed on the surface of the conductive metal foil having an Rz of 1.0 μm or less, and the surface of the conductive metal foil not in contact with the insulating layer is chemically polished to reduce the thickness of the conductive metal foil. A method for producing a laminated body for a COF substrate, characterized in that the conductor is formed with a surface roughness Rz of 1.0 μm or less while being 1 to 8 μm.
PCT/JP2005/022825 2004-12-22 2005-12-13 Stacked body for cof substrate, method for manufacturing such stacked body for cof substrate, and cof film carrier tape formed by using such stacked body for cof substrate WO2006068000A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008143032A (en) * 2006-12-11 2008-06-26 Nippon Steel Chem Co Ltd Manufacturing method of flexible copper clad laminate
JP2008168582A (en) * 2007-01-15 2008-07-24 Nippon Steel Chem Co Ltd Manufacturing method of flexible laminated plate
CN102612252A (en) * 2007-09-20 2012-07-25 揖斐电株式会社 Printed wiring board
JP2017069471A (en) * 2015-09-30 2017-04-06 大日本印刷株式会社 Substrate for light-emitting device, module and method for manufacturing substrate for light-emitting device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6094044B2 (en) * 2011-03-23 2017-03-15 大日本印刷株式会社 Heat dissipation board and element using the same
CN103442511A (en) * 2013-08-20 2013-12-11 珠海亚泰电子科技有限公司 High frequency substrate
CN110868799A (en) * 2019-11-15 2020-03-06 江苏上达电子有限公司 Transparent COF design method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003289177A (en) * 2002-03-28 2003-10-10 Asahi Kasei Corp Method of manufacturing wiring board for cof
WO2003096776A1 (en) * 2002-05-13 2003-11-20 Mitsui Mining & Smelting Co.,Ltd. Flexible printed wiring board for chip-on-film
JP2004119961A (en) * 2002-09-02 2004-04-15 Furukawa Techno Research Kk Copper foil for chip-on film, plasma display panel, and high-frequency printed wiring board

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462132B1 (en) * 1998-08-31 2004-12-17 히다치 가세고교 가부시끼가이샤 Abrasive liquid for metal and method for polishing
CN1803964B (en) * 1998-12-28 2010-12-15 日立化成工业株式会社 Materials for polishing liquid for metal, polishing liquid for metal, method for preparation thereof and polishing method using same
TW591089B (en) * 2001-08-09 2004-06-11 Cheil Ind Inc Slurry composition for use in chemical mechanical polishing of metal wiring
TW200404484A (en) * 2002-09-02 2004-03-16 Furukawa Circuit Foil Copper foil for soft circuit board package module, for plasma display, or for radio-frequency printed circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003289177A (en) * 2002-03-28 2003-10-10 Asahi Kasei Corp Method of manufacturing wiring board for cof
WO2003096776A1 (en) * 2002-05-13 2003-11-20 Mitsui Mining & Smelting Co.,Ltd. Flexible printed wiring board for chip-on-film
JP2004119961A (en) * 2002-09-02 2004-04-15 Furukawa Techno Research Kk Copper foil for chip-on film, plasma display panel, and high-frequency printed wiring board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008143032A (en) * 2006-12-11 2008-06-26 Nippon Steel Chem Co Ltd Manufacturing method of flexible copper clad laminate
JP2008168582A (en) * 2007-01-15 2008-07-24 Nippon Steel Chem Co Ltd Manufacturing method of flexible laminated plate
CN102612252A (en) * 2007-09-20 2012-07-25 揖斐电株式会社 Printed wiring board
US8959760B2 (en) 2007-09-20 2015-02-24 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
US9060459B2 (en) 2007-09-20 2015-06-16 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
JP2017069471A (en) * 2015-09-30 2017-04-06 大日本印刷株式会社 Substrate for light-emitting device, module and method for manufacturing substrate for light-emitting device

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