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WO2006041790A2 - Column decoding architecture for flash memories - Google Patents

Column decoding architecture for flash memories Download PDF

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Publication number
WO2006041790A2
WO2006041790A2 PCT/US2005/035528 US2005035528W WO2006041790A2 WO 2006041790 A2 WO2006041790 A2 WO 2006041790A2 US 2005035528 W US2005035528 W US 2005035528W WO 2006041790 A2 WO2006041790 A2 WO 2006041790A2
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WO
WIPO (PCT)
Prior art keywords
page
burst
reading
memory device
logical
Prior art date
Application number
PCT/US2005/035528
Other languages
French (fr)
Other versions
WO2006041790A3 (en
Inventor
Stefano Sivero
Simone Bartoli
Fabio Tassan Caser
Reggiori Riccardo Riva
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT001910A external-priority patent/ITMI20041910A1/en
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO2006041790A2 publication Critical patent/WO2006041790A2/en
Publication of WO2006041790A3 publication Critical patent/WO2006041790A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Definitions

  • the present invention relates to flash memory devices, and more particularly to the column decoder of flash memory devices.
  • An asynchronous flash memory with a page mode read feature reads out a page of four words at every memory access.
  • the memory device When configured in synchronous mode, the memory device must perform sequential reads starting from an initial address. Four words at once are always read.
  • several column decoder architectures have been proposed to implement the above mentioned reading parallelism.
  • Figure 1 illustrates a conventional column decoder for a single bit of a word.
  • SA sense amplifier
  • Each SA 102 is connected through three levels of decoding stages 103-105 to 128 bit lines (BL).
  • the selector multiplexer 101 is used to actively choose one word among the four reads.
  • the signals that control the three levels of decoding stages 103-105 are common for all the bits of the four words, and each group of four words (a logical page) has its own selector multiplexer 101.
  • the resulting total number of selector multiplexers is equal to the bit length of a read word, that in turn is equal to the number of outputs. For example, suppose that the subdivision of the column decoding control bits and selector multiplexer control bits is as follows:
  • the local BL selectors (YO sel ⁇ 7:0> form the first level 105 of the column decoder. These selectors connect the drains of the array cells (local BLs) to the global BLs running all over the device. Each sector has its own set of YO sel ⁇ 7:0> and its own local BLs. Each of the 16 global BL selectors (YO sel ⁇ 7:0> form the first level 105 of the column decoder. These selectors connect the drains of the array cells (local BLs) to the global BLs running all over the device. Each sector has its own set of YO sel ⁇ 7:0> and its own local BLs. Each of the 16 global
  • BLs is connected via YO sel ⁇ 7:0> gated by the eight YO ⁇ 7:0> signals) to eight cells in the array, for a total of 128 bits per output.
  • the 16 global BLs enter the second level of column decoder stage 104, which includes four groups of selectors, each group being made of four YN sel ⁇ 3:0> selectors. They are gated by the four YN ⁇ 3:0> signals.
  • the four global BLs of each group are connected via YN sel ⁇ 3:0> to a main BL, for a total of four main BLs, each connected to a group of four global BL.
  • the four main BLs enter the third level of column decoder stage 103, which includes a group of four selectors YM sel ⁇ 3 :0>, gated by YM ⁇ 3 :0> signals. These selectors connect in turn one of the four main BLs to the sense BL that feeds the sense circuitry.
  • this architecture has a significant limitation in performing reads of groups of consecutive words starting from a word whose initial address is not a multiple of four, or, is "misaligned" to a 4-word boundary.
  • the read implies what is called a logical page boundary crossing.
  • a 4-word boundary will be referred to as a "logical page boundary”
  • 4 words whose addresses only differ for ADD ⁇ 4:0> will be referred to as words belonging to the same logical page. Only the words within the logical page addressed by the first word to be read are valid. The memory device then enters a "wait state", during which invalid data are supplied to the output, negatively impacting the performance of the column decoder.
  • An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible.
  • the memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
  • Figure 1 illustrates a conventional column decoder for a single bit of a word.
  • Figure 2 illustrates a conventional implementation of a column decoder.
  • Figure 3 illustrates a logical page and a burst page in accordance with the present invention.
  • Figure 4 is a flowchart illustrating a preferred embodiment of a method for synchronous read of a memory device in accordance with the present invention.
  • Figure 5 illustrates an example wrap-read performed in accordance with the present invention.
  • Figure 6 illustrates a column decoder implementation in accordance with the present invention.
  • the present invention provides an improved method and device for column decoding for flash memory devices.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
  • Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments.
  • the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
  • the logical page should be somehow "enlarged".
  • the enlarged logical page will be referred to as a "burst page” and the enlarged logical boundary will be referred to as a "burst page boundary”.
  • the present invention thus utilizes a burst page with a length greater than the length of a logical page.
  • the memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of the column decoder level. Changes to the architecture or in the number of column decoder selectors are not required.
  • Figure 3 illustrates a logical page and a burst page in accordance with the present invention.
  • the logical page has a length of four words, while the burst page has a length of 16 words.
  • the minimum length of the burst page is determined by the specifications on the types of reads when the device is turned to synchronous mode.
  • Figure 4 is a flowchart illustrating a preferred embodiment of a method for synchronous read of a memory device in accordance with the present invention.
  • a reading of a plurality of words is started from an initial address, via step 401.
  • it is determined if the initial address is misaligned via step 402.
  • it is determined if the reading is within one burst page, via step 403, where the length of the burst page is greater than a length of the logical page.
  • the memory device If the initial address is misaligned and the reading is not within one burst page, i.e., it crosses the burst page boundary, then the memory device is placed in a wait state when the data corresponding to the burst page boundary crossing is being output, and after this phase, an internal counter is aligned to the last logical page boundary, via step 404.
  • the four bits ADD ⁇ 3:0> generates sixteen YM ⁇ 15:0> signals. Now, the eventual wait states would occur only if the initial address is misaligned to a logical-page boundary of four words (as determined by ADD ⁇ 1 :0>), and the stream of words to be read crosses a burst-page boundary of sixteen words.
  • the number of eventual wait states depends on the amount of misalignment to the logical page boundary:
  • Figure 6 illustrates a column decoder implementation in accordance with the present invention. This implementation is based on the architecture illustrated in Figure 2, but with the YM signals managed to perform the synchronous reads across logical page boundaries within a burst page, as described above with Figures 3 through 5.
  • YM at "x" values means that any YM selection would give invalid data, as shown by the correspondent read words, that are shielded by wait states.
  • the fourth read cycle crosses the burst page boundary. From the fifth cycle onwards, the read page is aligned with a logical page. No more wait states will occur.
  • the architecture for the column decoder illustrated in Figure 6 allows the four words to be read across two logical-pages, if these two logical pages belong to the same burst page.
  • One burst page is made of four consecutive logical pages.
  • the burst page boundary crossing occurs if two words, WA and WB, having
  • the device will align the internal counter to the last logical page boundary crossed, and no more wait states will occur.
  • the illustrated solution can be easily extended.
  • M selectors gated by M independent YM ⁇ M- l:0> signals are provided, and consequently have a total number of YO ⁇ i> and YN ⁇ i> signals equal to 32*(16/M), for an architecture that has 128 bits per output.
  • the burst page boundary M of 128 bits per output flash memory device can be selected in a wide range maintaining the total number of 128 selectors per output, by generating independent YM signals in a number equal to M.
  • the present invention utilizes a burst page with a length greater than the length of a logical page.
  • a misalignment of an initial address occurs, valid reads across logical page boundaries are possible, unless a burst page boundary is crossed.
  • the memory device thus enters the wait state only when a read with a misaligned initial address crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required.

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Abstract

An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.

Description

COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES
FIELD OF THE INVENTION
The present invention relates to flash memory devices, and more particularly to the column decoder of flash memory devices.
BACKGROUND OF THE INVENTION
An asynchronous flash memory with a page mode read feature reads out a page of four words at every memory access. When configured in synchronous mode, the memory device must perform sequential reads starting from an initial address. Four words at once are always read. In the existing state of the art, several column decoder architectures have been proposed to implement the above mentioned reading parallelism.
Figure 1 illustrates a conventional column decoder for a single bit of a word. Here, four words are simultaneously read by means of four sense amplifiers (SA) 102. Each SA 102 is connected through three levels of decoding stages 103-105 to 128 bit lines (BL). The selector multiplexer 101 is used to actively choose one word among the four reads. The signals that control the three levels of decoding stages 103-105 are common for all the bits of the four words, and each group of four words (a logical page) has its own selector multiplexer 101. The resulting total number of selector multiplexers is equal to the bit length of a read word, that in turn is equal to the number of outputs. For example, suppose that the subdivision of the column decoding control bits and selector multiplexer control bits is as follows:
* 2 address bits used to choose one word among the four reads: ADD<1 :0>. This choice follows directly from the memory device's specifications, which demands a scrolling of the read page in asynchronous mode by commuting the two less significant bits of the address. * 7 address bits used to address the 128 cells (bits) in the matrix array: ADD<8:2>
As illustrated in Figure 2, assume that these 7 bits are used to implement the three levels of column decoding states 103-105 in the following way:
* ADD<8:6> decode 8 independent signals (YO)
* ADD<5:4> decode 4 independent signals (YN) * ADD<3:2> decode 4 independent signals (YM) The architecture of the column decoder is hence the following:
* The local BL selectors (YO sel<7:0> form the first level 105 of the column decoder. These selectors connect the drains of the array cells (local BLs) to the global BLs running all over the device. Each sector has its own set of YO sel<7:0> and its own local BLs. Each of the 16 global
BLs is connected via YO sel<7:0> gated by the eight YO<7:0> signals) to eight cells in the array, for a total of 128 bits per output.
* The 16 global BLs enter the second level of column decoder stage 104, which includes four groups of selectors, each group being made of four YN sel<3:0> selectors. They are gated by the four YN<3:0> signals. The four global BLs of each group are connected via YN sel<3:0> to a main BL, for a total of four main BLs, each connected to a group of four global BL.
* The four main BLs enter the third level of column decoder stage 103, which includes a group of four selectors YM sel<3 :0>, gated by YM<3 :0> signals. These selectors connect in turn one of the four main BLs to the sense BL that feeds the sense circuitry.
However, this architecture has a significant limitation in performing reads of groups of consecutive words starting from a word whose initial address is not a multiple of four, or, is "misaligned" to a 4-word boundary. In this case, the read implies what is called a logical page boundary crossing. In this specification, a 4-word boundary will be referred to as a "logical page boundary", and 4 words whose addresses only differ for ADD<4:0> will be referred to as words belonging to the same logical page. Only the words within the logical page addressed by the first word to be read are valid. The memory device then enters a "wait state", during which invalid data are supplied to the output, negatively impacting the performance of the column decoder. The possibility of having wait states occurs in burst mode reading, when consecutive words must be read out from the matrix array starting from an arbitrary address. Some types of burst reads actually imply a logical page boundary crossing. Accordingly, there exists a need for an improved method and device for column decoding for flash memory devices. The improved method and device should minimize the need for the memory device to enter the wait state when a misalignment of the initial address of a read occurs. The present invention addresses such a need.
SUMMARY OF THE INVENTION
An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
BRIEF DESCRIPTION OF THE FIGURES
Figure 1 illustrates a conventional column decoder for a single bit of a word. Figure 2 illustrates a conventional implementation of a column decoder. Figure 3 illustrates a logical page and a burst page in accordance with the present invention. Figure 4 is a flowchart illustrating a preferred embodiment of a method for synchronous read of a memory device in accordance with the present invention.
Figure 5 illustrates an example wrap-read performed in accordance with the present invention.
Figure 6 illustrates a column decoder implementation in accordance with the present invention.
DETAILED DESCRIPTION
The present invention provides an improved method and device for column decoding for flash memory devices. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
To achieve the desired performances, the logical page should be somehow "enlarged". In this specification, the enlarged logical page will be referred to as a "burst page" and the enlarged logical boundary will be referred to as a "burst page boundary". The present invention thus utilizes a burst page with a length greater than the length of a logical page. When a misalignment with respect to a logical page boundary of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of the column decoder level. Changes to the architecture or in the number of column decoder selectors are not required.
To more particularly describe the features of the present invention, please refer to Figures 3 through 6 in conjunction with the discussion below.
Figure 3 illustrates a logical page and a burst page in accordance with the present invention. In the illustrated example, the logical page has a length of four words, while the burst page has a length of 16 words. The minimum length of the burst page is determined by the specifications on the types of reads when the device is turned to synchronous mode.
Figure 4 is a flowchart illustrating a preferred embodiment of a method for synchronous read of a memory device in accordance with the present invention. First, a reading of a plurality of words is started from an initial address, via step 401. Next, it is determined if the initial address is misaligned, via step 402. Then, it is determined if the reading is within one burst page, via step 403, where the length of the burst page is greater than a length of the logical page. If the initial address is misaligned and the reading is not within one burst page, i.e., it crosses the burst page boundary, then the memory device is placed in a wait state when the data corresponding to the burst page boundary crossing is being output, and after this phase, an internal counter is aligned to the last logical page boundary, via step 404.
For example, suppose that a wrap-read of fixed length of 16 words is to be performed without wait states. As illustrated in Figure 5, for such a wrap-read, the column decoder in accordance with the present invention must be able to simultaneously read out groups of four consecutive words among the 16, even with a misalignment of the initial address. This means that a burst page of 16 words length is needed. If the architecture illustrated in Figure 2 is used, in which sixteen YM signals are used instead of four, then the wrapped read could be managed. To properly generate the sixteen YM<15:0> signals in groups of four at every memory access, but in a way dependent on the type of read to be performed, a combination of ADD<3:0> instead of ADD<3:2> can be used. The four bits ADD<3:0> generates sixteen YM<15:0> signals. Now, the eventual wait states would occur only if the initial address is misaligned to a logical-page boundary of four words (as determined by ADD<1 :0>), and the stream of words to be read crosses a burst-page boundary of sixteen words.
The number of eventual wait states depends on the amount of misalignment to the logical page boundary:
*ADD<1 :0> = <00> [0 bit misalignment] → no misalignment, no wait states
*ADD<1 :0> = <01> [1 bit misalignment] → 1 wait state
* ADD<1 :0> = <10> [2 bit misalignment] → 2 wait states
* ADD<1 :0> = <11> [3 bit misalignment] → 3 wait states
Figure 6 illustrates a column decoder implementation in accordance with the present invention. This implementation is based on the architecture illustrated in Figure 2, but with the YM signals managed to perform the synchronous reads across logical page boundaries within a burst page, as described above with Figures 3 through 5.
TABLE 1
Figure imgf000006_0001
As an example, Table 1 above illustrates the YM<15:0> logical values for five consecutive memory accesses, for a continuous length burst read, starting from a word addressed by ADD<3:0> = <0010>. YM at "x" values means that any YM selection would give invalid data, as shown by the correspondent read words, that are shielded by wait states. The fourth read cycle crosses the burst page boundary. From the fifth cycle onwards, the read page is aligned with a logical page. No more wait states will occur.
The architecture for the column decoder illustrated in Figure 6 allows the four words to be read across two logical-pages, if these two logical pages belong to the same burst page. One burst page is made of four consecutive logical pages. The burst page boundary crossing occurs if two words, WA and WB, having |ADD<8:0>_WA- ADD<8:0>_WB|>16 must be read.
Providing the device with an appropriate control logic, once the first eventual burst page boundary has been crossed, causing eventual wait states in the case of an initial address misalignment, the device will align the internal counter to the last logical page boundary crossed, and no more wait states will occur.
If the minimum burst page length is a generic M, M being a multiple of 4, the illustrated solution can be easily extended. M selectors gated by M independent YM<M- l:0> signals are provided, and consequently have a total number of YO<i> and YN<i> signals equal to 32*(16/M), for an architecture that has 128 bits per output. Thus, the burst page boundary M of 128 bits per output flash memory device can be selected in a wide range maintaining the total number of 128 selectors per output, by generating independent YM signals in a number equal to M.
For the column scrambling of Figures 6, where YM<i> selects the ith word within the burst page, when the device operates in asynchronous mode and logical page reads must be performed with a four- word logical page,
YM<i>=YM<i+l>=YM<i+2>==YM<i+3>, for i=0, 4, 8, 12, depending on the values of bits ADD<3:2>:
* ADD<3 :2> = 00 → YM<0>, YM<1>, YM<2>, YM<3> selected * ADD<3 :2> = 01 → YM<4>, YM<5>, YM<6>, YM<7> selected * ADD<3 :2> = 10 → YM<8>, YM<9>, YM<10, YM<11> selected
*ADD<3:2> = 11 → YM<12>, YM<13>, YM<14>, YM<15> selected
An improved method and device for column decoding for flash memory devices has been disclosed. The present invention utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible, unless a burst page boundary is crossed. The memory device thus enters the wait state only when a read with a misaligned initial address crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved. Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A method for synchronous read of a memory device, comprising: reading a plurality of words across a plurality of logical pages starting from an initial address; determining if the initial address is misaligned; determining if the reading is within one burst page, wherein a length of the burst page is greater than a length of one logical page; and placing the memory device in a wait state when data corresponding to a burst page boundary crossing is being output, and then aligning an internal counter to the last logical page boundary, if the initial address is misaligned and the reading is not within one burst page .
2. The method of claim 1 , wherein a minimum length of the burst page is determined by specifications on types of reads when the memory device is turned to a synchronous mode.
3. The method of claim 1, wherein if the initial address is misaligned and the reading is not within one burst page, the reading across the plurality of logical pages within the burst page are valid.
4. A column decoder for a memory device, comprising: a plurality of selector control signals, wherein each selector control signal is independently controlled such that a length of a burst page is greater than a length of a logical page; and a plurality of sense amplifiers coupled to the plurality of selector control signals for reading a plurality of words across a plurality of logical pages starting from an initial address, wherein the memory device is placed within a wait state when data corresponding to a burst page boundary crossing is being output, and an internal counter is aligned to a last logical page boundary, if the initial address is misaligned and the reading is not within one burst page.
5. The device of claim 4, wherein a minimum length of the burst page is determined by specifications on types of reads when the memory device is turned to a synchronous mode.
6. The device of claim 4, wherein if the initial address is misaligned and the reading is not within one burst page, the reading across the plurality of logical pages within the burst page are valid.
7. The device of claim 4, wherein a third level of the column decoder comprises the plurality of selector control signals.
8. The device of claim 4, further comprising: a selector multiplexer for actively choosing a word among a logical page to be read.
PCT/US2005/035528 2004-10-08 2005-09-30 Column decoding architecture for flash memories WO2006041790A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IT001910A ITMI20041910A1 (en) 2004-10-08 2004-10-08 DECODING ARCHITECTURE WITH IMPROVED COLUMNS FOR FLASH MEMORIES
ITMI2004A001910 2004-10-08
US11/126,441 2005-05-11
US11/126,441 US7333389B2 (en) 2004-10-08 2005-05-11 Column decoding architecture for flash memories

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WO2006041790A3 WO2006041790A3 (en) 2007-11-15

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903496A (en) * 1997-06-25 1999-05-11 Intel Corporation Synchronous page-mode non-volatile memory with burst order circuitry
US20020085417A1 (en) * 2000-12-29 2002-07-04 Pekny Theodore T. Burst access memory with zero wait states
US6425062B1 (en) * 1999-09-14 2002-07-23 Intel Corporation Controlling burst sequence in synchronous memories

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903496A (en) * 1997-06-25 1999-05-11 Intel Corporation Synchronous page-mode non-volatile memory with burst order circuitry
US6425062B1 (en) * 1999-09-14 2002-07-23 Intel Corporation Controlling burst sequence in synchronous memories
US20020085417A1 (en) * 2000-12-29 2002-07-04 Pekny Theodore T. Burst access memory with zero wait states

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