WO2005104324A2

WO2005104324A2 - Folded, fully buffered memory module

Info

Publication number: WO2005104324A2
Application number: PCT/US2005/012854
Authority: WO
Inventors: Gary W. Smith
Original assignee: Smith Gary W
Priority date: 2004-04-15
Filing date: 2005-04-15
Publication date: 2005-11-03
Also published as: WO2005104324A3

Abstract

A folded, fully buffered memory module (6) comprising: a planar flexible circuit medium (12); first and second generally quadrangular printed circuit leaves (8, 10) flexibly joined in juxtaposed, spaced disposition by the flexible circuit medium (12), the flexible circuit medium (12) including a network of conductive leads for signal communication between the leaves, the flexible medium being (12) folded to an extent that the leaves are adjacent and parallel to each other; a memory buffer (26) disposed centrally on a face of the second leaf; a plurality of memory devices (28) distributed on the leaves in a star topology about the memory buffer. Preferably the backside of the memory buffer is clear enough for close decoupling of the buffer. Preferably the memory devices are staggered to allow close decoupling of the each memory devices at its backside.

Description

FOLDED, FULLY BUFFERED MEMORY MODULE FIELD OF THE INVENTION This invention relates in general to fully buffered, dual in-line memory modules for computers and network servers, especially those having low profile form factors, e.g., the 1U "blade servers," and more specifically to configuring such modules advantageously as described below. BACKGROUND OF THE INVENTION This invention addresses relatively new problems which have arisen in the art of computers and computer networks due to the increased use of "server blades," which are network servers typically conforming to the industry standard 1U form factor (1.2" in height), and to the growing need for faster memory modules to meet the memory access requirements of higher speed processors. At the Intel Development Forum in 2004, it was shown that meeting fixture server memory requirements using the heretofore widely implemented stub-bus memory architecture is a problem due to inherent impedance discontinuities that effect signal integrity, and that stub-bus channel capacity supply (in terms of gigabytes- capacity/channel) has hit a ceiling. The solution, as presented at the Forum, is an architecture that uses a fully buffered, dual in-line memory module (termed "FB- DIMM"). Figs. 5A and 5B illustrate a front and back side, respectively, of such an FB- DIMM. As can be seen, each FB-DIMM includes an advanced memory buffer ("AMB") 1 which communicates with the module's plurality of on-board dynamic random access memory ("DRAM") devices 2 using point-to-point links for reading and writing to same. The AMB also communicates through the contact comb 3 with an off-board processor memory controller via a high speed serial signaling channel for sending data read from the module and for receiving data to be written to the module. The FB-DIMM architecture solves motherboard level signal routing problems by significantly reducing memory channel pin count. For example, pin count is reduced from about 240 pins for a DDR2 (Double Data Rate II) channel to about 69 pins for a comparable FB-DIMM channel. Although the FB-DIMM architecture solves signal routing problems at the motherboard level, the routing problems are in effect transferred to behind the AMBs and are now at the ends and center of the FB-DIMMs. In the stub-bus architecture, signal routing was generally between the DRAMs and the contact comb, thus runs were fairly uniform in length and short. However, in the FB-DIMM architecture, all DRAM clocks, control signals and data go through the AMB. This causes topology (routing) problems because routing is very congested around the center of the module and routing length ratios are large. For example: (1) when placing components on the current FB-DIMM, the memory devices placed at the far ends of the DIMM are significant distances from the AMB; (2) because of the placement of ECC (error correction code) memory 4 (Fig. 5B) on the back side of the FB-DIMM there is a great deal of difference between the physical distances of the rank memory from the AMB; (3) routing can be difficult due to crowded routing channels running along the horizontal length of the FB-DIMM; and (4) placement of decoupling capacitors close to pins on both the AMB and DRAM are problematic, especially for the AMB because of the placement of the ECC memory directly behind the AMB on the backside of the FB-DIMM. These problems are especially true for 1U servers because of the height limitation imposed on FB-DIMMs. This invention solves the above-explained problems. FB-DIMMs according to this invention incorporate a novel topology in which memory components are placed and staggered on three sides of the AMB rather than just two, i.e., in a "star" pattern arrangement around the AMB. This star topology reduces or eliminates the routing problems by: (1) significantly reducing trace length ratios or deltas between the memory components in the rank; (2) significantly reducing maximum overall trace lengths; and (3) providing easier routing due to wider distribution of traces. This invention also provides improved power voltage decoupling of DRAMs and AMBs by allowing decoupling capacitors to be locate directly behind the devices. This star topology is also compatible with 1U standards - allows standard height (1.2"). Furthermore, this invention is also adaptable for high capacity FB-DIMMs, e.g., thirty-six on-board DRAM devices, without the need to physically stack devices atop each other, as is conventionally done to create high capacity DIMMs. Furthermore, this invention significantly enhances heat dissipation away from the integrated circuit devices by providing more (as compared to prior disclosed FB-DIMMs) board mass for thermal dispersion. As for pertinent art, United States Patent 5,224,023, discloses pairs of quadrangular, rigid printed circuit boards are mounted on opposite sides of a flexible printed circuit substrate having a network of conductive leads and connecting stations applied thereto. The rigid boards have memory devices mounted thereon, and the pairs of boards mounted on the flexible substrate are spaced to allow for folding of the substrate. United States Patent 5,949,657 discloses the attachment of a one rigid printed circuit board to another by means of soldering jumper wires, connectors or pins of various types between the two assemblies. Neither of these patents disclose fully buffered memory modules, and so they do not address or even mention the problems explained above. Further advantages and attributes of this invention are readily discernible upon a reading of the text hereinafter including the claims and abstract, and a viewing of the drawings. SUMMARY OF THE INVENTION An object of this invention is to provide FB-DIMMs that incorporate a novel topology in which memory components are placed on three sides of the AMB rather than just two, i.e., in a "star" pattern arrangement around the AMB. A further object of this invention is to provide FB-DIMMs with a topology that reduces or eliminates the routing problems of prior disclosed FB-DIMMs by significantly reducing trace length ratios or deltas between the memory components in the rank. A further object of this invention is to provide FB-DIMMs with a topology that reduces or eliminates the routing problems of prior disclosed FB-DIMMs by significantly reducing maximum overall trace lengths. A further object of this invention is to provide FB-DIMMs with a topology that reduces or eliminates the routing problems of prior disclosed FB-DIMMs by providing easier routing due to wider distribution of traces. A further object of this invention is to provide FB-DIMMs with a topology that also provides improved power voltage decoupling of DRAMs and AMBs by allowing decoupling capacitors to be located directly behind the devices. A further object of this invention is to provide FB-DIMMs with a star topology that is also compatible with 1U height requirements. A further object of this invention is to provide FB-DIMMs with one or more of the characteristics as described in the preceding text, but which is also adaptable for high capacity FB-DIMMs, e.g., thirty-six on-board DRAM devices, without the need to physically stack devices atop each other, as is conventionally done to create high capacity DIMMs. A further object of this invention is to provide FB-DIMMs that significantly enhance heat dissipation away from the integrated circuit devices by providing more (as compared to prior disclosed FB-DIMMs) board mass for thermal dispersion. These objects, and others unlisted above but readily discernible upon a reading of this document while viewing the appended drawings, are accomplished by a preferably pluggable folded memory module that includes, a folded, fully buffered memory module comprising: a planar flexible circuit medium; first and second generally quadrangular printed circuit leaves flexibly joined in juxtaposed, spaced disposition by the flexible circuit medium, the flexible circuit medium including a network of conductive leads for signal communication between the leaves, the flexible medium being folded to an extent that the leaves are adjacent and parallel to each other; a memory buffer disposed centrally on a face of the second leaf; a plurality of memory devices distributed on the leaves in a star topology about the memory buffer; and the second leaf including a terminal connector, the processor communicating with the memory buffer via the connector for accessing the memory devices. Preferably the backside of the memory buffer is clear enough for close decoupling of the memory buffer on its backside. Preferably each leaf comprises a pair of rigid printed circuit boards symmetrically mounted to opposite sides of the flexible circuit medium such that said each pair sandwiches the flexible medium therebetween. Preferably the memory devices are staggered to allow close decoupling of the each memory devices at its backside. The scope of protection sought by the inventor may be fairly gleaned from the specification herein which includes the appended claims and abstract. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a preferred embodiment of this invention in a partially folded state, this embodiment incorporating sixteen memory integrated circuits, i.e., devices. Fig. 2 is a side sectional view of the memory module of Fig. 1 in its folded, ready- to-use state. Fig. 3 is a plan view of the memory module of Fig. 1 in a pre-folded state. Fig. 4 is a plan view of an alternative embodiment of this invention in a pre-folded state, this embodiment incorporating thirty-two memory devices. Figs. 5A and 5B are plan views of the front and back of prior disclosed FB- DIMMs. DESCRIPTION OF THE PREFERRED EMBODIMENTS Turning now to the drawings, where elements are identified by numerals and like elements are identified by like numerals throughout, Figs.l and 2 illustrate a preferred folded memory module embodiment of this invention, generally designated 6, to include first and second generally quadrangular leaves, 8 and 10 respectively, flexibly joined in juxtaposed, spaced disposition by a planar flexible circuit medium 12 having a network of conductive leads for signal communication between the leaves. The leaves are spaced apart sufficiently to allow for folding of the flexible medium to an extent that in operative configuration the leaves are adjacent and parallel to each other, and held that way by rivets 13. Each leaf comprises a pair of rigid printed circuit boards, matching in form and symmetrically mounted to opposite sides of the flexible circuit medium such that said each pair sandwiches the flexible medium therebetween. The first leaf includes rigid boards 14 and 16, and the second leaf includes rigid boards 18 and 20. Signal vias (not shown) provide suitable communication between the flexible medium and the boards, and between the boards. The second leaf 10 has a comb-like contact terminal defined along a linear edge distal from the fold, the terminal being preferably in the form of a male edge connector 22, for physically and electrically coupling the memory module to a matching female connector 24 mounted to a system board, e.g., a motherboard 25. The terminal 22 provides the coupling by which the module is ultimately in signal communication with a processor's memory controller or the like (not shown) to provide access to the module's memory by the processor. The second leaf 10 is also illustrated to include a centrally disposed AMB 26 mounted to its outer face, i.e., rigid board 20, and both leaves are shown to further include a plurality of memory devices 28 mounted to all faces of the leaves. As illustrated especially in Figs. 2 and 3, the memory devices 28 of a folded memory module according to this invention are distributed around the AMB 26 in a "star" topology, i.e., they are placed on three sides of the AMB rather than just the two sides as in the prior art. As illustrated, the memory devices on the second leaf 10, both back and front side, are disposed in a symmetrical pattern to the right and left of the AMB (as referenced to the orientation of Fig. 1) leaving the back side of the AMB clear for close-in decoupling of the AMB. The memory devices on the first leaf 8 are all huddled symmetrically as close to the AMB as possible, and it can be seen, especially in Fig. 2, that the distance (<2X) of the most remote memory devices from the AMB is no more than about twice the distance (X) of the nearest devices. This is a very significant improvement over the prior art FB-DIMMs wherein the devices at the ends are much farther from the AMB. Thus, the star topology of this invention significantly reduces trace length ratios or deltas between the memory components in the rank, and significantly reduces the maximum overall trace lengths. This invention also provides easier signal trace routing because the routing can be more widely distributed via the flexible circuit medium. In addition, the two leaves and the flexible medium promote more efficient heat dissipation from the devices because the added mass has a much greater capacity for si-f-king heat. Referring again to Figs. 1-3, the memory devices 28 of both leaves, 8 and 10, are staggered to allow disposition of decoupling capacitors 30 for each device directly behind said each device. It should be noted that the star topology brings the devices so much closer to the AMB that space can be added between device for tight decoupling while still improving on trace ratios and deltas. Referring to Fig. 4, this invention can also be embodied in higher capacity modules, e.g., a thirty-six device module, while still having advantageous and novel features. Even in such more densely populated modules, the back of the AMB is still clear for tight decoupling, and the flexible circuit medium again allows for easier routing due to wider distribution of signal traces. Also, the increased module mass again promotes more efficient heat dissipation. While the invention has been described with reference to a particular embodiment thereof, those skilled in the art will be able to make various modifications to the described embodiment of the invention without departing from the true spirit and scope thereof.

I CLAIM:

Claims

1. For a processor, a folded, fully buffered memory module comprising: (a) a planar flexible circuit medium; (b) first and second generally quadrangular printed circuit leaves flexibly joined in juxtaposed, spaced disposition by the flexible circuit medium, the flexible circuit medium including a network of conductive leads for signal communication between the leaves, the flexible medium being folded to an extent that the leaves are adjacent and parallel to each other; (c) a memory buffer disposed centrally on a face of the second leaf; (d) a plurality of memory devices distributed on the leaves in a star topology about the memory buffer; and (e) the second leaf including a terminal connector, the processor communicating with the memory buffer via the connector for accessing the memory devices.

2. The module according to claim 1 wherein the backside of the memory buffer is clear enough for close-in decoupling of the memory buffer on its backside.

3. The module according to claim 1 wherein each leaf comprises a pair of rigid printed circuit boards symmetrically mounted to opposite sides of the flexible circuit medium.

4. The module according to claim 1 wherein the memory devices are mounted on both faces of each leaf, and the devices on one face of said each leaf are staggered with respect to the devices on the other face of said each leaf to allow close decoupling of the each memory device at its backside.

5. A buffered electronic memory module comprising: (a) two planar printed circuit leaves each for mounting memory devices thereon, the leaves being disposed parallel and spaced apart in relation to each other; (b) a planar flexible circuit medium folded along a line for mechanically joining the two leaves along the fold line, the flexible medium including a network of paths for signal communication between the two leaves; (c) a memory buffer centrally disposed on a face of one of the leaves; (d) a plurality of memory devices in communication with the buffer via signal paths in the leaves and in the flexible medium, the memory devices being distributed on the leaves about the memory buffer in a star topology for minimizing signal path distances between the memory devices and the memory buffer; and (e) said one of the leaves including a memory access signal terminal in communication with the memory buffer.

6. The memory module according to claim 5 fiirther comprising point to point links for communication between the memory devices and the memory buffer.

7. The memory module according to claim 5 wherein each leaf comprises a pair of rigid printed circuit boards symmetrically mounted to opposite sides of the flexible circuit medium.

8. The memory module according to claim 5 wherein memory devices are mounted on both faces of each leaf, and the devices on one face of said each leaf are staggered with respect to the devices on the other face of said each leaf to allow close decoupling of the each memory device at its backside.

9. The memory module according to claim 5 wherein the plugged-in height of the folded leaves is compatible with 1U form factor standards. The module according to claim 5 wherein the backside of the memory buffer is clear enough for close-in decoupling of the memory buffer on its backside.