WO2005041162A1

WO2005041162A1 - Method and apparatus for processing video pictures for display on a display device

Info

Publication number: WO2005041162A1
Application number: PCT/EP2004/011085
Authority: WO
Inventors: Sébastien Weitbruch; Cédric Thebault; Carlos Correa
Original assignee: Thomson Licensing
Priority date: 2003-10-15
Filing date: 2004-10-04
Publication date: 2005-05-06

Abstract

The present invention relates to a method for processing video pictures for display on a display device comprising a plurality of lines constituted by luminous elements called cells corresponding to the pixels of a picture, wherein the time duration of a video frame is divided into a plurality of sub-field periods during which the cells can be activated for light emission, a sub-field period being divided into an addressing period wherein the plurality of lines is scanned line by line, a sustaining period and an erasing period. The method comprises the following steps: measurement, for each sub-field, of the number of pixels per line using said sub-field, and determination of the length of the addressing period of said sub-field based on the result of the measurement.

Description

METHOD AND APPARATUS FOR PROCESSING VIDEO PICTURES FOR DISPLAY ON A DISPLAY DEVICE

The present invention relates to a method and an apparatus for processing video pictures for display on a display device as well as to an apparatus for carrying out said method. More specifically, the invention relates to a method which improves the brightness and/or the picture quality of pictures, which are displayed on matrix displays like plasma display panels (PDP) or other display devices based on the principle of duty cycle modulation (pulse width modulation) of light emission.

BACKGROUND OF THE INVENTION A Plasma Display Panel (PDP) utilizes a matrix array of discharge cells which could only be "ON" or "OFF". Also unlike a CRT or LCD in which gray levels are expressed by analog control of the light emission, a PDP controls the gray level by modulating the number of light pulses per frame. For that purpose each frame will be decomposed in sub-periods called "sub- fields". In order to produce these light pulses, an electrical discharge will appear in a gas called plasma and the produced UV radiation will illuminate a colored phosphor. In standard addressing methods like the method known as ADS (Address Display Separated), all the basic cycles of a sub-field period are made one after the other. In order to select which pixel should be lighted, a first selective operation called addressing (or scanning) will create a charge in the cell to be lighted. Each plasma cell can be considered as a capacitor which keeps the charge for a long time. Afterwards, a general operation called "sustain" applied during the lighting period will add charges in the cell. In the cell addressed during the first selective operation, the two charges will build up and that brings between two electrodes of the cell a firing voltage. The cell will light during the whole sustain operation of each specific sub- field. At the end, an erase operation will remove all the stored charges to prepare the cell for a new cycle. As mentioned above, the PDP controls the gray level by modulating the number of light pulses per frame. This time modulation will be integrated by the eye over a period corresponding to the human eye time response. In the field of video processing, a 8-bit representation of a luminance level is very common and will be taken as example used to simplify the disclosure. In that case each level will be represented by a combination of the

8 following bits: 1 - 2- 4 - 8 - 16 - 32 - 64 - 128 To realize such a coding scheme with the PDP technology, the frame period will be divided in 8 lighting periods (or sub-fields), each one corresponding to one of the 8 bits. The number of light pulses for the bit "2" is the double as for the bit "1", and so forth. With these 8 sub-fields, it is possible through sub-field combination, to build the 256 gray levels. For example, the value 19 corresponding to the binary code word (11001000) is obtained by combination of sub-fields 1+2+16. It is obvious that the number and weight of the used sub-fields may be modified according to the code used. The standard principle used to generate this gray modulation is based on the ADS (Address Display Separated) principle, in which all operations are performed at different times on the whole panel. For illustration, figure 1 represents an example of ADS principle based on an 8-bit encoding scheme with only one priming at the beginning of the frame. Each sub-field SF1 , SF2, SF3 SF8 comprises an erase period, an addressing period and a sustain period as shown in detail in figure 2. This figure illustrates the fact that excepted the addressing period, all operations are performed on the whole panel in an uniform way. The addressing operation, as already said, is a selective operation which is done line by line. The overall duration of the addressing period is commonly called addressing time and represented on the figures with T_a<_. On standard panels, this time is equivalent to the time used for each line (T) multiplied by the number of lines (N) since the addressing time T is the same for all lines. This principle can be seen on figures 2 and 3. Figure 2 shows that, for a given sub-field, the activation of the addressing operation for each line has the same duration T_/. Then, the complete addressing time per sub-field is computed as T_ad = NχT, where N represents the total amount of addressed lines. Actually, the only variation which can be found in the plasma field is a variation depending on the sub-field itself. In other words, the addressing time for all lines stays the same inside one sub-field writing stage but is different from sub-field to sub-field. The table A below gives an example of one flexible addressing found on one actual product: Table A

In the example described with table A, the addressing time becomes shorter when the sub-field weight increases. This is due to the fact that the more sustain pulses a sub-field contains the better the addressing efficiency is. To improve the panel brightness and the picture quality, it has been proposed, in European Patent Application 1 365 382 in the name of

Deutsche Thomson Licensing SA, to have for all sub-fields a different addressing speed depending on the panel behavior. In this case, as shown on Figure 4, the length of the addressing period will be different from line to line. This is shown by the length of the addressing pulses Tl,1 ; Tl,2; Tl,3;

TI.N-1; TI,N of the different lines linel , Iine2, Iine3 line N-1 , line N.

Therefore, the overall addressing time per sub-field becomes: n=N

T_ad(SF) = ∑T,(n,SF) where N represents the total number of lines. In order n=ι to simplify the exposition, the addressing time per line will be defined as following: T,(n,SF) = T_l(SF)χ f(n) where T(SF) represents the average addressing time per line and f(n) is a function of the line number called speed factor. Under this assumption, the value T(SF) will be similar to the standard addressing time known today and will follow the same rules. Concerning the evolution of the addressing time per line, there are three categories of dependency: - a panel homogeneity dependency: this parameter is related to the fact that the panel does not have the same behavior among the whole screen; - a dependency of priming efficiency: the priming operation enables a rapid writing but its efficiency could decreases in the time (depending on the panel technology); - a dependency of sustain efficiency: the writing operation is directly followed by the sustain operation; since the efficiency of the writing operation is linked to the capacity effect of the panel, this could change with the delay to the sustain operation. However, as shown on figure 5, the panels may have an addressing jitter that depends from the load of the line itself. SUMMARY OF THE INVENTION

So, the invention proposes a new method for processing video pictures for display on a display device comprising a plurality of lines constituted by luminous elements called cells corresponding to the pixels of a picture, wherein the time duration of a video frame is divided into a plurality of sub-field periods during which the cells can be activated for light emission, a sub-field period being divided into an addressing period wherein the plurality of lines is scanned line by line, a sustaining period and an erasing period.

The method comprises at least the following steps: - measurement, for each sub-field, of the number of pixels per line using said sub-field, and - determination of the length of the addressing period of said sub-field based on the result of the measurement.

According to the invention, the addressing period per sub-field is given by the formula n=N T_ad(SF) = ∑T,(n,SF) n=l

Where N represents the total number of lines of the display device, T^n.SF) represents the addressing time for the line n and the sub-field SF, and is defined by : T_l(n,SF) = T,(SF)xg(n,SF) where T,(SF) represents the average addressing time per line for the sub-field SF and g(n,SF) is equal to f(n)xh(n,SF) where f(n) is the speed factor defined in EP 1365382 for the line n and h(n,SF) is the number of pixels in line n using the sub-field SF.

With this method, when the number of pixels using a sub-field SF in a line n is zero, the addressing time for said sub-field and said line is minimal regardless of the other parameters (panel homogeneity, priming process efficiency, sustain period efficiency) of the speed factor and when the all pixels in a line n use a sub-field SF, the addressing time for this sub-field and this line is maximal.

The invention concerns also to an apparatus for processing video pictures to be displayed on a display device based on the principle of duty cycle modulation of light emission comprising a plurality of lines constituted by luminous elements called cells corresponding to the pixels of a picture, processing circuits for processing RGB data of a picture and driving circuits for scanning the lines of cells of the display device line by line. Said apparatus further comprises : a measurement circuit for measuring for each sub-field, of the number of pixels per line using said sub-field, and means for determining the length of the addressing period of said sub- field based on the result of the measured number.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are illustrated in the drawings and are explained in more details in the following description. In the figures: Figure 1 already described shows a sub-field organization according to the ADS principle; Figure 2 already described shows in detail the operations for one sub-field; Figure 3 already described shows standard addressing waveforms; Figure 4 already described shows addressing waveforms according to a prior art solution; Figure 5 is a schematic view of a panel showing the jitter problem; Figure 6 presents the decomposition of an input picture in a basic 8 sub-fields mode; Figure 7 presents the vertical repartition of sub-field load for two different sub-fields; Figure 8 is a block diagram of an apparatus implementing the present invention; Figure 9 is a schematic view explaining the operation of circuits 13, 14 and 15 in Figure 8, and Figure 10 is a schematic view explaining the present invention.

EXEMPLARY EMBODIMENTS According to the method of the present invention, for each sub- field, the number of pixels per line using this sub-field is measured. The counting is made line by line and sub-field per sub-field. The result of the counting is sent to a memory such as a Look-Up Table (LUT) which outputs a speed factor related to the possible reduction of the addressing speed from the current line compared to a full-loaded line. Depending on the sub-field and on its load (i.e. result of the counting), the LUT will determine the addressing speed that should be used for the specific line and the specific sub-field. Like in the European Patent Application 1 365 382, the addressing n=N period per sub-field is given by the formula T_ad(SF) = ^T,(n,SF) where n=ι - N represents the total number of lines of the display device, - T,(n,SF) represents the addressing time for the line n and the sub- field SF. But according to the invention, T,(n,SF) is defined by T_l(n,SF) = T,(SF)xg(n,SF) where T,(SF) represents the average addressing time per line for the sub-field SF and g(n,SF) is equal to f(n)xh(n,SF) where f(n) is the speed factor for the line n defined previously (depending on panel homogeneity, priming efficiency, sustain efficiency) and h(n,SF) is the number of pixels in line n using the sub- field SF (load of the line n for the sub-field SF).

With the method of the present invention, a really dedicated optimization of the addressing speed is obtained. It is also possible to save time for additional sub-fields. In case of peak white where the load is mainly very limited, it is possible to address faster and then to use more sub-fields or more sustains for better picture performances. According to another feature of the invention, when a sub-field is absolutely not used on a line, then the line could be addressed like a dummy line, i.e. with a very short addressing pulse. Figure 6 presents the decomposition of an input picture in a basic 8 sub-fields mode having the weights: 1-2-4-8-16-32-64-128. So the original picture coded on 8 bits video is decomposed in 8 pictures, each picture corresponding to a sub-field with a specific weight, such as sub-field 1 with a weight 1 , sub-field 2 with a weight 2, sub-field 3 with a weight 4 and so on up to sub-field 8 with a weight of 128. This figure shows that the various sub- fields have different vertical repartition of their load. So, as shown on figure 7, the sub-field 4 has a quite homogeneous vertical repartition while the sub- field 7 shows a vertical variation of its distribution among the screen. The present invention aims to use this type of information to adapt the addressing speed. So, in the above examples relating to sub-field 4 and sub- field 7, after measuring the sub-field distribution, it will be possible to adapt vertically the addressing speed (the curve will be similar to the load curve): the addressing speed will be quite constant for all lines of sub-field 4 whereas there will be a strong variation of the speed for sub-field 7 following the loading curve. The longest addressing time will be obtained for a full- loaded line and corresponds to the most critical situation. On the other hand, the less-loaded line will be addressed much faster. Figure 8 represents a possible implementation of an apparatus for carrying out the method of the invention. This type of apparatus is already described in PCT application WO 00/46782. It comprises a video degamma circuit 10. RGB data from circuit 10 is analyzed in an average power measure circuit 11 which gives the computed average power value (APL) to a PWE (peak white Enhancement) control circuit 12. One computation can ι ππ=M be done as following: APL = ^(R_m + G_m + B_m) where M represents 3 • M _m=1 the total amount of pixels and R_m, G_m, B_m are RGB video for the pixel m. The control PWE circuit 12 consults its internal power level mode table located in a LUT 16 and directly generates the selected mode control signals for the other processing circuits. It selects the sustain table to be used and the sub- field encoding table to be used (CODING). It also controls the writing of RGB pixel data in the frame memory 14 (WR), the reading of RGB sub-field data from the second frame memory 14 (RD), and the serial to parallel conversion circuit 15 (SP). After the serial-to-parallel conversion done in block 15, the sub-fields information are read line-by-line from the memory and forwarded to the line-load measurement block 17 that performs the analysis of the line- load for each sub-field. The output of this block is sent to the overall control block that will update the addressing parameters for the current line. Finally it generates the SCAN and SUSTAIN pulses required to drive the PDP driver circuits. Also in that case, the length of the addressing signal (addressing speed) will be taken from the LUT 16 and this, for each line of the panel and for each sub-field. Two frame memories are required. Data is written pixel-wise, but read sub-field-wise. In order to read the complete first sub-field a whole frame must already be present in the memory. In a practical implementation, two whole frame memories are present, and while one frame memory is being written, the other is being read, avoiding in this way reading the wrong data. In a cost optimized architecture, the two frame memories are probably located on the same SDRAM memory IC, and access to the two frames is time multiplexed. The whole computation of all parameters from the concept of the present invention will be made one time for a given panel technology and then stored in a PROM or LUT of the plasma dedicated IC. For a better understanding of the present invention, the operation of circuits 13, 14 and 15 will be explained with reference to figure 9. From the input picture, R, G, B video data stream is coming in parallel (all bits from one pixel being available at the same time) and is also converted in parallel in sub-field data in sub-field encoding tables (circuit 13 in figure 8). All sub- fields from one pixel are available at the same time. In this example, a sub- field code based on 11 sub-fields has been selected for illustration. The transposition will save the data in serial (all pixels from sub-field n are written together in the memory) and the read of the sub-field n will take place line by line from the same memory. These data will be analyzed by the line-load measurement unit 17 as described below. According to the invention, a counter (actually 13 bits are mandatory) is reset at the beginning of each line read out of the memory. Then, the total amount of pixels switched ON on this line are summed. The result is used as an entry in a Look-Up-Table (LUT). The output of the LUT is a speed factor related to the possible reduction of the addressing speed from the current line compared to a full-loaded line. The number of inputs of the LUT is at most equal to the number of cells from a line of the screen (WVGA=852x3=2556, WXGA= 1365x3=4095, HDTV= 1920x3=5760). The output of the LUT is then used to modify the standard addressing speed of the current line from standard concept (all line equal with only a difference from sub-field to sub-field or from APL level to another level). This concept is described with reference to figure 10. The current line is read out of the memory towards a line-memory used for storage of the data just before writing. This line memory is not compulsory. For each sample read out of the memory, a counter is increased from the value of this pixel (0 or 1); the counter being reset at the beginning of each new line. When the line has been fully read out, the output of this counter (65% in our example meaning 65% shorter addressing time), is then forwarded to a first LUT corresponding to a load speed factor LUT. The output of this LUT is multiplied by the general speed factor of the line and of the sub-field. For instance, the line speed of the current line, current sub-field and current APL is 1.9 μs. In that case, the new output of the block is 1.235 μs (1.9 x 0.65), which is used by the waveform generator to generate the appropriate scan pulse with now a duration of 1.235μs. During that time the column data are put on the output of the data driver.

Claims

1 - Method for processing video pictures for display on a display device comprising a plurality of lines constituted by luminous elements called cells corresponding to the pixels of a picture, wherein the time duration of a video frame is divided into a plurality of sub-field periods during which the cells can be activated for light emission, a sub-field period being divided into an addressing period wherein the plurality of lines is scanned line by line, a sustaining period and an erasing period, characterized by the following steps: - measurement, for each sub-field, of the number of pixels per line using said sub-field, and - determination of the length of the addressing period of said sub-field based on the result of the measurement.

2 - Method according to claim 1 , characterized in that the addressing period per sub-field is given by the formula

T_ad(SF) = ∑T,(n,SF) n=l

Where N represents the total number of lines of the display device, T,(n,SF) represents the addressing time for the line n and the sub-field SF, and is defined by : T,(n,SF) = T_l(SF)xg(n,SF) where T,(SF) represents the average addressing time per line for the sub-field SF and g(n,SF) is equal to f(n)xh(n,SF) where f(n) is a speed factor for the line n and h(n,SF) is the number of pixels in line n using the sub-field SF.

3. Method according to claim 2, characterized in that the speed factor f(n) is depending on panel homogeneity and/or priming process efficiency and/or sustaining period efficiency in said display device.

4. Method according to one of the preceding claims, characterized in that, when the number of pixels using a sub-field SF in a line n is zero, the addressing time for said sub-field and said line is minimal.

5. Apparatus for processing video pictures to be displayed on a display device based on the principle of duty cycle modulation of light emission comprising a plurality of lines constituted by luminous elements called cells corresponding to the pixels of a picture, processing circuits for processing RGB data of a picture and driving circuits for scanning the lines of cells of the display device line by line, said apparatus further comprising : a measurement circuit for measuring for each sub-field, of the number of pixels per line using said sub-field, and means for determining the length of the addressing period of said sub- field based on the result of the measured number.

6. Apparatus according to claim 5, characterized in that the measurement circuit is a counter.