WO2004114050A2

WO2004114050A2 - Method to evaluate and improve the testability of electronic products

Info

Publication number: WO2004114050A2
Application number: PCT/IL2004/000560
Authority: WO
Inventors: Shmuel Livne
Original assignee: Shmuel Livne
Priority date: 2003-06-25
Filing date: 2004-06-23
Publication date: 2004-12-29
Also published as: WO2004114050A3; IL156634A0

Abstract

A method for Design For Testing (DFT), which presents testability and a methodology to provide the testability. This method defines the testability presentation format of electronic products in a simple form (202). One number or few numbers is used from the initial stage of the electronic product design for integrated circuits (IC's), systems on chip (SOC's), electronic boards, and electronic systems, to the final stage of the design wherein volume production is begun. The testability number becomes more accurate as more information (203) is provided as progress is made through the design stages (201). The methodology is a complete technique to provide the testability numbers.

Description

METHOD TO EVALUATE AND IMPROVE THE TESTABILITY OF ELECTRONIC

PRODUCTS

5 FIELD OF THE INVENTION

The field of invention is the Design for Testability (DFT) of an electronic product that combines testing technologies. The DFT in this invention provides Multi Technology DFT mainly based on the advance testing method IEEE standards 1149.x 0 and combines the use of other testing technologies, i.e., In Circuit Testing (ICT), functional and Automatic Optic Inspection (AOI) to achieve testing of the Electronic product up to 100% testability.

5 BACKGROUND OF THE INVENTION

IEEE 1149.1 , also known as Joint Test Action Group (JTAG) or Boundary Scan, was introduced in 1990. JTAG is the informal name given to the consortium that developed the IEEE 1149.1 standard. This standard endeavors to solve test and 0 diagnostic problems arising from loss of physical access caused by the increasing use of high pin count and ball grid array (BGA) devices, multi-layer printed circuit boards

(RGB's), and densely packed circuit board assemblies. The standard outlines predefined protocols for testing and diagnosing manufacturing faults.

For the past 20+ years, access-based testing called In Circuit Testing (ICT) has 5 been the workhorse in board-level test. ICT provides component-level testing and diagnostics. Changes in device packaging technology, shrinking component geometries, increasing device pin-count and disappearance of test pads has challenged the practicality of ICT in many applications. The move in most designs to operate at higher frequencies has further shortened the distances between )0 semiconductor devices. Increased complexity and lack of physical access to circuits makes testing costly and time-consuming. Design for Test (DFT) is required to manage complexity, minimize test development time, and reduce overall manufacturing costs.

Boundary Scan, formally known as IEEE/ANSI 1149.1, is a standard which facilitates testing, device programming and debugging at the semiconductor, board and system levels. This methodology of incorporating design-for-test allows complete control and access to the boundary pins of a device without the need for a bed-of -nails or other test equipment.

The DFT is not getting appropriate attention during the design stages of electronic products, and particularly in the initial design stage, during which only components are chosen and the designer makes the connections between the components. The designer is usually concentrating at this design stage in the functionality of the design. The designer is not paying appropriate attention to the DFT in this critical design stage to the future testability of the electronic product being designed

The reasons that the testability is not getting the appropriate attention include: lack of a method to provide a meaningful form to present the testability of the electronic product that can be understood by the designer, by the managers, by the operation persons and by the full turn key production subcontractors; and lack of tools to provide user-friendly testability in a way that implements the information the design can provide during the different stages of the design of electronic products.

Therefore, there is a need to overcome the disadvantages of the prior art, and to improve the Design For Test (DFT) process

SUMMARY OF THE INVENTION

Accordingly, it is a principal object of the present invention to provide a Design For Test method, which is easy to use and effective for the designer, for his manager and for the production persons.

It is another principle object of the present invention that the testability form should be simple and intuitively understood by anyone using it. This is why a simple percentage number is chosen by way of example to represent the testability, but any single number or single value or a few numbers or a few values with a simple form can be used

The Testability Number is based on two kinds of items built into electronic products: components; and nets. Components can be single discrete components (resistors, capacitors, transistors, etc.) up to subsystems of the electronic product. The net is the physical connection between the components.

Testability is defined by three parameters: controllable; observable; and debug- able. Controllable is defined as being able to provide known input to the item in the electronic product. Observable is defined as being able to capture the output of the item in the electronic product. Debug-able is defined as the ability to detect the failure item in the electronic product that should be replaced and the ability to correct the failure in the electronic product. In the present invention the testability of items in an electronic product is defined as fully testable if the item can be controlled and observed, not testable if the item cannot be controlled or observed and partially testable if only a part of the Item (component or net) can be controlled and observed without interference from the part of the item that is not testable. The method and technique to generate the Testability Number for the electronic product during the design stages is based on information provided at the design stage, and as the electronic product design progresses and more information on the design can be provided, the Testability Number of the design gains more information and gets more accurate. The Testability Number and the methodology provide the electronic product designers with the tools to increase the testability of the electronic product and enable the designer to achieve an electronic product that is full testable. Such an electronic product can be produced by a full turn key subcontractor, tested by the subcontractor and sent by the subcontractor to the final customers with the confidence that the electronic product will function without any problems.

The simple form of Testability value/number that is chosen in the present invention, as an example, is the following Testability number. The Testability Number is defined as a five digit number in percentage form represented as ABC.DE, wherein the number 100.00 % presents full testability.

Each Item in the electronic product, components and nets are weighted in terms of the testability of the electronic product. If the Item is fully testable all the item weight contributes to the testability of the electronic product. An item that is not testable will contribute zero (0) value to the testability of the electronic product. If the item is partially testable only a fraction of the item's weight will contribute to the testability of electronic product. The items in the electronic product will be weighted according to the complexity of their testability in the electronic product. The components of items will be divided among K groups of components according to the complexity of the component in terms of the electronic product testability, and the nets will be divided among L groups of net items according to the complexity of the net in terms of the electronic product's testability.

Examples of the component groups are according to the number of pins per component: 1 - 3 pin components; 4 - 31 pin components; 32 - 63 pin components; 64 - 255 pin components; and components with more than 256 pins. Examples of net groups are: 2 node nets; 3 - 7 node nets; and nets with more than 8 nodes. Each group of items contributes to the total testability of the electronic product according to the number of items that are full testable and partially testable, and the testability weight of the complexity of the item group.

Partial testability for the items may be exemplified by component Items within a group that are defined by components with more than 256 pins and by net item within a group that is defined by a complex net with more than 8 nodes. If such a component has 300 pins and only 200 pins are controlled and observed, the other 100 pins are not testable, and do not interfere with the testability of the 200 pins that are fully testable, although the pins are apart of the electronic product and contribute to the functionality of the electronic product. This component will contribute only partially to the component testability weight of the electronic product Testability Number. If a net has 10 nodes and only 5 nodes are testable, and the 5 un-testable nodes can be controlled so as not to interfere with the testing of the 5 testable nodes, then only part of the testability weight of this net contributes to the electronic product Testability Number. The testability equation is represented as follows: Testability Number =

FK, FL are the Item weight (dynamic factor between 0 - 1) contributions to the testability;

KK, KL - are the group weight contributions to the testability; K, L are the total number of the items in groups K and L, respectively;

k, I - are the fully testable items in groups K and L, respectively, m, n - are the partially testable items;

KM, KN - are the dynamic factors of testability according to the degree of partial testability of the items;

KGroup - the component group defined as K group; and LGroup - the component group defined as L group.

Thus the first two terms in the numerator represent the testability weight of the fully testable and partially testable items in group K, respectively. The last two terms in the numerator represent the testability weight of the fully testable and partially testable items in group L, respectively. The two terms in the denominator represent the testability weight of all items in groups K and L, respectively.

The methodology to create the testability^* numbers is called DFTool, and it is based on the Component TesT Library (CTTL) that includes all testing information on the components.

An example of the information the CTTL should contain: the component support IEEE standards 1149.x (Boundary scan / JTAG); the controls pins of JTAG and JTAG BSDL (Boundary Scan Description Language); BIT (Build In Test) controls pins; the BIT function description; the control output pins and the controlled output pins (controlled output pins control the state of the output pins, e.g., the state of the output pins can change to a state of High Impedance, which will not interfere with the testing of the other nodes in the tested net); pictures of the components with the patterns that can be used by AOI testing technology; and any other information that is relevant to the testability of the component.

The testability equation can be further used for computing the time and cost of the testing procedure. These two parameters are valuable to the design process for planning more efficient testing procedures. For computing the time and cost of test procedures it is required to change the weight parameters of the equation (FK, FL) to present the time and cost values. The new weight parameters represent the effect of each testable item on the time or cost of the testing procedure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention in regard to the embodiments thereof, reference is made to the accompanying drawings and description, in which like numerals designate corresponding elements or sections throughout, and in which:

Fig 1 is a schematic illustration of electronic product design with JTAG and non- JTAG components and different kinds of nets that exemplify the DFTool, constructed in accordance with the principles of the present invention;

Fig. 2 is a schematic illustration of the DFTool overall view, presenting the four major components, constructed in accordance with the principles of the present invention;

Fig. 3 is flowchart representation of the Enter Function, presenting the internal functions performed in the Enter component, constructed in accordance with the principles of the present invention;

Fig. 4 is flowchart representation of the Testability Function, constructed in accordance with the principles of the present invention;

Fig. 5 is flowchart representation of the Improve Function, constructed in accordance with the principles of the present invention; and Fig. 6 is flowchart representation of the Expert Function, constructed in accordance with the principles of the present invention.

Fig. 7 is a flowchart of the presentation of the expert questions and predefined answers that will lead to expert decisions and recommendations to improve the electronic product design testability, in accordance with the principles of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The invention will now be described in connection with certain preferred embodiments with reference to the following illustrative figures so that it may be more fully understood. References to like numbers indicate like components in all of the figures.

Fig. 1 is a schematic illustration of an electronic product design with JTAG and non-JTAG components and different kinds of nets. JTAG component 102 and non-JTAG component 101 belong to a group of component with 3 - 32 pins. The circles on the component 103, for example, represent the component pins, for example, A1 , B1 and OEA. The Nets are connected to the components via the pins. The JTAG nets that accord with the JTAG standard are 111, 112, 113, 114, 115 and 116. Net1 121 , i et5 125, Nefβ 126 and Net? 127 belong to the group of nets with 2 nodes. Net2 122, Nef4 124 and Net8 128 belong to the group of nets with 3 - 8 nodes. Net3 123 belongs to group of nets with more than 8 nodes.

Fig. 2 is a schematic illustration of the DFTool overall view, presenting the four major components, constructed in accordance with the principles of the present invention. DFTool includes these components: the Enter Function 200; the Testability Function 202; the Improve Function 201 ; and the Expert Function 203

Fig. 3 is flowchart representation of Enter Function, constructed in accordance with the principles of the present invention. The enter function is used to create the Design Database that will include testability information from the electronic product design information, such as the net-list and the Bill of Material (BOM). The input 300 to the Enter Function is the design component information and the net-list.

For example, Fig. 1 is the electronic product design, which includes 5 components and 15 nets. The Component Test Library (CTTL) from the Database of the Component Testing Information 302, is used to create the Design Database. Continuing the example of Fig. 1 , the CTTL includes the following Test information: component 102 is JTAG and component 101 is non-JTAG, having control pins A1 , A2, A3 and A4 controlled by OEA, and pins B1 , B2, B3 and B4 controlled by OEB. Enter function 301 creates the Design Database base using the Design information and the information in the CTTL.

For the example in Fig 1, the Design Database will include the following information: 5 components in a group of components that have 3 - 31 pin components; 3 components 102 are marked as JTAG components; 2 components that are connected to nets TDI and TDO are marked as fully testable; and the center component 102 is marked as partially testable because 1 pin that is connected to net6 126 cannot be tested.

There are 6 nets: netlO 111 , net11 114, net12 115, net13 116, net14 113 and net15 112 marked as JTAG nets and 8 nets: netl 121 , net2 122, net3 123, net4 124, netδ 125, net 6 126, net7 127 and net8 128 that are divided to 3 groups: group 1 consists of 2 node nets: netl 121 , nets 125, net 6 126 and net? 127 that are marked fully testable netl 121 and partially testable net5 125. Group 2 consists of nets with 3 - 7 nodes: net2 122, net4 124 and netδ 128 that are marked fully testable: net2 122 and partially testable: net4 124. Group 3 consists of nets with more than 8 nodes: nets 123 that are marked fully testable.

After creating the Test design Database 301 , the Enter Function will store the Design Database 303 for use in the Testability, Improve and Expert Functions described herein below.

Fig. 4 is a flowchart representation of the Testability Function, constructed in accordance with the principles of the present invention. The testability function calculates the testability 401 from the information in the Design Database that the Enter Function in Fig 3 created. The Testability Equation is calculated 401 from the Design Database information 400 that was created in the Enter function Fig.3 and the information in the configuration Data 402. The calculated testability is displayed 403. The information in the configuration file that contains the values of the weights that appear in the Testability Equation are represented by KK, KL, KM, KN, FK and FL.

The weight values can be any number that will define the range of the weight, for example the range is the numbers from 1 to 10, and wherein 1 is a low weight and 10 is a

5 high weight. The Dynamic weight factors KM and KN are calculated for each item that is defined as partially testable. KM and KN are numbers between 0 and 1. KM and KN contribution to the testability of the electronic products provide only a fraction of the testability item weight. The KM and KN values can be predefined values for testing technologies such as ICT, Functional and AOI. For example: An ICT fully testable

L0 component or net will have KM =1 and KN = 1. Alternatively, if the ICT test covers an 80% of the component, the KM = 0.8 and if the AOI test covers 20% of the net the KN = 0.2. As another example, JTAG testing technology can be calculated from the information of a component or of a net that can be extracted from the Design Data-Base. An example of a simple calculation can be the liner ratio, described as follows: a

15 component pin that can be tested versus all the component pins in the electronic product, or for a net, the node that is tested versus all the net's nodes.

For example, in Fig 1 the electronic product design component 102 is partially testable, wherein the KM value is used with the assumption that the component has 24 pins, and only 1 pin cannot be tested. The liner ratio for the KM value will be (24-1 )/24.

20 The KN value for net net5 125 is (2-1 )/2 and for net4 124 the KN value is (6-4)/6.

Fig. 5 is flowchart representation of the Improve Function, constructed in accordance with the principles of the present invention. The Improve Function provides the designer with the ability to improve the Design Database by adding more information

25 that Enter Function could not have found in the net-list, BOM and CTTL (Component Test Library). The Improve Function has the ability to add new information related to other testing technology, such as ICT, AOI, functional Test, BIST (Build In Self Testing) and more, that can contribute to the Testability of the electronic products as the design progresses and more testability information can be defined by the designer according to

30 the testing strategy defined.

The Improve Function uses the Design Database 500 and lists all components and nets that are partially testable and untestable and asks the designer of the electronic product to provide more information 501 based on the design that was used to create the Design Database. The information that the designer provides 502 can be used to update the design Database 503.

For example, in Fig 1 the electronic product designer can be provided with the information that A3, A4 that is connected to Net4 124 and A4 that is connected to net6 126 are cluster. Cluster is defined in the JTAG standard. Cluster here means that components 101 can be partially tested and net4 124, net6 126 and net7 127 will change their status to fully testable, thereby changing the result of the Testability Number according to the Testability Equation.

Other kinds of information can be provided, such that netδ 128 can be tested with ICT if the designer chooses to use the In Circuit Testing (ICT) in the testing strategy for the electronic product of Fig. 1. Thus, netδ 128 will change its status to fully testable, which will change the result of the Testability Number according to the Testability

Equation.

Fig. 6 is flowchart representation of the Expert Function, constructed in accordance with the principles of the present invention. The Expert Function contains a "tree" of expert questions and answers that the designer should chose. The chosen answers of the designer lead the expert system in Expert Function to provide recommended changes in the electronic product design that should improve the testability of the electronic product. The designer will get a list of recommendations when he decides to finish Expert Function in the DFTool 603. The designer should go back to the design table and make the changes in the electronic product design and create a new net-list and BOM and start again with Enter Function to create an updated Design Database. The Expert Function uses the Design Database 600 and lists all components and nets that are partially testable and untestable 601 , and asks the designer of the electronic product to choose the component or net 602. The Expert Function will display a tree of questions and predefined answers. When the Expert Function has a clear understanding what can be recommended to the designer to change in electronic product that will lead to better testability 603, the Expert Function will ask no further questions and will wait for the designer to choose another item or will exit the Expert Function.

Fig. 7 is a flowchart of the presentation of the expert questions and predefined answers that will lead to expert decisions and recommendations to improve the electronic product design testability, in accordance with the principles of the present invention. The Expert Function in Fig 6 contains a "tree" of expert questions and answers for an item 700 that the designer chooses from the Design Bata base. In the Expert questions and answers tree, the question 701 progresses in the tree according to the path of the designer's answer 702. When the answer is chosen, it provides the expert system with a clear idea of what the recommendation should be 703. The questions and answers will continue 704 until a clear recommendation can be reached, or the expert system will recommend choosing another question and answer path for the chosen item, or to choose other item. For example, questions and answers can be asked concerning the electronic product design of Fig 1. Question 1, for example, may be: can component 101 be replaced with a JTAG component? Assuming answer 11 is: "yes, it can be replaced by a JTAG component that is chosen by the designer. Recommendation 11 may be to replace the non-JTAG component by a JTAG component. The designer will have to go back to the drawing board to change the design, and replace the non-JTAG component by a JTAG component and connect the JTAG signals. The designer will then create a new net-list and start again with Enter to create a new Design Database that will lead to better testability results, according to the principles of the present invention.

Having described the present invention with regard to certain specific embodiments thereof, it is to be understood that the description is not meant as a limitation, since further modifications will now suggest themselves to those skilled in the art, and it is intended to cover such modifications as fall within the scope of the appended claims.

Claims

I claim:

1. A method for the improving testability of at least one electronic product during the design process, said product comprising a plurality of components and a plurality of nets, the method comprising: entering a netlist of design information for the at least one electronic product to create a design database; calculating a testability number/value, wherein the calculation is based on the relation between actual testability and absolute possible testability of the at least one product according to said created design database; improving said testability number/value by entering additional information; and implementing expert software recommendations to improve said testability number/value by changing the design of the at least one product.

2. The method according to claim 1 , wherein said testability number/value is calculated by dividing the plurality of components and a plurality of nets into fully and partially testable groups.

3. The method according to claim 1 , wherein entering further comprises entering a BOM (Bill of Material), a CTTL (Component Test Library) test information in to a Database of the component testing information for the at least one electronic product being tested.

4. The method according to claim 1 , wherein said testability is calculated from information in said design database and a configuration file.

5. The method according to claim 4, wherein said netlist of design information is a pre defined table in said configuration file that contains testability weights for the plurality of components and the plurality of nets.

6. The method according to claim 1, wherein improving uses added design information about the plurality of components and at least one technology from the group comprising: Joint Test Action Group (JTAG), In Circuit Testing (ICT); functional test; Automatic Optic Inspection (AOI); and Buil-ln Self Testing (BIST) technology.

7. The method according to claim 1 , wherein improving further comprises providing expert ideas to improve the at least one electronic product by choosing different components and means to change the connections in the at least one electronic product.

8. The method according to claim 1, wherein improving further comprises providing expert ideas to improve the at least one electronic product by adding components and means to add the connections in the at least one electronic product.

9. The method according to claim 1 , wherein the at least one electronic product is one of the group comprising: an integrated circuit (IC); a very large scale integrated circuit (VLSI); a system on a chip (SOC); a block design in an electronic printed circuit board; a board design; an electronic module for a subsystem design; and a system.

10. The method according to claim 1 , wherein the testability level of said expert software is designed for a construct of modules with test/debug features for components and test/debug messages for nets.

11. The method according to claim 1 , wherein calculating said testability number/value uses data from design information arising from a plurality of design phases of the electronic product.

12. The method according to claim 1, wherein calculating further comprises entering a dynamic factor between 0 and 1 to each of the plurality of components and each of the plurality of nets in the electronic product, according to the degree of partial testability.

3. A method for the estimating the testability of at least one electronic product through design process, said product comprising a plurality of components and a plurality of nets, the method comprising: entering a netlist of the electronic component design to create a design database; calculating a testability factor wherein the factor calculation is base on the relation between actual testability and absolute possible testability of the product according to created design database and configuration file;

14. The method according to claim 14, wherein said testability number/value is calculated by dividing the plurality of components and a plurality of nets into fully and partially testable groups.

15. The method according to claim 14, wherein entering further comprises entering a BOM (Bill of Material), a CTTL (Component Test Library) test information in to a Database of the component testing information for the at least one electronic product being tested.

16. The method according to claim 14, wherein said testability is calculated from information in said design database and a configuration file.

17. The method according to claim 16, wherein said netlist of design information is a pre defined table in said configuration file that contains testability weights for the plurality of components and the plurality of nets.

18. The method according to claim 14, wherein the at least one electronic product is one of the group comprising: an integrated circuit (IC); a very large scale integrated circuit (VLSI); a system on a chip (SOC); a block design in an electronic printed circuit board; a board design; an electronic module for a subsystem design; and a system.

19. The method according to claim 14, wherein calculating said testability number/value uses data from design information arising from a plurality of design phases of the electronic product.

20. The method according to claim 14, wherein calculating further comprises entering a dynamic factor between 0 and 1 to each of the plurality of components and each of the plurality of nets in the electronic product, according to the degree of partial testability.

5

21. The method according to claim 1 wherein the testability number/value represents the testing procedure time.

22. The method according to claim 1 wherein the testability number/value 10 represents the testing procedure cost.

23. The method according to claims 21 , wherein calculating further comprises entering a dynamic factor between 0 and 1 to each of the plurality of components and each of the plurality of nets in the electronic product,

[5 according to the respective testing time of each component.

24. The method according to claims 21 , wherein calculating further comprises entering a dynamic factor between 0 and 1 to each of the plurality of components and each of the plurality of nets in the electronic product,

20 according to the respective testing cost of each component.

25. A method for the estimating and improving by multi-technology test techniques, 25 the testability of at least one electronic product during the design process, said product comprising a plurality of components and a plurality of nets, the method comprising: entering a netlist of design information for the at least one electronic product to create a design database; 30 calculating a testability number/value, wherein the calculation is based on the relation between actual testability and absolute possible testability of the at least one product according to said created design database; improving said testability number/value by entering additional multi -technology test techniques testing information.

26. The method according to claim 21 , wherein improving uses added design information about the plurality of components and at least one technology from the group comprising: Joint Test Action Group (JTAG), In Circuit Testing (ICT); functional test; Automatic Optic Inspection (AOI); and Buil-ln Self Testing (BIST) technology.

27. The method according to claim 21 , wherein the at least one electronic product is one of the group comprising: an integrated circuit (IC); a very large scale integrated circuit (VLSI); a system on a chip (SOC); a block design in an electronic printed circuit board; a board design; an electronic module for a subsystem design; and a system.

28. The method according to claim 21 , wherein calculating said testability number/value uses data from design information arising from a plurality of design phases of the electronic product.

29. The method according to claim 21 , wherein calculating further comprises entering a dynamic factor between 0 and 1 to each of the plurality of components and each of the plurality of nets in the electronic product, according to the degree of partial testability.