WO2004040768A1

WO2004040768A1 - Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit

Info

Publication number: WO2004040768A1
Application number: PCT/JP2002/011319
Authority: WO
Inventors: Kouichi Suzuki
Original assignee: Fujitsu Limited
Priority date: 2002-10-30
Filing date: 2002-10-30
Publication date: 2004-05-13
Also published as: JP3908764B2; JPWO2004040768A1

Abstract

A phase comparison gain detecting circuit of PLL in which the phase is compared between a data signal DA and a clock signal CL, the phase is compared between the data signal DA and a clock signal CL’ obtained by delaying the clock signal CL by a specified amount, and a phase comparison gain is detected based the difference between respective phase comparison results and the specified amount of delay.

Description

Description Phase comparison gain detection circuit, false synchronization detection circuit, and PLL circuit

The present invention relates to a phase comparison gain detection circuit, a false synchronization detection circuit, and a PLL circuit, and particularly to a PLL circuit that can be applied to a case where a reference cook signal is extracted from received data in an optical transceiver for optical communication, and The present invention relates to a phase comparison gain detection circuit and a false synchronization detection circuit that can be applied thereto. Conventional technology

FIG. 1A shows a general configuration of a PLL circuit for clock extraction. In the peripheral configuration, the phase difference between the clock signal CL, which is the output of the VCO (voltage controlled oscillation circuit) 40, and the input data DA is detected by the phase comparator 10, and the charge pump 20 is driven according to the detected output. As a result, a current proportional to the output of the phase comparator is supplied to the loop filter 30. Then, the supply current is smoothed by the loop filter 30, and the result is fed back to VC400. FIG. 1B is a circuit diagram showing an example of the configuration of the loop filter 30. As shown in the figure, in this example, the loop filter 30 is composed of a series circuit of a resistor R and a capacitor C, and has a function of smoothing an input current and converting it into an output voltage. By the above operation, the PLL circuit can obtain the clock signal CL synchronized with the input data signal DA. Here, the phase comparison gain in phase comparator 10 is Kp, the current amplitude in charge pump 20 is Ic, the transfer function of loop filter 30 is F (s), and the gain of VCO is KV. The pertinent? The loop gain of the L L circuit is expressed by the following known equation. Open loop gain = [Κρ · I c · F (s) · Kv] / s

Closed loop gain = iη / out

= [K · Ic · F (s) · Kv] / [s + p · Ic · F (s) · Kv] When a perfect quadratic filter is used as the loop filter, open loop gain = [Kp · Ic · R · KvZs] · [1 + 1 / s CR] closed loop gain = [Κρ · Ic · R · Κ ν · (1 + s CR)] / [s ^ 2 · CR + Kp · Ic · R · Kv · (1 + sCR)]

From the above equation, it can be seen that the closed loop gain power-off frequency is a frequency at which the open loop gain becomes 0 dB, and is proportional to the respective gains of the phase comparator 10, the charge pump 20, and the VC040 (Fig. 2A). See). Here, when the gain of each part is large, the cutoff frequency becomes high, and as a result, the output jitter tends to increase. On the other hand, when these gains are small (see Fig. 2B), the cutoff frequency is low, which tends to reduce the phase margin and increase peaking. In that case, the phase error response tends to be poor.

Here, the closed-loop characteristic as the jitter characteristic of PLL is equivalent to a so-called jitter transfer, and is represented by the amplification factor of the output jitter with respect to the input jitter when the PLL is locked. This value is better as the response speed of PLL is slower. On the other hand, from the viewpoint of the so-called jitter tolerance, which is an index of how much jitter the PLL can withstand in a licked state, conversely, the higher the response speed of the PLL, the greater the tolerance. Therefore, they are in a trade-off relationship with each other.

FIG. 3 is a block diagram showing an example of an identification timing signal extraction circuit to which the PLL method is applied. The data of the input data signal DA is extracted by the identification circuit 100 based on the clock signal CL extracted by the PLL circuit function as described above. In a PLL circuit in such an optical transmitting and receiving circuit, unlike a PLL circuit used in a general frequency synthesizer, random data is input as an input data signal. Therefore, when the frequency of the input signal fluctuates greatly, the level of the frequency component value to be extracted relatively decreases, and as a result, the PLL loop gain decreases and the operation becomes unstable.

FIG. 4 shows a well-known half-rate clock Bang— A circuit example when a Bang circuit is applied is shown. In the figure, two D-FF (D-flip-flop) circuits detect the input data signal DA and detect the edge of the clock signal for data identification by delaying it by π / 2 phase. The data identification operation is performed by the clock signals CL and. The exclusive OR circuit EXOR performs an exclusive OR operation on the resulting signals Da and Db to obtain a signal Dc.

As a result, if the phase of the data signal DA is behind the phase of the discrimination signal CL, the exclusive OR sum Dc becomes an intermittent signal as shown in FIG. On the other hand, when the phase of the data signal DA is advanced with respect to the phase of the identification clock signal CL, as shown in FIG. 7, the exclusive logical sum output Dc is likely to be a continuous signal.

As a result, the level of the signal obtained through such a low-pass filter by the charge pump 20 and the loop filter 30 with respect to such a phase comparison result is, as shown in FIG. In the case of a phase comparison output that is likely to be continuous as in the case of FIG. 7, the output level of the low-pass filter becomes high. The oscillation frequency of VCO 40 is controlled according to the output level of the low-pass filter.

That is, when the phase of the data signal is delayed, the VOC input level is reduced, and as a result, the VCO oscillation frequency is reduced to act to delay the phase of the clock signal CL in accordance with the phase of the data signal. Conversely, when the phase of the data signal is advanced, the VCO oscillation frequency increases, and acts to advance the phase of the clock signal with respect to the data signal.

Here, in the case of FIG. 6, when the sign of the A-system data in the input data signal changes, an H signal of 1Z4 cycle of the clock signal is output in the phase comparison output. On the other hand, if the sign of the data of the A system continues, the H signal will not be output during that time. This situation is shown in FIGS.

In addition, in the case of FIG. 7, that is, when the phase of the data signal is advanced, since the exclusive OR between the same data does not occur as shown in FIG. 7, the H signal is statistically used as the phase comparison output. And the L signal are generated by half. However, system A If the same code is continuous in both and the B system, the L signal is output, and if the repetition of the different code continues, the H signal is output. This situation is shown in FIGS. 11 to 13.

As described above, the phase comparison output is not necessarily affected by not only the phase difference between the data signal and the clock signal but also the content of the data signal itself (in this case, the so-called edge rate, duty 1, etc.). As a result, the gain Kp of the phase comparator 10 fluctuates, and the loop gain of the entire PLL circuit also fluctuates. FIGS. 14A and 14B show examples of output waveforms of the phase comparator 10 having the configuration as shown in FIG. As shown in Fig. 14A, the ideal output characteristic shown by the broken line is actually shown by the solid line due to the input jitter, the effect of the setup and hold operation characteristics of the D-FF circuit in the phase comparator, etc. The waveform is rounded as described above. In addition, as shown in FIG. 14 波形, the waveform becomes rounded depending on the edge ratio of the input data. As a result, the loop gain of the PLL circuit fluctuates, thereby causing the above-mentioned unstable circuit operation. Disclosure of the invention

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a PLL circuit capable of providing a stable PLL circuit operation irrespective of fluctuations in the edge ratio and duty of input data, effects of circuit characteristics, and the like.

In the present invention, a plurality of phase comparison operations are performed with different phase conditions with respect to identification of an input data signal, and the phase comparison gain is detected by comparing the respective phase comparison results. Therefore, it is possible to detect the on-time phase comparison gain in consideration of the fluctuation factors of the phase comparison gain such as the edge ratio and duty of the input data signal and the setup and hold characteristics of the discriminator. As a result, on-time and accurate loop gain compensation control can be realized by controlling the loop gain of the PLL circuit based on the phase comparison detection result. BRIEF DESCRIPTION OF THE FIGURES

1A and 1B are diagrams showing a configuration of a conventional PLL circuit. FIGS. 2A and 2B are diagrams illustrating the loop gain of the PLL circuit.

FIG. 3 is an explanatory diagram of the operation of the conventional PLL circuit.

FIG. 4 is a diagram showing a circuit example of a conventional half-rate clock Bang-Bang phase comparator.

FIG. 5 is a diagram for explaining the data identification phase.

FIG. 6 is a time chart (part 1) of each signal in the circuit of FIG.

FIG. 7 is a time chart (part 2) of each signal in the circuit of FIG.

FIG. 8 is a time chart (part 3) of each signal in the circuit of FIG.

FIG. 9 is a time chart (part 4) of each signal in the circuit of FIG.

FIG. 10 is a time chart (part 5) of each signal in the circuit of FIG. FIG. 11 is a time chart (part 6) of each signal in the circuit of FIG. FIG. 12 is a time chart (part 7) of each signal in the circuit of FIG. FIG. 13 is a time chart (No. 8) of each signal in the circuit of FIG. FIGS. 1A and 4B are diagrams (part 1) for explaining the state of deterioration of the phase comparison characteristic.

FIG. 15 is a circuit block diagram of an example of a PLL circuit having a phase comparison gain compensation function.

FIG. 16 is a circuit diagram showing an example of the phase comparison gain detection circuit.

FIG. 17 is a diagram (part 2) for explaining the state of deterioration of the phase comparison characteristic. FIG. 18 is a block diagram of one embodiment of the present invention.

FIG. 19 is a diagram for explaining the principle of detecting the phase comparison gain by the configuration shown in FIG.

FIG. 20 is a circuit diagram of one embodiment of the present invention.

FIG. 21 is a time chart of each signal in the circuit shown in FIG.

FIG. 22 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG. 20.

FIG. 23 is a circuit diagram of a P-mode according to an embodiment of the present invention using the phase comparison detection circuit having the configuration shown in FIG.

Figure 24 shows FIG. 25 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG.

FIG. 26 is a circuit diagram of a false synchronization detecting circuit according to still another embodiment of the present invention. FIG. 27 is a diagram for explaining the principle of false synchronization detection by the configuration shown in FIG. Description of the preferred embodiment

Hereinafter, the configuration of an embodiment of the present invention will be described with reference to the drawings.

Assuming that the gain change of the PLL circuit (for example, the circuit shown in FIG. 15) as described above is compensated by detecting the gain of VC040, the gain of phase comparator 10 is detected based on the edge rate of data DA. Then, a method of adjusting the output current of the charge pump 20 based on the detection result, or adjusting the capacitance value or the resistance value of the filter 30 and compensating the same can be considered. In the case of FIG. 15, the gain of the phase comparison note 10 is detected by the phase comparison gain circuit 210, and the characteristics of the charge pump are controlled by the control circuit 220 based on the detection result.

In this case, if the phase comparator 10 has a sawtooth phase comparison characteristic (see FIG. 17) like a well-known Hogge phase comparator as shown in FIG. 16, for example, the phase period is determined. The output amplitude determines the gain. Then, in the phase comparison gain compensating circuit as shown in FIG. 15, the fluctuation of the amplitude due to the fluctuation of the edge ratio of the data is detected. That is, in this case, the output of the EXOR circuit 21 3 becomes “H” when the data has an edge, that is, “H” when the data changes, and “L” when there is no data. The edge rate of the data can be detected by averaging this with L PF (a circuit using R and C). Then, the control circuit 220 compensates for the fluctuation of the output amplitude of the phase detector by adjusting the current of the charge pump 20.

On the other hand, when a well-known B nag -Bang phase comparator, which requires fewer components because the discriminator and the frequency divider can be configured as a part of the phase comparator, is applied. Is represented by a step function (Bang-Bang phase comparison characteristic) (for example, the characteristic of the broken line in FIG. 14A), and has a characteristic in which the phase comparison gain value is determined according to the stochastic fluctuation of the phase comparator output. In this case, the fluctuation factors of the phase comparison gain include, in addition to the fluctuation of the data edge ratio, (1) the jitter of the input data, and (2) the input data. Data duty, (3) Variations and variations in the setup and hold characteristics of the discriminator (FF) in the phase comparator. Therefore, in this case, the design for the phase comparison gain is more complicated than in the cases of Figs. 16 and 17, and the loop gain of the entire PLL including the phase comparison gain is adjusted after installing the phase comparison circuit in the relevant system. There is a need to.

Therefore, in the present invention, in the PLL circuit having the above-described BangBang phase comparator, the jitter of the input data, the duty of the input data, and the setup / hold characteristics of the discriminator (FF) of the phase comparator vary. And a circuit for accurately detecting a change in the phase comparison gain due to the change and the like.

FIG. 18 is a principle diagram of one embodiment of the present invention. This figure shows a phase comparison gain detector using the above-mentioned Bang-Bang phase comparator. As shown in the figure, the phase comparison detector 300 includes a phase comparator 311, which receives a clock signal CL for identifying the data DA as an input, and delays the data identification clock signal CL by a predetermined time to generate a clock signal CL. It comprises a delay unit 313 for outputting, a phase comparator 312 having the delayed clock signal CL, as an input, LPFs 314 and 315 for smoothing the output, and a difference voltage detection circuit 316.

In the circuit shown in the figure, while the data signal DA and the clock signal CL are synchronized, that is, when the input data identification clock is synchronized, the data identification operation is performed by the two clock signals CL and CL having different phases, respectively. A desired phase comparison gain is detected from the time difference between each of the phase comparator outputs D 1 and D 2 and the clock signals CL and CL ′, that is, from the predetermined delay time. This makes it possible to detect the phase comparison gain that incorporates the setup and hold time of the phase comparator, the edge rate and jitter of the input data, and the fluctuation of the duty and the parallelism, etc. Therefore, by controlling based on the detection output, the loop gain of the entire PLL circuit can be compensated so as to be constant. Therefore, a stable response characteristic is obtained, and a PLL circuit satisfying a desired jitter transfer characteristic can be provided.

FIG. 19 shows the output levels of the phase comparators 311 and 312 for explaining the principle of the embodiment of the present invention. The phase comparison characteristics in FIG. 19 correspond to those shown in FIGS. 14A and 14B. I do. As shown in the figure, the phase comparison output is The rate of change, that is, AVZ (Δt / T), corresponds to the phase comparison gain Kp. In the above equation, AV is the difference voltage between the values D 1 and D 2 obtained by smoothing the phase comparison output under different phase conditions, and Δt is the delay unit 313 that provides the difference in the phase conditions. T is the signal period of the clock signal.

FIG. 20 shows a configuration of a phase comparison detection circuit according to an embodiment of the present invention, which further embodies the configuration of FIG. This circuit is a phase comparison gain detection circuit to which a Bang-Bang phase comparator using a half-rate clock is applied. As shown in the figure, the circuit is provided with data discriminators 411, 412, data edge detection discriminator 413, and phase comparison gain detection discriminator 414 as discriminators (FF). A circuit 431 that performs a logic operation between the data identification FF output DO a and the data edge detection FF output DOc as an OR circuit (EX OR). Similarly, a logic between the data identification FF output DO b and the data edge detection FF output DO c. And a circuit 433 for performing logic between the data identification FF output DOb and the phase comparison gain detection FF output DOd. These outputs are smoothed by LPFs 441, 442, and 443, respectively, and output as phase comparison outputs Ph1, Ph2, and Ph3.

In the circuit of FIG. 20, as shown in the waveform diagram of FIG. 21, in a state where the data signal DA and the clock signal CL are synchronized, data of the A system is obtained as the output DO a of the discriminator 411. As the output DOb of the discriminator 412, data of the B system is obtained. On the other hand, as the output DOc of the edge detection discriminator 413, the rising timing of the clock signal coincides with the transition point of the data signal DA. Is equal to the probability. On the other hand, as the output of the phase comparison gain detection discriminator 414, the rising timing of the clock signal is slightly delayed from the changing point of the data signal DA. The probability of obtaining system data is greater.

As a result, as a result of the exclusive OR between these data, the appearance probability of the H level at the output P h1 of the EXOR circuit 441 is approximately equal to the appearance probability of the H level at the output P h 2 of the EXOR 442. Become equal. On the other hand, at the output P h 3 of the EXOR circuit 443, the appearance probability of the H level is higher than each of the former. That is, EXOR circuit The probability that DO a and DO d as inputs of 443 match is the probability that DO a and DO c as inputs of EXOR circuit 441 match or DO b and DO c as inputs of EXOR circuit 442 This is because the probability of matching is lower. This is because, as described above, the occurrence probability of the A-system data in the signal DO d is smaller than the appearance probability of the A-system data in the signal DO c, and similarly, the occurrence probability of the B-system data in the signal DO c This is because the appearance probability of A-system data in DO d is smaller.

As described above, in the present embodiment, the clock signal C Lb intentionally delayed by a predetermined time Δt is generated to perform data identification, and the identification result data is identified by the clock CL not delayed by At. Exclusive OR with the data of the identified result. Further, an exclusive OR of the identification result data obtained by performing the data identification using the edge detection clock signal CLa and the identification result data obtained by using the clock CL which is not delayed by Δt is calculated. The result of these two types of exclusive OR is smoothed by LPF, and the level difference is divided by the phase obtained by standardizing the delay amount Δt with the period T to obtain the phase comparison gain Kp. Can be

In other words, here, a delay Δt is intentionally generated after synchronization is established, and a clock signal (signal C Lb in the examples of FIGS. 20 and 21) is generated in a pseudo manner in synchronization with the data signal DA. Pseudo-synchronous shift ”The same data signal DA is identified by the clock signal. Then, the exclusive OR output between the identification data obtained therefrom and the data identified by the clock signal CLa delayed by π / 2 is smoothed to obtain a “pseudo synchronization shift” phase comparison detection value. Then, for the pseudo-synchronization phase comparison detection value, the exclusive data between the identification data identified by the clock signal CL in the synchronized state and the data identified by the clock signal CLa also delayed by π 2 The value obtained by smoothing the logical sum output, that is, "the phase comparison detection value at the time of synchronization" is compared. It can be said that the larger the difference between the comparison results, the higher the phase comparison detection sensitivity to the phase difference between the data signal DA and the clock signal CL, which is synonymous with the higher phase comparison gain. As described above, in the present embodiment, the phase comparison gain incorporating all of the current edge ratio, duty, setup / hold characteristics of each discriminator (FF), and the like is obtained, and therefore, it is very accurately turned on. Effective phase comparison gain of time Is possible.

FIG. 23 shows an example of a PLL circuit having a phase comparison gain compensation function according to an embodiment of the present invention. The phase comparison output Ph 1 and Ph 3 of the phase comparator detection circuit 400 having the configuration of FIG. A / D converter 510 that converts the difference voltage between the two into a digital signal, compares the digital difference voltage with a predetermined reference value, adjusts the output current of the charge pump based on the comparison result, and thereby adjusts the PL. It has a configuration to compensate for the loop gain of the L circuit.

In the configuration of FIG. 23, the data outputs D Oa and DOb of the phase comparison detection circuit 400 shown in FIG. 20 can be used as they are as the reproduction data of the input data. That is, these data outputs DOa and DOb correspond to the outputs of the identification circuit 100 in FIG.

That is, in the PLL circuit of FIG. 23, the loop gain of the PLL circuit is determined based on the phase comparison output difference voltage between the “pseudo-synchronization” identification signal and the “synchronization” identification signal obtained by the phase comparison detection circuit 400. For control, it is possible to provide a PLL circuit having an accurate loop gain compensation function taking into account the current input signal characteristics and phase comparison circuit characteristics.

The control circuit 520 is not limited to the circuit configuration shown in FIG. 23, and the transfer function F (s) of the filter 30 and the gain of the VC040, which determine the loop gain of the PLL circuit other than the output current amplitude Ic of the charge pump, It goes without saying that a configuration may be adopted in which the loop gain of the PLL circuit is compensated by controlling Kv and the like.

In the above-described embodiment, the Bang-angang phase comparator using the half-rate clock is applied to the phase comparison detection circuit 400. However, in addition to this, the phase comparison characteristic using the full-rate clock has a sawtooth waveform. The present invention can be applied to a phase comparator as shown in FIG. FIG. 24 shows a circuit configuration example of the phase comparison detection circuit in that case. In the circuit shown in the figure, the discriminator 611 that identifies the data signal DA at the timing of the clock signal C and the data signal DA are delayed by a predetermined amount by the delay signal 622 from the clock signal CL. And a discriminator 612 for discriminating by. EXO which takes the exclusive OR of each of the discrimination outputs DO 1 and DO 2 by these discriminators 611 and 612 and the data signal DA R631, 632 are provided, and low-pass filters 641, 642 for smoothing the outputs of these EXORs 631, 632 are provided.

According to the phase comparison detection circuit of FIG. 24, as in the case of FIG. 20, the difference between the identification result signals DO 1 and DO 2 due to the phase difference between the identification cook signals CL, CL, and these identification result signals DO 1 , DO 2 and the original data signal DA, perform an exclusive OR operation, and smooth the EXOR operation results to obtain the difference, thereby detecting the difference. FIG. 25 is a diagram for explaining the difference voltage obtained in that case. The difference voltage Δν between the outputs Ph 1, Ph 2 of the LPFs 64 1, 642 detected here and Ph 2 is the delay phase amount obtained by standardizing Δt, which is the delay amount by the delay unit 622, with the period T. By dividing by Δt / T, which represents, the phase comparison gain Kp can be obtained (see the following equation).

Kp = AV / (Δt / T) Based on the phase comparison detection value obtained in this way, the control circuit 520 shown in FIG. 23 determines the loop gain determining factor parameters such as the current amplitude value Ic of the charge pump 20. By compensating the loop gain, the loop gain of the PLL circuit is compensated.

In this case, as compared with the example of FIG. 16, the phase comparison gain can be compensated even when there is a gain variation due to factors other than the edge rate of the input data.

Further, the phase comparator may have another configuration, and has a function of delaying or advancing the phase of the clock signal CL or the phase of the input data signal DA by a predetermined amount, and has a circuit configuration similar to the phase comparator. A PLL circuit may be configured by incorporating the detection circuit. As described above, according to the present invention, the phase comparison gain is compensated for in accordance with the variation of the phase comparator of the PLL circuit and the jitter of the input data, etc. It is possible to stabilize the jitter frequency characteristics while maintaining the same, thereby improving the performance of the PLL circuit.

FIG. 26 and FIG. 27 are diagrams for explaining an erroneous synchronization detection device according to another embodiment of the present invention. FIG. 26 is substantially the same as the circuit configuration of FIG. 18, and the corresponding components are denoted by the same reference numerals, and redundant description will be omitted.

In this case, a sawtooth wave characteristic as shown by a broken line in FIG. 27 is used as a phase comparator of the PLL circuit. It is assumed that there is a property. That is, it has a characteristic that a detection voltage output according to the detected phase difference changes in a sawtooth waveform according to the detected phase difference. In such a PLL circuit, a phase lock is applied at an intermediate portion of the rising ramp portion of the sawtooth wave, that is, at a point P in the figure, so that a central portion between signal change points of the input data signal DA, that is, The phase of the clock signal CL can be locked so that data can be identified at the timing of the center of the clock (see Fig. 5).

However, in practice, the waveform distortion as shown by the solid line in FIG. 27 may occur in the sawtooth characteristic due to the fluctuation of the duty of the input data signal DA, and the like. In that case, the PLL circuit may erroneously lock the phase at point Q in Fig. 27. In this case, erroneous synchronization occurs, and the clock signal performs data identification at the timing of the crosspoint of the data eye pattern, so that the identification data is likely to be erroneous.

In order to prevent such erroneous synchronization, in the erroneous synchronization detection device according to another embodiment of the present invention, as described with reference to FIGS. 20 to 25, for example, the phase comparison detection output of the phase comparator It depends on the delay amount Δt given by 3 1 3 and 6 2 2. However, the amount of change has a characteristic that depends on the absolute phase between the data signal DA and the clock signal CL. That is, when the phase difference between the data signal DA and the clock signal CL is near zero, that is, when the data is identified at the timing of the center of the eye pattern of the data signal DA (see FIG. 5), the data can be correctly identified. The exclusive OR result of the identification signal and the data signal DA indicates that even if the data identification timing is delayed by the delay device 3 13, as long as the delay Δt is somewhat smaller than the period T, the delay Only a difference approximately proportional to the amount occurs.

Conversely, when data is identified with the timing of the eye pattern cross point, that is, the value of the data signal DA being undefined, the possibility of identifying correct data is about 50%. On the other hand, if the delay is delayed by the predetermined amount Δt from that timing, and the delay amount At exceeds the above-mentioned indeterminate state (dead zone) and is large enough to be an identification timing at which data can be identified almost accurately, correct data identification is performed. Is nearly 100%. As a result, the discrimination result based on such a discrimination timing is significantly different from the discrimination result when there is no delay (that is, when the discrimination rate is about 50% in an undefined state). The difference is much larger than in the case of the above-described identification near the center of the eye pattern. This point will be described again with reference to FIG. 27. In the case of data identification near the center of the eye pattern, that is, the phase comparison output with and without delay at point P in FIG. 27 is D 1 and D 2, respectively. , The difference is AV. On the other hand, in the vicinity of the eye pattern cross point, that is, in the case of point Q, the phase comparison outputs with and without delay are D1, D2 ', respectively, and the difference is Δν'. As shown, clearly

ΔV <ΔV. Therefore, erroneous synchronization can be detected by detecting that AV has increased beyond a predetermined reference value.

It should be noted that the present invention is not limited to the above embodiment, and various modifications in accordance with the basic idea of the present invention can be implemented, and it goes without saying that these modifications are also included in the scope of the present invention. .

The present invention includes the following configurations.

(Configuration 1)

Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain,

First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal;

Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount;

Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal;

A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit. (Configuration 2)

In the phase comparison gain detection circuit of the above configuration 1,

The first phase comparison means detects a phase relationship between the input data signal and the identification timing signal in a substantially synchronized state,

The second phase comparison means is a phase comparison gain detection circuit configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.

(Configuration 3)

In the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data to the predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle, the phase relationship between the input data signal and the identification timing signal is determined. A phase comparison gain detection circuit for detecting a phase comparison gain when comparing phases,

A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. First phase comparing means for comparing the phases of the two by detecting the data correlation between

By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. Phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a second predetermined amount for shifting the identification timing. And a phase comparison gain detection circuit.

(Configuration 4)

The data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal by the identification timing signal is detected. First phase comparing means for comparing phases by

The phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison means for comparing

A phase comparison gain detection circuit comprising phase comparison gain detection means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparison means and a predetermined amount for shifting the identification timing of the identification timing signal. .

(Configuration W

The phase comparison gain detecting circuit according to the above configuration 3 or 4, wherein the data correlation detection between the data in the first and second phase comparing means has a configuration realized by an exclusive OR operation.

(Configuration 6)

The phase comparison gain detection circuit according to the above configuration 5, wherein the exclusive OR output is smoothed and input to the phase comparison gain detection means.

(Configuration 7)

The phase comparison gain detection circuit according to any one of the above configurations 3 to 6, wherein each data is identified by a flip-flop circuit.

(Configuration 8)

An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,

An erroneous synchronization state is detected based on a difference between respective outputs of the first and second phase comparison means. Erroneous synchronization detection circuit.

(Configuration 9)

By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the phase of both is detected. And a false synchronization detection means for detecting a false synchronization state based on the difference between the outputs of the first and second phase comparison means.

False sync detection circuit.

(Configuration 10)

First phase comparing means for comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. When,

The phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. Second phase comparing means for comparing;

An erroneous synchronization detection circuit comprising erroneous synchronization detection means for detecting an erroneous synchronization state based on a difference between respective outputs of the first and second phase comparison means.

(Configuration 1 1) A PLL circuit comprising at least one of the phase comparison gain detection circuit of any of the above configurations 1 to 7 and the false synchronization detection circuit of any of the above configurations 8 to 11.

A control circuit for controlling the loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit, and a control for controlling the phase lock operation based on the false synchronization detection result of the false synchronization detection circuit A PLL circuit further comprising at least one control circuit of the circuits.

(Configuration 1 2)

The control circuit is configured to change at least one of a current amplitude of a charge pump constituting the PLL circuit, a transfer function of a loop filter, and a control gain of a VCO; The PLL circuit having the above configuration 11.

(Configuration 13)

Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain,

A first phase comparing step of detecting a phase relationship between the input data signal and the identification timing signal;

Shifting a phase relationship between the input data signal and the identification timing signal by a predetermined amount;

A second phase comparing step of detecting a phase relationship between the input data signal shifted by the phase relationship shifting means and the identification timing signal;

A phase comparison gain detection step for detecting a phase comparison gain based on a difference between output values obtained in each of the first and second phase comparison steps and a predetermined amount for shifting the phase relation in the phase relation shift step. Phase comparison gain detection method.

(Configuration 14)

In the phase comparison detection method of the above configuration 13,

In the first phase comparison method, the input data signal and the identification timing signal are substantially synchronized. Detect the phase relationship between the two states,

In a second phase comparison step, a phase comparison detection method configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.

(Configuration 15)

In the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data to the predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle, the phase relationship between the input data signal and the identification timing signal is determined. A phase comparison gain detection method for detecting a phase comparison gain when comparing phases,

A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. A first phase comparison step of comparing the two phases by detecting the data correlation of the

By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. A phase comparison step of detecting a phase comparison gain based on a difference between comparison output values in each of the first and second phase comparison steps and a second predetermined amount that shifts the identification timing. A phase comparison gain detection method comprising a gain detection step.

(Configuration 16).

A first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. A comparison stage,

The data of the input data signal is obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison step of comparing phases by detecting a data correlation between the data of the identification output and

A phase comparison gain detecting step of detecting a phase comparison gain based on a difference between comparison outputs in each of the first and second phase comparison steps and a predetermined amount for shifting the identification timing of the identification timing signal. Detection method.

(Configuration 17)

An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,

An erroneous synchronization detection method configured to detect an erroneous synchronization state based on a difference between respective outputs in the first and second phase comparison stages.

(Configuration 18)

The data identification output of the data identification unit that identifies the data of the input data signal, and the data identification output of the switching detection unit that detects the switching of the data of the input data signal by shifting the data identification timing by the first predetermined amount. A first phase comparison step of comparing the phases of the two by detecting the data correlation between

By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. Error synchronizing state based on the output difference in each of the second phase comparing step and the first and second phase comparing steps. PT / JP2002 / 011319

20

An error synchronization detection method including an error synchronization detection step of detecting.

(Configuration 19)

An erroneous synchronization detection circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,

A first phase comparison step of comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal; When,

The phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison stage to compare;

An erroneous synchronization detection method comprising: an erroneous synchronization detection step of detecting an erroneous synchronization state based on a difference between outputs in each of the first and second phase comparison steps.

Claims

The scope of the claims

1. Compare the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship. A phase comparison gain detection circuit for detecting the phase comparison gain at the time of

A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit.

2. Between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal whose data switches at a predetermined cycle to the predetermined phase relationship. A phase comparison gain detection circuit for detecting a phase comparison gain when comparing the phases of

A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. First phase comparing means for comparing the phases of the users by detecting the data correlation between

The phase of the user is detected by detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount. A phase comparison gain for detecting a phase comparison gain based on a difference between respective outputs of the second phase comparison means to be compared and the first and second phase comparison means and a second predetermined amount for shifting the identification timing. Detection means and more Phase comparison gain detection circuit.

3. Compare the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship. A phase comparison gain detection circuit for detecting the phase comparison gain at the time of

A first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. Means of comparison;

A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective output values of the first and second phase comparing means and a predetermined amount for shifting the identification timing of the identification timing signal; circuit.

4. An erroneous synchronization detection circuit for detecting an erroneous synchronization state between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with the input data signal. ,

First phase comparing means for detecting a phase relationship between the input data signal and the identification timing ϊί symbol,

An erroneous synchronization detection circuit configured to detect an erroneous synchronization state based on respective output values of the first and second phase comparison means.

5. A PLL circuit comprising at least one of the phase comparison gain detection circuit according to any one of claims 1 to 3 and the false synchronization detection circuit according to claim 4. And

A control circuit for controlling loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit or a control circuit for controlling a phase lock operation based on a false synchronization detection output of the false synchronization detection circuit. Equipped PLL circuit.