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WO2003003459A3 - Anordnung eines halbleiterbauelementes auf einem substrat - Google Patents

Anordnung eines halbleiterbauelementes auf einem substrat Download PDF

Info

Publication number
WO2003003459A3
WO2003003459A3 PCT/DE2002/001896 DE0201896W WO03003459A3 WO 2003003459 A3 WO2003003459 A3 WO 2003003459A3 DE 0201896 W DE0201896 W DE 0201896W WO 03003459 A3 WO03003459 A3 WO 03003459A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
chip
semiconductor component
arrangement
contact surfaces
Prior art date
Application number
PCT/DE2002/001896
Other languages
English (en)
French (fr)
Other versions
WO2003003459A2 (de
Inventor
Holger Huebner
Original Assignee
Infineon Technologies Ag
Holger Huebner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Holger Huebner filed Critical Infineon Technologies Ag
Publication of WO2003003459A2 publication Critical patent/WO2003003459A2/de
Publication of WO2003003459A3 publication Critical patent/WO2003003459A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Die Erfindung schlägt eine Anordnung eines Halbleiterbauelementes auf einem Substrat vor, bei der das Substrat (30) auf einer Bestückungsseite (31) Kontaktflächen (32) aufweist. Das Halbleiterbauelement besteht aus einem ersten Chip (10) und zumindest einem zweiten Chip (20), wobei der zweite Chip (20) auf dem ersten Chip (10) angeordnet ist. Der erste und der zweite Chip (10, 20) sind dabei elektrisch miteinander verbunden. Darüber hinaus weist der erste Chip (10) auf seiner ersten Hauptseite (11) Kontaktflächen (12) auf, mit der er der Bestückungsseite (31) des Substrates (30) zugewandt ist. Die Kontaktflächen des ersten Chips (10) sind mit einander zugeordneten Kontaktflächen (32) des Substrates (30) über ein Verbindungsmittel elektrisch miteinander verbunden.
PCT/DE2002/001896 2001-06-27 2002-05-23 Anordnung eines halbleiterbauelementes auf einem substrat WO2003003459A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10131011.0 2001-06-27
DE10131011.0A DE10131011B4 (de) 2001-06-27 2001-06-27 Halbleiterchip und Anordnung eines Halbleiterbauelementes auf einem Substrat

Publications (2)

Publication Number Publication Date
WO2003003459A2 WO2003003459A2 (de) 2003-01-09
WO2003003459A3 true WO2003003459A3 (de) 2003-05-30

Family

ID=7689650

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/001896 WO2003003459A2 (de) 2001-06-27 2002-05-23 Anordnung eines halbleiterbauelementes auf einem substrat

Country Status (3)

Country Link
DE (1) DE10131011B4 (de)
TW (1) TW552696B (de)
WO (1) WO2003003459A2 (de)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
DE19907276A1 (de) * 1999-02-20 2000-09-07 Bosch Gmbh Robert Verfahren zur Herstellung einer Lötverbindung zwischen einem elektrischen Bauelement und einem Trägersubstrat
US6121682A (en) * 1998-12-26 2000-09-19 Hyundai Electronics Industries Co., Ltd. Multi-chip package
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6154370A (en) * 1998-07-21 2000-11-28 Lucent Technologies Inc. Recessed flip-chip package
US6225699B1 (en) * 1998-06-26 2001-05-01 International Business Machines Corporation Chip-on-chip interconnections of varied characteristics

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11177020A (ja) * 1997-12-11 1999-07-02 Oki Electric Ind Co Ltd 半導体実装構造およびその実装方法
US5897341A (en) * 1998-07-02 1999-04-27 Fujitsu Limited Diffusion bonded interconnect
DE19856573C1 (de) * 1998-12-08 2000-05-18 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration von aktiven Schaltungsebenen und unter Verwendung desselben erzeugte vertikale integrierte Schaltung
JP3235589B2 (ja) * 1999-03-16 2001-12-04 日本電気株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6225699B1 (en) * 1998-06-26 2001-05-01 International Business Machines Corporation Chip-on-chip interconnections of varied characteristics
US6154370A (en) * 1998-07-21 2000-11-28 Lucent Technologies Inc. Recessed flip-chip package
US6121682A (en) * 1998-12-26 2000-09-19 Hyundai Electronics Industries Co., Ltd. Multi-chip package
DE19907276A1 (de) * 1999-02-20 2000-09-07 Bosch Gmbh Robert Verfahren zur Herstellung einer Lötverbindung zwischen einem elektrischen Bauelement und einem Trägersubstrat

Also Published As

Publication number Publication date
DE10131011B4 (de) 2016-02-18
WO2003003459A2 (de) 2003-01-09
DE10131011A1 (de) 2003-01-16
TW552696B (en) 2003-09-11

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