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WO2003088514A1 - Systeme et procede de production d'un signal d'horloge dans un systeme de communications - Google Patents

Systeme et procede de production d'un signal d'horloge dans un systeme de communications Download PDF

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Publication number
WO2003088514A1
WO2003088514A1 PCT/US2003/010695 US0310695W WO03088514A1 WO 2003088514 A1 WO2003088514 A1 WO 2003088514A1 US 0310695 W US0310695 W US 0310695W WO 03088514 A1 WO03088514 A1 WO 03088514A1
Authority
WO
WIPO (PCT)
Prior art keywords
period
signal
isdn
noise
clock signal
Prior art date
Application number
PCT/US2003/010695
Other languages
English (en)
Inventor
Ehud Langbergh
Laurent Alloin
Peter Kleewein
Jean-François LOPEZ
Shareq Rahman
Patrick Duvaut
Original Assignee
Globespan Virata, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globespan Virata, Inc. filed Critical Globespan Virata, Inc.
Priority to AU2003221675A priority Critical patent/AU2003221675A1/en
Publication of WO2003088514A1 publication Critical patent/WO2003088514A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13039—Asymmetrical two-way transmission, e.g. ADSL, HDSL
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13209—ISDN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13214—Clock signals

Definitions

  • the present disclosure relates generally to communication systems and, more particularly, to systems and methods for generating clock signals in communication systems.
  • High-speed Internet services are becoming more popular as Internet users are accessing more complex applications over the Internet. These high-speed services include Digital Subscriber Lines (DSL), cable modems, Integrated Services Digital Networks (ISDN), Tl lines, satellite networks, etc.
  • DSL Digital Subscriber Lines
  • ISDN Integrated Services Digital Networks
  • Tl lines satellite networks, etc.
  • the ISDN clock signal In order for ISDN services and DSL services to be synchronized to each other, the ISDN clock signal must typically be provided to the DSL service because DSL services are typically not governed by the ISDN clock. Normally, the ISDN clock signal is provided by the TELCO at a cost to the DSL service provider or the DSL service subscriber. This added expense gives rise to a need in the industry for alternative approaches to synchronizing DSL services to ISDN services.
  • the present disclosure provides systems and methods for generating clock signals in communication systems.
  • one embodiment of the system comprises a receiver and logic components.
  • the receiver is adapted to receive a signal from a line.
  • the signal has a first period and a second period, which are correlated to an active period and an inactive period of disturbances in the signal.
  • the logic components are adapted to set a rising edge of a clock signal and a falling edge of the clock signal. The rising edge and the falling edge correspond to an onset of the active period and the onset of the inactive period, respectively.
  • the present disclosure also provides methods for generating clock signals in communication systems.
  • one embodiment of the method comprises the steps of receiving a signal from a line and setting a rising edge and a falling edge of a clock signal in response to the received signal.
  • the received signal has a first period and a second period that are correlated to an active and inactive period of disturbances to the signal.
  • the rising edge of the clock signal is set to correspond to an onset of the active period, while the falling edge of the clock signal is set to correspond to an onset of the inactive period.
  • FIG. 1 is a block diagram showing a non-limiting example of a digital communication system as an asymmetric Digital Subscriber Line (ADSL) system.
  • ADSL Digital Subscriber Line
  • FIG. 2 is a block diagram showing the ADSL modem of FIG. 1 in greater detail.
  • FIG. 3 is a block diagram showing the encoder and gain sealer of FIG. 2 in greater detail.
  • FIGS. 4 through 6 are flowcharts showing embodiments of a method for generating a clock signal.
  • FIG. 7 is an example timing diagram showing an example embodiment in which cyclostationary disturbances are generated by concurrent deployment of integrated services digital network (ISDN) and ADSL.
  • ISDN integrated services digital network
  • ADSL integrated services digital network
  • FIG. 1 is a block diagram showing a non-limiting example of a digital communication system as an asymmetric Digital Subscriber Line (ADSL) system 100.
  • a central office 110 is connected to a customer premises 160 via a two-conductor pair wire 155.
  • an ADSL service rack 140 gathers information for transmission.
  • the information may be in the form of video conferencing 115, Internet 120, telephone services 125, movies on demand 130, or broadcast media 135. All of the information is gathered at a Digital Subscriber Line access multiplexer (DSLAM) 145, which assembles the data for transmission by ADSL modems 150. Once the information has been coded and framed, it is sent to the customer premises 160 via a local loop, generally a two-conductor pair 155. The data is received at the customer premises 160 by an ADSL modem 180. The information is then decoded and provided to the user.
  • Several non-limiting examples of communication services that use the decoded information include a fax 165, a user's computer 170, a television set 175, an analog telephone 185, or, in the alternative, a digital telephone 195.
  • FIG. 2 is a block diagram showing the ADSL modem 150 of FIG. 1 in greater detail. While FIG. 2 shows only one ADSL modem 150, it should be appreciated that each of the ADSL modems 150 of FIG. 2 may have similar components.
  • the ADSL modem 150 at the central office 110 comprises an ADSL transceiver unit (ATU-C) 205 configured to assemble data for transmission on the communication line 155.
  • the ATU-C 205 comprises both a fast path and an interleaved path between a multiplexer (MUX) and synchronization (sync) control block 210 and a tone ordering circuit 250.
  • MUX multiplexer
  • sync synchronization
  • the fast path which provides low latency, comprises a fast cyclic redundancy checking (CRC) block 215 and a scrambling and forward error correcting (FEC) block 225.
  • the interleaved path which provides a lower error rate at a greater latency, comprises an interleaved CRC block 220, a scrambling and FEC block 230, and an interleaver 240. Since MUX/sync control blocks 210, CRC blocks 215, 220, scrambling and FEC blocks 225, 230, interleavers 240, and tone ordering circuits 250 are known to those of ordinary skill in the art, further discussion of these components is omitted here.
  • the signal upon traversing either the fast path or the interleaved path, enters an encoding and gain scaling block 255, which encodes the data into a constellation and also scales the data for transmission.
  • the encoding and gain scaling block 255 is discussed in greater detail with reference to FIG. 3.
  • IFT inverse Fourier transform
  • P/S parallel-to-serial
  • the serial data stream is conveyed to a digital-to-analog (D/A) converter and analog processor 270, which produces an analog signal for data transmission. Since LFT blocks 250, P/S converters 255, D/A converters and analog processors 270 are known to those of ordinary skill in the art, further discussion of these components is omitted here.
  • the analog signal is transmitted through the communication line 155 by a transmitter 275 in the ATU-C 205.
  • FIG. 3 is a block diagram showing the encoder and gain sealer 255 of FIG. 2 in greater detail.
  • the encoder and gain sealer 255 comprises a receiver 310 and a processor 320.
  • the receiver 310 and the processor 320 are part of a DSL system employing discrete multi-tone (DMT) modulation.
  • DMT discrete multi-tone
  • the DSL system may also be capable of dual-modulation tuning (e.g., dual bit-mapping). Since dual bit-mapping techniques are known to those of ordinary skill in the art, further discussion of dual bit- mapping techniques is omitted here.
  • the receiver 310 receives data from the tone-ordering circuit 250 as well as signals from the communication line 155. Since upstream and downstream signals are impacted by the cyclostationary nature of the TCM-ISDN interferences, it is desirable to synchronize the transmission and reception of DSL signals with the TCM-ISDN interferences using, for example, known dual bit-mapping techniques. h the absence of a TCM-ISDN clock signal, which normally indicates whether or not self-disturbance is present in the system, by indicating whether or not the TCM-ISDN service is transmitting or receiving, the synchronization between DSL and TCM-ISDN would be provided using an alternative approach.
  • the encoder/gain sealer 255 is continuously updated with line information. If a cyclostationary interference, such as that exhibited by TCM-ISDN, is present, then that cyclostationary interference manifests itself in the line information. Hence, the line information may be used to generate a clock signal that is substantially synchronous to the cyclostationary interference.
  • the processor 320 of FIG. 3 is adapted to extract this information from the line 155 and to generate a clock signal using the extracted information.
  • the processor 320 may have two broad sets of logic components: the first set 330 being configured to determine the periodicity of the cyclostationary noise, and the second set 340 being configured to set the rising and falling edges of the clock signal.
  • the edge- setting logic components 340 generate a signal that drives a clock-generating circuit such as a phase-locked loop (PLL) circuit.
  • PLL phase-locked loop
  • the first set 330 of logic components comprise TCM-ISDN transmitting-period-determination logic 332 and TCM-ISDN receiving-period-determination logic 334.
  • the second set 340 of logic components comprise rising-edge-setting logic 342 and falling- edge-setting logic 344.
  • the receiver 310 receives a signal from the line 155, which is characterized by a signal-to-noise ratio (SNR), line attenuation information, and other known characteristics. Since these characteristics are affected by the different cycles (i.e., transmit or receive) of concurrently deployed TCM-ISDN services, these signal characteristics are reflective of whether the TCM-ISDN service is transmitting or receiving.
  • SNR signal-to-noise ratio
  • the received signal is conveyed to the first set 330 of logic components in the processor 320 at which point the TCM-ISDN transmitting-period-determination logic 332 determines the time periods in which the TCM-ISDN service is transmitting signals.
  • the TCM-ISDN receiving-period-determination logic 334 determines the time periods in which the TCM-ISDN service is receiving signals. Alternatively, the TCM- ISDN receiving period may be presumed to be the non-transmitting period. In this regard, the TCM-ISDN receiving-period-determination logic 334 may be wholly removed from the system without adverse effect to the invention. In any event, once the first set 330 of logic components determines the onset of the transmitting period and the onset of the receiving period, this information is conveyed to the second set 340 of logic components.
  • the second set 340 of logic components receives this information and, using this information, the rising-edge-setting logic 342 generates a signal at the onset of the TCM- ISDN transmission period. The generated signal is used to drive the rising edge of a clock. Similarly, using the information indicative of the onset of the TCM-ISDN receiving period, the falling-edge-setting logic 344 generates a signal that is used to drive the falling edge of the clock. As shown in FIG. 3, the system, therefore, generates a clock signal that is substantially synchronous with the TCM-ISDN interferences without the need for a separate TCM-ISDN clock signal.
  • the data may be loaded by the data-loading logic 350 using a dual bit- mapping scheme or other technique that accounts for such a cyclostationary interference. As shown in FIGS. 1 through 3, the DSL service may be synchronized to the TCM-ISDN service without directly providing a TCM-ISDN clock signal to the DSL system 100.
  • FIGS. 4 through 6 are flowcharts showing embodiments of methods that may be implemented by the systems of FIGS. 1 through 3. It should, however, be appreciated that the embodiments of the methods of FIGS. 4 through 6 are not necessarily limited to the systems of FIGS. 1 through 3. Rather, the embodiments of the methods may be implemented in any system exhibiting cyclostationary disturbances.
  • one embodiment of the method begins with the step of receiving (420) a signal from a line.
  • the signal is characterized by a cyclostationary disturbance having a first period and a second period.
  • the first period is designated as an active period in which the disturbance is relatively large, while the second period is designated as an inactive period in which the disturbance is relatively small.
  • the periodicity of the cyclostationary disturbance is determined (430).
  • the determining (430) of the periodicity may be seen as comprising the steps of determining (440) the active period of the disturbance of the signal, and determining (450) the inactive period of the disturbance of the signal.
  • the active period may be seen as the transmitting period of TCM-ISDN and the inactive period may be seen as the receiving period of TCM-ISDN.
  • the inactive period may be seen as the transmitting period of TCM-ISDN while the active period may be seen as the receiving period of TCM-ISDN.
  • a rising edge of a clock is set (520) to correspond to the onset of the active period.
  • the rising edge of the clock is set (520) to correspond to the onset of the TCM-ISDN transmitting period.
  • the falling edge of the clock is set (530) to correspond to the onset of the inactive period, which, in the context of TCM-ISDN, would be the TCM-ISDN receiving period.
  • the setting (520, 530) of the rising and falling edges of the clock results in a generation of a clock signal that is substantially synchronized to the periodicity of the cyclostationary disturbance.
  • the generation of the clock signal now permits synchronization of the system with the cyclostationary disturbance.
  • the generated clock signal may correspond exactly with the TCM-ISDN clock signal
  • the generated clock signal need not correspond exactly to the TCM-ISDN clock signal.
  • the phase of the clock signals may be offset from each other due to timing delays, etc.
  • the frequency of the clock signals may differ from each other due to clock dividing functions, which are described below with reference to FIG. 6.
  • the generated clock signal may optionally be divided (620) to produce a higher frequency clock signal.
  • the frequency of the clock signal may also be reduced by known techniques, h any event, upon generating the clock signal, as shown in FIGS.4 and 5, signals may be transmitted (630) during the active period, and received (640) during the inactive period.
  • FIG. 7 is an example timing diagram showing an example embodiment in which cyclostationary disturbances are generated by concurrent deployment of integrated services digital network (ISDN) and ADSL.
  • the top line of the timing diagram shows the actual TCM-ISDN clock signal, while the remaining lines show the relationship between the TCM-ISDN clock signal and other TCM-ISDN and ADSL signals.
  • ISDN integrated services digital network
  • the TCM-ISDN clock is defined by a fixed cyclostationary behavior.
  • the transmission of ISDN signals from the ISDN central office (CO) are gated by the rising edge of the TCM-ISDN clock.
  • the ISDN CO beings transmission of the ISDN signal when the TCM-ISDN clock signal rises.
  • the transmitted ISDN signal is received at the ISDN customer premises (CP) after a short delay, which is due to propagation of the signal across the communication line.
  • the ISDN-CP transmits ISDN signals
  • the ISDN-CO receives the ISDN signals.
  • the ISDN-CP and ISDN-CO exhibit cyclostationary behavior. This cyclostationary behavior exhibits itself as cyclostationary disturbance in the ADSL system.
  • the disturbance on the ADSL-CO is greater during the ISDN-CO signal transmitting period than the ISDN-CO signal receiving period.
  • the disturbance on the ADSL-CO is reduced during the ISDN-CO signal receiving period.
  • the behavior of the ADSL-CP displays converse behavior. In other words, when the ISDN-CO is transmitting, then the ADSL-CP exhibits a reduced disturbance.
  • the ADSL data-loading scheme corresponds to the transmission and reception of ISDN signals.
  • the generated clock signal need not have an exact one-to-one correspondence with the actual TCM-ISDN clock but may, in some embodiments, have a delayed correspondence in which the phase of the rising edge and falling edge are slightly offset from the actual TCM-ISDN clock.
  • the processor 320 and the logic components 330, 332, 334, 340, 342, 344 described above may be implemented in hardware, software, firmware, or a combination thereof. In the preferred embodiment(s), the processor 320 and the logic components
  • 330, 332, 334, 340, 342, 344 are implemented in hardware using any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
  • ASIC application specific integrated circuit
  • PGA programmable gate array
  • FPGA field programmable gate array
  • the processor 320 and the logic components 330, 332, 334, 340, 342, 344 are implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system.
  • a clock signal may be generated by recovering any cyclostationary noise.
  • a disturbance may be used to generate a clock signal.
  • the generated clock signal is shown as having the same periodicity as the cyclostationary disturbance in the above-described embodiments, it should be appreciated that the generated clock signal may be further divided by clock- dividing techniques that are known in the art.
  • the logic components are shown as being within the encoder and gain sealer of the ATU, it should be appreciated that these logic components may be located in other portions of the DSL modem. In other words, as long as these components perform substantially the same function of determining the periodicity of the cyclostationary noise (e.g., the transmit and receive periods of TCM-ISDN signals) and setting the rising and falling edges of a clock signal, then these components may be located almost anywhere within the DSL modem. Also, while the embodiments of FIGS.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne des procédés de production de signaux d'horloges dans lesquels un signal est reçu à partir d'une ligne (420) et un signal d'horloge est produit en fonction du signal reçu. Ledit signal reçu présente des parties qui sont corrélées à une perturbation (430) cyclostationnaire présente sur la ligne. Par conséquent, le réglage du front montant et du front descendant de l'horloge en fonction du signal reçu peut entraîner un signal d'horloge sensiblement synchrone par rapport au signal cyclostationnaire sur la ligne.
PCT/US2003/010695 2002-04-08 2003-04-07 Systeme et procede de production d'un signal d'horloge dans un systeme de communications WO2003088514A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003221675A AU2003221675A1 (en) 2002-04-08 2003-04-07 System and method for generating a clock signal in a communication system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37100602P 2002-04-08 2002-04-08
US60/371,006 2002-04-08

Publications (1)

Publication Number Publication Date
WO2003088514A1 true WO2003088514A1 (fr) 2003-10-23

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WO (1) WO2003088514A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648778A (en) * 1994-11-02 1997-07-15 Advanced Micro Devices, Inc. Stereo audio CODEC
US5991311A (en) * 1997-10-25 1999-11-23 Centillium Technology Time-multiplexed transmission on digital-subscriber lines synchronized to existing TCM-ISDN for reduced cross-talk
US6393051B1 (en) * 1998-06-30 2002-05-21 Fujitsu Limited Digital subscriber line communicating system and a transceiver in the system
US6510184B1 (en) * 1998-02-27 2003-01-21 Nec Corporation Multi-carrier transmission system and method thereof
US6580752B1 (en) * 1998-12-08 2003-06-17 Globespanvirata, Inc. Alternative configurations for an ADSL system operating in a time duplex noise environment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648778A (en) * 1994-11-02 1997-07-15 Advanced Micro Devices, Inc. Stereo audio CODEC
US5991311A (en) * 1997-10-25 1999-11-23 Centillium Technology Time-multiplexed transmission on digital-subscriber lines synchronized to existing TCM-ISDN for reduced cross-talk
US6510184B1 (en) * 1998-02-27 2003-01-21 Nec Corporation Multi-carrier transmission system and method thereof
US6393051B1 (en) * 1998-06-30 2002-05-21 Fujitsu Limited Digital subscriber line communicating system and a transceiver in the system
US6580752B1 (en) * 1998-12-08 2003-06-17 Globespanvirata, Inc. Alternative configurations for an ADSL system operating in a time duplex noise environment

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