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WO2003065203A3 - Method for recognising a correct command entry address, when command words of different lengths are used - Google Patents

Method for recognising a correct command entry address, when command words of different lengths are used Download PDF

Info

Publication number
WO2003065203A3
WO2003065203A3 PCT/DE2003/000218 DE0300218W WO03065203A3 WO 2003065203 A3 WO2003065203 A3 WO 2003065203A3 DE 0300218 W DE0300218 W DE 0300218W WO 03065203 A3 WO03065203 A3 WO 03065203A3
Authority
WO
WIPO (PCT)
Prior art keywords
command
recognising
entry address
different lengths
correct
Prior art date
Application number
PCT/DE2003/000218
Other languages
German (de)
French (fr)
Other versions
WO2003065203A2 (en
Inventor
Gerd Dirscherl
Michael Smola
Original Assignee
Infineon Technologies Ag
Gerd Dirscherl
Michael Smola
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Gerd Dirscherl, Michael Smola filed Critical Infineon Technologies Ag
Publication of WO2003065203A2 publication Critical patent/WO2003065203A2/en
Publication of WO2003065203A3 publication Critical patent/WO2003065203A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Communication Control (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

The invention relates to a method for recognising a correct command entry address, according to which each command word has a predetermined start bit code, which indicates the length of said word.
PCT/DE2003/000218 2002-02-01 2003-01-27 Method for recognising a correct command entry address, when command words of different lengths are used WO2003065203A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10204038.9 2002-02-01
DE10204038A DE10204038B4 (en) 2002-02-01 2002-02-01 Method for detecting a correct command entry address when using command words of different lengths

Publications (2)

Publication Number Publication Date
WO2003065203A2 WO2003065203A2 (en) 2003-08-07
WO2003065203A3 true WO2003065203A3 (en) 2006-01-19

Family

ID=27588225

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/000218 WO2003065203A2 (en) 2002-02-01 2003-01-27 Method for recognising a correct command entry address, when command words of different lengths are used

Country Status (3)

Country Link
DE (1) DE10204038B4 (en)
TW (1) TW200302978A (en)
WO (1) WO2003065203A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200910195A (en) * 2007-08-20 2009-03-01 Sunplus Technology Co Ltd A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US6209079B1 (en) * 1996-09-13 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Processor for executing instruction codes of two different lengths and device for inputting the instruction codes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US588260A (en) * 1897-08-17 Adding-machine
US5881260A (en) * 1998-02-09 1999-03-09 Hewlett-Packard Company Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
DE10120522A1 (en) * 2001-04-26 2002-11-07 Infineon Technologies Ag Method for recognizing a correct command entry address when using command words of different lengths

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US6209079B1 (en) * 1996-09-13 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Processor for executing instruction codes of two different lengths and device for inputting the instruction codes

Also Published As

Publication number Publication date
TW200302978A (en) 2003-08-16
DE10204038A1 (en) 2003-08-14
WO2003065203A2 (en) 2003-08-07
DE10204038B4 (en) 2005-03-03

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