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WO2002027792A3 - Low inductive wire bond chip packaging - Google Patents

Low inductive wire bond chip packaging Download PDF

Info

Publication number
WO2002027792A3
WO2002027792A3 PCT/US2001/029643 US0129643W WO0227792A3 WO 2002027792 A3 WO2002027792 A3 WO 2002027792A3 US 0129643 W US0129643 W US 0129643W WO 0227792 A3 WO0227792 A3 WO 0227792A3
Authority
WO
WIPO (PCT)
Prior art keywords
wire bond
chip packaging
low inductive
inductive wire
bond chip
Prior art date
Application number
PCT/US2001/029643
Other languages
French (fr)
Other versions
WO2002027792A2 (en
Inventor
Siamak Fazelpour
Hassan S Hashemi
Original Assignee
Conexant Systems Inc
Siamak Fazelpour
Hassan S Hashemi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems Inc, Siamak Fazelpour, Hassan S Hashemi filed Critical Conexant Systems Inc
Priority to AU2001292949A priority Critical patent/AU2001292949A1/en
Publication of WO2002027792A2 publication Critical patent/WO2002027792A2/en
Publication of WO2002027792A3 publication Critical patent/WO2002027792A3/en

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A chip that comprises a plurality of chip pads and a substrate that comprises a first tier and a second tier are provided. The first tier of the substrate comprises a plurality of substrate bond pads and the second tier of the substrate comprises a plurality of substrate bond pads. At least two of the chip pads are connected to at least two of the substrate bond pads on the first tier. Additionally, at least two of the chip pads are connected to at least two of the substrate bond pads on the second tier.
PCT/US2001/029643 2000-09-27 2001-09-20 Low inductive wire bond chip packaging WO2002027792A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001292949A AU2001292949A1 (en) 2000-09-27 2001-09-20 Low inductive wire bond chip packaging

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67222200A 2000-09-27 2000-09-27
US09/672,222 2000-09-27

Publications (2)

Publication Number Publication Date
WO2002027792A2 WO2002027792A2 (en) 2002-04-04
WO2002027792A3 true WO2002027792A3 (en) 2002-05-30

Family

ID=24697654

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029643 WO2002027792A2 (en) 2000-09-27 2001-09-20 Low inductive wire bond chip packaging

Country Status (2)

Country Link
AU (1) AU2001292949A1 (en)
WO (1) WO2002027792A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5787575A (en) * 1996-09-09 1998-08-04 Intel Corporation Method for plating a bond finger of an intergrated circuit package
EP0959648A1 (en) * 1997-01-30 1999-11-24 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5787575A (en) * 1996-09-09 1998-08-04 Intel Corporation Method for plating a bond finger of an intergrated circuit package
EP0959648A1 (en) * 1997-01-30 1999-11-24 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor

Also Published As

Publication number Publication date
WO2002027792A2 (en) 2002-04-04
AU2001292949A1 (en) 2002-04-08

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