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WO2002027792A2 - Boitiers de puces a liaison par fils a faible induction - Google Patents

Boitiers de puces a liaison par fils a faible induction Download PDF

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Publication number
WO2002027792A2
WO2002027792A2 PCT/US2001/029643 US0129643W WO0227792A2 WO 2002027792 A2 WO2002027792 A2 WO 2002027792A2 US 0129643 W US0129643 W US 0129643W WO 0227792 A2 WO0227792 A2 WO 0227792A2
Authority
WO
WIPO (PCT)
Prior art keywords
chip
substrate
tier
pads
substrate bond
Prior art date
Application number
PCT/US2001/029643
Other languages
English (en)
Other versions
WO2002027792A3 (fr
Inventor
Siamak Fazelpour
Hassan S. Hashemi
Original Assignee
Conexant Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Priority to AU2001292949A priority Critical patent/AU2001292949A1/en
Publication of WO2002027792A2 publication Critical patent/WO2002027792A2/fr
Publication of WO2002027792A3 publication Critical patent/WO2002027792A3/fr

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to integrated circuit packaging, and more particularly, to improved wire bonded chip packaging.
  • bondwire inductance is usually the limiting parameter regarding signal integrity.
  • SONET SONET
  • Wire bonding of a chip on a MCM or BGA substrate uses chip-to-package (or chip-to-substrate) connections comprising bondwires .
  • Chip-to-package connections with low inductance are desired and thus, short chip-to- package connections are preferred.
  • high pin count chips require large fan out angles, which increase the length of the bondwires and subsequently the inductance of the bondwires. Therefore, there is a need for an improved wire bond structure that reduces undesirable high inductance associated with traditional wire bond chips .
  • the present invention relates to a chip that is wire bonded to a substrate having at least two tiers. Both the first tier and the second tier of the substrate comprises a plurality of substrate bond pads. At least two chip pads are connected to at least two substrate bond pads on the first tier and at least two other chip pads are connected to at least two substrate bond pads on the second tier.
  • a device and a method in an embodiment according to the present invention are capable of providing less inductance through bondwires used in the chips.
  • a device and a method in an embodiment according to the present invention are capable of providing low inductance for high pin count, low chip pad pitch chips, thereby avoiding the problems associated with conventional chips utilizing bondwires.
  • FIG. 1 shows a top plan view of a chip as used in an embodiment according to the present invention
  • FIG. 2 shows a sectional view of a chip connected to a substrate in an embodiment according to the present invention
  • FIG. 3 shows a top plan view of a chip in a substrate in an embodiment according to the present invention
  • FIG. 4 shows a bondwire diagram of a chip to a substrate in an embodiment according to the present invention.
  • FIG. 5 shows a conventional bondwire diagram of a chip to a substrate.
  • FIG. 1 shows a top plan view of a chip 100 as used in an embodiment according to the present invention.
  • Chip 100 receives inputs from input sides 110 and 120, which are opposite to each other.
  • Chip 100 outputs signals from output sides 130 and 140, which are opposite to each other.
  • chip 100 has input sides 110 and 120 adjacent to each other and
  • chip 100 has one input side and one output side.
  • Chip 100 has a plurality of chip pads (or chip pins) 150, 152, 154, . . . 162.
  • Chip 100 comprises as many chip pads as necessary to perform the desired results of the chip. For example, a high pin count chip may be used that has between one hundred and two thousand chip pads, or alternatively, one hundred or more chip pads .
  • the chip pads are made of a material capable of sending and/or receiving signals.
  • the chip pads may comprise a metal or some other conductive material.
  • the chip pads may be made of aluminum or copper .
  • the chip pads may be made of gold.
  • the chip pads are set up such that chip pads 150 and 162 are "grounded," which means that the pads are capable of being connected to ground.
  • Chip pads 152 transmits or receives a signal "SI” and chip pad 154 transmits or receives a signalbar "S1BAR" , which means that the pads are capable of transmitting or receiving a signal or signalbar, respectively.
  • Chip pad 156 is connected to "power,” which means that the pad is capable of being connected to power. Further, chip pad 158 transmits or receives a signal “S2" and chip pad 160 transmits or receives a signalbar "S2BAR.” Therefore, a signal, ground or power may be running through these pads during operation of the chip, but not necessarily when disconnected or in transit. In another embodiment, the chip pads are configured to transmit or receive signals necessary to carry out the desired result of the chip.
  • chip 100 is organized such that in operation, signals such as SI and SIBAR are surrounded by a power and a ground signal to help prevent interference and noise in the signals.
  • signals such as SI and SIBAR are surrounded by a power and a ground signal to help prevent interference and noise in the signals.
  • the signals are isolated, preventing noise and unwanted cross-talk between one signal and other signals.
  • Chip 200 is connected to substrate 202 via a die attach material 204.
  • Substrate 202 is capable of including multiple layers of materials, such as multiple layers of different metals.
  • copper may be in the inner layers of substrate 202 and copper, nickel and/or gold may be on the outer layers of substrate 202.
  • die attach material 204 is made of an epoxy, such as a silver filled epoxy.
  • substrate 202 is attached to a mother board.
  • Substrate 202 can be attached to a mother board using BGA connections.
  • a heat spreader which is used to dissipate heat, may be placed between substrate 202 and the mother board.
  • Substrate 202 includes a plurality of tiers. For example, in the embodiment shown in FIG. 2, substrate 202 includes a first tier 214 and a second tier 210. Substrate 202 may also include any number of additional tiers such as a third tier or a fourth tier.
  • substrate 202 is made of an organic material, such as a BT-based substrate or other organic materials.
  • the tiers may be cut out of a single substrate.
  • the tiers in the substrate may be constructed separately and attached to one another.
  • any other method of constructing tiers on a substrate may be used to create the tiers of substrate 202.
  • Chip 200 comprises a plurality of chip pads 234. Chip 200 rests in a cavity 206 of substrate 202.
  • the chip pads are electrically connected to the substrate bond pads using bondwires. Alternatively, besides bondwires, other methods of electrically connecting the chip pads to the substrate bond pads can be used in an embodiment of the present invention. In one embodiment, each chip pad is electrically connected to a single substrate bond pad.
  • Chip pads 234 are connected to bondwires 230 and 232.
  • Bondwire 230 connects one of the chip pads 234 to a substrate bond pad 236 on first tier 214.
  • Bondwire 232 connects one of the chip pads 234 to a substrate bond pad 236 on second tier 210. While two bondwires 230 and 232 are shown in FIG. 2, multiple bondwires connecting chip pads to substrate bond pads are used in an embodiment according to the present invention.
  • the substrate bond pads are made of a material capable of sending and/or receiving signals from the bondwire.
  • the substrate bond pads may be made of copper, nickel, gold, and/or other conductive materials .
  • the number of chip pads used is equal to the number of substrate bond pads used.
  • the number of chip pads used may be unequal to the number of substrate bond pads used.
  • Bondwires 230 and 232 electrically connect chip 200 with substrate 202 over gap 220.
  • Gap 220 is designed to separate the chip and the substrate.
  • gap 220 can be less than 1.0 mm wide, such as between 0.5 mm and 1.0 mm.
  • gap 220 is 0.750 mm.
  • Bondwires 230 and 232 are at least as long as gap 220 is wide.
  • the length of bondwire 230 is approximately 1.0 mm, for example 0.9 mm to 1.1 mm
  • bond wire 232 is approximately 2.0 mm, for example 1.9 mm to 2.1 mm.
  • When a bondwire has a length of 1.0 mm it has an inductance of approximately 750 pH.
  • the length of the bondwires are usually between 1.0-4.0 mm, depending on the distance between the chip pad and the substrate bond pad.
  • substrate bond pad 236 on first tier 214 is connected to a wrap around pad 244.
  • Substrate bond pad 236 on second tier 210 is connected to a wrap around pad 246.
  • Wrap around pads 244 and 246 wrap around the edge of substrate 202.
  • wrap around pads 244 and 246 are integrated into substrate 202. Wrap around pads 244 and 246 connect substrate bond pad 236 to planes 240 and 242, respectively, where planes 240 and 242 are underneath the top of first tier 214 and second tier 210, respectively.
  • planes 242 and 240 are either a ground or a power plane, depending on whether a ground or power signal is needed for that plane. For example, if a bondwire is connected to a chip pad needing a power signal, then the bondwire is connected to a substrate bond pad that is connected to a power plane. Alternatively, if a bondwire is connected to a grounded chip pad, then the bondwire is connected to a substrate bond pad that is connected to a ground plane. As shown in FIG. 2, plane 240. is a power plane and plane 242 is a ground plane. Therefore, in this embodiment, power pins of chip 200 are connected to first tier 214 and subsequently plane 240, and grounded pads of chip 200 are connected to second tier 210 and subsequently plane 242.
  • chip 200 and first tier 214 are at substantially the same height. This allows the length of the bondwires 230 between chip 200 and the first tier 214 to be minimized.
  • Second tier 210 is then at a height above the height of chip 200, for example the height of second tier 210 is 225 microns higher than the height of chip 200.
  • the height of 225 microns is derived from second tier 210 having a height that is 125 microns higher than plane 242 and the power or ground signal plane 242 having a height that is 100 microns higher than the height of first tier 214.
  • the above stated heights of the tiers in the substrate may be adjusted as needed.
  • chip 200 is at substantially the same height as the height of second tier 210, allowing bondwires 232 to be minimized in length. In such an instance, the height of the first tier is less than the height of chip 200.
  • Chip 300 has various chip pads 352, 354, 356, 358, 360, 362. Chip pads 352, 354,
  • Substrate bond pads 382, 384, 386 are on a first tier 314 of substrate 302. Bondwires 330 electrically connect chip pads 352,
  • Chip pads 358, 360, 362 electrically connect to substrate bond pads 388, 390, 392, respectively, over gap 320 and first tier 314.
  • Substrate bond pads 388, 360, 362 electrically connect to substrate bond pads 388, 390, 392, respectively, over gap 320 and first tier 314.
  • Substrate bond pads 388, 360, 362 electrically connect to substrate bond pads 388, 390, 392, respectively, over gap 320 and first tier 314.
  • 390, 392 are on a second tier 310 of substrate 302.
  • Bondwires 332 electrically connect chip pads 358, 360,
  • corner split 370 is provided at one or more of the four corners of substrate 302. Corner split 370 provides a gap at the corners of substrate 302, as shown in FIG. 3.
  • a corner split 370 may be located at all of the corners of substrate 302, at one of the corners of substrate 302, or at multiple corners of substrate 302. Corner split 370 is useful for splitting input and output power signals . This may be desired because the input signal travels to the core of the chip while the output signal travels through output buffers. Therefore, the noise requirements on the input and output signals differ. For example, without corner split 370, if several of the output buffers switch at the same time (simultaneous switching output buffer noise ("SSO noise”)), the SSO noise can cause a voltage change to occur in the input signal. Corner split 370, however, reduces noise, such as SSO noise, thus decreasing interference with the input signal cause by the noise.
  • SSO noise simultaneous switching output buffer noise
  • corner split 370 is a size that is appropriate for the package. In one embodiment, corner split 370 is between 1.0 mm to 2.0 mm. Alternatively, corner split 370 is 1.0 mm or less. Further, corner split 370, along with other gaps in the substrate may be filled with prepreg.
  • FIG. 4 a bondwire diagram of a chip to a substrate in an embodiment according to the present invention is shown.
  • a crosspoint switch bondwire connection is shown in FIG. 4, however, other bondwire connections that are appropriate for the package may be used in an embodiment of the present invention.
  • Bondwires 430 electrically connect chip pads 440 to substrate bond pads 410 and 414.
  • Chip pads 440 are electrically connected to substrate bond pads 410 and 414.
  • Substrate bond pads 410 are on a first tier of the substrate and substrate bond pads 414 are on a second tier of the substrate.
  • Chip pads 440 have a chip pad pitch 442 that is measured from the middle of one chip pad to the middle of the next chip pad. As the chip pads are generally evenly spaced, a chip will generally have one chip pad pitch. For example, chip pad pitch 442 is between 60- 100 microns, such as 80 microns. Alternatively, the chip pad pitch 442 may be any size that is needed on the chip.
  • Substrate bond pads 410 and 414 have a substrate bond pad pitch 444. Substrate bond pad pitch 444 is measured from the middle of one substrate bond pad to the middle of the next substrate bond pad. As the substrate bond pads are generally evenly spaced, a substrate will generally have one substrate bond pad pitch. In this embodiment, substrate bond pad pitch 444 is between 140-200 microns. For example, substrate bond pad pitch 444 is 160 microns. Alternatively, the substrate bond pad pitch 444 may be any size that is needed on the substrate .
  • Two tiers are shown in FIG. 4. However, the number of tiers are increased to accommodate as many tiers as appropriate for the package.
  • a formula that is used to determine the number of tiers is as follows: divide the substrate bond pad pitch by the chip pad pitch; the result is the number of tiers. For example, with a chip pad pitch of 80 and a substrate bond pad pitch of 160, two tiers may be used. Additionally, with a chip pad pitch of 85 and a substrate bond pad pitch of 170, two tiers may be used. If the chip pad pitch is one half or more of the substrate bond pad pitch, two tiers are used in the substrate. If the chip pad pitch is one third or more of the substrate bond pad pitch, three tiers are used in the substrate.
  • the result is rounded to a whole number.
  • the result is rounded to the closest whole number; for example, with a chip pad pitch of 80 and a substrate bond pad pitch of 165, two tiers may be used.
  • the result is rounded up to the next whole number; for example, with a chip pad pitch of 60 and a substrate bond pad pitch of 135, three tiers may be used. If these two embodiments result in different values for the number of tiers to be used for a certain chip pad pitch and substrate bond pitch, and use of the different number of tiers results in a significant change in the fan out angle, the higher number of tiers may be used.
  • the chip pads are not evenly spaced on the chip (e.g., there are multiple chip pad pitches for the chip) an average of the chip pad pitches on the chip is used in the above formula.
  • the minimum chip pad pitch may be used in the above formula.
  • the substrate bond pads are not evenly spaced on the substrate (e.g., there are multiple substrate bond pad pitches for the substrate) an average of the substrate bond pad pitches on the substrate is used in the above formula.
  • the minimum substrate bond pad pitch may be used in the above formula.
  • Substrate bond pad pitch 444 is larger than chip pad pitch 442. Substrate bond pad pitch 444 is larger than chip pad pitch 442 to make the process of connecting the bondwire to the substrate bond pad easier, as described below.
  • One method of attaching the bondwire to the substrate bond pad and the chip pad is a conventional ultrasound technique.
  • a conventional ultrasound technique the bondwire is connected to the chip pad. Then, to attach the bondwire to the substrate bond pad, the bondwire is scrubbed against the surface of the substrate bond pad.
  • the ultrasound technique entails scrubbing the bondwire back and forth against the substrate bond pad, which because of the friction, connects the bondwire to the substrate bond pad.
  • the substrate bond pad width is at approximately three times the diameter of the bondwire. For example, the bondwire has a diameter that is 25 microns. Therefore, a width of approximately 75 microns is used on the substrate bond pad.
  • the substrate bond pad makes the process easier. This extra space may be 25 microns, making the substrate bond pad 100 microns. Having more extra space results in a higher yield of successfully produced packages, but more of a fan out angle.
  • the substrate bond pads are also separated by a distance, which may be 60 microns. Therefore, in this embodiment, the pitch for the substrate bond pads is 160 microns.
  • Chip pads 540 are electrically connected to substrate bond pads 514 via bondwires 530. However, because of the difference in pitch between chip pads 540 and substrate bond pads 514, bondwires 530 are longer at the first and last bondwires 530 than the center bondwires 530.
  • chip pads 440 are electrically connected to substrate bond pads on a specific tier in groups of signals.
  • groups of signals may be any size, such as one, two, three or four.
  • SI and SIBAR together with one of power or ground to make a group of three signals.
  • the chip pads are connected to the first tier and the second tier in groups of three signals.
  • a group of four signals is used, wherein the signals SI, SIBAR, ground and power are grouped together.
  • the bondwires are connected to tiers in groups of three.
  • Chip pads transmitting or receiving "SI” 452, “SIBAR” 454, and power 456 are electrically connected to the first tier 414 substrate bond pads 482, 484, and 486, respectively.
  • Chip pads transmitting or receiving "S2" 458, “S2BAR” 460, and ground 462 are electrically connected to the second tier substrate bond pads 488, 490, 492, respectively.
  • the signal eye A graph showing the maximum and minimum levels of the signal is known as the "signal eye;" it is beneficial to have as large a signal eye as possible. Therefore, by decreasing the length of the bondwires, the inductance through the bondwires decrease, the rise and fall time of the signal decreases, and the signal eye is larger. Thus, the signal quality is improved. For example, for a 3 Gb/s crosspoint switch, a signal with a rise/fall time of greater than 50 picoseconds will see a degradation of about 11 picoseconds if the bondwire inductance is about 1.5 nH .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne une puce comprenant plusieurs plots et un substrat comprenant un premier niveau et un second niveau. Le premier niveau et le second niveau du substrat comportent plusieurs plots de connexion. Au moins deux des plots de la puce sont connectés à au moins deux des plots de connexion du premier niveau. Au moins deux des plots de la puce sont, en outre, connectés à au moins deux des plots de connexion du second niveau.
PCT/US2001/029643 2000-09-27 2001-09-20 Boitiers de puces a liaison par fils a faible induction WO2002027792A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001292949A AU2001292949A1 (en) 2000-09-27 2001-09-20 Low inductive wire bond chip packaging

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67222200A 2000-09-27 2000-09-27
US09/672,222 2000-09-27

Publications (2)

Publication Number Publication Date
WO2002027792A2 true WO2002027792A2 (fr) 2002-04-04
WO2002027792A3 WO2002027792A3 (fr) 2002-05-30

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5787575A (en) * 1996-09-09 1998-08-04 Intel Corporation Method for plating a bond finger of an intergrated circuit package
EP0959648A1 (fr) * 1997-01-30 1999-11-24 Ibiden Co., Ltd. Carte imprimee et son procede de production

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027191A (en) * 1989-05-11 1991-06-25 Westinghouse Electric Corp. Cavity-down chip carrier with pad grid array
US5701233A (en) * 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US5787575A (en) * 1996-09-09 1998-08-04 Intel Corporation Method for plating a bond finger of an intergrated circuit package
EP0959648A1 (fr) * 1997-01-30 1999-11-24 Ibiden Co., Ltd. Carte imprimee et son procede de production

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AU2001292949A1 (en) 2002-04-08

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