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WO2002012995A3 - A parallel counter and a logic circuit for performing multiplication - Google Patents

A parallel counter and a logic circuit for performing multiplication Download PDF

Info

Publication number
WO2002012995A3
WO2002012995A3 PCT/GB2001/003415 GB0103415W WO0212995A3 WO 2002012995 A3 WO2002012995 A3 WO 2002012995A3 GB 0103415 W GB0103415 W GB 0103415W WO 0212995 A3 WO0212995 A3 WO 0212995A3
Authority
WO
WIPO (PCT)
Prior art keywords
parallel counter
logic circuit
performing multiplication
bit
binary number
Prior art date
Application number
PCT/GB2001/003415
Other languages
French (fr)
Other versions
WO2002012995A2 (en
Inventor
Peter Meulemans
Dmitriy Rumynin
Sunil Talwar
Original Assignee
Automatic Parallel Designs Ltd
Peter Meulemans
Dmitriy Rumynin
Sunil Talwar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0019287A external-priority patent/GB2365636B/en
Application filed by Automatic Parallel Designs Ltd, Peter Meulemans, Dmitriy Rumynin, Sunil Talwar filed Critical Automatic Parallel Designs Ltd
Priority to EP01984499A priority Critical patent/EP1307812A2/en
Priority to JP2002517614A priority patent/JP2004506260A/en
Priority to KR10-2003-7001637A priority patent/KR20030045021A/en
Priority to AU2002229155A priority patent/AU2002229155A1/en
Publication of WO2002012995A2 publication Critical patent/WO2002012995A2/en
Publication of WO2002012995A3 publication Critical patent/WO2002012995A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)

Abstract

A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.
PCT/GB2001/003415 2000-08-04 2001-07-27 A parallel counter and a logic circuit for performing multiplication WO2002012995A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01984499A EP1307812A2 (en) 2000-08-04 2001-07-27 A parallel counter and a logic circuit for performing multiplication
JP2002517614A JP2004506260A (en) 2000-08-04 2001-07-27 Parallel counters and logic circuits for performing multiplications.
KR10-2003-7001637A KR20030045021A (en) 2000-08-04 2001-07-27 A parallel counter and a logic circuit for performing multiplication
AU2002229155A AU2002229155A1 (en) 2000-08-04 2001-07-27 A parallel counter and a logic circuit for performing multiplication

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0019287.2 2000-08-04
GB0019287A GB2365636B (en) 2000-08-04 2000-08-04 A parallel counter and a multiplication logic circuit
GB0101961.1 2001-01-25
GB0101961A GB2365637B (en) 2000-08-04 2001-01-25 A parallel counter and a multiplication logic circuit

Publications (2)

Publication Number Publication Date
WO2002012995A2 WO2002012995A2 (en) 2002-02-14
WO2002012995A3 true WO2002012995A3 (en) 2003-03-13

Family

ID=26244799

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/003415 WO2002012995A2 (en) 2000-08-04 2001-07-27 A parallel counter and a logic circuit for performing multiplication

Country Status (5)

Country Link
EP (1) EP1307812A2 (en)
JP (1) JP2004506260A (en)
CN (1) CN1468396A (en)
AU (1) AU2002229155A1 (en)
WO (1) WO2002012995A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
WO2003034200A1 (en) * 2000-08-11 2003-04-24 Arithmatica Limited A parallel counter and a logic circuit for performing multiplication
US7136888B2 (en) 2000-08-04 2006-11-14 Arithmatica Limited Parallel counter and a logic circuit for performing multiplication
US6883011B2 (en) 2000-08-04 2005-04-19 Arithmatica Limited Parallel counter and a multiplication logic circuit
GB2373602B (en) 2001-03-22 2004-11-17 Automatic Parallel Designs Ltd A multiplication logic circuit
US7260595B2 (en) 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
GB2398944B (en) 2003-01-14 2005-07-20 Arithmatica Ltd A logic circuit
US7042246B2 (en) 2003-02-11 2006-05-09 Arithmatica Limited Logic circuits for performing threshold functions
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
GB2401962B (en) 2003-05-23 2005-05-18 Arithmatica Ltd A sum bit generation circuit
CN101091157B (en) * 2004-07-12 2010-09-01 哈利尔·基利克 Digital processor and method for processing digital data
CN112068802B (en) * 2020-08-14 2022-11-11 清华大学 Design method, device and counter of counter

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634658A (en) * 1970-03-19 1972-01-11 Sperry Rand Corp Parallel bit counter
US3757098A (en) * 1972-05-12 1973-09-04 Rca Corp Carry generation means for multiple character adder
EP0168650A2 (en) * 1984-07-16 1986-01-22 International Business Machines Corporation Method of designing a logic circuitry
EP0309292A2 (en) * 1987-09-25 1989-03-29 Matsushita Electric Industrial Co., Ltd. Circuit transformation system, circuit transformation method, inverted logic generation method, and logic design system
US5175862A (en) * 1989-12-29 1992-12-29 Supercomputer Systems Limited Partnership Method and apparatus for a special purpose arithmetic boolean unit
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
US6023566A (en) * 1997-04-14 2000-02-08 Cadence Design Systems Cluster matching for circuit implementation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634658A (en) * 1970-03-19 1972-01-11 Sperry Rand Corp Parallel bit counter
US3757098A (en) * 1972-05-12 1973-09-04 Rca Corp Carry generation means for multiple character adder
EP0168650A2 (en) * 1984-07-16 1986-01-22 International Business Machines Corporation Method of designing a logic circuitry
EP0309292A2 (en) * 1987-09-25 1989-03-29 Matsushita Electric Industrial Co., Ltd. Circuit transformation system, circuit transformation method, inverted logic generation method, and logic design system
US5175862A (en) * 1989-12-29 1992-12-29 Supercomputer Systems Limited Partnership Method and apparatus for a special purpose arithmetic boolean unit
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
US6023566A (en) * 1997-04-14 2000-02-08 Cadence Design Systems Cluster matching for circuit implementation

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
CHAKRABORTY S ET AL: "Synthesis of symmetric functions for path-delay fault testability", VLSI DESIGN, 1999. PROCEEDINGS. TWELFTH INTERNATIONAL CONFERENCE ON GOA, INDIA 7-10 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 January 1999 (1999-01-07), pages 512 - 517, XP010320035, ISBN: 0-7695-0013-7 *
DEBNATH D ET AL: "MINIMIZATION OF AND-OR-EXOR THREE-LEVEL NETWORKS WITH AND GATE SHARING", IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E80-D, no. 10, 1 October 1997 (1997-10-01), pages 1001 - 1008, XP000730839, ISSN: 0916-8532 *
DRECHSLER R ET AL: "Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions", EUROPEAN DESIGN AND TEST CONFERENCE, 1995. ED&TC 1995, PROCEEDINGS. PARIS, FRANCE 6-9 MARCH 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 6 March 1995 (1995-03-06), pages 91 - 97, XP010148035, ISBN: 0-8186-7039-8 *
DRECHSLER R ET AL: "Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, JAN. 1997, IEEE, USA, vol. 16, no. 1, pages 1 - 5, XP002217407, ISSN: 0278-0070 *
NIENHAUS H A: "Efficient multiplexer realizations of symmetric functions", IEEE SOUTHEASTCON 1981 CONFERENCE PROCEEDINGS, HUNTSVILLE, AL, USA, 5-8 APRIL 1981, 1981, New York, NY, USA, IEEE, USA, pages 522 - 525, XP010277476 *

Also Published As

Publication number Publication date
AU2002229155A1 (en) 2002-02-18
WO2002012995A2 (en) 2002-02-14
JP2004506260A (en) 2004-02-26
EP1307812A2 (en) 2003-05-07
CN1468396A (en) 2004-01-14

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