WO2002004968A2

WO2002004968A2 - Universal burn-in socket for testing integrated circuit chip

Info

Publication number: WO2002004968A2
Application number: PCT/US2001/020924
Authority: WO
Inventors: Rafiqul Hussain; Phuc Dinh Do; Benjamin G. Tubera
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2000-07-12
Filing date: 2001-06-29
Publication date: 2002-01-17
Also published as: AU2001271717A1; WO2002004968A3

Abstract

An apparatus and method of testing different integrated circuit chip models with different dimensions on the same burn-in socket. The opening of a burn-in socket is modified using different shaped frames that are attachable to and removable from the burn-in socket. The different frames adapt the burn-in socket for the testing of different integrated circuit chip models, with each diffent frame complementing a specific integrated circuit chip model. An attached frame, specific to an integrated circuit model, guides and aligns an integrated circuit chip onto the burn-in socket such that the electrical contacts of the integrated circuit chip connect with a selected subset of the contact pins of the burn-in substrate (12).

Description

UNIVERSAL BURN-IN SOCKET FOR TESTING INTEGRATED CIRCUIT CHIPS

TECHNICAL FIELD

The present invention relates to the field of integrated circuit chip testing, and more particularly, to an apparatus and method of testing different integrated circuit chips of different dimensions on the same burn-in socket.

BACKGROUND ART

Burn-in sockets are well known in the integrated circuit chip manufacturing industry as the hardware needed to test the integrity of integrated circuit chips in the quality control phase of the manufacturing process. An integrated circuit chip is typically placed in a burn-in socket and electrically communicates with a test control system to test the chip's computational integrity. One important quality standard that integrated circuit chip manufacturers test is the computational performance of integrated circuit chips at high temperatures. This high temperature test is important because integrated circuit chips are required to perform with computational integrity in environments of high temperature. The temperature of an integrated circuit chip affects computational performance of the chip, which necessitates verification by a chip manufacturer of the computational integrity of the chips at high temperatures.

This high temperature computational performance test is begun by placing the integrated circuit chip to be tested on a burn-in socket. The integrated circuit chip electrically communicates with the test control system. A thermal head is lowered onto the integrated circuit chip. Heat from the thermal head is conducted into the integrated circuit chip raising the temperature of the chip. Once the integrated circuit chip has been raised to a predetermined temperature, the computational performance of the chip is tested by the test control system.

Integrated circuit chip manufacturers typically manufacture large quantities of chips. Additionally, integrated circuit chip manufacturers typically produce several different models of integrated circuit chips. These chips are produced in high quantity to reduce the average cost of manufacturing each integrated circuit chip. One challenge manufacturers encounter is controlling the integrity of each chip that are sold to consumers. The manufacturers use burn-in sockets, like the one described above, to determine the computational integrity of the chips.

Conventional burn-in sockets are designed around the parameters of a particular chip. These conventional burn-in sockets accommodate the particular shape of a particular integrated circuit chip model. The conventional burn-in socket also provides a medium for the test control system to communicate with the integrated circuit chip through the connection of the electrical contacts of the integrated circuit chip with the contact pins of the burn-in substrate. The test control system communicates with the integrated circuit chip by instructing the chip to perform computations with known outputs. The integrated circuit chip is determined to be a quality chip if the known computational outputs are correctiy computed from the test control system instructions. A conventional burn-in socket for testing one particular model of integrated circuit chip is useless for testing a different model chip because of the shape of the burn-in socket, the alignment of the contact pins, and the communication protocol between the test control system and the integrated circuit chip. When a manufacturer stops manufacturing a particular integrated circuit chip model, the burn-in socket associated with that chip model is obsolete. It is expensive to redesign and implement a completely new burn- in socket every time the design of chips change. Costs associated with complete replacement of a burn-in socket may deter a manufacturer from introducing a new superior integrated circuit chip model to consumers.

For example, an integrated chip manufacturer may mass produce several models of integrated circuit chips. For each of these models there is at least one manufacturing line where semiconductor substrates are processed and packaged into integrated circuit chips. Particular to each manufactured integrated circuit chip model is at least one quality control station where integrated circuit chips are tested. At the quality control station, the computational integrity of integrated circuit chips are measured at high temperatures. The hardware at a particular quality control station that corresponds with a particular integrated circuit chip model is tailored to that chip model. Different chip models cannot be tested at the same quality control station. The differences in size, shape, pin locations, communication protocol, and computational performance between different integrated circuit chip models make conventional burn-in sockets exclusive to a single integrated circuit chip model.

There are several disadvantages to the conventional method of testing integrated circuit chips at high temperatures, as described above. Conventional burn-in sockets for testing a particular integrated circuit chip model are not adaptable to other integrated circuit chip models. The conventional burn-in socket does not have the versatility of readily accommodating the testing of different integrated circuit chip models when there is a sudden need for a manufacturer to change the quantities or models of chips they produce. The lack of adaptability and the lack of versatility of the conventional burn-in socket have the disadvantages of long lead times and high costs associated with changing quantities or models of chips produced by manufacturers. Due to this lack of adaptability and versatility, chip manufacturers implement relatively low quality burn-in sockets when implementing a test control system due to the limited time that a particular chip model is manufactured and the corresponding burn-in sockets are useful.

DISCLOSURE OF THE INVENTION

There is a need for a burn-in socket capable of readily accommodating different integrated circuit chip models to minimize lead times and costs to manufacturers that result from changes in models and quantities of integrated circuit chips manufactured.

These and other needs are met by the embodiments of the present invention which provide an integrated circuit chip testing system. The burn-in socket of the present invention utilizes different frames that are attachable to a burn-in socket for adapting the burn-in socket to different integrated circuit chip models. Each different frame corresponds to a specific integrated circuit chip model. When a change from the testing of one integrated circuit chip model to another integrated circuit chip model is required, a first frame is removed from the burn-in socket corresponding to a first integrated circuit chip model and replaced by attaching a second frame that corresponds to a second integrated circuit chip model. When a second integrated circuit chip model is tested, it is placed on the burn-in socket with the second frame attached to the burn-in socket. The present invention enables the electrical contacts of the chip and the contact pins of the burn-in substrate to align such that the test control system communicates with the chip to test its computational performance. A thermal head is then lowered onto the chip and heat is conducted from the thermal head into the chip, while the computational integrity of the chip is tested.

The present invention has the advantage of being adaptable for accommodating different integrated circuit chip models without the disadvantage of having to completely replace a burn-in socket when a change in quantities or models of chips production is required. The adaptability of the present invention reduces the overall cost of such a change.

Another advantage of the present invention is that the manufacturer can afford a high quality burn-in socket for the quality control station which reduces costs in the long run. The bum-in sockets of the present invention have a relatively long life, as it is not limited to the time that a particular chip model is produced. Manufacturers can therefore afford higher quality bum-in sockets with superior test quality and lower maintenance costs; this minimizes manufacturing costs in the long run and positively affects the profits of a manufacturer. The lower costs also benefit consumers as they will receive a superior product at a lower price. Additionally, the reduction of lead time is a significant advantage to manufacturers in the fast paced integrated circuit chip industry because the quicker and more efficiently a manufacturer can implement changes in quantities or models of chips produced, the higher profits a manufacturer can earn.

The present invention provides the versatility for a manufacturer to readily change quantities or models of chips produced. A shift in demand for the quantities or models of chips is common in the integrated circuit chip market due to the fast pace of innovation and short life time of many integrated circuit chip models before they are obsolete.

The lowered costs and the shortened lead time facilitated by the present invention enable a manufacturer to adapt to the changing market demand for integrated circuit chips, increasing profits and benefiting chip consumers.

The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A is a top view of the bum-in socket with a first frame attached to the bum-in socket.

Figure IB is a top view of the bum-in socket with a second frame attached to the burn-in socket.

Figure 2A is a cross-sectional side view of the burn-in socket with a first integrated circuit chip resting on top of the first frame and the burn-in substrate.

Figure 2B is a cross-sectional side view of the burn-in socket with a second integrated circuit chip resting on top of the second frame and the burn-in substrate.

Figure 3 A is a top view of the first frame.

Figure 3B is a top view of the second frame.

Figure 4A is a bottom view of the first integrated circuit chip.

Figure 4B is a bottom view of the second integrated circuit chip.

Figure 5 is a cross-sectional view of the burn-in substrate. MODES FOR CARRYING OUT THE INVENTION

The present invention relates to an integrated circuit chip testing system utilizing a burn-in socket with attachable and removable frames. The present invention has the capability of adapting to the testing of different integrated circuit chips by changing the frame attached to a bum-in substrate. The particular frame attached to the bum-in substrate is designed for the testing of a particular model of integrated circuit chip. The particular frame has a shape that complements the shape of the particular integrated circuit chip model that is to be tested. A chip of a particular model rests on the burn-in substrate and a frame corresponding to that particular chip model. The electrical contacts of the chip are aligned with the contact pins of the burn-in substrate with the aid of the frame. The different integrated circuit chip models that are tested on the burn-in socket have electrical contacts of the same size and pitch. Additionally, the pitch of the contact pins of the burn-in substrate is the same as the pitch of the electrical contacts of the chips. The burn-in substrate has a matrix of contact pins in the maximum possible dimensions to accommodate many different integrated circuit chip models. In order to adapt the burn-in socket to a particular chip model, a frame is attached to the burn-in substrate to cover contact pins that are not necessary for the electrical contacts of a particular chip to connect with. Additionally, because the frame is shaped to accommodate a particular chip model, when a chip of that model rests on the substrate and the corresponding shaped frame, the frame guides the electrical contacts of the chip onto the appropriate contact pins of the burn-in substrate.

For example, a bum-in socket of the present invention is configured to test a first integrated circuit chip model and can be adapted to test a second integrated circuit chip model which has different dimensions. A first frame that was used for testing the first integrated circuit chip model is removed and a second frame that will be used for testing the second integrated circuit chip model is attached. The second frame guides and aligns a chip of a second chip model onto the bum-in substrate, aligning the appropriate contact pins of the burn-in substrate with the electrical contacts of the chip. The removable and attachable frames adapt a bum-in socket to accommodate the different dimensions and other attributes of a plurality of different integrated circuit chip models.

Figure 1 A is a top view of a sixteen pin burn-in socket 10 with a first frame 14 attached to the burn-in substrate 12 exposing sixteen contact pins 16. The first frame 14 is attachable to and removable from the bum-in substrate 12. The burn-in substrate 12 comprises sixteen contact pins 16 formed in a 4x4 matrix. The first frame 14 has an opening such that the 4x4 matrix of contact pins 16 are exposed. The number of contact pins 16 is exemplary only, however, as other embodiments of the invention provide different numbers of pins.

Figure IB is a top view of a four pin burn-in socket 20 with a second frame 18 attached to the burn-in substrate 12 exposing four of the contact pins 16. Since only four of the sixteen contact pins 16 are exposed, twelve of the sixteen contact pins 16 are covered by the second frame 18.

Figure 2A is a side cross-sectional view of the sixteen pin burn-in socket 10 with a sixteen electrical contact integrated circuit chip 24 resting on the bum-in substrate 12 and the first frame 14. The first frame 14 complements the sixteen electrical contact integrated circuit chip 24 in shape and aligns the electrical contacts 26 of the integrated circuit chip 24 with the contact pins 22 of the burn-in substrate 12. The sloped sides 36 of the first frame 14 serve to align the electrical contacts 26 with the contact pins 22. The contact pins 22 and the electrical contacts 26 must be distributed in the same matrix formation with the same pitch in order to align (i.e., mirror images of each other).

Figure 2B is a side cross-sectional view of the four pin burn-in socket 20 with a four electrical contact integrated circuit chip 32 resting on the burn-in substrate 12 and second frame 18. This figure depicts the contact pins 28 exposed through the opening of the second frame 18 attached to the burn-in substrate 12. Figure 2B also shows contact pins 30 covered by the second frame 18. Hence, the second integrated circuit chip 32 has four protruding electrical contacts 34 that are exposed. The second frame 18 complements the shape of the second integrated circuit chip 32. Similar to Figure 2A, the second integrated circuit chip 32 rests on the burn-in substrate 12 with the second frame 18 attached. The second integrated circuit chip's 32 electrical contacts 34 align with the contact pins 28. The burn-in substrate 12 of Figure 2B is the same burn-in substrate 12 of Figure 2A, but adapted to accommodate the different size second integrated circuit chip 32 by replacement of the first frame 14 of Figure 2A with the attachment of the second frame 18 of Figure 2B. Contact pins 30 are covered by the second frame 18 and are prevented from contacting with the electrical contacts 34 of the second integrated circuit chip 32.

Figure 3A is a top view of the first frame 14. The first frame 14 comprises sloped sidewalls 36 and an opening in the center 38. The opening 38 is the appropriate size to expose the sixteen contact pins 22 of Figure 2A to accommodate the sixteen electrical contacts 26 of the first integrated circuit chip 24 of Figure 2A.

Figure 3B is a top view of the second frame 18. The second frame 18 comprises sloped sides 42 and an opening in the center 40. The opening 40 is the appropriate size to expose the four contact pins 34 of Figure 2B to accommodate the four electrical contacts 34 of the second integrated circuit chip 32 of Figure 2B.

There are some differences between the first frame 14 of Figure 3 A and the second frame 18 of Figure 3B. Although the outer perimeter of the first frame 14 and the second frame 18 are the same size and shape, the first frame 14 has a larger opening than the second frame 18. The opening is larger because the first frame 14 exposes sixteen contact pins 22 of the bum-in substrate of Figure 2A while the second frame 18 exposes only four contact pins 28 of Figure 2B. Additionally, the sloped sides 36 of Figure 3A are steeper than the sloped sides 42 of Figure 3B to accommodate the guiding of the different shaped integrated circuit chips 24, 32 onto the bum-in substrate 12 of Figures 2 A and 2B.

The shape, configuration, and size of the frames 14 and 18 depicted in the Figures are exemplary only, as other shapes, configurations, and sizes are employed in other embodiments, in accordance with the configurations of the integrated circuit chips to be tested.

Figure 4A is a bottom view of the first integrated circuit chip package 44. The first integrated circuit chip package 44 comprises a substrate 24 and sixteen contact pins 26. As exemplified in this figure, the sixteen contact pins 26 are arranged in a 4x4 matrix. The first integrated circuit chip package 44 is representative of a particular integrated circuit chip model having a set shape and standard locations of electrical contacts 26.

Figure 4B is a bottom view of the second integrated circuit chip package 46. The second integrated circuit chip package 46 comprises a substrate 32 and four electrical contacts 34. As exemplified in this figure, the four electrical contacts 34 form a 2x2 matrix. The pitch of the electrical contacts 34 of the second integrated circuit chip package 46 is the same as the pitch of the electrical contacts 26 on the first integrated circuit chip package 44 of Figure 4A. The second integrated circuit chip package 46 is representative of a particular integrated circuit chip model having set dimensions and locations of the electrical contacts 34.

Figure 5 is a side cross-sectional view of the burn-in substrate 12. The burn-in substrate 12 comprises sixteen contact pins 16. The same burn-in substrate 12 is used for testing both the first integrated circuit chip package 44 and the second integrated circuit chip package 46 when the first or second frames 14, 18 are attached to the bum-in substrate. The configuration of the bum-in substrate 12 is exemplary only as changes in the number or arrangement of contact pins 16 may be made without departing from the invention.

The present invention offers adaptability and versatility that cannot be accomplished by conventional burn-in sockets. This adaptability and versatility feature is accomplished by the burn-in socket comprising a burn-in substrate and a plurality of frames that are attachable and removable to the burn-in substrate. Each particular frame corresponds to a particular integrated circuit chip model. Changes in quantities or models manufactured can be readily accommodated by simply changing the frame and reconfiguring the test control software.

Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. An integrated circuit chip testing system comprising: a burn-in substrate (12) with a top surface having a plurality of contact pins protruding therefrom; a first frame (14) attachable to and removable from the burn-in substrate (12) having a first frame (14) opening configured to expose a first subset of contact pins when attached to the burn-in substrate (12); and a second frame (18) attachable to and removable from the burn-in substrate (12) having a second frame (18) opening configured to expose a second subset of contact pins when attached to the bum-in substrate (12), the second subset of contact pins being different than the first subset of contact pins.

2. The integrated circuit chip testing system of claim 1, wherein: at least one contact pins protrudes either through the first frame (14) opening or through the second frame (18) opening, respectively, when the first frame (14) or second frame (18) is attached to the burn-in substrate (12).

3. The integrated circuit chip testing system of claim 2 wherein: the plurality of contact pins is a matrix of contact pins.

4. The integrated circuit chip testing system of claim 3 further comprising a first integrated circuit chip and a second integrated circuit chip, wherein: both the first integrated circuit chip and the second integrated circuit chip have at least one electrical contact protruding therefrom; the at least one electrical contact is formed in a matrix of electrical contacts, wherein the first subset of contact pins and the second subset of contact pins form matrices of different dimensions; and the pitch of the matrices of electrical contacts for both the first integrated circuit chip and second integrated circuit chip are the same as the pitch of the matrix of contact pins of the burn-in substrate (12).

5. The integrated circuit chip testing system of claim 4 wherein: the first frame (14) or the second frame (18) is attached to the substrate (12); the first or the second integrated circuit chip rests on the substrate (12) and the first frame (14) or second frame (18); and each electrical contact of the first integrated circuit chip or the second integrated circuit chip touches a contact pin on the burn-in substrate (12) when resting on the bum-in substrate (12)

6. A method of testing an integrated circuit chip, comprising the steps of: attaching a first frame (14) having a first frame (14) opening to a bum-in substrate (12) to expose a first portion of the burn-in substrate (12); positioning a first integrated circuit chip on the burn-in substrate (12) inside the first frame (14), wherein the shape of the first integrated circuit chip complements the shape of the first frame (14) opening; testing the first integrated circuit chip; removing the first integrated circuit chip from the burn-in substrate (12); removing the first frame (14) from the burn-in substrate (12); attaching a second frame (18) having a second frame (18) opening to the burn-in substrate (12) to expose a second portion of the burn-in substrate (12), wherein the first portion is different than the second portion; positioning a second integrated circuit chip on the burn-in substrate (12) inside the second frame (18), wherein the shape of the second integrated circuit chip complements the shape of the second frame (18) opening and the second integrated circuit chip is a different shape than the first integrated circuit chip; and testing the second integrated circuit chip.

7. The method of claim 6, wherein: the burn-in substrate (12) comprises a plurality of contact pins wherein the contact pins protrude from the substrate (12) and at least some of the plurality of contact pins protrude through the first frame (14) or second frame (18) when either frame is attached to the burn-in substrate (12); and the first integrated circuit chip and the second integrated circuit chip each comprise a plurality of electrical contacts, wherein the electrical contacts are aligned to at least some of the plurality of contact pins on the bum-in substrate (12) when the first integrated circuit chip rests on the burn-in substrate (12) through the first frame (14) or the second integrated circuit chip rests on the burn-in substrate (12) through the second frame (18).

8. The method of claim 7, wherein: the plurality of contact pins on the burn-in substrate (12) forms a matrix of contact pins; and the plurality of electrical contacts on the first integrated circuit chip and the second integrated circuit chip form matrices of electrical contacts.

9. The method of claim 7, wherein: the first frame (14) opening exposes a first subset of contact pins when the first frame (14) is attached to the burn-in substrate (12); and the second frame (18) opening exposes a second subset of contacts pins when the second frame (18) is attached to the burn-in substrate (12).

10. The method of claim 9, wherein: the dimensions of the matrix of electrical contacts of the first integrated circuit chip is different than the dimensions of the matrix of electrical contacts of the second integrated circuit chip; the dimensions of the matrix of electrical contacts of the first integrated circuit chip is the same as the dimensions of the first subset of contacts pins exposed through the first frame (14) when attached to the burn- in substrate (12); and the dimensions of the matrix of electrical contracts of the second integrated circuit chip is the same as the dimensions of the second subset of contact pins exposed through the second frame (18) when attached to the burn-in substrate (12).