WO2002089491A1

WO2002089491A1 - Image processing device and image processing method

Info

Publication number: WO2002089491A1
Application number: PCT/JP2002/004074
Authority: WO
Inventors: Haruo Togashi
Original assignee: Sony Corporation
Priority date: 2001-04-25
Filing date: 2002-04-24
Publication date: 2002-11-07
Also published as: JP2005051276A

Abstract

Inversion of the DCT mode for the same block is prevented, and the degradation of the quality of image is reduced. A frame DCT unit carries out frame-DCT of a block of an image signal. A field DCT unit carries out field-DCT of the block of the image signal. An encoding determining unit gives a weight to at least either block frame correlation information or block field correlation information so that the result of determination of the same block may be the same and adaptively determines which encoding of the frame DCT and field DCT is to be done.

Description

Specification

Image processing apparatus and image processing method

The present invention relates to an image processing device and an image processing method, and more particularly to an image processing device and an image processing method for performing image compression processing. Background art

Digital video coding systems have been internationally standardized by MPEG (Moving Pictures Experts Group) of IS0 / IEC and H.262 of ITU_T, and with the development of multimedia communications in recent years, Further higher quality is required.

In image coding, DCT (Discrete Cosine Transform), which converts a digital image into frequency components and compresses the image, is widely used. The pixel configuration of one screen has a field structure that is independent of the first field and the second field, and a frame structure that combines the two fields. Field DCT, frame D

Called CT.

Switching between the frame DCT mode and the field DCT mode is determined based on a picture in macroblock units. As a conventional DCT mode determination method, first, the correlation between each pixel in a field and the correlation between each pixel in a frame are calculated. Then, these are simply compared, and if the field correlation is stronger than the frame correlation, the field DCT is selected. If the frame correlation is stronger than the field correlation, the frame DCT is selected. However, with the conventional DCT mode determination technology as described above, when dubbing the VTR or cascading the encoder and decoder, it differs from the previous DCT mode due to distortion during encoding. There was a problem that the DCT mode might be determined and image quality deteriorated.

Considering a VTR (Video Tape Recorder), for the first encoding / decoding, for example, a macroblock that had been coded by performing frame DCT, was repeatedly dubbed, but was subject to distortion due to encoding / decoding. May be added, and the mode may be switched to the field DCT mode.

In other words, if the same macroblock is coded in the frame DCT the previous time and then coded in the field DCT, the image quality will deteriorate if the DCT mode is reversed. Will be. Disclosure of the invention

The present invention has been made in view of such a point, and an object of the present invention is to provide an image processing apparatus and an image processing method that prevent inversion of the DCT mode for the same block and reduce image quality deterioration. . -In order to solve the above-described problem, the present invention detects, in an image processing apparatus that compresses and codes an image signal, correlation information in which one of a frame correlation and a field correlation is weighted for a block of the image signal. An image comprising: correlation information detecting means; and coding means for performing intra-frame coding or intra-field coding on a block of an image signal according to the correlation information detected by the correlation information detecting means. It is a processing device. The present invention also provides an image processing method for compressing and encoding an image signal, comprising: a step of detecting correlation information in which one of a frame correlation and a field correlation is weighted with respect to a block of the image signal; An encoding step of performing intra-frame encoding or intra-field encoding on a block of the image signal in accordance with the correlation information detected in the detecting step.

As described above, the present invention detects correlation information in which one of the frame correlation and the field correlation is weighted for a block of an image signal, and detects the correlation information according to the detected correlation information. Intra-frame coding or intra-field coding is performed, so that even if the frame correlation and the field correlation of the image signal are close to each other, the intra-frame coding or the intra-field coding for the block is performed. Can be performed adaptively. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a principle diagram of the image processing apparatus of the present invention, FIG. 2 is a diagram showing a macro block, FIG. 3 is a diagram for explaining frame correlation information Var1, and FIG. FIG. 5 is a diagram for explaining the field correlation information Var 2, FIG. 5 is a diagram showing a determination formula in a graph, FIG. 6 is a diagram showing a flowchart of an image processing method of the present invention, FIG. Figures A and 7B show the structure of a digital VTR, Figure 8 shows the structure of an MPEG encoder, Figure 9 shows an overview of packing, and Figure 10 shows the structure of packing. It is a figure showing an outline. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a principle diagram of the image processing apparatus of the present invention. The image processing apparatus 10 performs image compression processing using orthogonal transform coding on the input image.

As the orthogonal transform coding, for example, DCT (Discrete Cosine Transform) can be applied. Hereinafter, the orthogonal transform coding will be described assuming that it is DCT.

The frame DCT unit 11 performs frame DCT on the block of the image signal based on the determination result of the coding determination unit 13. Field DCT section 12 performs field DCT on the block of the image signal based on the determination result of coding determination section 13.

The coding determination unit 13 weights at least one of the frame correlation information indicating the frame correlation of the block or the field correlation information indicating the field correlation so that the determination result is constant for the same block. Then, whether to perform frame DCT or field DCT coding is adaptively determined and controlled.

Here, it is assumed that the frame DCT is selected in the first encoding for the block bL of the image G. When dubbing or encoding / decoding of this image G is repeated N times, the field DCT is selected for the block b L of the image G a which is conventionally encoded N times due to the distortion due to dubbing and the like. Could be If the DCT mode is inverted and different coding is performed on the same block bL, the image quality of the image Ga is degraded.

On the other hand, in this embodiment, once the frame DCT is performed on the block bL of the image G, the image G is thereafter dubbed N times, and the image Gb to which distortion due to dubbing is added is also performed. The encoding determination unit 13 always outputs the block bL without inverting the DCT mode. The first executed frame DCT is selected. As a result, it is possible to suppress the occurrence of image quality degradation of the image Gb.

Next, a specific operation of the encoding determination unit 13 of this embodiment will be described in detail. For the coding determination unit 13, the adaptive switching between the frame DCT and the field DCT for a block (macroblock) is performed by using a vertically adjacent pixel considered to be highly correlated with the vertical component of the DCT coefficient. Calculates the sum of squares of the difference between blocks in the frame and field, and weights the calculated value to determine whether to execute the DCT mode of frame DCT or field DCT. Decide adaptively.

The calculation formulas are the following formulas (1) and (2). Varl in equation (1) indicates the sum of squares of the difference values between vertically adjacent pixels in the frame, and Var2 in equation (2) indicates the sum of squares between vertically adjacent pixels in the field. The sum of squares of the difference values is shown. V a r1 is the frame correlation information in this embodiment, and V a r 2 is the field correlation information.

Varl = ∑ _{(u = 0} , ₁₅₎ ∑ _{(v = 0} , ₆₎ ((X [2v] [u] -X [2vll] [u]) ² + ([2v + l] [u] -X [ 2v + 2] [u]) ² } · · · (1)

Var2 = ∑ _{(u = 0} , ₁₅ ) ∑ (v = o, 6) {(X [2] [u] -X [2v + 2] [u]) ² + (X [2vH] [u] -X [2v + 3] [u]) ² } · · · (2)

Here, u means the horizontal direction, v means the vertical direction, and X [a] [b] indicates the value of the pixel located at the vertical coordinate value a, the horizontal coordinate value = b. I have. The values of the correlation information V ar 1 and V ar 2 are small when the correlation is strong, and large when the correlation is weak.

Next, the contents shown by equations (1) and (2) will be described with reference to the drawings. FIG. 2 is a diagram showing a macroblock. One macroblock is 1 It consists of 6 lines x 16 pixels. Then, u is set in the horizontal direction and V is set in the vertical direction, and the pixel values of the coordinates in the macroblock are represented by X [a] [b]. So, for example, the top left pixel value of the macroblock is X [0] [0], the top right pixel value is X [0] [15], and the bottom left pixel value is X [15] [0], right The pixel value at the bottom can be expressed as X [15] [15].

FIG. 3 is a diagram for explaining the frame correlation information V a r1. For equation (1), if u = 0 and v = 0, then X [2v] [u] = X [0] [0], [2v + 1] [u] = X [l] CO ], X [2v + 2] [u] = X [2] [0]. Therefore, when u = 0 and v = 0, Var 1 is the pixel value X [0] [0] of the first line of the top field and the pixel value X [l] [0] of the first line of the bottom field. And the square of the difference h2 between the pixel value X [l] [0] of the first line in the bottom field and the pixel value X [2] [0] of the second line in the top field And the sum of Thereafter, calculation is performed in the same manner (obtained in the range of u = 0 to 15 and v = 0 to 6).

FIG. 4 is a diagram for explaining the field correlation information V ar 2. For equation (2), if u = 0 and v = 0, X [2v] [u] = X [0] [0], X [2v + 2] [u] -X [2] [0], X [2v + 1] [u] = X [l] [0] X [2v + 3] [u] = X [3] [0]. Therefore, Var 2 when u = 0 and v = 0 is the pixel value X [0] [0] on the first line of the top field and the pixel value X [2] [0] on the second line of the top field. 0] and the square of the difference value H2 between the pixel value X [l] [0] of the first line of the bottom field and the pixel of the second line of the bottom field ΙίΧ [3] [0] Is the sum of Thereafter, the calculation is performed in the same way (calculated in the range of lι = 0 to 15, v = 0 to 6).

Then, the DCT mode is determined by weighting Var 1 and Var 2 calculated in this way. The weighted judgment formula is the following formula (3). Note that a, b, c, and d are constants. a XV ar 1 + b> c XV ar 2 + d (3)

Here, if Equation (3) is satisfied, the macroblock to be encoded is recognized as a macroblock with strong field correlation and strong motion, and the field DCT is selected. If Equation (3) is not satisfied, the macroblock to be encoded is recognized as a macroblock with strong frame correlation and little movement, and the frame DCT is selected.

As described above, in this embodiment, the DCT mode is determined by comparing the weighted mutual correlation information, instead of simply comparing the correlation for the frame and the field. Note that the values of the constants a, b, c, and d in Equation (3) may be fixedly determined or may be variably set according to the input image.

FIG. 5 is a diagram in a case where a determination formula is shown in a graph. The vertical axis shows Var 1 and the horizontal axis shows Var 2. When V arl = AXV ar 2 + B is used as the determination formula in this embodiment, the result is shown in the figure. Here, A = cZa and B = (d-b) Za. Also, A> 1 and B> 0. From the figure, go to the point above V arl = V ar 2 (V ar l> V a r 2) with V ar 1 = V ar 2 as the boundary There are blocks that move more rapidly, and blocks that move further down (Var 1 and Var 2). In general, many blocks of the image signal are distributed in the vicinity of V arl = V ar 2 (referred to as a block group B, where V arl = V ar 2 is determined in the DCT mode determination). When the DCT mode is determined based on V ar 1 = V ar 2, it can be used for dubbing, cascade connection between encoder and decoder, etc. Therefore, there is a high possibility that the DCT mode is inverted for the same block and the image quality is degraded.

For example, frame DCT is selected in the first encoding for block bL 1 that was initially positioned in a direction that satisfies Var 1 <V ar 2 for Var 1 = V ar 2 Will be. However, when dubbing is repeated several times, the distortion of dubbing causes the position of the block b L1 to be in the direction of Var1> Var2 with respect to Var1 = Var2. May be lost.

Then, a DCT mode inversion occurs, and a field DCT different from the coding initially applied to the same block is selected at this time. As described above, when the determination is made based on V a r 1 = V a r 2, the inversion of the DCT mode is likely to occur with respect to the power scale connection between the dubbing encoder and the decoder.

On the other hand, in the decision formula of this embodiment set at the position as shown in the figure, the block group BL near V ar 1 = V ar 2 satisfies V ar 1 <AXV ar 2 + B for the decision formula. A block that exists in a direction that satisfies the condition and has a remarkable motion is positioned in a direction that satisfies Var1> AXVar2 + B with respect to the determination formula.

Therefore, a field DCT is selected for a block having a remarkable motion, and a frame DCT is set for a block existing in a direction satisfying V ar 1 <AX V ar 2 + B with respect to the determination formula of this embodiment. Will be selected. As described above, in this embodiment, a dubbing or encoder is used in order to determine the DCT mode by providing a boundary (V ar 1 = AX Var 2 + B) in a place where blocks are not densely packed. Even if coding distortion is added in the cascade connection between the block and the decoder, the possibility that the block jumps over the boundary line is reduced. This allows the same block Inverting the DCT mode can be prevented, and image quality degradation can be reduced.

Here, the block near V a r 1 = V a r 2 may be regarded as a block having almost no motion. Therefore, rather than determining a block group BL composed of blocks having almost no motion by V ar 1 = V ar 2 and determining the field DCT / frame DCT for the blocks in the block group BL, As in the embodiment, it is better to provide a boundary line (the decision formula of this embodiment) in which the block group BL is a group of blocks that do not move and select the frame DCT for the block group BL. It is possible to reduce the frequency of image quality degradation for connection.

Note that the block group BL is obtained experimentally.

Next, an image processing method according to this embodiment will be described with reference to a flowchart. FIG. 6 is a diagram showing a flowchart of the image processing method of this embodiment.

[S1] At least one of the frame correlation information V arl and the field correlation information V a2 of the block is weighted so that the determination result is constant for the same block of the image signal.

[S2] Based on the decision formula of the above-mentioned formula (3), the decision control is adaptively performed as to which of the frame DCT and the field DCT is to be coded. If equation (3) is satisfied, go to step S3; otherwise, go to step S4.

[S3] The field DCT is encoded for the block.

CS 4] Encode framed DCT for the block. In the above description, the judgment formula V arl = AXV ar 2 + B is set in a direction that satisfies V ar 1> V ar 2 for the block group BL. Is not limited to this example. That is, assuming that 0 <A <1, and B <0, the determination formula V ar 1 = AX V ar 2 + B is applied to the block group BL as illustrated by the dotted line in FIG. It can also be set to a direction that satisfies Var2.

Here, since the frame DCT has a stronger spatial correlation than the field DCT, the compression efficiency is higher. Therefore, in general, a decision formula with A> 1 and B> 0 shown by a solid line in FIG. 5 can increase the compression efficiency and is more preferable.

7A and 7B show an example of the configuration of a digital VTR 100 to which this embodiment is applied. The digital VTR 100 is capable of directly recording a digital video signal compression-encoded by the MPEG system on a recording medium.

First, the configuration and processing operation of the recording system in the digital VTR 100 will be described. The signals input from the outside to this recording system are two types of serial digital input and output signals, a serial data interface (SDI) signal and a serial data transfer interface (SDTI) signal. Reference signal REF.

SDI is an interface specified by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. The SDTI is an interface for transmitting an MPEG elementary stream (hereinafter referred to as MPEG ES), which is a stream in which a digital video signal is compression-encoded by the MPEG method. The ES is a 4: 2: 2 © component, and, as described above, is a stream of all I pictures, and has a relationship of 1 GOP = 1 picture. SDT I—CP (Content Package) format uses MPEG ES Access unit and is packed into packets in frame units. SDT I-CP uses a sufficient transmission bandwidth (27 MHz or 36 MHz at clock rate, 270 Mbps or 360 Mbps at stream bit rate), and bursts in one frame period. It is possible to send the ES in a way.

The SDI signal transmitted by the SDI is input to the SDI input unit 101. The SDI input section 101 converts the supplied SDI signal from a serial signal to a parallel signal and outputs the signal, extracts the input synchronization signal that is the phase reference of the input included in the SDI signal, and outputs the timing signal. Output to TG102.

Also, the SDI input unit 101 separates a video signal and an audio signal from the converted parallel signal. The separated video input signal and audio input signal are output to the MPEG encoder 103 and the delay circuit 104, respectively.

The timing generator TG102 extracts a reference synchronization signal from the input external reference signal REF. The timing generator TG synchronizes the reference synchronizing signal and the input synchronizing signal supplied from the SDI input section 101 with a predetermined designated reference signal, and generates a signal necessary for this digital VTR 100. Generates a timing signal and supplies it to each block as a timing pulse.

The MPEG encoder 103 is a component including the functions of the image processing device 10 or the image processing method according to the present embodiment. The MPEG encoder 103 converts the input image signal, that is, the video input signal, into coefficient data by DCT conversion, quantizes the coefficient data, and then performs variable length coding. The variable length coded (VLC) data output from the MPEG encoder 103 is an elementary stream conforming to MPEG2. (ES). This output is supplied to one input terminal of a recording-side multi-format comparator (hereinafter, referred to as recording-side MFC) 106.

The delay circuit 104 functions as a delay line for adjusting the input audio input signal to the processing delay of the video signal in the MPEG encoder 103 without any compression. It is. The audio signal delayed by the delay circuit 104 is output to the ECC encoder 107. This is because the audio signal appears as an uncompressed signal in the digital VTR 100 according to this embodiment.

The SDTI signal transmitted and supplied from the outside by the SDTI is input to the SDTI input section 105. The SDT I signal is synchronously detected by the input section 105 of the 30-piece. Then, it is temporarily stored in the buffer, and the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the MFC 106 on the recording side. The synchronization signal obtained by the synchronization detection is supplied to the above-described timing generator TG 102 (not shown).

The SDTI receiving section 108 further extracts a digital audio signal from the input SDTI signal. The extracted digital audio signal is supplied to the ECC encoder 107.

Thus, the digital VTR 100 according to the present embodiment can directly input MPEGES independently of the baseband video signal input from the SDI input section 101.

The recording-side MFC circuit 106 has a stream comparator and a selector, and selects one of the MPEGES supplied from the SDI input unit 101 and the SDTI input unit 105. Selected and selected MP EG The DCT coefficients of the ES are grouped for each frequency component through a plurality of DCT blocks constituting one macroblock, and the grouped frequency components are sorted in order from the low frequency component. The stream in which the MPEG ES coefficients are rearranged is hereinafter referred to as a “conversion elementary stream”. By rearranging MPEGES in this way, as many DC coefficients and low-order AC coefficients as possible during search playback are picked up, contributing to the improvement of the quality of search images. The converted elementary stream is supplied to the ECC encoder 107.

The ECC encoder 107 is connected to a large-capacity main memory (not shown), and has a packing and shuffling unit, an outer code encoder for audio, an outer code encoder for video, an inner code encoder, a shuffling unit for audio, and Built-in video shuffling unit. Further, the ECC encoder 109 includes a circuit for adding an ID in sync block units and a circuit for adding a synchronization signal. In the first embodiment, a product code is used as an error correction code for a video signal and an audio signal. The product code encodes the outer code in the vertical direction of a two-dimensional array of video signals or audio signals, encodes the inner code in the horizontal direction, and double encodes the data symbol. is there. As the outer code and the inner code, a Reed-Solomon code can be used.

The conversion element stream output from the MFC circuit 106 is supplied to the ECC encoder 107, and the audio signal output from the SDTI input section 105 and the delay circuit 104 is supplied to the ECC encoder 107. . EC. The encoder 107 performs shuffling and error correction coding on the supplied conversion elementary stream and audio signal, adds an ID and a synchronization signal for each sync block, and records the data. Output as overnight.

The recording data output from the ECC encoder 107 is converted into a recording RF signal by an equalizer EQ 108 including a recording amplifier. The recording RF signal is supplied to a rotating drum 109 provided with a rotating head in a predetermined manner, and is recorded on a magnetic tape 110. The rotating drum 109 is actually provided with a plurality of magnetic heads having different azimuths of heads forming adjacent tracks.

The recording data may be subjected to scramble processing as needed. Further, digital modulation may be performed at the time of recording, and further, a partial response class 4 and Viterbi code may be used. The equalizer 108 includes both a recording-side configuration and a reproduction-side configuration.

Next, the configuration and processing operation of the reproduction system in the digital VTR 100 will be described. At the time of reproduction, a reproduction signal reproduced by the rotating drum 109 from the magnetic tape 110 is supplied to a reproduction-side configuration of an equalizer 108 including a reproduction amplifier and the like. In the equalizer 108, equalization and waveform shaping are performed on the reproduced signal. Also, demodulation of digital modulation, Viterbi decoding, etc. are performed as needed. The output of the equalizer 108 is supplied to the ECC decoder 111.

The ECC decoder 111 performs processing reverse to that of the ECC encoder 107 described above, and includes a large-capacity main memory, an inner code decoder, a deshuffling unit for audio and video, and an outer code decoder. . Further, the ECC decoder 111 includes a deshuffling and depacking unit and a data interpolation unit for video. Similarly, it includes an audio AUX separation unit and a data interpolation unit for audio.

The ECC decoder 1 1 1 performs synchronization detection on the playback data, 'Detect the synchronization signal added to the beginning of the lock. Cut out the lock. The reproduced data is subjected to error correction of the inner code for each sync block, and thereafter, ID interpolation processing is performed on the sync block. The playback data with the interpolated ID is separated into video data and audio 5 data. Video data and audio data are each subjected to deshuffling processing, and the order of the data shuffled during recording is restored. Each of the deshuffled data is subjected to outer code error correction.

In the ECC decoder 111, an error flag is set for data having an error that exceeds the error correction capability and cannot be corrected.

Here, regarding the error in the video data, a signal ERR indicating the data including the error is output.

The error-corrected reproduction audio data is supplied to the SDTI output unit 115, and is also supplied to the SDDI output unit 116 after being given a predetermined delay by the delay circuit 114. The delay circuit 114 will be described later.

It is provided to absorb a delay due to processing of video data in the MPEG decoder 112.

On the other hand, the error-corrected video data is supplied to the playback-side MFC circuit 112 as a playback conversion element stream. The signal 0 ERR described above is also supplied to the reproduction-side MFC circuit 112. Playback side MFC 1 1

Numeral 2 performs a process reverse to that of the recording-side MFC 106 described above, and includes a stream converter. In the stream converter, the reverse process is performed with the stream converter on the recording side. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for every DCT 5 block. As a result, the reproduced signal is converted into an elementary stream compliant with MPEG2. With this, ECC When the signal ERR is supplied from the data 111, the corresponding data is replaced with a signal completely compliant with MPEG2 and output.

The MPEGES output from the reproduction side MFC circuit 112 is supplied to the MPEG decoder 113 and the SDTI output unit 115. The MPEG decoder 113 decodes the supplied MPEGES and restores the original uncompressed video signal. That is, the MPEG decoder 113 performs an inverse quantization process and an inverse DCT process on the supplied MPEGES. The decoded video signal is supplied to the SDI output unit 116. As described above, the 301 output unit 116 is supplied with the audio data separated from the video data by the ECC decoder 111 via the delay 114. In the 301 output unit 116, the supplied video data and audio data are mapped into an SDI format and converted into an SDI signal having an SDI format data structure. This SDI signal is output to the outside.

On the other hand, audio data separated from video data by the ECC decoder 111 is supplied to the SDTI output unit 115 as described above. In the SDT I output section 115, the supplied video data and audio data as elementary streams are mapped to the SDT I format, and the SDT I format has an SDT format data structure. The SDTI signal converted to the DTI signal is output to the outside. The system controller 117 (abbreviated as system controller 117 in FIGS. 7A and 7B) is composed of, for example, a microcomputer and communicates with each block by a signal SY-IO. Thus, the entire operation of the digital VTR 100 is controlled. The Servo 118 communicates with the System Controller 117 by the signal SY-SV, while the signal SV__I〇 controls the running and rotation of the magnetic tape 110. The drive control of the transfer drum 109 is performed.

FIG. 8 schematically shows an example of the configuration of the MPEG encoder 103 in the digital VTR 100 shown in FIG. The MPEG encoder 103 is roughly composed of a blocking circuit 300, a delay circuit 301, and a DCT mode determination circuit 302,0. It has a chopping circuit 303, a quantization circuit 304, and a variable length coding (VLC) circuit 305.

The digital video signal supplied to the MPEG encoder 103 is divided by a blocking circuit 300 into 16-line × 16-pixel block (macroblock) units and output. The data output from the blocking circuit 300 in block units is given a predetermined delay by the delay circuit 301, supplied to the DCT circuit 303, and supplied to the DCT mode determination circuit 302. The DCT mode determination circuit 302 determines whether to perform the field DCT or the frame DCT on the blocked digital video signal by the determination control according to the above-described embodiment. The result of the determination is output from the DCT mode determination circuit 302 as a mode determination signal and supplied to the DCT circuit 303.

The DCT circuit 303 performs a DCT operation on the data in block units output from the delay circuit 301 based on the DCT mode determined by the DCT mode determination circuit 302 to generate a DCT coefficient. . The generated DCT coefficient is supplied to the quantization circuit 304. In the DCT circuit 303, a DCT operation is performed in units of a DCT block composed of 8 lines and 8 pixels.

The DCT coefficient output from the DCT circuit 303 is quantized by the quantization circuit 304. The output of the quantization circuit 304 is supplied to a VLC circuit 305, subjected to variable-length coding, converted into MPEG ES, and output. Next, high-speed playback and high-speed reverse playback (shuttle Mode), the advantages of this embodiment will be described below. A magnetic tape is generally used as a recording medium for recording a video signal. Video signal recording on magnetic tape is performed by a magnetic head (rotating head) provided on a rotating drum, forming a helical track that is inclined with respect to the tape running method. Also, during playback, the rotating head accurately traces the helical tracks formed during recording.

On the other hand, by making the running speed of the tape higher than the speed at the time of recording during reproduction, it is possible to perform reproduction such as double speed, triple speed, or search. In this case, the trace angle of the rotary head on the tape is different from the tilt angle of the helical track. This makes it impossible to trace all the signals recorded on the helical track. That is, at the time of high-speed reproduction, reproduction is performed by scanning a part of each helical track.

In the digital VTR 100 for MPEG-VTR, data is packed and recorded in consideration of such high-speed reproduction and shuffling. Packing refers to applying different length streams to a fixed frame. That is, the streams created by the MPEG encoders 113 are variable-length coded, and therefore have different lengths for each macroblock. Therefore, data is recorded by performing a packing operation of applying the different streams to a fixed frame.

FIG. 9 and FIG. 10 are diagrams showing an outline of packing. Here, an example in which 8 macro blocks are applied to a fixed frame is shown. Number each macro block from # 1 to # 8.

As shown in FIG. 9, the lengths of the eight macroblocks are different from each other due to the variable length coding. In this example, the fixed frame is 1 Macro block # 1, data # 3, data # 6 are longer than macro block # 1, macro block # 2, data # 5, data # 7, and data # 8 Are short. The length of macro block # 4 is equal to one sync block.

By the packing process, the macroblock is poured into a fixed-length frame of one sync block length, and the entire data generated in one frame period is fixed-length. Therefore, a macro block longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the portion that protrudes from the sync block length is stuffed into the extra area in order from the beginning, that is, after the macroblock whose length is less than the sync block length.

In Fig. 10, the part that protrudes from the sync block length of macro block # 1 is packed first after macro block # 2, and when it reaches the length of sync block, it follows macro block # 5. Stuffed into.

Next, the portion of macro block # 3 that exceeds the sync block length is packed after macro block # 7. In addition, the portion that protrudes from the sync block length of macro block # 6 is stuffed after macro block # 7, and the protruding portion is stuffed after macro block # 8. Thus, each macroblock is packed into a fixed frame of the sync block length.

In addition, the high-speed reproduction described above cannot trace all the signals recorded on the helical track. For this reason, data that is out of the sync block length without packing cannot be reproduced. (In Fig. 9, 10 the data that exceeds the sync block length cannot be reproduced. , All packed and reproducible examples are shown).

On the other hand, consider a case in which the DCT mode is fixed to either the field DCT or the frame DCT for encoding. For example, if the frame DCT is fixed, a large amount of streams will be allocated to a rapidly moving image with strong temporal correlation because there is little spatial correlation, and the length will greatly exceed the sync block length.

As a result, there is a lot of data that exceeds the sync block length, and many data parts that cannot fit in the fixed-length frame are truncated due to packing. In addition, data that exceeds the sync block length contains many AC coefficients. Therefore, if high-speed reproduction and high-speed reverse reproduction are performed and this portion is deleted, the image quality deteriorates.

Also, in the fixed field DCT, the coding efficiency is inferior to that of the fixed frame DCT for an image having a strong spatial correlation which is common in general images. For this reason, image quality is deteriorated not only during high-speed reproduction and high-speed reverse reproduction, but also during normal reproduction.

Furthermore, even when the DCT mode is inverted for the same block due to dubbing or cascading connection between the encoder and the decoder, for example, a frame that is originally intended for field DCT can be used. If the DCT is executed, a large number of data appearing outside the sync block length will appear, and image degradation will be conspicuous during high-speed playback and high-speed reverse playback.

In this way, when the DCT mode is fixed to either the field DCT or the frame DCT, or when the DCT mode is inverted for the same block due to dubbing or cascading the encoder and decoder, the Out of sync block length The number of days and evenings will increase.

On the other hand, in this embodiment, the above-described determination control is performed so that the determination result is constant for the same block (so that the DCT mode is not inverted even when dubbing or cascading the encoder and the decoder is performed). The DCT mode is adaptively selected based on. This makes it possible to reduce the number of data pieces that extend beyond the sink block length, thereby improving the image quality not only during normal playback but also during high-speed playback and high-speed reverse playback.

In the above description, adaptive switching in the case of performing DCT computation on each of the frame and the field has been described. However, the orthogonal transform other than DCT and other high-efficiency coding algorithms are used to perform frame switching. It is also possible to apply the encoding determination control of this embodiment to an encoding device that switches for each field. As described above, the image processing apparatus according to the present embodiment weights at least one of the frame correlation information and the field correlation information of a block so that the determination result is constant for the same block. Therefore, a configuration is adopted in which whether frame DCT or field DCT is to be encoded is adaptively determined and controlled. As a result, the inversion of the DCT mode for the same block can be prevented, and the deterioration of the image quality can be reduced.

Further, the image processing method according to this embodiment performs weighting on at least one of the frame correlation information and the field correlation information of a block so that the determination result is constant for the same block. Alternatively, it was decided to adaptively judge and control which field DCT coding should be performed. As a result, it is possible to prevent the DCT mode from being inverted for the same block, and to reduce image quality degradation. become.

Claims

The scope of the claims

1. In an image processing device that compresses and encodes an image signal,

Correlation information detecting means for detecting correlation information in which one of frame correlation and field correlation is weighted with respect to the block of the image signal; and detecting the image signal according to the correlation information detected by the correlation information detecting means. Encoding means for performing intra-frame or intra-field encoding on the block;

An image processing apparatus comprising:

2. In the image processing apparatus according to claim 1,

When the above-mentioned frame correlation based on the difference value between adjacent pixels in the frame is Var1, the above-mentioned field correlation based on the difference value between adjacent pixels in the field is Var2, and A> 1 and B> 0. ,

The encoding means,

V a r 1> AX V a r 2 + B

An image processing apparatus, wherein the intra-field encoding is performed on the image signal block at the time of (i).

3. In the image processing apparatus according to claim 1,

The above-mentioned frame correlation based on the difference value between adjacent pixels in the frame is set to Var1, the above-mentioned field correlation based on the difference value between adjacent pixels in the field is set to Var2, and 1> A> 0 and B <0 In case,

The encoding means,

V a r 1> AX V a r 2 + B

An image processing apparatus, wherein the intra-field encoding is performed on a block of the image signal at the time of (i).

4. The image processing apparatus according to claim 1,

The image processing apparatus is characterized in that the coding is orthogonal transform coding.

5. The image processing device according to claim 4, wherein the orthogonal transform coding is a DCT.

6. In an image processing method for compressing and encoding an image signal,

A step of detecting correlation information in which one of frame correlation and field correlation is weighted with respect to a block of the image signal, and the image signal according to the correlation information detected in the step of detecting correlation information. Encoding steps to perform intra-frame encoding or intra-field encoding for

An image processing method comprising:

7. The image processing method according to claim 6, wherein

The encoding step includes:

V a r 1> AX V a r 2 + B

An image processing method, wherein the intra-field encoding is performed on the block of the image signal at the time of (i).

8. The image processing method according to claim 6, wherein

The above-mentioned frame correlation based on the difference value between adjacent pixels in the frame is V ar 1, and the above-described field correlation based on the difference value between adjacent pixels in the field is V ar 2, where 1> A> 0 and B <0 In case,

The encoding step includes:

V a r 1> AX V a r 2 + B

In this case, the intra-field encoding is performed on the image signal block. An image processing device, characterized in that:

9. In the image processing method according to claim 6,

An image processing method, wherein the encoding is orthogonal transform encoding.

I 10. The image processing method according to claim 9, wherein the orthogonal transform coding is DCT.