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WO2002082527A1 - Method of forming electrical connections - Google Patents

Method of forming electrical connections Download PDF

Info

Publication number
WO2002082527A1
WO2002082527A1 PCT/SG2001/000055 SG0100055W WO02082527A1 WO 2002082527 A1 WO2002082527 A1 WO 2002082527A1 SG 0100055 W SG0100055 W SG 0100055W WO 02082527 A1 WO02082527 A1 WO 02082527A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
die
electrically conductive
contact
dice
Prior art date
Application number
PCT/SG2001/000055
Other languages
French (fr)
Inventor
Chek Lim Kho
Kum Weng Loo
Original Assignee
Stmicroelectronics Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics Pte Ltd filed Critical Stmicroelectronics Pte Ltd
Priority to PCT/SG2001/000055 priority Critical patent/WO2002082527A1/en
Publication of WO2002082527A1 publication Critical patent/WO2002082527A1/en

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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Definitions

  • This invention relates to a method of forming electrical connections to a die.
  • the invention is applicable to form connections to an integrated circuit.
  • the invention also relates to a die or other integrated circuit element having connections thereto formed by the method of the invention, and to integrated circuit packages utilising such a die.
  • Integrated circuits may be formed by effecting on a semiconductor substrate operations which result in formation, on the substrate, of circuit elements such as resistors, diodes, and transistors.
  • a plurality of the integrated circuits may be formed on a single substrate, with the substrate subsequently being cut into discrete parts, called dice, each of which then forms a respective integrated circuit.
  • a single die or a plurality of these are usually packaged in suitable packaging which provides mechanical protection for each die and also supports other components such as internal connective elements and external contacts which connect to the die and by means of which electrical signals are conveyed to and from the integrated circuit constituted by each die.
  • Electrical connections to each die may be made by bonding an interconnecting wire to a contact of the die and to a suitable contact element.
  • One technique known in the art for forming such an interconnection is ball-stitch bonding. In one example of performing this technique, at the beginning of each bonding cycle, a gold wire is fed through a hollow capillary and an end of the wire is melted by a high voltage spark to thereby form a ball on the end of the wire.
  • Ball-stitch bonding is generally effected using thermosonic bonding techniques which involve an ultrasonic transducer, transmitting ultrasonic energy and force, and a heat block to effect bonding.
  • a capillary with a ball hanging below it, is positioned over a contact on a die.
  • the ball is effected by the mentioned thermosonic bonding techniques and the capillary is brought down onto the ball so that the ball is engaged, and subjected to compressive force between the first contact element and the adjacent end of the capillary. This causes a bond, a "ball bond", to be formed between the ball and the contact element.
  • the capillary is raised, so as to withdraw the capillary over the wire to leave an exposed length of the wire extending away from the formed bond.
  • the capillary With the end of the capillary from which the wire extends positioned over a second contact element to which connection is to be made, the capillary is brought down again onto the wire, where it extends from the capillary, and the wire is "stitch bonded" to the second contact element. After raising the capillary again, withdrawing it over the wire, a high voltage electric spark is used to melt a section of the wire between the capillary and the stitch bond to break the wire and in doing so form a ball on the end of the wire for the next bonding cycle. The process may be repeated to form interconnections between a number of pairs of first and second contact elements.
  • Thermsonic bonding may be applied to form interconnections between contact pads of a die, and posts or other contact elements of an integrated circuit package.
  • Electrical interconnections for integrated circuit packages may make use of conventional ball-stitch wire bonding techniques, as above described, where the contact pads of a die are subjected to ball type bonds and lead fingers of the integrated circuit package are subjected to stitch type bonds.
  • a factor limiting the minimum vertical spacing between successive dice in the stack is the vertical height above each die to which the wires bonded to these extend.
  • the wires customarily extend upwardly from the die contact pads, and then loop outwardly from the stack to the lead fingers.
  • the loop height the height above a contact on a die to which a connecting wire extends, is limited by the presence of conventional ball bonds, particularly so because the wire is connected vertically to the contact and has to be bent sidewardly to connect the contact on the die to a lead finger on an integrated circuit package. Loop heights for bonds formed from balls are of a typical minimum height of 120 ⁇ m.
  • a low profile integrated circuit package such as a TSOP (thin small outline package) may have a maximum height of 1mm. Accordingly, if a number of dice are to be stacked on top of one another, each separated by an adhesive layer, and packaged in a TSOP, the height of the stacked dice must be less than 1mm.
  • US 5,291,061 discloses a multiple stacked die device that contains up to four dies and is said not to exceed the height of single die packages. Close-tolerance stacking is made possible by a low profile loop wire bonding operation and thin adhesive layers between the stacked dies.
  • US 5,291,061 discloses forming an interconnection between a contact pad of a die end and a respective lead finger of an integrated circuit package. At the die end, an ultrasonic ball bond is formed. At the other end, wires are attached to the lead fingers by ultrasonic wedge bonds.
  • the controlled adhesive layer thickness can be from 0.001 to 0.005 inches.
  • the individual dies may have a thickness of 0.012 inches and the critical controlled adhesive-layer thickness between each die are between 0.008 and 0.010 inches. These thin layers have to be slightly greater than the low-loop wire dimension which is about 0.006 inches.
  • US 5,323,060 describes a multichip module, including a plurality of first loop bonding wires bonded to respective first chip bonding pads and a multichip substrate.
  • the first bonding wires may have outwardly projecting loops having a defined loop height between a respective upper bonding surface and the maximum extent of the loop.
  • a plurality of second loop bonding wires are bonded to and between respective second chip bonding pads and the multichip module substrate.
  • the adhesive layer may have a thickness of 0.008 inches, the loop height being 0.006 inches.
  • the above two known techniques employ conventional ball-wedge (ball-stitch) wire bonding techniques with a typical loop height of about 120mm. Accordingly, a two die studs with die thicknesses of 180 ⁇ m may have a final assembled height of about 800 ⁇ m. Practically, this cannot be fitted into a 1 mm thick TSOP (thin small outline package) with a 200 ⁇ m clearance for moulding.
  • TSOP thin small outline package
  • the clearance between the two adjacent die in a stack is critical and a small variation in the thickness of intervening adhesive layer, or in the wire loop height, may cause wires to be exposed from the package or the wire loops of an underlying die to contact or interfere with a die positioned above it.
  • a second end of said lead is ball bonded to a contact element.
  • a plurality of stacked dice have electrically conductive leads stitch bonded to electrically conductive bumps formed on contacts of the dice.
  • a method for connecting an electrically conductive lead between a contact element and a contact pad of a die, the contact pad having an electrically conductive bump formed thereon including the steps of: (a) ball bonding a first end of the lead to the contact element; and (b) stitch bonding a second end of the lead to said electrically conductive bump.
  • each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the
  • plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads:
  • a second end is stitch bonded to an electrically conductive bump formed on the contact pad which corresponds to said lead finger.
  • each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including the steps of: (a) backgrounding ' each die in the plurality of dice;
  • a second end is stitch bonded to an electrically conductive bump formed - : ' on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die;
  • the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of electrically conductive leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
  • a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
  • steps (e) and (f) are repeated for each die there after in the plurality of dice.
  • the plurality of dice includes two dice and said integrated circuit packaging is a TSOP.
  • the electrically conductive bump is a gold bump.
  • apparatus for connecting a first end of an electrically conductive lead to a surface of an electrically conductive bump formed on a contact of a die, the apparatus having means for stitch bonding the lead to the surface of the bump.
  • apparatus for connecting an electrically conductive lead between a contact pad of a die and a corresponding post lead finger of an integrated circuit package, wherein the contact pad has an electrically conductive bump formed thereon including means for: (a) ball bonding a first end of the electrically conductive lead to the lead finger; and
  • apparatus for connecting a plurality of leads between a plurality of contact pads of a die and a plurality of lead fingers of an integrated circuit package, wherein each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the .plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads means is provided for:
  • apparatus for stacking a plurality of dice for an integrated circuit package wherein each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including means for:
  • a first end is ball bonded to a lead finger of said second plurality of lead fingers of the integrated circuit package; and (ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die;
  • the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
  • a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
  • steps (e) and (f) are repeated for each die there after in the plurality of dice.
  • Figure 1 is a diagrammatic vertical section of a single die package, in accordance with the invention.
  • Figure 2 is a flow diagram of a wire bonding sequence, in accordance with the invention.
  • Figure 3 is a flow chart of a manufacturing process, in accordance with the invention.
  • FIGS. 4(a), 4(b) and 4(c) together form a flow chart of a manufacturing process, in accordance with the invention
  • Figures 5- (a) and 5(b) are vertical sections of respective ones of two packages of stacked dice, wherein the dice are stacked in accordance with the invention
  • Figure 6 (a) and 6 (b) are vertical sections of respective ones of two further packages of stacked dice, wherein the dice are stacked in accordance with the invention
  • Figure 7 is a diagram illustrating the loop height of a die end of a wire interconnection.
  • Figure 8 illustrates conventional ball bonding and stitch bonding techniques.
  • the wire 20 protrudes downwardly from the internal passage of a capillary 23.
  • a ball 24, created during a previous step, is formed at the lower end of the wire 20.
  • the capillary 23 is moved downwardly over the wire 20, to contact tlie ball 24 and press it against the contact pad 21. Ultrasonic energy and heat are applied by an ultrasonic transducer, the ball 24 deforms and bonds with the contact pad 21.
  • the capillary is moved upwardly, so that the wire is fed from the capillary, and also sidewardly, to position the capillary as shown in Figure 8 (d).
  • the part of the wire extending from the capillary is positioned on or immediately above the lead finger 22.
  • the capillary 23 is then moved downwardly again to contact the wire 20 and press it against the lead finger 22 ( Figure 8 (e)).
  • Ultrasonic pressure and heat are applied by an ultrasonic transducer and the wire 20 bonds to the lead finger 22.
  • the capillary is moved upwardly to feed a length of wire therefrom, and a high voltage electric spark is applied to break the wire.
  • the action of breaking the wire 20 with a high voltage spark also creates a new ball 24 on the end of the wire 20.
  • Figure 7 shows a completed wire interconnection produced by the method of Figure 8.
  • the wire 20 interconnecting the illustrated contact pad 21 and lead fingers 22 extends upwardly from the contact pad 21 and then loops to the lead finger 22.
  • the loop height the height to which the looped wire extends above the die 21, designated by reference numeral ---28.
  • the connection formed is a ball bond 29, and the connection at the lead finger 22 is a stitch bond 30.
  • the use of heat is not essential, if ultrasonic bonding is used.
  • the single integrated circuit (“IC") package 1, shown in Figure 1, is a TSOP thin small outline package ("TSOP").
  • TSOP packages typically have a thickness 13 of 1000 ⁇ m.
  • IC package 1 has moulded electrically insulative encapsulant 5, which encapsulates first and second dice 2, 3, where the second die 3 is stacked on top of the first die 2.
  • wafers forming the dice are thinned using any suitable known backgrounding process so that each die is of a predetermined desirable thickness 5. This thickness may for example be 180 ⁇ m.
  • Contact pads 4 of the first and second dice 2,3, are gold bumped. This may be effected prior to separation of the dice from the wafers from which they are formed.
  • the resultant gold bumps 4 may be created by conventional gold stud bumping techniques, gold electroplating or by electroless Nickel/gold bumping. The height of each gold bump created is typically:
  • Figure 3(a) shows the gold bumped die 2.
  • the gold bumped die 2 is then secured to a substrate 6 ( Figure 3(b)).
  • the die 2 may be secured to the substrate 6 using a conventional epoxy die attachment processes. After curing, the height of the bond line between the substrate 6 and the die 2 is approximately 30 ⁇ m.
  • Leads 1.-.- interconnecting the gold bumps 4 of the first die 2, and respective lead fingers 8, of the single IC package 1, are connected by a reverse wire bonding technique.
  • This technique involves first securing a first end of a lead 7 to a respective lead finger 8 using a conventional ball bond 18, shown in Figure 2. The lead 7 is then secured to a respective gold bump 4 on the first die 2 using a stitch bond technique.
  • Figure 3(c) shows the result of these operations.
  • the second gold bumped die 3 is then secured to the top of the first gold bumped die 2 by means of a non-conductive adhesive, to thereby form a non-conductive adhesive layer 9.
  • the thickness 10 of the non-conductive adhesive layer 9 is greater than the loop height 11 of the bonds formed with the bumps 4 and the leads 7 connected to the first die 2.
  • the non- conductive adhesive layer 9 may be a non-Ag filled system.
  • the stacked dice are then cured.
  • Figures 3(d) and 3(e) show the results of these steps.
  • Leads 12 interconnecting the gold bumps 4, of the second die 3, and the respective lead fingers 8, of the single IC package 1, are again connected by a reverse wire bonding technique.
  • the first end of a lead 12 is secured to a respective lead finger 8 using a conventional ball bond 18, shown in Figures 2 and 3.
  • the lead 12 is then secured to a respective gold bump 4 on the second die 3 using a stitch bond technique.
  • the resultant structure is shown in Figure 3(f).
  • a typical height of the above-described stacked die configuration 14 is 600 ⁇ m, well within the typical height limit of a TSOP of lOOO ⁇ m 13.
  • SBOB Switch Bond On Bump
  • the SBOB technique is applicable for packaging stacked dice, where the dice are at least of the same width.
  • the SBOB technique may is applicable when the stacked dice are of different sizes, as shown in Figure 5(a).
  • the IC package 50 shown is an "exposed die pad" design which is able to accommodate an increase in adhesive thickness 56 in cases where the top die 52 is larger than the bottom die 53.
  • the IC package 54 in Figure 5(b) is designed to accommodate a dice configuration where the top die 56 is smaller than the bottom die 58.
  • the SBOB technique can be applied to various IC packages because of its low loop profile 11.
  • the package 60 of Figure 6(a) includes a chip 61, mounted on an organic substrate 62.
  • the chip 61 and the organic substrate 62 are encased within a plastic encapsulant 63.
  • plastic encapsulant 63 examples of such an embodiment are PBGA (plastic ball grid array), TBGA (tape ball grid array), etc.
  • the SBOB technique can be used in the IC package 64 of Figure 6(b)where a metal lead frame 65 is moulded within a plastic encapsulant 66.
  • a metal lead frame 65 is moulded within a plastic encapsulant 66.
  • Examples of such an arrangement are TSOP, TSSOP (thin shrink small outline package), SOP (small outline package), PQFP (plastic quad flat pack), PLCC (plastic lead chip carrier), TQFP (thin quad flat pack), QFN (quad flat non-leaded), etc.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A method of connecting an end of an electrically conductive lead (7) to a surface of an electrically conductive bump (4) formed on a contact of a die, wherein the end is stitch bonded to the surface of the bump (4).

Description

METHOD OF FORMING ELECTRICAL CONNECTIONS
This invention relates to a method of forming electrical connections to a die. The invention is applicable to form connections to an integrated circuit. The invention also relates to a die or other integrated circuit element having connections thereto formed by the method of the invention, and to integrated circuit packages utilising such a die.
Integrated circuits may be formed by effecting on a semiconductor substrate operations which result in formation, on the substrate, of circuit elements such as resistors, diodes, and transistors. A plurality of the integrated circuits may be formed on a single substrate, with the substrate subsequently being cut into discrete parts, called dice, each of which then forms a respective integrated circuit. A single die or a plurality of these are usually packaged in suitable packaging which provides mechanical protection for each die and also supports other components such as internal connective elements and external contacts which connect to the die and by means of which electrical signals are conveyed to and from the integrated circuit constituted by each die.
Electrical connections to each die may be made by bonding an interconnecting wire to a contact of the die and to a suitable contact element. One technique known in the art for forming such an interconnection is ball-stitch bonding. In one example of performing this technique, at the beginning of each bonding cycle, a gold wire is fed through a hollow capillary and an end of the wire is melted by a high voltage spark to thereby form a ball on the end of the wire.
Ball-stitch bonding is generally effected using thermosonic bonding techniques which involve an ultrasonic transducer, transmitting ultrasonic energy and force, and a heat block to effect bonding.
A capillary, with a ball hanging below it, is positioned over a contact on a die. The ball is effected by the mentioned thermosonic bonding techniques and the capillary is brought down onto the ball so that the ball is engaged, and subjected to compressive force between the first contact element and the adjacent end of the capillary. This causes a bond, a "ball bond", to be formed between the ball and the contact element. After this, the capillary is raised, so as to withdraw the capillary over the wire to leave an exposed length of the wire extending away from the formed bond. With the end of the capillary from which the wire extends positioned over a second contact element to which connection is to be made, the capillary is brought down again onto the wire, where it extends from the capillary, and the wire is "stitch bonded" to the second contact element. After raising the capillary again, withdrawing it over the wire, a high voltage electric spark is used to melt a section of the wire between the capillary and the stitch bond to break the wire and in doing so form a ball on the end of the wire for the next bonding cycle. The process may be repeated to form interconnections between a number of pairs of first and second contact elements.
Thermsonic bonding may be applied to form interconnections between contact pads of a die, and posts or other contact elements of an integrated circuit package.
Electrical interconnections for integrated circuit packages may make use of conventional ball-stitch wire bonding techniques, as above described, where the contact pads of a die are subjected to ball type bonds and lead fingers of the integrated circuit package are subjected to stitch type bonds.
Where dice are to be stacked one above the other using conventional techniques, a factor limiting the minimum vertical spacing between successive dice in the stack is the vertical height above each die to which the wires bonded to these extend. The wires customarily extend upwardly from the die contact pads, and then loop outwardly from the stack to the lead fingers. The loop height, the height above a contact on a die to which a connecting wire extends, is limited by the presence of conventional ball bonds, particularly so because the wire is connected vertically to the contact and has to be bent sidewardly to connect the contact on the die to a lead finger on an integrated circuit package. Loop heights for bonds formed from balls are of a typical minimum height of 120 μm.
A low profile integrated circuit package, such as a TSOP (thin small outline package), may have a maximum height of 1mm. Accordingly, if a number of dice are to be stacked on top of one another, each separated by an adhesive layer, and packaged in a TSOP, the height of the stacked dice must be less than 1mm.
US 5,291,061 discloses a multiple stacked die device that contains up to four dies and is said not to exceed the height of single die packages. Close-tolerance stacking is made possible by a low profile loop wire bonding operation and thin adhesive layers between the stacked dies.
US 5,291,061 discloses forming an interconnection between a contact pad of a die end and a respective lead finger of an integrated circuit package. At the die end, an ultrasonic ball bond is formed. At the other end, wires are attached to the lead fingers by ultrasonic wedge bonds.
It is indicated that, by careful control of layer thickness it is possible to fabricate a four stacked die device having an overall height of 0.110 inches which is the same height as a current single die. In US 5,291,061, the controlled adhesive layer thickness can be from 0.001 to 0.005 inches. The individual dies may have a thickness of 0.012 inches and the critical controlled adhesive-layer thickness between each die are between 0.008 and 0.010 inches. These thin layers have to be slightly greater than the low-loop wire dimension which is about 0.006 inches.
US 5,323,060 describes a multichip module, including a plurality of first loop bonding wires bonded to respective first chip bonding pads and a multichip substrate. The first bonding wires may have outwardly projecting loops having a defined loop height between a respective upper bonding surface and the maximum extent of the loop. A plurality of second loop bonding wires are bonded to and between respective second chip bonding pads and the multichip module substrate. The adhesive layer may have a thickness of 0.008 inches, the loop height being 0.006 inches.
The above two known techniques employ conventional ball-wedge (ball-stitch) wire bonding techniques with a typical loop height of about 120mm. Accordingly, a two die studs with die thicknesses of 180μm may have a final assembled height of about 800μm. Practically, this cannot be fitted into a 1 mm thick TSOP (thin small outline package) with a 200 μm clearance for moulding.
The clearance between the two adjacent die in a stack is critical and a small variation in the thickness of intervening adhesive layer, or in the wire loop height, may cause wires to be exposed from the package or the wire loops of an underlying die to contact or interfere with a die positioned above it.
In accordance with the present invention there is provided a method of connecting a first end of an electrically conductive lead to a surface of an electrically conductive bump formed on a contact of a die, wherein the first end is stitch bonded to the surface of the bump.
Preferably, a second end of said lead is ball bonded to a contact element.
Preferably, a plurality of stacked dice have electrically conductive leads stitch bonded to electrically conductive bumps formed on contacts of the dice.
In accordance with the invention there is also provided a method for connecting an electrically conductive lead between a contact element and a contact pad of a die, the contact pad having an electrically conductive bump formed thereon, including the steps of: (a) ball bonding a first end of the lead to the contact element; and (b) stitch bonding a second end of the lead to said electrically conductive bump.
In accordance with the present invention there is also provided a method for connecting a plurality of electrically conductive leads between a plurality of contact pads of a die and a
■plurality of lead fingers of an integrated circuit package, wherein each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the
, plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads:
(a) a first end is ball bonded to a lead finger; and
(b) a second end is stitch bonded to an electrically conductive bump formed on the contact pad which corresponds to said lead finger.
In accordance with the present invention there is also provided a method of stacking a plurality of dice for an integrated circuit package, wherein each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including the steps of: (a) backgrounding'each die in the plurality of dice;
(b) forming an electrically conductive bump on each contact pad of each die of the plurality of dice;
(c) securing a first die of the plurality of dice to a substrate within the integrated circuit package; (d) connecting a first plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said first die and each lead finger of a second plurality of lead fingers, the second plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the first die, wherein for each lead of said first plurality of electrically conductive leads: (i) a first end is ball bonded to a lead finger of said second plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed -:' on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die;
(e) securing a second die of the plurality of dice to the top of the first mentioned die by means of a non-conductive adhesive;
(f) connecting a second plurality of electrically conductive leads between each .contact pad of the plurality of contact pads of said second die and each lead finger of a third plurality of lead fingers, the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of electrically conductive leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
(g) steps (e) and (f) are repeated for each die there after in the plurality of dice.
Preferably, the plurality of dice includes two dice and said integrated circuit packaging is a TSOP.
Preferably, the electrically conductive bump is a gold bump.
In accordance with the present invention there is also provided apparatus for connecting a first end of an electrically conductive lead to a surface of an electrically conductive bump formed on a contact of a die, the apparatus having means for stitch bonding the lead to the surface of the bump.
In accordance with the present invention there is also provided apparatus for connecting an electrically conductive lead between a contact pad of a die and a corresponding post lead finger of an integrated circuit package, wherein the contact pad has an electrically conductive bump formed thereon, including means for: (a) ball bonding a first end of the electrically conductive lead to the lead finger; and
(b) stitch bonding a second end of the electrically conductive lead to said electrically conductive bump.
,In accordance with the present invention there is also provided apparatus for connecting a plurality of leads between a plurality of contact pads of a die and a plurality of lead fingers of an integrated circuit package, wherein each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the .plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads means is provided for:
(a) ball bonding a first end of the lead to a respective to a respective said lead finger; and
(b) stitch bonding a second end of the lead to a respective said electrically conductive bump.
In accordance with the present invention there is also provided apparatus for stacking a plurality of dice for an integrated circuit package, wherein each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including means for:
(a) backgrounding each die in the plurality of dice;
(b) forming an electrically conductive bump on each contact pad of each die of the plurality of dice;
(c) securing a first die of the plurality of dice to a substrate within, the integrated circuit package;
(d) connecting a first plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said first die and each lead finger of a second plurality of lead fingers, the second plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the first die, wherein for each lead of said first plurality of electrically conductive leads:
(i) a first end is ball bonded to a lead finger of said second plurality of lead fingers of the integrated circuit package; and (ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die;
(e) securing a second die of the plurality of dice to the top of the first mentioned die by means of a non-conductive adhesive;
(f) connecting a second plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said second die and each lead finger of a third plurality of lead fingers, the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
(g) steps (e) and (f) are repeated for each die there after in the plurality of dice.
The invention is described below, by way of non-limiting example, with reference to the accompanying drawings, in which:
Figure 1 is a diagrammatic vertical section of a single die package, in accordance with the invention;
Figure 2 is a flow diagram of a wire bonding sequence, in accordance with the invention; Figure 3 is a flow chart of a manufacturing process, in accordance with the invention;
Figures 4(a), 4(b) and 4(c) together form a flow chart of a manufacturing process, in accordance with the invention;
Figures 5- (a) and 5(b) are vertical sections of respective ones of two packages of stacked dice, wherein the dice are stacked in accordance with the invention; Figure 6 (a) and 6 (b) are vertical sections of respective ones of two further packages of stacked dice, wherein the dice are stacked in accordance with the invention;
Figure 7 is a diagram illustrating the loop height of a die end of a wire interconnection; and
Figure 8 illustrates conventional ball bonding and stitch bonding techniques. Reference is first made to Figure 8, which illustrates conventional steps of interconnecting a contact pad 21 of an integrated circuit and a lead finger 22 of an integrated circuit package with a wire 20. At step (a), the wire 20 protrudes downwardly from the internal passage of a capillary 23. A ball 24, created during a previous step, is formed at the lower end of the wire 20. At step (b), the capillary 23 is moved downwardly over the wire 20, to contact tlie ball 24 and press it against the contact pad 21. Ultrasonic energy and heat are applied by an ultrasonic transducer, the ball 24 deforms and bonds with the contact pad 21. At step (c), the capillary is moved upwardly, so that the wire is fed from the capillary, and also sidewardly, to position the capillary as shown in Figure 8 (d). At this position, the part of the wire extending from the capillary is positioned on or immediately above the lead finger 22. The capillary 23 is then moved downwardly again to contact the wire 20 and press it against the lead finger 22 (Figure 8 (e)). Ultrasonic pressure and heat are applied by an ultrasonic transducer and the wire 20 bonds to the lead finger 22. Subsequently, the capillary is moved upwardly to feed a length of wire therefrom, and a high voltage electric spark is applied to break the wire. The action of breaking the wire 20 with a high voltage spark also creates a new ball 24 on the end of the wire 20. These steps are repeated as necessary to form connections between a number of pairs of contact pads and lead fingers.
Figure 7 shows a completed wire interconnection produced by the method of Figure 8. The wire 20 interconnecting the illustrated contact pad 21 and lead fingers 22 extends upwardly from the contact pad 21 and then loops to the lead finger 22. The loop height, the height to which the looped wire extends above the die 21, designated by reference numeral ---28. At the contact pad, the connection formed is a ball bond 29, and the connection at the lead finger 22 is a stitch bond 30. The use of heat is not essential, if ultrasonic bonding is used.
The single integrated circuit ("IC") package 1, shown in Figure 1, is a TSOP thin small outline package ("TSOP"). TSOP packages typically have a thickness 13 of 1000 μm.
IC package 1 has moulded electrically insulative encapsulant 5, which encapsulates first and second dice 2, 3, where the second die 3 is stacked on top of the first die 2. Prior to packaging the first and second dice, wafers forming the dice are thinned using any suitable known backgrounding process so that each die is of a predetermined desirable thickness 5. This thickness may for example be 180 μm.
Contact pads 4 of the first and second dice 2,3, are gold bumped. This may be effected prior to separation of the dice from the wafers from which they are formed. The resultant gold bumps 4 may be created by conventional gold stud bumping techniques, gold electroplating or by electroless Nickel/gold bumping. The height of each gold bump created is typically:
electroless Ni/Au bumping 20 μm; Au electroplating 20 μm; and stud bumping 30 μm
Figure 3(a) shows the gold bumped die 2.
To manufacture the IC package 1, the gold bumped die 2 is then secured to a substrate 6 (Figure 3(b)). The die 2 may be secured to the substrate 6 using a conventional epoxy die attachment processes. After curing, the height of the bond line between the substrate 6 and the die 2 is approximately 30 μm.
Leads 1.-.- interconnecting the gold bumps 4 of the first die 2, and respective lead fingers 8, of the single IC package 1, are connected by a reverse wire bonding technique. This technique involves first securing a first end of a lead 7 to a respective lead finger 8 using a conventional ball bond 18, shown in Figure 2. The lead 7 is then secured to a respective gold bump 4 on the first die 2 using a stitch bond technique. Figure 3(c) shows the result of these operations.
The second gold bumped die 3 is then secured to the top of the first gold bumped die 2 by means of a non-conductive adhesive, to thereby form a non-conductive adhesive layer 9.
The thickness 10 of the non-conductive adhesive layer 9 is greater than the loop height 11 of the bonds formed with the bumps 4 and the leads 7 connected to the first die 2. The non- conductive adhesive layer 9 may be a non-Ag filled system. The stacked dice are then cured. Figures 3(d) and 3(e) show the results of these steps.
Leads 12 interconnecting the gold bumps 4, of the second die 3, and the respective lead fingers 8, of the single IC package 1, are again connected by a reverse wire bonding technique. The first end of a lead 12 is secured to a respective lead finger 8 using a conventional ball bond 18, shown in Figures 2 and 3. The lead 12 is then secured to a respective gold bump 4 on the second die 3 using a stitch bond technique. The resultant structure is shown in Figure 3(f).
A typical height of the above-described stacked die configuration 14 is 600μm, well within the typical height limit of a TSOP of lOOOμm 13.
This reverse wire bonding technique is referred to hereafter as SBOB (Stitch Bond On Bump). The purpose of performing a SBOB is to minimise the loop height of the leads 7 on the die 2. In this way, the two stacked dice 2, 3 are able to fall within the height limitations of the single IC package 1.
The SBOB technique is applicable for packaging stacked dice, where the dice are at least of the same width. The SBOB technique may is applicable when the stacked dice are of different sizes, as shown in Figure 5(a). The IC package 50 shown, is an "exposed die pad" design which is able to accommodate an increase in adhesive thickness 56 in cases where the top die 52 is larger than the bottom die 53.
The IC package 54 in Figure 5(b) is designed to accommodate a dice configuration where the top die 56 is smaller than the bottom die 58. The SBOB technique can be applied to various IC packages because of its low loop profile 11.
The SBOB technique can be used with numerous styles of packages. For example, the package 60 of Figure 6(a) includes a chip 61, mounted on an organic substrate 62. In this example, the chip 61 and the organic substrate 62 are encased within a plastic encapsulant 63. Examples of such an embodiment are PBGA (plastic ball grid array), TBGA (tape ball grid array), etc.
Further, the SBOB technique can be used in the IC package 64 of Figure 6(b)where a metal lead frame 65 is moulded within a plastic encapsulant 66. Examples of such an arrangement are TSOP, TSSOP (thin shrink small outline package), SOP (small outline package), PQFP (plastic quad flat pack), PLCC (plastic lead chip carrier), TQFP (thin quad flat pack), QFN (quad flat non-leaded), etc.

Claims

Claims:
1. A method of connecting a first end of an electrically conductive lead to a surface of an electrically conductive bump formed on a contact of a die, wherein the first end is stitch bonded to the surface of the bump.
2. The method claimed in claim 1, wherein a second end of said lead is ball bonded to a contact element.
3. The method claimed in claim 1, wherein a plurality of stacked dice have electrically conductive leads stitch bonded to conductive bumps formed on contacts of the dice.
4. A method for connecting an electrically conductive lead between a contact element and a contact pad of a die, the contact pad having an electrically conductive bump formed thereon, including the steps of:
(a) ball bonding a first end of the lead to the contact element; and
(b) stitch bonding a second end of the lead to said electrically conductive bump.
5. A method claimed in claim 4, wherein the contact element is a post
6. A method claimed in claim 4, wherein the contact element is a lead finger.
7. A method claimed in any one of claim 4, claim 5, or claim 6, wherein the contact pad, electrically conductive bump, electrically conductive lead and contact element are each one of a respective plurality of these, in which method each lead is ball bonded at the first end to a respective said contact element and stitch bonded at the second end to a respective said electrically conductive bump.
8. A method as claimed in any one of claims 4 to claim 7, wherein said die is an underlying one of a plurality of stacked dies.
9. A method as claimed in claim 7, wherein said die is an underlying one of a plurality of stacked dies, each having a said plurality of contact pads and electrically conductive bumps, in which method each of the stacked dies has a respective said lead ball bonded at the first end to a respective said contact element of that die, and stitch bonded at the second end to a said electrically conductive bump on a respective contact pad thereof.
10. A method for connecting a plurality of electrically conductive leads between a plurality of contact pads of a die and a plurality of lead fingers of an integrated circuit package, wherein each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads:
(a) a first end is ball bonded to a lead finger; and
(b) a second end is stitch bonded to an electrically conductive bump formed on the contact pad which corresponds to said lead finger.
11. A method of stacking a plurality of dice for an integrated circuit package, wherein each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including the steps of: (a) backgrounding each die in the plurality of dice;
(b) foπning an electrically conductive bump on each contact pad of each die of the plurality of dice;
(c) securing a first die of the plurality of dice to a substrate within the integrated circuit package; (d) connecting a first plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said first die and each lead finger of a second plurality of lead fingers, the second plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the first
. die, wherein for each lead of said first plurality of electrically conductive leads: (i) a first end is ball bonded to a lead finger of said second plurality of lead fingers of the integrated circuit package; and (ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die; (e) securing a second die of the plurality of dice to the top of the first mentioned die by means of a non-conductive adhesive;
(f) connecting a second plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said second die and each lead finger of a third plurality of lead fingers, the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of electrically conductive leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
(g) steps (e) and (f) are repeated for each die there after in the plurality of dice.
12. The method claimed in claim 11, wherein the plurality of dice includes two dice and said integrated circuit packaging is a TSOP.
13. The method claimed in any one of the preceding claims, wherein said electrically conductive bump is a gold bump.
14. Apparatus for connecting a first end of an electrically conductive lead to a surface of an electrically conductive bump formed on a contact of a die, the apparatus having means
. for stitch bonding the lead to the surface of the bump.
15. The apparatus claimed in claim 14, having means for ball bonding the lead to a lead finger.
16. The apparatus claimed in claim 14 or claim 15, wherein said ball bonding is effected by forming a ball on the electrically conductive lead by passing a high voltage electric spark past an end of the electrically conductive lead and pressing the ball against the lead finger.
17. Apparatus for connecting an electrically conductive lead between a contact pad of a die and a corresponding post lead finger of an integrated circuit package, wherein the contact pad has an electrically conductive bump formed thereon, including means for:
(a) ball bonding a first end of the electrically conductive lead to the lead finger; and
(b) stitch bonding a second end of the electrically conductive lead to said electrically conductive bump.
18. Apparatus for connecting a plurality of leads between a plurality of contact pads of a die and a plurality of lead fingers of an integrated circuit package, wherein each contact pad of the plurality of contact pads has a corresponding lead finger, and each contact pad of the plurality of contact pads has an electrically conductive bump formed thereon, and wherein for each lead of the plurality of leads means is provided for: (a) ball bonding a first end of the lead to a respective to a respective said lead finger; and
(b) stitch bonding a second end of the lead to a respective said electrically conductive bump.
19. Apparatus for stacking a plurality of dice for an integrated circuit package, wherein each die of said plurality of dice includes a plurality of contact pads and the integrated circuit package includes a first plurality of lead fingers, including means for:
(a) backgrounding each die in the plurality of dice;
(b) forming an electrically conductive bump on each contact pad of each die of the plurality of dice;
(c) securing a first die of the plurality of dice to a substrate within the integrated circuit package;
(d) connecting a first plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said first die and each lead finger of a second plurality of lead fingers, the second plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the first die, wherein for each lead of said first plurality of electrically conductive leads:
(i) a first end is ball bonded to a lead finger of said second plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said first die, wherein said a lead finger of the second plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said first die;
(e) securing a second die of the plurality of dice to the top of the first mentioned die by means of a non-conductive adhesive; (f) connecting a second plurality of electrically conductive leads between each contact pad of the plurality of contact pads of said second die and each lead finger of a third plurality of lead fingers, the third plurality of lead fingers includes lead fingers of the first plurality of lead fingers which correspond to the plurality of contact pads of the second die, wherein for each lead of said second plurality of leads: (i) a first end is ball bonded to a lead finger of said third plurality of lead fingers of the integrated circuit package; and
(ii) a second end is stitch bonded to an electrically conductive bump formed on a contact pad of said plurality of contact pads of said second die, wherein said a lead finger of the third plurality of lead fingers of the integrated circuit package corresponds to said a contact pad of said plurality of contact pads of said second die;
(g) steps (e) and (f) are repeated for each die there after in the plurality of dice.
20. The apparatus claimed in claim 19, wherein the plurality of dice includes two dice and said integrated circuit packaging is a TSOP.
21. The apparatus claimed in any one claims 14 to claim. -20, wherein said electrically conductive bump is a gold bump.
22. A die having a lead bonded thereto by the method of any one of claims 1 to 3.
23. A die having a conductive pad connected to a conductive element by the method claimed in any one of claims 4 to 8.
24. A die having contact pads connected to conductive elements by the method claimed in claim 9.
25. A die having contact pads connected to lead fingers by the method claimed in claim 10.
26. Stacked dice produced by the method of any one of claims 11 to 13.
PCT/SG2001/000055 2001-04-05 2001-04-05 Method of forming electrical connections WO2002082527A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003061003A1 (en) * 2002-01-04 2003-07-24 Sandisk Corporation Reverse wire bonding techniques
US6650013B2 (en) 2001-08-29 2003-11-18 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
US7691680B2 (en) 2003-03-04 2010-04-06 Micron Technologies, Inc. Method of fabricating microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
US7741208B2 (en) 2006-03-30 2010-06-22 Oerlikon Assembly Equipment Ltd. Method for making a wedge wedge wire loop

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293626A (en) * 1988-05-23 1989-11-27 Ricoh Co Ltd Wire bonding method in flexible wiring board
EP0397426A2 (en) * 1989-05-09 1990-11-14 Citizen Watch Co., Ltd. IC packaging structure and packaging method
JPH05211192A (en) * 1991-07-02 1993-08-20 Oki Electric Ind Co Ltd Wire binding method of semiconductor device
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293626A (en) * 1988-05-23 1989-11-27 Ricoh Co Ltd Wire bonding method in flexible wiring board
EP0397426A2 (en) * 1989-05-09 1990-11-14 Citizen Watch Co., Ltd. IC packaging structure and packaging method
JPH05211192A (en) * 1991-07-02 1993-08-20 Oki Electric Ind Co Ltd Wire binding method of semiconductor device
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 082 (E - 0889) 15 February 1990 (1990-02-15) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 649 (E - 1468) 2 December 1993 (1993-12-02) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650013B2 (en) 2001-08-29 2003-11-18 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
US6864166B1 (en) 2001-08-29 2005-03-08 Micron Technology, Inc. Method of manufacturing wire bonded microelectronic device assemblies
WO2003061003A1 (en) * 2002-01-04 2003-07-24 Sandisk Corporation Reverse wire bonding techniques
US7691680B2 (en) 2003-03-04 2010-04-06 Micron Technologies, Inc. Method of fabricating microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
US7741208B2 (en) 2006-03-30 2010-06-22 Oerlikon Assembly Equipment Ltd. Method for making a wedge wedge wire loop

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