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WO2002049114A2 - High withstand voltage semiconductor device - Google Patents

High withstand voltage semiconductor device Download PDF

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Publication number
WO2002049114A2
WO2002049114A2 PCT/JP2001/010852 JP0110852W WO0249114A2 WO 2002049114 A2 WO2002049114 A2 WO 2002049114A2 JP 0110852 W JP0110852 W JP 0110852W WO 0249114 A2 WO0249114 A2 WO 0249114A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
withstand voltage
high withstand
carrier injection
Prior art date
Application number
PCT/JP2001/010852
Other languages
French (fr)
Other versions
WO2002049114A3 (en
Inventor
Katsunori Asano
Yoshitaka Sugawara
Ranbir Singh
Original Assignee
The Kansai Electric Power Co., Inc.
Cree, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Kansai Electric Power Co., Inc., Cree, Inc. filed Critical The Kansai Electric Power Co., Inc.
Publication of WO2002049114A2 publication Critical patent/WO2002049114A2/en
Publication of WO2002049114A3 publication Critical patent/WO2002049114A3/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 

Definitions

  • the present invention relates to a high withstand voltage power semiconductor device for controlling large current .
  • a wide-gap semiconductor material such as silicon carbide ( SiC )
  • SiC silicon carbide
  • SiC silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • the impurity diffusion coefficient of SiC is far lower than that of Si .
  • advanced technology is required to produce semiconductor devices by using SiC.
  • a high withstand voltage diode having a planar structure is available as a conventional example of a wide-gap high withstand voltage semiconductor device of SiC and has a withstand voltage of about 3.4 kV .
  • This high withstand voltage diode was disclosed on pages 136 to 137 of the preliminary manuscript collection for the 1997 International Conference on Silicon Carbide, Ill-Nitride and Related Materials.
  • a cathode electrode 50 is formed on one face of a drain region 1 of n-type SiC, an n-type drift layer 2 is formed on the other face thereof, and a p-type layer 3 is formed at the central portion of the n-type drift layer 2.
  • the p-type layer 3 is provided with an anode electrode 51.
  • a p-type layer 34 for termination is formed on both sides of the p-type layer 3.
  • “Termination” is an act of obtaining a special structure at the regions near the end portions of a high withstand voltage semiconductor device in order to prevent electric field concentration at the end portions.
  • the pn-junction between the n-type drift layer 2 and the p-type layer 3 serves as carrier injection to flow current, and the pn-junction between the drift layer 2 and the p-type layer 34 serves as the termination to reduce electric field concentration.
  • Both the ,pn- junctions are formed by ion implantation technology for implanting ions , such as boron ions, aluminum ions or the like.
  • a high withstand voltage diode shown in the sectional view of FIG. 10 is also available as another conventional example.
  • the pn-junction for carrier injection between a p-type layer 13 and an n-type drift layer 2 is formed by the epitaxial growth technology, and a termination region T for reducing electric field concentration is formed by the mesa etching method.
  • the withstand voltage of the diode is about 4.5 kV .
  • This high withstand voltage diode was disclosed on pages 1561 to 1563 of the Applied Physics Letter, Volume 67, 1995. This high withstand voltage diode is produced as described below.
  • Both end portions of the p-type epitaxial layer 13 having a thickness of 1.5ftm and formed on the entire face of the n-type drift layer 2 are eliminated up to 2 U m in depth by the mesa etching method as shown in the sectional view of FIG. 10.
  • a passivation film covers the surface of the structure except for the portion having an anode electrode 51.
  • FIG. 11 is a sectional view showing a high withstand voltage diode described on pages 1600 to 1601 of the lecture paper collection [4] for the 2000 Nationalwide Convention of the Institute of Electrical Engineers of Japan.
  • a p-type layer 3 is formed by the epitaxial growth technology, and an anode electrode 51 is formed on the p-type layer 3.
  • a pn-junction for carrier injection is formed between the p-type layer 3 and the n-type drift layer 2.
  • the right region of the figure is subjected to mesa etching at a shallow depth in order to reduce electric field concentration at the end portions of the semiconductor device.
  • a p-type layer 44 is formed by implanting ions, such as boron ions, aluminum ions or the like, near a mesa bottom face ' 18 thereby to form a pn-junction in the n-type drift layer 2.
  • a passivation film 6 having a thickness of about 0.4 li m protects the termination region T and other regions except for the anode electrode 51 on the p-type layer 3.
  • the p-type layer 3 is formed by ion implantation, whereby crystal defects are formed in the p-type layer 3 and its surroundings . For this reason, the efficiency of carrier injection is low at the time of a forward bias (when the anode 51 is positive) , and an ON voltage is relatively high. In addition, a leak current is large at the time of a reverse bias. It is therefore difficult to realize a high withstand voltage semiconductor device having a low loss.
  • the diode shown in FIG. 10 since the p-type layer 3 is formed by the epitaxial growth method, there are small number of crystal defects, and the efficiency of carrier injection at the time of a forward bias is relatively high.
  • the leak current at the time of a reverse bias is relatively small, about 5 x 10 "3 A/cm 2 .
  • the diode is broken. It is therefore impossible to assert that this diode is a high withstand voltage semiconductor device .
  • the diode shown in FIG. 11 since the p-type layer 3 is formed by the epitaxial growth method, there are small number of crystal defects, and the efficiency of carrier injection at the time of a forward bias is relatively high. Furthermore, the leak current at the time of a reverse bias is small, about 1 x 10 "3 A/cm 2 .
  • the withstand voltage of the diode is high , 5.8 kV . However, since a strong electric field is applied to the passivation film 6 of the mesa corner portion 6A, the diode is apt to cause trouble and cannot maintain its high reliability for a long time.
  • the present invention is intended to provide a highly reliable semiconductor device having a low ON voltage and a high withstand inverse voltage.
  • the value of its critical electric field is close to the dielectric breakdown electric field value of a passivation film. If the passivation film is exposed to a strong electric field for a long time, the leak current of the semiconductor device increases, and the reliability of the semiconductor device is lowered. Accordingly, the present invention is intended to solve these problems.
  • a high withstand voltage semiconductor device in accordance with the present invention comprises a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion, and a surface protection film formed on the termination portion and the carrier injection layer, the thickness of which is made larger at the boundary portion of the termination portion and the carrier injection layer.
  • the surface protection film is made thicker at the boundary portion of the termination portion and the carrier injection layer, the electric field strength at the boundary portion is not so higher than, those of other portions. As a result, the reliability of the device is improved in the use for a long period of time.
  • a high withstand voltage semiconductor device in accordance with another aspect of the present invention comprises a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion and the boundary portion of the termination portion and the carrier injection layer, and a surface protection film formed on the termination portion and the carrier injection layer.
  • a depletion region expands from the junction of the layer of the second conductive type and the drift layer near the boundary portion to the substrate. This depletion region reduces electric field concentration to the passivation film of the boundary portion, whereby the semiconductor device has high withstand voltage.
  • a high withstand voltage semiconductor device in accordance with still another aspect of the present invention comprises a drift layer of a first conductive type formed on a face of a substrate of a wide-gap semiconductor material having a drain electrode on the other face , a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a source region of the first conductive type formed on a part of the carrier injection layer, a trench formed so as to pass through the source region and the carrier injection layer and reach the drift layer, a gate electrode formed on the inner wall faces of the trench via an insulation film, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion and the boundary portion of the termination portion and the carrier injection layer, a source electrode formed on the source region and the carrier injection region, and a surface protection film formed on the termination portion and the side face of the carrier injection layer
  • the layer of the second conductive type is formed at the boundary portion of the termination portion and the carrier injection layer, electric field concentration near the boundary portion can be reduced.
  • FIG. 1 is a sectional view showing a pn diode in accordance with a first embodiment of the present invention
  • FIG. 2 is a sectional view showing a pn diode in accordance with a second embodiment of the present invention ;
  • FIG. 3 is a sectional view showing a pn diode in accordance with a third embodiment of the present invention.
  • FIG. 4 is a sectional view showing a pn diode in accordance with a fourth embodiment of the present invention.
  • FIG. 5 is a sectional view showing a pn diode in accordance with a fifth embodiment of the present invention.
  • FIG. 6 is a sectional view showing a pn diode in accordance with a sixth embodiment of the present invention.
  • FIG. 7 is a sectional view showing a MOSFET in accordance with a seventh embodiment of the present invention.
  • FIG. 8 is a sectional view showing an IGBT in accordance with an eighth embodiment of the present invention .
  • FIG. 9 is the sectional view showing the pn diode in accordance with the conventional example.
  • FIG . 10 is the sectional view showing the pn diode in accordance with another conventional example.
  • FIG .11 is the sectional view showing the pn diode in accordance with still another conventional example.
  • FIG. ltoFIG.8 Preferred embodiments of the present invention will be described below referring toFIG. ltoFIG.8.
  • FIG. 8 are sectional views each showing the right half of a semiconductor device in accordance with each embodiment.
  • the left half having a structure symmetrical with that of the right half is not shown.
  • each semiconductor device has a stripe shape extending in a direction perpendicular to the paper face of each figure.
  • FIG. 1 is a sectional view showing a SiC (silicon carbide) pn diode having a withstand voltage of 6.5 kV in accordance with a first embodiment of the present invention .
  • an n-type SiC drift . layer 2 having a thickness of about 50 im and a low impurity concentration is formed on an n-type SiC drain region 1 having a thickness of about 350 i and a high impurity concentration and also having a cathode electrode 50 formed on the bottom face.
  • a p-type layer 3 for carrier injection having a thickness of about
  • the drift layer 2 is etched at a shallow depth by the reactive ion etching method, a kind of mesa etching method, to form a termination region T.
  • Boron ions, aluminum ions or the like are implanted on the face of the termination region T to form a p-type termination region ( termination portion) 4.
  • An n-type channel stopper 5 is formed at the right end of the termination region T.
  • a passivation film 16 of a thin film of silicon dioxide, silicon nitride or the like is formed on the entire face including the surface of the p-type termination region 4 as a surface protection film.
  • the thickness of the most portion of the passivation film 16 isabout0.4Aim.
  • the thickness of the passivation film 16 is made far larger to 1 to 2 Aim.
  • the region between the mesa corner portion 20 and a position A in the termination region T located sufficiently away from the mesa corner portion 20 is covered with the passivation film 16, the thickness of which is larger than the distance L between a mesa bottom face 18 and the junction face 3A of the p-type layer 3 and the drift layer 2.
  • the mesa angle ⁇ formed by the side face of the carrier injection layer 3 and the mesa bottom face 18 is in the range of 100 to 150 degrees. Since the p-type layer 3 of the SiC pn diode in accordance with this embodiment is formed by the epitaxial growth method, there are small number of crystal defects.
  • a forward bias when a voltage is applied in the forward direction (hereinafter referred to as a forward bias), sufficiently large amount of holes are injected from the p-type layer 3 to the n-type drift layer 2. As a result, a conductivity modulation occurs and the ON voltage lowers .
  • the current per unit area (current density) was 100 A/cm 2
  • the ON voltage was 4.9V.
  • a reverse bias When a voltage is applied in the reverse direction (hereinafter referred to as a reverse bias ) , a depletion region expands from the junction face 3A of the p-type layer 3 and the n-type drift layer
  • the depletion region expanding in the drift layer 2 further expands to the right end area in the figure by the action of the p-type termination region 4.
  • a high withstand inverse voltage is obtained by this depletion region. If the p-type termination region 4 has a high impurity concentration, electric field concentration occurs at the end portion 4A of the p-type termination region 4 located away from the mesa corner portion 20. On the other hand, if the p-type termination region 4 has a low impurity concentration, the electric field strength at the p-type region 3. and the passivation film 16 near the mesa corner portion 20 becomes high.
  • the depletion region does not expand so widely in the p-type layer 3 near the mesa corner portion 20, and electric field concentration occurs at the mesa corner portion 20.
  • the mesa angle ⁇ is 150 degrees or more , the electric field concentration at the mesa corner portion 20 is reduced. However, electric field concentration occurs at the passivation film 16, and the electric field strength raises inside the drift layer 2 near the mesa corner portion 20 by mutual actions.
  • the impurity concentration at the p-type termination region 4 is in the range of 10 16 to 10 18 at /cm 3 and the mesa angle is in the range of 100 to 150 degrees, a high withstand voltage of 6.5 V is obtained.
  • the depletion region expands to the entire region of the p-type termination region 4 at a cathode voltage of 6 kV.
  • the voltage is shared by the entire region of the p-type termination region 4 , whereby it is possible to obtain a high withstand voltage diode.
  • the passivation film 16 at the mesa corner portion 20 is as thin as the passivation film 6 of the conventional example shown in FIG. 9, the electric field strength at the mesa corner portion 20 becomes as high as the critical electric field strength of SiC, that is, 2 MV/cm.
  • the passivation film 16 at the mesa corner portion 20 is made thicker in the range of 1 to 2 Aim by using PSG (phosphor-silicate glass) or the like. With this configuration, the electric field strength at the mesa corner portion 20 can be reduced to 1 MV/cm or less, and the reliability in the use for a long period of time can be improved.
  • the passivation film 16 may be formed of two or more kinds of materials.
  • FIG. 2 is a sectional view showing a SiC pn diode having a withstand voltage of 6.5 kV in accordance with a second embodiment of the present invention .
  • the thickness of a passivation film 26 is made far larger than the distance L between the mesa bottom face 18 and the junction face 3A on the entire region of the termination region T. It is preferable that the thickness is in the range of 0.5
  • the thickness may be 3 Ai m or more.
  • Other configurations are substantially the same as those of the first embodiment. Since the passivation film 26 is made thick, electric field concentration at the mesa corner portion 20 can be reduced, and the device can have high withstand voltage. In addition, it is possible to reduce local electric field concentration at the surfaces of the drift region 2 and the p-type termination region 4 owing to alkaline ions, such as Na ions, attaching to the surface of the passivation film 26. Furthermore, even if moisture or the like attaches to the surface of the passivation film 26, it does not enter the inside, thereby not affecting the inside. As a result, the reliability of the high withstand voltage semiconductor device of the second embodiment is further improved in the use for a long period of time. ( ⁇ Third embodiment))
  • FIG. 3 is a sectional view showing a SiC pn diode having a withstand voltage of 6.9 kV in accordance with a third embodiment of the present invention.
  • a p-type termination region 14 is extended to the mesa corner portion 20.
  • the left end of the p-type termination region 14 is required to be disposed away from the p-type layer 3 in order to improve forward-direction characteristics.
  • the left end of the p-type termination region 14 may be joined to the p-type layer 3 by carrying out ion implantation for forming the p-type termination region 14 in proximity to the mesa corner portion 20 in the esa inclinedregion .
  • adiodehaving this configuration was produced by way of trial. Changes in the forward-direction characteristics of the diode were examined in a first case when the left end of the p-type termination region 14 was joined to the p-type layer 3 and in a second case when there was no junction therebetween. As the result of the experiment , there is no difference between the first case and the second case in the forward-direction characteristic. It is thus found that no adverse effect occur even when the p-type termination region 14 is joined to the p-type layer 3.
  • a passivation film 6 having a thickness, of about 0.4 A m is formed on the entire face of the termination region T including the p-type termination region 14.
  • Other configurations are substantially the same as those of the first embodiment.
  • a depletion region also expands from the junction portion of the p-type termination region 14 and the n-type drift layer 2 near the mesa corner portion 20 to the cathode electrode 50. By this depletion region, electric field concentration to the passivation film 6 at the mesa corner portion 20 is reduced, and the device can have high withstand voltage.
  • the electric field strength of the passivation film 6 at the mesa corner portion 20 was 0.19 MV/cm. Therefore, the strength in the case of this embodiment is lower by about 15% than the strength in the case of the diode of the conventional example, i.e. , about 1.3 MV/cm. As a result, the high withstand voltage semiconductor device of this embodiment can have a high withstand voltage and can attain higher reliability. ((Fourth embodiment))
  • FIG. 4 is a sectional view showing a SiC pn diode having a withstand voltage of 6.9 kV in accordance with a fourth embodiment of the present invention.
  • the thickness of the passivation film 26 covering the entire region of the termination region T is made far larger than the distance L between the mesa bottom face 18 and the junction face 3A.
  • the thickness is in the range of 2 Aim to 3 Ai m .
  • the thickness may be 3 Ai m or more.
  • Other configurations are substantially the same as those of the first embodiment. Since the passivation film 26 is made thick, electric field concentration at the mesa corner portion 20 can be reduced.
  • FIG. 5 is a sectional view showing a SiC pn diode having a withstand voltage of 7.5 kV in accordance with a fifth embodiment of the present invention.
  • the p-type termination region 14 in the third embodiment shown in FIG. 3 is divided into two regions 14A and 14B. Other configurations are the same as those of the third embodiment.
  • the impurity concentration of the region 14A located near the mesa corner portion 20 is made higher than the impurity concentration of the region 14B located away from the mesa corner portion 20.
  • the depletion region expands to the entire p-type termination region 14, that is, the regions 14A and 14B, and the regions 14A and 14B share the voltage in the case when the impurity concentration of the p-type termination region 14 is about 5 x 10 17 atm/cm 3 or less.
  • This configuration can therefore prevent electric field concentration at the end portion 14C of the p-type termination region 14A, and the diode can have high withstand voltage.
  • the impurity concentration of the p-type termination region is more than about 5 x lO 17 atm/cm 3
  • a depletion region expands in the region 14B, but no depletion region expands to the upper layer portion of the region 14A.
  • the voltage is thus shared by the region 14B and the lower layer portion of the region 14A. Therefore, a high voltage is not applied to the mesa corner portion 20, and electric field concentration is reduced at the mesa corner portion 20 in the passivation film 6. As a result , a highly reliable diode can be obtained.
  • FIG. 6 is a sectional view showing a SiC pn diode having a withstand voltage of 7.5 kV in accordance with a sixth embodiment of the present invention.
  • the p-type termination region 14 in the third embodiment shown in FIG. 3 is divided into plural regions, for example, four regions 14D, 14E, 14F and 14G.
  • the regions 14D, 14E, 14F and 14G are separated from one another.
  • the regions 14D, 14E, 14F and 14G may have the same size, it is preferable that the region 14D near the mesa corner portion 20 is larger than the other regions 14E to 14G.
  • the regions 14D to 14G have nearly the same impurity concentration.
  • the regions 14D to 14G may have impurity concentrations different from one another.
  • Other configurations are the same as those of the third embodiment.
  • a positive voltage is applied to the cathode electrode 50 of the diode in this embodiment, a depletion region expands from the region 14D to the region 14G of the p-type termination region 14, and the diode withstands the inverse voltage by this depletion region.
  • the withstand voltage of the diode rose as the number of the p-type regions 14D to 14G increased.
  • FIG. 7 is a sectional view showing an n-channel SiC MOSFET having a withstand voltage of 2500 V in accordance with a seventh embodiment of the present invention.
  • an n-type drain region 11 is about 200 Aim thick and has a high impurity concentration.
  • a drain electrode 52 is provided on the lower face of the n-type drain region 11.
  • the n-type drift layer 2 formed on the drain region 11 is about 20 Aim thick.
  • a p-type body layer 33 formed on a part of the n-type drift layer 2 is about 4 Ai m thick.
  • an n-type source region 7 formed on a part of the p-type body layer 33 is about 0.5 Ai m thick.
  • a trench 60 is formed at the nearly central position of the p-type body layer 33.
  • the depth of the trench 60 is about 6 Ai m, and the width thereof is about 3 Aim.
  • the thickness of a gate insulation layer 8 in the trench 60 is about 1 Ai m at the bottom of the trench 60 and about 0.1 Ai m at the side thereof .
  • the trench 60 and the gate electrode 54 of this embodiment have a stripe shape extending in a direction perpendicular to the paper face of the figure, the shape may be circular, square or the like.
  • an h-type SiC substrate having an impurity concentration of 10 18 to 10 zo atm/cm 3 is prepared, and functions as the drain region 11.
  • The' SiC n-type drift layer 2 having an impurity concentration of 10 15 to 10 16 atm/cm 3 is formed on the upper face of the drain region 11 by epitaxial growth.
  • the SiC p-type body layer having an impurity concentration of about 10 16 atm/cm 3 is formed on the entire n-type drift layer 2 by the vapor phase growth method or the like.
  • a right-hand portion of the p-type body layer is removed by the mesa etching method so that the left-hand portion of the p-type body layer 33 remains, thereby forming the termination region T.
  • the p-type termination region 14 having an impurity concentration of 10 16 to 10 18 atm/cm 3 is formed in the termination region
  • the n-type source region 7 having an impurity concentration of about 10 18 atm/cm 3 is formed at the central region of the remaining p-type body layer 33 by implantation of, nitrogen ions, phosphor ions, etc.
  • the trench 60 is formed by the anisotropic etching method so as to pass through the p-type body layer 33 and reaching the n-type drift layer 2.
  • the gate insulation film 8 of Si0 2 is formed on the inner wall faces of the trench 60, polysilicon including phosphor at a high concentration is heaped up so as to be embedded in the trench 60.
  • the polycilicon in the trench 60 is removed inamanner that the ilm of the polysilicon remains on the inner wall of the trench 60, thereby forming the gate electrode 54 of the polysilicon ilm.
  • a source electrode 53 of aluminum, nickel or the like is formed on the surfaces of the n-type region 7 and the p-type body layer 33.
  • the passivation film 26 having a thickness of 0.5 Ai m or more is formed on the termination region T, thereby completing the production.
  • the left end portion of the p-type termination region 14 covers the mesa corner portion 20 in the configuration shown in FIG. 7, the left end portion is not always required to cover the mesa corner portion. Since the thickness of the passivation film 26 is 0.5 Aim or more and is larger than the distance L between the mesa bottom face 18 and the junction face 33A of the p-type body layer 33 and the n-type drift layer 2, it is possible to reduce the electric field concentration near the mesa corner portion 20 of the passivation film 26. In addition, it is possible to reduce the effect of alkaline ions, such as Na ions, attaching to the surface, of the passivation film 26 and producing local electric field concentration on the SiC substrate face.
  • alkaline ions such as Na ions
  • the effect due to moisuture attached on the passivation film 26 is limited to the vicinity of the surface thereof, and does not affect the inside.
  • the p-type body layer 33 is formed by the epitaxial growth method, crystal defects are very scarce.
  • the mobility in a channel region formed on the interface between the p-type body layer 33 and the gate insulation film 8 has a high value of 83 cm 2 /Vs . ((Eighth embodiment))
  • FIG. 8 is a sectional view showing a SiC IGBT having a withstand voltage of 8500 V in accordance with an eighth embodiment of the present invention.
  • a collector electrode 62 is formed on one face of the collector region 12 of a SiC p-type substrate .
  • the drift layer 2 is also formed on the other face of the collector region 12.
  • the thickness of the drift layer 2 is about 70 Aim, and the impurity concentration thereof is about 5 x 10 14 atm/cm 3 . Since the p-type body layer 33 is formed by the epitaxial growth metho similar to the case of the MOSFET of the ifth embodiment , the layer has very few crystal defects.
  • An emitter region 57 is formed on a part pf the p-type body layer 33 , and an emitter electrode 63 is provided on the emitter region 57.
  • the mobility in a channel region formed on the interface between the p-type body layer 33 and the gate insulation film 8 has a high value of 92 cm 2 /Vs during ON-state. Since holes are injected from the collector region 12 into the drift layer 2 during the ON-state, the conductivity modulation occurs and the ON voltage can be lowered. When the current density is 100 A/cm 2 , the ON voltage is 4.3 V.
  • the present invention is not limited to the above-mentioned embodiments but covers more application ranges or derivative structures.
  • the present invention is effectively applicable to semiconductor devices of other wide-gap semiconductor materials, such as diamond, gallium nitride, etc.
  • the semiconductor devices of which the drift layer 2 is an n-type are taken as an example in the above-mentioned first to eighth embodiments.
  • the configuration of the present invention is also applicable by changing the n-type region of another element to a p-type region and by changing the p-type region of the element to an n-type region.
  • the present invention is applicable to all semiconductor devices having a p-type region (or an n-type region) in the inclined face and the drift layer at the mesa corner portion 20.
  • the passivation film is formed of a film of two or more kinds of materials, the configuration of the present invention is applicable.
  • the angle formed by the inclined face of the p-type layer and the face of the termination region near the mesa corner portion is an obtuse angle.
  • the impurity concentration of the p-type layer is within a predetermined range, and the thickness of the passivation film at least at themesa corner portion is made larger than the distance between mesa bottom face and the junction face of the p-type layer and the n-type drift layer.

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Abstract

A semiconductor device provided with a p-type layer (3) for carrier injection formed by the epitaxial method, a mesa structure portion for reducing electric field concentration at the time of a reverse bias and JTE formed by ion implantation, wherein a mesa inclined face disposed in the shortest distance from the corner portion of a passivation film (16) formed of an inorganic film and a mesa bottom face (18) are formed of a p-type layer, the impurity concentration of the p-type layer formed at the mesa corner portion (20) and on the mesa bottom face (18) is within a predetermined range, and the thickness of the passivation film at least at the mesa corner portion is 0.5 νm or more, thereby to have a high withstand voltage and a low ON voltage.

Description

DESCRIPTION
High withstand voltage semiconductor device
TECHNICAL FIELD
The present invention relates to a high withstand voltage power semiconductor device for controlling large current . BACKGROUND ART
A wide-gap semiconductor material, such as silicon carbide ( SiC ) , is excellent in dielectric breakdown electric field strength, about 10 times as high as that of silicon (Si) , and receives attention as a material suited for high withstand voltage power semiconductor devices having high withstand inverse voltage characteristics. However, the impurity diffusion coefficient of SiC is far lower than that of Si . For this reason, advanced technology is required to produce semiconductor devices by using SiC. In particular, it has been difficult to realize high withstand voltage semiconductor devices having high withstand voltage pn- junctions .
A high withstand voltage diode having a planar structure, as shown in the sectional view of FIG. 9 for example, is available as a conventional example of a wide-gap high withstand voltage semiconductor device of SiC and has a withstand voltage of about 3.4 kV . This high withstand voltage diode was disclosed on pages 136 to 137 of the preliminary manuscript collection for the 1997 International Conference on Silicon Carbide, Ill-Nitride and Related Materials. In this conventional example, a cathode electrode 50 is formed on one face of a drain region 1 of n-type SiC, an n-type drift layer 2 is formed on the other face thereof, and a p-type layer 3 is formed at the central portion of the n-type drift layer 2. The p-type layer 3 is provided with an anode electrode 51. A p-type layer 34 for termination is formed on both sides of the p-type layer 3. "Termination" is an act of obtaining a special structure at the regions near the end portions of a high withstand voltage semiconductor device in order to prevent electric field concentration at the end portions. The pn-junction between the n-type drift layer 2 and the p-type layer 3 serves as carrier injection to flow current, and the pn-junction between the drift layer 2 and the p-type layer 34 serves as the termination to reduce electric field concentration. Both the ,pn- junctions are formed by ion implantation technology for implanting ions , such as boron ions, aluminum ions or the like.
A high withstand voltage diode shown in the sectional view of FIG. 10 is also available as another conventional example. In this conventional example, the pn-junction for carrier injection between a p-type layer 13 and an n-type drift layer 2 is formed by the epitaxial growth technology, and a termination region T for reducing electric field concentration is formed by the mesa etching method. The withstand voltage of the diode is about 4.5 kV . This high withstand voltage diode was disclosed on pages 1561 to 1563 of the Applied Physics Letter, Volume 67, 1995. This high withstand voltage diode is produced as described below. Both end portions of the p-type epitaxial layer 13 having a thickness of 1.5ftm and formed on the entire face of the n-type drift layer 2 are eliminated up to 2 U m in depth by the mesa etching method as shown in the sectional view of FIG. 10. In order to protect the surface, a silicon dioxide film 10 having a thickness of
0.4 m (hereinafter referred to as a passivation film) covers the surface of the structure except for the portion having an anode electrode 51.
FIG. 11 is a sectional view showing a high withstand voltage diode described on pages 1600 to 1601 of the lecture paper collection [4] for the 2000 Nationwide Convention of the Institute of Electrical Engineers of Japan. In the figure, in the left region of an n-type drift layer 2 formed on a drain region 1 of n-type SiC, a p-type layer 3 is formed by the epitaxial growth technology, and an anode electrode 51 is formed on the p-type layer 3. As a result, a pn-junction for carrier injection is formed between the p-type layer 3 and the n-type drift layer 2. The right region of the figure is subjected to mesa etching at a shallow depth in order to reduce electric field concentration at the end portions of the semiconductor device. A p-type layer 44 is formed by implanting ions, such as boron ions, aluminum ions or the like, near a mesa bottom face' 18 thereby to form a pn-junction in the n-type drift layer 2. A passivation film 6 having a thickness of about 0.4 li m protects the termination region T and other regions except for the anode electrode 51 on the p-type layer 3.
In the case of the high withstand voltage diode having a planar structure shown in FIG. 9 , the p-type layer 3 is formed by ion implantation, whereby crystal defects are formed in the p-type layer 3 and its surroundings . For this reason, the efficiency of carrier injection is low at the time of a forward bias (when the anode 51 is positive) , and an ON voltage is relatively high. In addition, a leak current is large at the time of a reverse bias. It is therefore difficult to realize a high withstand voltage semiconductor device having a low loss.
In the case of the diode shown in FIG. 10, since the p-type layer 3 is formed by the epitaxial growth method, there are small number of crystal defects, and the efficiency of carrier injection at the time of a forward bias is relatively high. The leak current at the time of a reverse bias is relatively small, about 5 x 10"3 A/cm2. However, if the inverse voltage slightly exceeds 4.5 kV, the diode is broken. It is therefore impossible to assert that this diode is a high withstand voltage semiconductor device .
In the case of the diode shown in FIG. 11, since the p-type layer 3 is formed by the epitaxial growth method, there are small number of crystal defects, and the efficiency of carrier injection at the time of a forward bias is relatively high. Furthermore, the leak current at the time of a reverse bias is small, about 1 x 10"3 A/cm2. The withstand voltage of the diode is high , 5.8 kV . However , since a strong electric field is applied to the passivation film 6 of the mesa corner portion 6A, the diode is apt to cause trouble and cannot maintain its high reliability for a long time.
DISCLOSURE OF INVENTION
The present invention is intended to provide a highly reliable semiconductor device having a low ON voltage and a high withstand inverse voltage. In particular, in the case of a wide-gap semiconductor material, such as SiC, the value of its critical electric field is close to the dielectric breakdown electric field value of a passivation film. If the passivation film is exposed to a strong electric field for a long time, the leak current of the semiconductor device increases, and the reliability of the semiconductor device is lowered. Accordingly, the present invention is intended to solve these problems.
A high withstand voltage semiconductor device in accordance with the present invention comprises a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion, and a surface protection film formed on the termination portion and the carrier injection layer, the thickness of which is made larger at the boundary portion of the termination portion and the carrier injection layer.
Since the surface protection film is made thicker at the boundary portion of the termination portion and the carrier injection layer, the electric field strength at the boundary portion is not so higher than, those of other portions. As a result, the reliability of the device is improved in the use for a long period of time.
A high withstand voltage semiconductor device in accordance with another aspect of the present invention comprises a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion and the boundary portion of the termination portion and the carrier injection layer, and a surface protection film formed on the termination portion and the carrier injection layer.
Since the layer of the second conductive type is formed at the boundary portion of the termination portion and the carrier injection layer, a depletion region expands from the junction of the layer of the second conductive type and the drift layer near the boundary portion to the substrate. This depletion region reduces electric field concentration to the passivation film of the boundary portion, whereby the semiconductor device has high withstand voltage.
A high withstand voltage semiconductor device in accordance with still another aspect of the present invention comprises a drift layer of a first conductive type formed on a face of a substrate of a wide-gap semiconductor material having a drain electrode on the other face , a carrier injection layer of a second conductive type for carrier injection formed on the drift layer by the epitaxial growth method, a source region of the first conductive type formed on a part of the carrier injection layer, a trench formed so as to pass through the source region and the carrier injection layer and reach the drift layer, a gate electrode formed on the inner wall faces of the trench via an insulation film, a termination portion formed in an end portion of the semiconductor device to reduce electric field concentration at the end portion at the time of application of an inverse voltage across the substrate and the carrier injection layer, a layer of the second conductive type formed in the termination portion and the boundary portion of the termination portion and the carrier injection layer, a source electrode formed on the source region and the carrier injection region, and a surface protection film formed on the termination portion and the side face of the carrier injection layer.
Since the layer of the second conductive type is formed at the boundary portion of the termination portion and the carrier injection layer, electric field concentration near the boundary portion can be reduced.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a sectional view showing a pn diode in accordance with a first embodiment of the present invention;
FIG. 2 is a sectional view showing a pn diode in accordance with a second embodiment of the present invention ;
FIG. 3 is a sectional view showing a pn diode in accordance with a third embodiment of the present invention;
FIG. 4 is a sectional view showing a pn diode in accordance with a fourth embodiment of the present invention;
FIG. 5 is a sectional view showing a pn diode in accordance with a fifth embodiment of the present invention;
FIG. 6 is a sectional view showing a pn diode in accordance with a sixth embodiment of the present invention;
FIG. 7 is a sectional view showing a MOSFET in accordance with a seventh embodiment of the present invention;
FIG. 8 is a sectional view showing an IGBT in accordance with an eighth embodiment of the present invention ;
FIG. 9 is the sectional view showing the pn diode in accordance with the conventional example;
FIG . 10 is the sectional view showing the pn diode in accordance with another conventional example; and
FIG .11 is the sectional view showing the pn diode in accordance with still another conventional example.
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the present invention will be described below referring toFIG. ltoFIG.8. FIG.
1 to FIG. 8 are sectional views each showing the right half of a semiconductor device in accordance with each embodiment. The left half having a structure symmetrical with that of the right half is not shown. Furthermore, each semiconductor device has a stripe shape extending in a direction perpendicular to the paper face of each figure.
{(First embodiment))
FIG. 1 is a sectional view showing a SiC (silicon carbide) pn diode having a withstand voltage of 6.5 kV in accordance with a first embodiment of the present invention . In the figure , an n-type SiC drift.layer 2 having a thickness of about 50 im and a low impurity concentration is formed on an n-type SiC drain region 1 having a thickness of about 350 i and a high impurity concentration and also having a cathode electrode 50 formed on the bottom face. A p-type layer 3 for carrier injection having a thickness of about
2 i m and a low impurity concentration is formed on the left portion of the drift layer 2 by the epitaxial growth method . The drift layer 2 is etched at a shallow depth by the reactive ion etching method, a kind of mesa etching method, to form a termination region T. Boron ions, aluminum ions or the like are implanted on the face of the termination region T to form a p-type termination region ( termination portion) 4. An n-type channel stopper 5 is formed at the right end of the termination region T. In order to prevent moisture or alkaline ions, such as Na ions, from attaching to the surface of the semiconductor device, a passivation film 16 of a thin film of silicon dioxide, silicon nitride or the like is formed on the entire face including the surface of the p-type termination region 4 as a surface protection film. The thickness of the most portion of the passivation film 16isabout0.4Aim. However , at the mesa corner portion 20 of the boundary portion between the p-type layer 3 and the termination region 4, the thickness of the passivation film 16 is made far larger to 1 to 2 Aim. Therefore, the region between the mesa corner portion 20 and a position A in the termination region T located sufficiently away from the mesa corner portion 20 is covered with the passivation film 16, the thickness of which is larger than the distance L between a mesa bottom face 18 and the junction face 3A of the p-type layer 3 and the drift layer 2. The mesa angle θ formed by the side face of the carrier injection layer 3 and the mesa bottom face 18 is in the range of 100 to 150 degrees. Since the p-type layer 3 of the SiC pn diode in accordance with this embodiment is formed by the epitaxial growth method, there are small number of crystal defects. Therefore, when a voltage is applied in the forward direction (hereinafter referred to as a forward bias), sufficiently large amount of holes are injected from the p-type layer 3 to the n-type drift layer 2. As a result, a conductivity modulation occurs and the ON voltage lowers . When the current per unit area (current density) was 100 A/cm2, the ON voltage was 4.9V. When a voltage is applied in the reverse direction (hereinafter referred to as a reverse bias ) , a depletion region expands from the junction face 3A of the p-type layer 3 and the n-type drift layer
2 to the cathode electrode 50 and the anode electrode 51 provided on the p-type layer 3. Since the p-type layer
3 has small crystal defects, it is possible to obtain a critical electric field value nearly equivalent to a theoretical value. As the applied voltage rises, the depletion region expanding in the drift layer 2 further expands to the right end area in the figure by the action of the p-type termination region 4. A high withstand inverse voltage is obtained by this depletion region. If the p-type termination region 4 has a high impurity concentration, electric field concentration occurs at the end portion 4A of the p-type termination region 4 located away from the mesa corner portion 20. On the other hand, if the p-type termination region 4 has a low impurity concentration, the electric field strength at the p-type region 3. and the passivation film 16 near the mesa corner portion 20 becomes high. If the mesa angle θ is 100 degrees or less, the depletion region does not expand so widely in the p-type layer 3 near the mesa corner portion 20, and electric field concentration occurs at the mesa corner portion 20. On the other hand , if the mesa angle θ is 150 degrees or more , the electric field concentration at the mesa corner portion 20 is reduced. However, electric field concentration occurs at the passivation film 16, and the electric field strength raises inside the drift layer 2 near the mesa corner portion 20 by mutual actions. When the impurity concentration at the p-type termination region 4 is in the range of 1016 to 1018 at /cm3 and the mesa angle is in the range of 100 to 150 degrees, a high withstand voltage of 6.5 V is obtained. In particular, when the impurity concentration at the p-type termination region 4 is about 5 x 1017 atm/cm3 or less, the depletion region expands to the entire region of the p-type termination region 4 at a cathode voltage of 6 kV. As a result, the voltage is shared by the entire region of the p-type termination region 4 , whereby it is possible to obtain a high withstand voltage diode. If the passivation film 16 at the mesa corner portion 20 is as thin as the passivation film 6 of the conventional example shown in FIG. 9, the electric field strength at the mesa corner portion 20 becomes as high as the critical electric field strength of SiC, that is, 2 MV/cm. For this reason, the leak current increases and other problems occur, thereby lowering the reliability in the use for a long period of time . In the present embodiment , the passivation film 16 at the mesa corner portion 20 is made thicker in the range of 1 to 2 Aim by using PSG (phosphor-silicate glass) or the like. With this configuration, the electric field strength at the mesa corner portion 20 can be reduced to 1 MV/cm or less, and the reliability in the use for a long period of time can be improved. The passivation film 16 may be formed of two or more kinds of materials.
((Second embodiment))
FIG. 2 is a sectional view showing a SiC pn diode having a withstand voltage of 6.5 kV in accordance with a second embodiment of the present invention . In the diode of the present embodiment, unlike the case of the diode in the first embodiment shown in FIG. 1, the thickness of a passivation film 26 is made far larger than the distance L between the mesa bottom face 18 and the junction face 3A on the entire region of the termination region T. It is preferable that the thickness is in the range of 0.5
A to 3 Aim, but the thickness may be 3 Ai m or more. Other configurations are substantially the same as those of the first embodiment. Since the passivation film 26 is made thick, electric field concentration at the mesa corner portion 20 can be reduced, and the device can have high withstand voltage. In addition, it is possible to reduce local electric field concentration at the surfaces of the drift region 2 and the p-type termination region 4 owing to alkaline ions, such as Na ions, attaching to the surface of the passivation film 26. Furthermore, even if moisture or the like attaches to the surface of the passivation film 26, it does not enter the inside, thereby not affecting the inside. As a result, the reliability of the high withstand voltage semiconductor device of the second embodiment is further improved in the use for a long period of time. ({Third embodiment))
FIG. 3 is a sectional view showing a SiC pn diode having a withstand voltage of 6.9 kV in accordance with a third embodiment of the present invention. In the diode of this embodiment, a p-type termination region 14 is extended to the mesa corner portion 20. In the conventional technology for high withstand voltage semiconductor devices, it is supposed that the left end of the p-type termination region 14 is required to be disposed away from the p-type layer 3 in order to improve forward-direction characteristics. In this embodiment, it is confirmed by an experiment that the left end of the p-type termination region 14 may be joined to the p-type layer 3 by carrying out ion implantation for forming the p-type termination region 14 in proximity to the mesa corner portion 20 in the esa inclinedregion . In the experiment , adiodehaving this configuration was produced by way of trial. Changes in the forward-direction characteristics of the diode were examined in a first case when the left end of the p-type termination region 14 was joined to the p-type layer 3 and in a second case when there was no junction therebetween. As the result of the experiment , there is no difference between the first case and the second case in the forward-direction characteristic. It is thus found that no adverse effect occur even when the p-type termination region 14 is joined to the p-type layer 3.
Furthermore, a passivation film 6 having a thickness, of about 0.4 A m is formed on the entire face of the termination region T including the p-type termination region 14. Other configurations are substantially the same as those of the first embodiment. With this configuration, in addition to the depletion region described 'in the above-mentioned first embodiment, a depletion region also expands from the junction portion of the p-type termination region 14 and the n-type drift layer 2 near the mesa corner portion 20 to the cathode electrode 50. By this depletion region, electric field concentration to the passivation film 6 at the mesa corner portion 20 is reduced, and the device can have high withstand voltage. When an inverse voltage of 3 kV was applied to the diode of this embodiment, the electric field strength of the passivation film 6 at the mesa corner portion 20 was 0.19 MV/cm. Therefore, the strength in the case of this embodiment is lower by about 15% than the strength in the case of the diode of the conventional example, i.e. , about 1.3 MV/cm. As a result, the high withstand voltage semiconductor device of this embodiment can have a high withstand voltage and can attain higher reliability. ((Fourth embodiment))
FIG. 4 is a sectional view showing a SiC pn diode having a withstand voltage of 6.9 kV in accordance with a fourth embodiment of the present invention. In the diode of this embodiment, unlike the case of the diode in the third embodiment shown in FIG. 3, the thickness of the passivation film 26 covering the entire region of the termination region T is made far larger than the distance L between the mesa bottom face 18 and the junction face 3A. The thickness is in the range of 2 Aim to 3 Ai m . The thickness may be 3 Ai m or more. Other configurations are substantially the same as those of the first embodiment. Since the passivation film 26 is made thick, electric field concentration at the mesa corner portion 20 can be reduced. In addition, it is possible to reduce the effect of alkaline ions, such as Na ions, attaching to the surface of the passivation film 26 on local electric field concentration at the SiC surfaces. Furthermore, the effect due to moisture attached on the passivation film 26 is limited to the vicinity of the surface thereof, and does not affect the inside. ((Fifth embodiment))
FIG. 5 is a sectional view showing a SiC pn diode having a withstand voltage of 7.5 kV in accordance with a fifth embodiment of the present invention. In the diode of this embodiment, the p-type termination region 14 in the third embodiment shown in FIG. 3 is divided into two regions 14A and 14B. Other configurations are the same as those of the third embodiment. The impurity concentration of the region 14A located near the mesa corner portion 20 is made higher than the impurity concentration of the region 14B located away from the mesa corner portion 20. When a positive voltage is applied to the cathode electrode 50 , a depletion region first expands in the region 14A, and the diode withstands the inverse voltage by this depletion region . When the positive voltage to the cathode electrode 50 is raised further, the depletion region expands to the entire p-type termination region 14, that is, the regions 14A and 14B, and the regions 14A and 14B share the voltage in the case when the impurity concentration of the p-type termination region 14 is about 5 x 1017 atm/cm3 or less. This configuration can therefore prevent electric field concentration at the end portion 14C of the p-type termination region 14A, and the diode can have high withstand voltage. In the case when the impurity concentration of the p-type termination region is more than about 5 x lO17 atm/cm3 , when the positive voltage to the cathode electrode 50 is raised further, a depletion region expands in the region 14B, but no depletion region expands to the upper layer portion of the region 14A. The voltage is thus shared by the region 14B and the lower layer portion of the region 14A. Therefore, a high voltage is not applied to the mesa corner portion 20, and electric field concentration is reduced at the mesa corner portion 20 in the passivation film 6. As a result , a highly reliable diode can be obtained.
((Sixth embodiment))
FIG. 6 is a sectional view showing a SiC pn diode having a withstand voltage of 7.5 kV in accordance with a sixth embodiment of the present invention. In the diode of this embodiment, the p-type termination region 14 in the third embodiment shown in FIG. 3 is divided into plural regions, for example, four regions 14D, 14E, 14F and 14G. The regions 14D, 14E, 14F and 14G are separated from one another. Although the regions 14D, 14E, 14F and 14G may have the same size, it is preferable that the region 14D near the mesa corner portion 20 is larger than the other regions 14E to 14G. The regions 14D to 14G have nearly the same impurity concentration. However, the regions 14D to 14G may have impurity concentrations different from one another. Other configurations are the same as those of the third embodiment. When a positive voltage is applied to the cathode electrode 50 of the diode in this embodiment, a depletion region expands from the region 14D to the region 14G of the p-type termination region 14, and the diode withstands the inverse voltage by this depletion region. According to an experiment, the withstand voltage of the diode rose as the number of the p-type regions 14D to 14G increased. Since the voltage is shared by the plural p-type regions 14D to 14G and also shared by the portions of the drift layer 2 each disposed between the p-type regions, electric field concentration is reduced in the passivation film 6 at the mesa corner portion 20 , and a highly reliable diode can be realized. {(Seventh embodiment))
FIG. 7 is a sectional view showing an n-channel SiC MOSFET having a withstand voltage of 2500 V in accordance with a seventh embodiment of the present invention. In the figure, an n-type drain region 11 is about 200 Aim thick and has a high impurity concentration. A drain electrode 52 is provided on the lower face of the n-type drain region 11. The n-type drift layer 2 formed on the drain region 11 is about 20 Aim thick. A p-type body layer 33 formed on a part of the n-type drift layer 2 is about 4 Ai m thick. and an n-type source region 7 formed on a part of the p-type body layer 33 is about 0.5 Ai m thick. A trench 60 is formed at the nearly central position of the p-type body layer 33. The depth of the trench 60 is about 6 Ai m, and the width thereof is about 3 Aim. The thickness of a gate insulation layer 8 in the trench 60 is about 1 Ai m at the bottom of the trench 60 and about 0.1 Ai m at the side thereof . Although the trench 60 and the gate electrode 54 of this embodiment have a stripe shape extending in a direction perpendicular to the paper face of the figure, the shape may be circular, square or the like.
The method of producing the MOSFET in accordance with the present embodiment will be described below. In FIG. 7, an h-type SiC substrate having an impurity concentration of 1018 to 10zo atm/cm3 is prepared, and functions as the drain region 11. The' SiC n-type drift layer 2 having an impurity concentration of 1015 to 1016 atm/cm3 is formed on the upper face of the drain region 11 by epitaxial growth. The SiC p-type body layer having an impurity concentration of about 1016 atm/cm3 is formed on the entire n-type drift layer 2 by the vapor phase growth method or the like. A right-hand portion of the p-type body layer is removed by the mesa etching method so that the left-hand portion of the p-type body layer 33 remains, thereby forming the termination region T. The p-type termination region 14 having an impurity concentration of 1016 to 1018 atm/cm3 is formed in the termination region
T by ion implantation. The n-type source region 7 having an impurity concentration of about 1018 atm/cm3 is formed at the central region of the remaining p-type body layer 33 by implantation of, nitrogen ions, phosphor ions, etc. Next, the trench 60 is formed by the anisotropic etching method so as to pass through the p-type body layer 33 and reaching the n-type drift layer 2. After the gate insulation film 8 of Si02 is formed on the inner wall faces of the trench 60, polysilicon including phosphor at a high concentration is heaped up so as to be embedded in the trench 60. The polycilicon in the trench 60 is removed inamanner that the ilm of the polysilicon remains on the inner wall of the trench 60, thereby forming the gate electrode 54 of the polysilicon ilm. A source electrode 53 of aluminum, nickel or the like is formed on the surfaces of the n-type region 7 and the p-type body layer 33. Lastly, the passivation film 26 having a thickness of 0.5 Ai m or more is formed on the termination region T, thereby completing the production.
Although the left end portion of the p-type termination region 14 covers the mesa corner portion 20 in the configuration shown in FIG. 7, the left end portion is not always required to cover the mesa corner portion. Since the thickness of the passivation film 26 is 0.5 Aim or more and is larger than the distance L between the mesa bottom face 18 and the junction face 33A of the p-type body layer 33 and the n-type drift layer 2, it is possible to reduce the electric field concentration near the mesa corner portion 20 of the passivation film 26. In addition, it is possible to reduce the effect of alkaline ions, such as Na ions, attaching to the surface, of the passivation film 26 and producing local electric field concentration on the SiC substrate face. Furthermore, the effect due to moisuture attached on the passivation film 26 is limited to the vicinity of the surface thereof, and does not affect the inside. Moreover, since the p-type body layer 33 is formed by the epitaxial growth method, crystal defects are very scarce. As a result, the mobility in a channel region formed on the interface between the p-type body layer 33 and the gate insulation film 8 has a high value of 83 cm2/Vs . ((Eighth embodiment))
FIG. 8 is a sectional view showing a SiC IGBT having a withstand voltage of 8500 V in accordance with an eighth embodiment of the present invention. In the IGBT of this embodiment, a collector electrode 62 is formed on one face of the collector region 12 of a SiC p-type substrate . The drift layer 2 is also formed on the other face of the collector region 12. The thickness of the drift layer 2 is about 70 Aim, and the impurity concentration thereof is about 5 x 1014 atm/cm3. Since the p-type body layer 33 is formed by the epitaxial growth metho similar to the case of the MOSFET of the ifth embodiment , the layer has very few crystal defects. An emitter region 57 is formed on a part pf the p-type body layer 33 , and an emitter electrode 63 is provided on the emitter region 57. In this configuration, the mobility in a channel region formed on the interface between the p-type body layer 33 and the gate insulation film 8 has a high value of 92 cm2/Vs during ON-state. Since holes are injected from the collector region 12 into the drift layer 2 during the ON-state, the conductivity modulation occurs and the ON voltage can be lowered. When the current density is 100 A/cm2, the ON voltage is 4.3 V.
The present invention is not limited to the above-mentioned embodiments but covers more application ranges or derivative structures.
Although only the semiconductor devices of SiC are taken as examples in the above-mentioned embodiments, the present invention is effectively applicable to semiconductor devices of other wide-gap semiconductor materials, such as diamond, gallium nitride, etc.
The semiconductor devices of which the drift layer 2 is an n-type are taken as an example in the above-mentioned first to eighth embodiments. However, when the drift layer 2 is a p-type, the configuration of the present invention is also applicable by changing the n-type region of another element to a p-type region and by changing the p-type region of the element to an n-type region. Furthermore, the present invention is applicable to all semiconductor devices having a p-type region (or an n-type region) in the inclined face and the drift layer at the mesa corner portion 20. Moreover, even when the passivation film is formed of a film of two or more kinds of materials, the configuration of the present invention is applicable.
INDUSTRIAL APPLICABILITY
As being clarified by the detailed descriptions of the embodiments, in the semiconductor device in accordance with the present invention, the angle formed by the inclined face of the p-type layer and the face of the termination region near the mesa corner portion is an obtuse angle. Furthermore, the impurity concentration of the p-type layer is within a predetermined range, and the thickness of the passivation film at least at themesa corner portion is made larger than the distance between mesa bottom face and the junction face of the p-type layer and the n-type drift layer. With this configuration, electric field concentration to the passivation film at the mesa corner portion is reduced, and the withstand voltage characteristic and reliability of the semiconductor device are improved. In addition, by thickening the passivation film, electric field concentration at the mesa corner portion can be reduced. Furthermore, the effect of electric field concentration on the SiC surface owing to alkaline ions, such as Na ions, attaching to the surface of the passivation film can also be reduced. Moreover, the effect due to moisture attached on the passivation film is limited to the vicinity of the surface thereof, and does not affect the inside.

Claims

1. A high withstand voltage semiconductor device comprising: a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on said drift layer by the epitaxial growth method, a termination portion formed in an end portion of said semiconductor device to reduce electric field concentration in said end portion on the application of an inverse voltage across said substrate and said carrier injection layer, a layer of said second conductive type formed in said termination portion, and a surface protection film formed on said termination portion and said carrier injection layer, said surface protection film being thicker in the boundary portion of said termination portion and said carrier injection layer than other portion.
2. A high withstand voltage semiconductor device comprising: a drift layer of a first conductive type formed on a substrate of a wide-gap semiconductor material, a carrier injection layer of a second conductive type for carrier injection formed on said drift layer by the epitaxial growth method, a termination portion formed in an end portion of said semiconductor device to reduce electric field concentration in said end portion on the application of an inverse voltage across said substrate and said carrier injection layer, a layer of said second conductive type formed in said termination portion and the boundary portion of said termination portion and said carrier injection layer, and a surface protection film formed on said termination portion and said carrier injection layer.
3. A high withstand voltage semiconductor device in accordance with claim 1 or 2 , wherein the impurity concentration of said layer of said second conductive type is in the range of 1016 to 1018 atm/cm3.
4. A high withstand voltage semiconductor device in accordance with claim 1 or 2 , wherein the angle formed by the side face of said carrier injection layer and the face of said termination portion is in the range of 100 to 150 degrees.
5. A high withstand voltage semiconductor device in accordance with claim 1 or 2 , wherein the thickness of said surface protection film is 1 Ai m or more in the boundary portion of said carrier injection layer and said termination portion.
6. A high withstand voltage semiconductor device in accordance with claim 1 or 2 , wherein the thickness of said surface protection film is 0.5 Aim or more .
7. A high withstand voltage semiconductor device in accordance with claim 1, wherein said layer of said second conductive type is formed near said carrier injection layer or in contact with said carrier injection layer.
8. A high withstand voltage semiconductor device in accordance with claim 1, wherein the impurity concentration of said layer of said second conductive type formed in said termination portion is high in a portion adjacent to the boundary portion of said termination portion and said carrier injection layer, and is low in a portion spaced from said boundary portion.
9. A high withstand voltage semiconductor device in accordance with claim 8, wherein the impurity concentration of said layer of said second conductive type formed in said termination portion is lowered continuously in the direction from said portion adjacent to the boundary portion of said termination portion and said carrier injection layer to said portion spaced from said boundary portion.
10. A high withstand voltage semiconductor device in accordance with claim 8, wherein the impurity concentration of said layer of said second conductive type formed in said termination portion is lowered stepwise in the direction from the portion adjacent to the boundary portion of said termination portion and said carrier injection layer to the said portion spaced from said boundary portion.
11. A high withstand voltage semiconductor device in accordance with claim 1, wherein plural layers of said second conductive type having approximately equal impurity concentrations are formed in said termination portion.
12. A high withstand voltage semiconductor device in accordance with claim 11, wherein plural layers of said second conductive type formed in said termination portion have impurity concentrations different from each another.
13. A high withstand voltage semiconductor device comprising: a drift layer of a first conductive type formed on a face of a substrate of a wide-gap semiconductor material having a drain electrode on the other face, a body layer of a second conductive type formed on said drift layer by the epitaxial growth method, a source region of said first conductive type formed on a part of said body layer. a trench formed so as to pass through said source region and said body layer, and reach said drift layer, a gate electrode formed on the inner wall faces of said trench via an insulation film, a termination portion formed in an end portion of said semiconductor device to reduce electric field concentration in said end portion on the application of an inverse voltage across said substrate and said body layer, a layer of said second conductive type formed in said termination portion and the boundary portion of said termination portion and said body layer, a source electrode formed on said source region and said body region, and a surface protection film formed on said termination portion and the side face of said body layer.
14. A high withstand voltage semiconductor device in accordance with claim 13, wherein said substrate of said wide-gap semiconductor material is the second conductive type.
15. A high withstand voltage semiconductor device in accordance with claim 13, wherein the thickness of said surface protection film is 0.5 Ai m or more.
16. A high withstand voltage semiconductor device in accordance with claim 13, wherein the impurity concentrations of said layers of the second conductive type are in the range of 1016 to 1018 atm/cm3.
17. A high withstand voltage semiconductor device in accordance with claim 13, wherein the angle ormed by the side face of said carrier injection layer and the face of said termination portion is in the range of 100 to 150 degrees.
18. A high withstand voltage semiconductor device in accordance with claim 13, wherein the thickness of said surface protection film is 1 Ai m or more at the boundary portion of said carrier injection layer and said] termination portion.
19. A high withstand voltage semiconductor device in accordance with claim 13, wherein said layer of said second conductive type is formed near said body layer.
20. A high withstand voltage semiconductor device in accordance with claim 13, wherein said layer of said second conductive type is formed in contact with said body layer.
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