WO2001028243A1 - Method and system for eliminating edge effects at the end of frame in video signals - Google Patents

Abstract

A method and apparatus for processing video signals to be displayed on a digital display device without edge effects or artifacts at the end of frame intervals. Specifically, video signals consist of a plurality of pixel frames, with each of the pixel frames further consisting of a plurality of pixel lines. A typical video signal processing system includes a vertical format converter (VFC) (402 and 403) for converting signal formats in vertical direction. A typical VFC includes a memory to store 'future' pixel lines that can be used to create a current pixel line to be displayed on a digital display device. However, at the end of a pixel frame, there are no 'future' pixel lines that can be used to create a current pixel line. This causes edge effects or artifacts on the digital display device along the vertical direction at end of frame intervals. The edge effect or artifact problem is solved by repeating (704) at least one pixel line that is located on or preceding to the end position in each of the pixel frames.

Description

METHOD AND SYSTEM FOR ELIMINATING EDGE EFFECTS AT THE END OF FRAME IN VIDEO SIGNALS

FIELD OF THE INVENTION

The present invention generally relates to a video signal processing system suitable for converting video signal formats. In particular, the present invention relates to a video signal processing system, which comprises a vertical format converter (VFC) and a horizontal format converter (HFC), for converting video signal formats.

BACKGROUND OF THE INVENTION

In displaying an image on a display screen, conventional analog display products use overscan to hide edge effects or artifacts of the image. Overscan refers to a technique to create an image that is larger than that is actually displayed on a display screen with aberrant edge effects (i.e. horizontal and vertical thin bars on the edges of an image) . Because overscan region of an image extends beyond visible region of a display screen, the edge effects or artifacts of the image will not be shown on the display screen. FIG. 1 shows a conventional CRT (cathode ray tube) display screen 1 00 that displays approximately 93% of an image on a display screen 1 02. The overscan region 1 04 is masked to ensure that edge effects or artifacts will not be displayed on the display screen 102.

In displaying an image on a display screen, digital display products (such as plasma displays) also suffer from edge effect or artifact problems. However, the overscan technique cannot be used to solve edge effect or artifact problems for a digital display because the number of pixels to be displayed is dictated by the digital display. FIG. 2 shows a conventional digital display 1 10 on which an entire image is displayed on the digital display panel 1 1 2. As a result, the edge effects or artifacts 1 14 are visible. More specifically, a typical television broadcast station sends out video signals in a standard resolution. The video signals are presented as a series of frames. Each of the frames contains a plurality of lines, and each of the lines contains a plurality of pixels. When the video signals are received at a display terminal, the standard resolution may be converted depending on the resolution of the receiving display terminal. The standard resolution is expanded when the resolution of a receiving display terminal is higher than the standard resolution, and the standard resolution is compressed when the resolution of a receiving display terminal is lower than the standard resolution. A conventional digital video processing system typically has a main-channel format converter (FMC) that further comprises a vertical format converter (VFC) and a horizontal format converter (HFC) . The HFC portion of the system performs format conversion in horizontal direction, and the VFC portion of the system performs format conversion in vertical direction. The VFC portion of the system typically includes a memory to store lines of "previous" and "future" pixels. These stored pixel lines are then used to compute the current line of video signals. However, at the beginning of a frame there are no "previous" pixel lines in the memory that can be used to create the first few lines to be displayed. Likewise at the end of a frame, there are no "future" pixel lines in the memory that can be used to create the last few lines to be displayed. Thus, among frame intervals where actual pixel data is not available, the VFC typically would compute a current line of video based on zero values. Thus, a relatively abrupt transition occurs from computing actual pixel data to computing zero values, thereby producing a visible edge effects or artifacts in the form of a thin bar along the vertical edges of the display.

The HFC portion of the system typically includes a multi-tap filter that performs computing functions on the received video pixels line by line. At the beginning and end of pixel lines where actual data is not available (i.e., before all taps of the filter are loaded with actual pixel data at the beginning of a line or after actual pixel data ends at the end of a line), the filter typically would compute zero values. Thus, a relatively abrupt transition occurs from computing actual pixel data to computing zero values, thereby producing a visible edge effects or artifacts in the form of a thin bar on the horizontal edges of the display.

For processing video signals in vertical direction, two aspects of the described problem exist. The first, referred to as vertical "filter run-in", occurs at the beginning of frame intervals. The second, referred to as vertical "filter runout", occurs at the end of frame intervals.

Similarly, for processing signals in horizontal direction, two aspects of the described problem exist. The first, referred to as horizontal "filter run-in", occurs at the beginning of line intervals. The second, referred to as horizontal "filter run-out", occurs at the end of line intervals.

The present invention provides a method and system for processing digital video signals without generating edge effects or artifacts at the end of frame intervals.

SUMMARY OF THE INVENTION

In a broad aspect, the present invention provides a method for processing pixel frames frame by frame for a display device. Each of the pixel frames contains a plurality of pixel lines and has an end position. The method includes the steps of: receiving a plurality of pixel lines, processing the received pixel lines, outputting the processed pixel lines to the display device, detecting an end position for a pixel frame, and eliminating edge effects or artifacts on the display device at the end position of the pixel frame. The present invention also provides an apparatus for performing the steps in above-described method.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 shows a conventional CRT display screen that displays approximately 93% of an image on a display screen; FIG. 2 shows an image that is displayed on a digital display with edge effects or artifacts; FIG. 3 is a block diagram for an exemplary digital video receiving system that operates according to the principle of the invention;

FIG. 4 is a block diagram for an exemplary MFC (main-channel format converter); FIG. 5 is a Table I showing the definition for four control signals;

FIG. 6 is a Table II showing the definition showing the definition for a set of registers;

FIG. 7 is a block diagram for an exemplary VFC (vertical format converter) for luma; FIG. 8 is a block diagram for an exemplary VFC for chroma;

FIG. 9 is a block diagram for an exemplary VFC luma control;

FIG. 1 0 is a block diagram for an exemplary VFC chroma control;

FIG. 1 1 shows line positions if Y GO LINE initialization value is used without a raster correction; FIG. 1 2 is a block diagram showing further detail for the luma VFC output control shown in FIG. 9;

FIG. 1 3 is a block diagram showing a state machine for operating the luma VFC output control shown in FIG. 10;

FIG. 1 4 is a block diagram showing further detail for read/write protection and end of line detection block shown in FIG. 9; and

FIG. 1 5 is a coefficient table for the VFC luma filter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The characteristics and advantages of the present invention will become more apparent from the following description, given by way of example.

Referring now to FIG. 3, there is shown a block diagram of an exemplary digital video receiving system 300 that operates according to the principles of the invention. The video receiver system includes an antenna 10 and input processor 1 5 for receiving and digitizing a broadcast carrier modulated with signals carrying audio, video, and associated data, a demodulator 20 for receiving and demodulating the digital output signal from input processor 1 5, and a decoder 30 outputting a signal that is trellis decoded, mapped into byte length data segments, de-interleaved, and Reed-Solomon error corrected. The corrected output data from decoder unit 30 is in the form of an MPEG compatible transport data stream containing program representative multiplexed audio, video, and data components.

A processor 25 processes the data output from decoder 30 such that the processed data can be displayed on a HDTV plasma display unit 75 in accordance with requests input by a user via a remote control unit 1 25. More specifically, processor 25 includes a controller 1 1 5 that interprets requests received from remote control unit 1 25 via remote unit interface 1 20 and appropriately configures the elements of processor 25 to carry out user requests (e.g., channel, website, and/or OSD display). In one exemplary mode, controller 1 1 5 configures the elements of processor 25 to provide MPEG decoded data and an OSD for display on display unit 75. Processor 25 includes a decode PID selection unit 45 that identifies and routes selected packets in the transport stream from decoder 30 to transport decoder 55. The transport stream from decoder 30 is demultiplexed into audio, video, and data components by transport decoder 55 and is further processed by the other elements of processor 25, as described in further detail below. The transport stream provided to processor 25 comprises data packets containing program channel data, ancillary system timing information, and program specific information such as program content rating and program guide information. Transport decoder 55 directs the ancillary information packets to controller 1 1 5 which parses, collates, and assembles the ancillary information into hierarchically arranged tables. Individual data packets comprising the user selected program channel are identified and assembled using the assembled program specific information. The system timing information contains a time reference indicator and associated correction data (e.g. a daylight savings time indicator and offset information adjusting for time drift, leap years, etc.) . This timing information is sufficient for a decoder to convert the time reference indicator to a time clock (e.g., United States east coast time and date) for establishing a time of day and date of the future transmission of a program by the broadcaster of the program. The time clock is useable for initiating scheduled program processing functions such as program play, program recording, and program playback. Further, the program specific information contains conditional access, network information, and identification and linking data enabling the system of FIG. 3 to tune to a desired channel and assemble data packets to form complete programs. The program specific information also contains ancillary program content rating information (e.g., an age based suitability rating), program guide information (e.g., an Electronic Program Guide - EPG) and descriptive text related to the broadcast programs as well as data supporting the identification and assembly of this ancillary information.

Transport decoder 55 provides MPEG compatible video, audio, and sub- picture streams to MPEG decoder 65. The video and audio streams contain compressed video and audio data representing the selected channel program content. The sub-picture data contains information associated with the channel program content such as rating information, program description information, and the like.

MPEG decoder 65 cooperates with a random access memory (RAM) 67 to decode and decompress the MPEG compatible packetized audio and video data from unit 55 and derives decompressed program representative pixel data. Decoder 65 also assembles, collates and interprets the sub-picture data from unit 55 to produce formatted program guide data for output to an internal OSD module. The OSD module cooperates with RAM 67 to process the sub-picture data and other information to generate pixel mapped data representing subtitling, control, and information menu displays including selectable menu options and other items for presentation on display device 75 in accordance with the present invention.

The control and information displays, including text and graphics produced by the OSD module, are generated in the form of overlay pixel map data under direction of controller 1 1 5. The overlay pixel map data from the OSD module is combined and synchronized with the decompressed pixel representative data from MPEG decoder 65 under direction of controller 1 1 5. Combined pixel map data representing a video program on the selected channel together with associated sub-picture data is encoded by decoder/processor 65 and output to plasma display device 75, via display drivers 80, for display. Referring now to FIG. 4, there is shown a block diagram for an exemplary

MFC 400 illustrating further detail for decoder/processor 65 shown in FIG. 3, in accordance with the present invention. MFC 400 includes a VFC (Y) 402, a VFC

(U, V) 403, an HFC (Y) 404 and an HFC (U, V) 405.

In a video processing system, the color of a pixel can be represented as a dot position in a three-dimensional color space. A color space is a mathematical representation of a set of colors. One color model is called YUV color space, in which color representation is divided into two components, namely, luminance (Y) information and chrominance information (U and V). In YUV color space, a black-white receiving system uses only luminance (Y) information; chrominance (or color) information (U and V) is added in such a way that a black-white receiving system still displays a normal black-white picture. A color receiving system decodes both luminance and chrominance information to display a color picture.

Using YUV color space as a selected color model in the present invention, the components in FIG. 4 are therefore deployed in two functional sets. The first set of components 402 and 404 is used to process signals and data for luminance (luma), and the second set of components 403 and 405 is used to process signals and data for chrominance (chroma) .

MFC 400 receives a serial (8 bit wide) progressive or interlace (4:2:0 or 4:2:2) input. The MFC output can be progressive or interlace (4:2:2) . The FMC uses handshake signals (RTS and RTR) for data flow control between each block. (Note: RTS stands for Ready To Send, and RTR for Ready To Receive).

MFC 400 can perform a linear or non-linear zoom in both vertical and horizontal directions. An external microprocessor sets zoom ratio for MFC 400. The limit of vertical conversion is given by input and output clock frequency and line length of input. MFC 400 has the following features: ( 1 ) five free programmable zones in horizontal and vertical directions;

(2) zone 1 , 2, 4 or 5 has a free programmable zoom change per pixel/line;

(3) the sign of the zoom change is free programmable (zoom up/down);

(4) the input size is programmable multiple steps of two or four; (5) compressions in vertical direction;

(6) expansion in vertical direction;

(7) compression in horizontal direction;

(8) expansion in horizontal direction;

(9) no blanking regions; and ( 1 0) automatic phase correction for H/2, H/4, V.2 and V/4 decimation modes.

Input field ID (V_IID), which is one for odd field and zero for even field, is used to indicate interlace inputs. Output field ID (V OID), which is also one for odd field and zero for even field, is used to indicate interlace outputs. V_RST_DR is used as field /frame reset signal.

H/2, H/4, V/2 and V/4 decimation modes change the spatial position. To perform a phase correction, the VFC (402 or 403) or HFC (404 or 405) has an automatic phase correction. Five signals (disp_h2, disp_h4, disp_v2, disp_v4, and xcomp type) are used to detect decimation modes. The definition of these three signals is listed in Table I as shown in FIG. 5.

For the automatic phase correction feature, the VFC (402 or 403) assumes that V/2 or V/4 decimation must be done in a field when the VFC input is interlace, and that the V2 or V4 decimation must be done in a frame when the VFC input is progressive.

For the programmable zoom feature, the present invention defines a quantity of steps between two input lines or pixels. The number of steps for vertical dimension (i.e. DISTANCE) depends on the input format, as follows: (1 ) for interlace luma inputs: DISTANCE = 1 6384; (2) for interlace chroma inputs: DISTANCE = 32768;

(3) for progressive luma inputs: DISTANCE = 81 92; and (4) for progressive chroma inputs: DISTANCE = 1 6384.

The number of steps in horizontal direction is defined to 81 92.

For the output of MFC 400, the present invention defines two programmable values LSTEP and PSTEP as the distance of two output lines or pixels. With this definition, the present invention derives the following formulas:

( 1 ) number of input lines x 81 92 = number of output lines x LSTEP;

(2) vertical zoom factor = 81 92/LSTEP;

(3) number of input pixels x 81 92 = number of output pixels x PSTEP; and

(4) horizontal zoom factor = 81 92/PSTEP.

In describing the embodiments of the present invention, a set of signals in the form of UC_xxxx denotes micro control registers, which can either be mapped to input/output ports or to memory. These are the registers used for controlling the behavior of the concerned algorithms. The values of these registers are written by an external microprocessor. The definitions of these registers are listed in table II as shown in FIG. 6.

VFC (402 or 403) can perform a linear or non-linear conversion (i.e., expansion or depression) in vertical direction for MFC 400. The input and output of the VFC can be interlace or progressive depending on UC VIID and

UC_VOID. The input can be 4:2:0 (UC_4_2_0 = 1 ) or 4:2:2 (UC_4_2_0 = 0) .

For each input, the VFC output is 4:2:2.

The vertical zooms can be linear or non-linear. For this reason, the display is divided into five zones. Four of the five zones have a programmable zoom change per line. The maximum vertical compression depends on the relation of the line length and clock frequency of the input and display of the VFC (402 and

403). The zoom factor can be calculated by the following formula:

input line size VFC clock frequency zoom factor >= output line size display clock frequency _, Referring to FIG. 7, there is shown a block diagram for an exemplary luma

VFC 700 illustrating further detail for VFC (Y) 402 shown in FIG. 4. The luma

VFC includes an Y multiplex 702, an Y_switch1 704, four line memories (Line

MemO, Line Mem1 , Line Mem2 and Line Mem3), a VFC luma filter 71 4 (which is a 4 tap and 32 phase polyphase filter with 1 28 coefficients), and a limiter 71 6.

VFC luma filter 71 4 further includes four filter multiplexes (MUXO, MUX1 , MUX2 and MUX3), an Y_switch2 731 , four multipliers (MUPO, MUP1 , MUP2 and

MUP3), an adder 734 and a normalizer 736. The four multiplexes (MUXO,

MUX1 , MUX2 and MUX3), Y_switch2 731 and four multipliers (MUPO, MUP1 , MUP3 and MUP4) form four taps (TO, T1 , T2 and T3) for VFC luma filter 714. Each of the four taps includes a respective filter multiplex, an Y_switch2 input, an Y_switch2 output and a multiplier. For example, tap TO includes MUXO, I0, 00 and MUPO. The coefficients (YCO, YC1 , YC2 and YC3) are stored in a programmable RAM (shown as element 91 0 in FIG. 9). Y_multiplex 702, which is controlled by Y_WMUX, receives inputs from the luminance (Y) source (i.e. Y_VFC_IN) and generates outputs at its four output terminals (0, 1 , 2 and 3) for Y switch l 704. Y switchl 704, which is controlled by Y_RUN_IN, receives inputs at its four input terminals (10, 11 , 12 and 14) from respective outputs of Yjnultiplex 702 and generates outputs at its four output terminals (00, 01 , 02 and 03) for the four line memories. The four line memories (Line MemO, Line Mem1 , Line Mem2 and Line Mem3) receive inputs from respective outputs (00, 01 , 02 and 03) of Y switch l 704 and generate four outputs for VFC luma filter 71 4.

Within VFC luma filter 71 4, the four filter multiplexes (MUXO, MUX1 , MUX2, and MUX3) receive four inputs from line memories (Line MemO, Line Mem1 , Line Mem2 and Line Mem3) and generate four outputs for Y_switch2 724. Y_switch2 724 receives inputs at its four input terminals (I0, 11 , 12 and 14) from respective filter multiplexes (MUXO, MUX1 , MUX3 and MUX 4) and generates outputs at its four output terminals (00, 01 , 02 and 03) for the four filter multipliers (MUPO, MUP1 , MUP2 and MUP3) . Y_switch2 731 is controlled by Y RUN OUT. The four filter multipliers (MUPO, MUP1 , MUP2 and MUP3) multiply the four outputs (00, 01 , 02 and 03) from Y_switch2 71 3 with respective coefficients (YCO, YC 1 , YC2 and YC3). Adder 734 generates a sum based on the four outputs from the four filter multipliers (MUPO, MUP1 , MUP2 and MUP3). For a particular pixel to be displayed on a display screen, the output from adder 734 represents its luma value. Normalizer 736 truncates the least significant bits in the output from adder 734. Limiter 71 6 converts the output from adder 734 into a value between - 1 28 and 1 27. Operating together, normalizer 736 and limiter 71 6 ensure that the output from VFC luma filter is within a displayable range. In FIG. 7, Y WMUX and Y_RMUX are used to control the four line memories when luma VFC 700 is not operated in "filter run-in" or "filter run-out" mode. Y WMUX points to the line memory that will be overwritten with the next input line requested by the luma VFC. If luma VFC 700 requests no line, Y WMUX will be stable for the actual output line. If VFC luma 700 requests more than one line, the first line will be written to the line memory where Y WMUX points. The next line will be written to the line memory Y MUX + 1 . When the Y_WMUX value reaches the number of used line memories (4 for luma), Y_WMUX is set to 0 (modulo function). Y RMUX is used for decoding the line memory organization to VFC luma filter 71 4. It is set to 0 if the value reaches the number of used line memories.

In "filter run-in" mode for luma, Y_SWITCH 1 704 selects its data path based on the value of Y_RUN_IN according to the following function table:

Y RUNJN Function

0 00 = I0

01 = 11

02 = 12

03 = 13

1 00 = 11 (the first input line)

01 = 11 (the first input line)

02 = 11 (the first input line)

03 = 11 (the first input line)

In "filter run-in" mode for luma, the first step is to copy the first input line of a frame/field to all four line memories. Therefore, Y switchl 702 is set to 1 during the first input line. It should be noted that the above-described embodiment repeats the first input line in an incoming frame. However, the display quality can also be improved by repeating another line in the incoming frame (the second input line in the incoming frame for example).

In "filter run-out" mode for luma, Y SWITCH2 731 selects its data path based on the value of Y RUN OUT according to the following function table:

It should be noted that when Y_RUN_OUT is 3 (i.e., no zoom is needed), the above-described embodiment repeats the last input line n in an outputting frame. However, the displaying quality can also be improved by repeating other line in an outputting frame (the n - 1 line in an outputting frame for example) .

Referring to FIG. 8, there is shown a block diagram for an exemplary chroma VFC 800 illustrating further detail for the VFC (U, V) 403 shown in FIG. 4. Chroma VFC 800 includes a Cjnultiplex 802, a C switchl 804, two line memories (Line MemO and Line Mem1 ), a VFC chroma filter 81 4 (which is a 2 tap and 32 phase linear polyphase filter), and a limiter 81 6. VFC chroma filter

81 4 further includes two filter multiplexes (MUXO and MUX1 ), a C_switch2

831 , an adder 832 , two multipliers (MUPO and MUP1 ), and an adder 834. The two multiplexes (MUXO and MUX1 ), C_switch2 831 and two multipliers (MUPO and MUP1 ) form two taps (TO and T1 ) for VFC chroma filter 81 4. Each of the two taps includes a respective filter multiplex, a C_switch2 input, a C_switch2 output and a multiplier. For example, tap T1 includes MUX1 , 11 , 01 and MUP1 .

C multiplex 802, which is controlled by C WMUX, receives inputs from the chrominance (U, V) source (i.e. C VFCJN) and generates two outputs for C_switch1 804. C switchl 804, which is controlled by C RUNJN, receives inputs at its two input terminals (10 and 11 ) from C_multiplex 802 and generates outputs at its two output terminals (00 and 01 ) for the two line memories. The two line memories (Line MemO and Line Mem1 ) receive inputs from respective outputs (00 and 01 ) of C switch l 804, and generate two outputs (00 and, 01 ) for VFC chroma filter 814.

Within VFC chroma filter 81 4, the two filter multiplexes (MUXO and MUX1 ) receive inputs from line memories (Line MemO and Line Mem1 ) and generate two outputs for C_switch2 831 . C_switch2 831 receives inputs at its two input terminals (I0 and 11 ) from respective filter multiplexes (MUXO and MUX1 ) and generates outputs at its two output terminals (00 and 01 ) . C_switch2 831 is controlled by C_RUN_OUT. Output 00 from C_switch2 is sent to multiplier MUXO and adder 832. Output 01 of C_switch2 is sent to adder 832. Adder 832 adds the inputs from 00 and 02 of C_switch2 and sends its output to multiplier MUX1 . The two filter multipliers (MUPO and MUP1 ) multiply its two inputs with respective coefficients (32 and CC1 ) . Adder 834 generates a sum based on the two outputs from the two filter multiplexes

(MUPO and MUP1 ) . For a particular pixel to be displayed on a display screen, the output from the adder 834 represents its chroma value. Limiter 81 6 converts the output from adder 834 into a value between - 1 28 and 1 27, to ensure that the output from VFC luma filter is in displayable range.

In FIG. 8, C WMUX and C RMUX are used to control the two line memories when chroma VFC 800 is not operated in "filter run-in" or "filter runout" mode. C WMUX points to the line memory that will be overwritten with the next input line, which is requested by chroma VFC 800. If the chroma VFC requests no line, C_WMUX will be stable for the actual output line. If the VFC requests more than one line, the first line will be written to the line memory where C WMUX points. The next line will be written to the line memory C_MUX + 1 . When the C_WMUX value reaches the number of used line memories (2 for chroma), C WMUX is set to 0 (modulo 2 function) .

In "filter run-in" mode for chroma, C_SWITCH 1 sets its data path based on the value of C RUN IN according to the following function table:

C RUNJN Function

0 00 = I0

01 = 11

1 00 = 11 (the first input line)

01 = 11 (the first input line)

When in "filter run-in" mode for chroma, the above-described embodiment repeats the first input line of an incoming frame. However, it should be noted that the display quality can also be improved by repeating another line in the incoming frame (the second line in the incoming frame for example).

In "filter run-out" mode for chroma, C SWITCH2 sets its path based on the value of C RUN OUT according to the following function table:

When in "filter run-out" mode for chroma, the above-described embodiment repeats the last input line of an outputting frame. However, it should be noted that the display quality can also be improved by repeating another line in the outputting frame (the n - 1 line in the outputting frame for example).

For luma or chroma, the occurrence of "filter run-out" depends on the number of input lines that are actually requested. The non-zero value of Y_RUN_OUT (or C_RUN_OUT) indicates the occurrence of "filter run-out". Y_RUN_OUT (or C_RUN_OUT) stays 0 while any lines in a frame are being requested and changes its value when all input lines in the frame have been requested. A line input counter (Y LIC or C_LIC) in VFC luma control (shown in FIG. 9) or VFC chroma control (shown in FIG.1 0) counts the number of requested lines. If additional lines more than available in a frame are requested, the present invention does not actually requests a new line; instead it sets a nonzero value in a run-out control signal (Y_RUN_OUT or C RUN OUT), indicating additional line(s) is/are requested. Specifically, in processing for luma, for the value of Y LIC being one greater than the available lines, Y RUN OUT is 1 ; for the value of Y LIC being two greater than the available lines, Y RUN OUT is 2; and for the value of Y_LIC being three or more greater than the available lines, Y RUN OUT is 3. The processing for chroma is the same as that for luma, except that for all request values being greater than 1 , C RUN OUT is 1 . During a vertical expansion, the number of output lines is greater than that of input lines. Thus the contents of the VFC line memories (as shown in FIG . 7 and FIG.8) are used for more than one input line. For such situations no new input line is necessary for the output line. During a vertical compression, the number of output lines is less than the input lines. Thus the contents of the VFC line memories can change for one input line. For such situations two or more input lines are necessary for this output line. The maximum of new input lines for one output line depends on the maximum vertical compression, which is round up ( 1 /maximum vertical zoom factor) .

For the supported vertical formats, the maximum appears in the 720 progressive to 480 interlace letterbox conversion. For a linear conversion, the vertical zoom factor is 0.25, which means up to 4 new lines for one output line is needed. For a vertical non linear conversion, an additional increment of zoom factor is needed.

Because the read/write time must not be the same, line memories (shown in FIG. 7 or 8) need their own write and read reset pulses. The read resets are Y_H_VFC for luma and C_H_VFC for chroma. The write resets are Y NEW LINE for luma and C NEWJJNE for chroma. Referring to FIG. 9, there is shown a VFC luma control 900 illustrating further detail for VFC 402 shown in FIG. 4. The VFC luma control includes a DTO1 block 902, a DTO2 block 904, a phase calculation block 906, a shifter block 908, a VFC filter coefficient RAM 91 0, an Y line detection block 91 2, a run in and run out control block 91 4, a read/write protection and end of line detection block 91 6, and a VFC luma output line control block 91 8.

DTO1 block 902 includes a two-way multiplexer, an adder, a D register (for storing the current value for next calculation) and a shifter. It generates LSTEP for luma. DTO2 block 904 includes a two-way multiplexer, a MOD(X) function, a D register and an adder. It specifies the phase of VFC luma filter 714 (shown in FIG. 7) and calculates number of lines needed for next output line (Y GO LINE) . Phase correction block 904 generates Y_PHASE INIT. Because a correction value is needed for some input formats, Y PHASEJNIT contains a raster correction value. Phase calculation block 906 generates Y PHASEJNIT for first progressive line for luma. Shifter block 908 generates Y PHASE. The coefficient RAM 91 0 includes a phase to address conversion, and it stores coefficients and provides a particular coefficient according to Y PHASE value. Y line detection block 91 2 generates Y GO LINE. Run in and run out control block

914 generates Y_RUN_IN and Y_RUN_OUT. Read/write protection and end of line detection block 91 6 generates Y WR EN, Y RD EN, Y_INPUT_EOL and

Y_OUTPUT_EOL. VFC luma output line control 91 8 generates Y_RMUX, Y_WMUX, Y H PROG, YJNIT VFC, Y .DELTA and Y H VFC.

The five control signals (Y RMUX, Y WMUX, Y_H_PROG, YJNIT VFC and Y LDELTA) from VFC luma output line control block 91 8 are always in progressive mode. With an additional control signal (Y_H_VFC), the five control signals can also control interlace display operation. More specifically, for an interlace output (even or odd), the output from control block 91 8 is only active for the correct output field ID. This progressive controlling is necessary for the nonlinear vertical zooms. An advantage is that the zoom calculation is the same for interlaced and progressive outputs. Thus, two horizontal output sync pulses are generated by VFC luma output line control block 91 8. One of the pulses is Y_H_VFC. After this pulse, the output line calculation is active if the handshaking signal (see FIG. 4) enables the output. The second sync pulse is Y_H_PROG and is always high when Y_H_VFC is high. In addition Y_H_PROG is also high when the output of VFC (Y) 402 is interlace and the VFC (Y) is able to calculate a new output line but the line is not in the correct field raster (an even line for an odd field or an odd line for an even field) .

VFC luma output line control block 91 8 requests new input lines for VFC luma filter 714 (shown in FIG. 7) from read/write protection and end of line detection block 91 6 by means of generating a pulse on Y_NEW_LINE control line. VFC luma output line control 91 8 also generates Y_RMUX and Y WMUX. Y RMUX species the reading order to the VFC luma filter multipliers (shown in FIG. 7), and Y_WMUX selects the VFC line memory (shown in FIG. 7) that can be overwritten by a new input line.

UCJ-STEP INIT is for subline scanning. Y PHASEJNIT is a raster correction value with an UC LSTEP INIT offset. Y_PHASEJNIT points to the first vertical progressive output line position so that all input formats start with the same vertical position. Y JNIT_VFC goes after V RSTJDR becomes high until the next Y_H_PROG pulse. With an active Y JNIT VFC signal and the first

Y H PROG pulse, the DTO 1 block 902 and DTO2 block 904 go to the initial output state. With this pulse, the first line of an odd field or the first line of a frame is available. If this output line is in right output raster, Y_H_VFC is generated and output calculation is active.

YJNPUT_EOL signal specifies the state of input line transmission. If it is zero, a line is written to the VFC line memories (shown in FIG. 7). If it is one, the transmission of an input line has been finished and VFC luma output line control block 91 8 can request a new line if it needs for the next Y_H_PROG pulse.

Y OUTPUT EOL signal specifies the state of output line calculation. If it is zero, the output is active and no Y_H_PROG and Y_H_VFC pulses are allowed. If it is high, Y_H_PROG and Y H VFC pulse generation is possible. The values of UC VZONEs ( 1 , 2, ..., 5) divide an output picture in five zones for non linear zoom. A counter inside VFC luma output line control block 91 8 counts Y_H_PROG pulses and specifies progressive output line number. This number is compared with four zones. Each of the four zones has its own LDELTA value. UC LDELTA1 is for zone one, UC LDELTA2 for zone two, UCJ.DELTA4 for zone four and UC_LDELTA5 for zone five. All LDELTA values have two fractional bits. The DTO1 block 902 adds LDELTA to (LSTEP < < 2). It starts with UC LSTEP < < 2 + LDELTA. So LSTEP is a function of:

LSTEP = (UC_ LSTEP « 2 + ∑ LDELTA(o tput line position)) » 2 Symbol " < < x" denotes shifting the input to the left by x bit positions, and symbol " > > x" denotes shifting the input to the right by x bit positions.

As mentioned above, DTO2 block 904 specifird the phase of the polyphase filter (shown as 71 4 in FIG. 7) and performs Y GOJJNE calculation. DTO2 block 904 has a sub-phase resolution of 1 /256 or 1 /51 2, which means the 32 phases are expanded to 81 92 (progressive inputs) or 1 6384 (interlace inputs) phases.

VFC (Y) 402 (shown in FIG . 4) produces a progressive output when

UC_VOID = 1 and an interlace when UC VOID = 0. The luma input is progressive when UC_VIID[0] = 1 and interlace when UC_VIID[0] = 0. (The chroma input is progressive when UC_VIID[1 ] = 1 and interlace when UC_VIID[1 ] = 0).

Run in and run out control block 91 4 is for filter initialization and for Y_GO_LINE limitation when input is at the end of a field or frame. Referring to FIG. 1 0, there is shown a block diagram for an exemplary

VFC chroma control 1000 illustrate further detail for VFC 403 shown in FIG. 4. The VFC chroma control includes a DTO3 block 1 002, a DTO4 block 1 004, a phase calculation block 1 006, a shifter block 1 008, a C line detection block 101 2, a run in and run out control block 1 014, a read/write protection and end of line detection block 1 01 6, and a VFC chroma output line control block 1 01 8. DTO3 block 1 002 includes a two-way multiplexer, a D register, an adder and a shifter. It generates LSTEP for chroma. DTO4 block 1 004 includes a two- way multiplexer, a MOD(x) function, a D register and an adder. It specifies the phase of VFC chroma filter 81 4 (shown in FIG. 8) and calculates number of lines needed for the next output line (C_GO_LINE). Phase calculation block 1 006 generates C PHASEJNIT for chroma first progressive line. Shifter block 1 008 generates coefficient CC1 . C line detection block 101 2 generates C GO LINE. Run in and run out control block 1 01 4 generates C RUN IN and C_RUN_OUT. Read/write protection and end of line detection block 101 6 generates C_WR_EN, C RD EN, CJNPUT_EOL and C_OUTPUT_EOL. VFC chroma output line control 1 01 8 generates C RMUX, C WMUX, C_H_PROG, CJNIT VFC, C LDELTA and

C H VFC.

The operation of the VFC chroma control is in principle the same as that of the VFC luma control, except that the VFC chroma control can perform an additional 4:2:0 to 4:2:2 conversion. Thus, some of the values in the VFC chroma control have other ranges. In addition, unlike the VFC luma control shown in FIG. 9, VFC chroma control 1 000 does not have coefficient RAM because the VFC chroma control only needs two coefficients. One coefficient is a fixed value (32), and the other (CC1 ) is a function of DTO3 block 1 1 04. For VFC luma control 900 shown in FIG. 9, the MOD(x) function in DOT2 block 904 performs a modulo x function, which can be described by the following algorithm: if(UC_VIID[0] = = INTERLACE)

Out = IN% 16384; else

Out = ln%8192;

For VFC chroma control 1 000 shown in FIG. 1 0, the MOD(x) function in DOT4 block 1 004 performs a modulo x function, which can be described by the following algorithm:

if(UC_4_2_0 = = 1)/* 4:2:0 input*/

{ if(UC_V/ID[1] = = INTERLACE)

Out = IN%32768; else

Out = ln % 16384;

} else /* 4:2:2 input */

{ if(UC_VIID[1] = = INTERLACE)

Out = IN% 16384; else

Out = ln%8192;

}

For VFC luma control 900 shown in FIG. 9, Y line detection block 91 2 calculates the necessary number of input lines for the next input line for luma (Y GO LINE). Its function can be described by the following algorithm:

if(UC_V/ID[0] = = INTERLACE)

DISTANCE = 16384 else DISTANCE = 8192

Y_GO_L/NE = /NO/DISTANCE; /* Division with DISTANCE is a shift V /* left operator of 13, 14 or 15 bits V if (Y I NIT VFC == 1) { iff (UC_VIID[0] = = INTERLACE && VJID = = EVEN) I I disp_v2 = = 1 | | disp_v4 = = 1 ) Y GO L/NE + = 2 else Y GO L/NE + = 3

}

For VFC chroma control 1000 shown in FIG. 10, C line detection block

1012 calculates the necessary number of input lines for the next input line for chroma (C GO LINE). Its function can be described by the following algorithm:

if(UC_4_2_0 = = 1) /* 4:2:0 input V

{ if(UC_V//D[1] = = INTERLACE) DISTANCE = 32768 else

DISTANCE = 16384

} else /* 4:2:2 input */ { if(UC_V//D[1] = = INTERLACE)

DISTANCE = 16384 else

DISTANCE = 8192

C GO LINE = /NO/DISTANCE; /* Division with DISTANCE is a shift */ /* left operator of 13, 14 or 15 bits V if (C INIT VFC = = 1) { if(UC_4_2_0 = = 1) /* 4:2:0 input V

{ C GO LINE + = 1;

} else /* 4:2:2 input V

{ if((UC_VIID[1] = = INTERLACE &&

VJ/D = = EVEN) | | disp_v2 = = 7 | | disp_v4 = = 1 )

C GO LINE + = 1; else

C GO LINE + = 2;

} }

For VFC luma control 900 shown in FIG. 9, the shift function > > (X) in shifter block 908 performs a shift right function where the shift value is x. Its function can be described by the following algorithm:

if(UC_V//D[0] = = INTERLACE)

Out = In > > 9 else Out = In > > 8

For VFC chroma control 1 000 shown in FIG . 1 0, the shift function > > (X) in block 1 008 performs a shift function where the shift value is x. Its function can be described by the following algorithm: if(UC_4_2_0 = = 1) /* 4:2:0 input V

{ if(UC_VIID[1] = = INTERLACE)

Out = In > > 10 else

Out = In > > 9

} else /* 4:2:2 input V

{ if(UC_V//D[1] = = INTERLACE)

Out = In > > 9 else Out = In > > 8

} For VFC luma control 900 shown in FIG. 9 and VFC chroma control 1 000 shown FIG. 1 0, the Y PHASEJNIT and C PHASEJNIT values consist of a raster correction and a subline scanning value. FIG. 1 1 shows line positions at center if the Y_GO_LINE initialization value is used without a raster correction. Because the VFC start position must be the same for all input formats, a correction value is for some input formats necessary.

Thus, phase calculation 906 (shown in FIG . 9) generates Y PHASEJNIT according to the following algorithm:

if(disp_v2 = = 0 && disp_v4 = = 0) /* no vertical decimation is active */ if(UC_VIID[0] = = INTERLACE) iffVJ/D = = EVEN FIELD) Y PHASEJNIT = 8192 + UC LSTEP INIT; else

Y PHASE INIT = UC LSTEPJNIT; else

Y PHASEJNIT = UC LSTEP INIT;

if(disp_v2 = = 1 && disp_v4 = = 0) /* V/2 decimation is active V if(UC_V//D[0] = = INTERLACE) IffVJ/D = = EVEN FIELD) Y PHASEJNIT = 8192 + UCJ.STEPJNIT; else

Y_PHASEJNIT = 12288 + UC LSTEPJNIT; else

Y_PHASEJNIT = 6144 + UC LSTEPJNIT; if(disp_v2 = = 0 && disp_v4 = = 1)

/* V/4 decimation is active*/ if(UC_V//D[0] = = INTERLACE) iffVJ/D = = EVEN FIELD)

Y PHASEJNIT = 8192 + UC LSTEP INIT; else

Y_PHASEJN/T = 10240 + UC LSTEP INIT; else

Y PHASE INIT = 5120 + UC LSTEP INIT;

Likewise, phase calculation 1006 (shown in FIG. 10) generates C PHASEJNIT according to the following algorithm:

if(UC_4_2JD = = 1) /* 4:2:0 input */ if(disp_v2 = = 0 && disp_v4 = = 0)

/* no vertical decimation is active */ if(UC_VIID[l] = = INTERLACE) iffVJ/D = = EVEN FIELD)

C_PHASEJN/T = 12288 + UC LSTEPJNIT; else

C PHASEJNIT = 28672 + UC LSTEPJNIT; else C PHASEJNIT = 12288 + UC LSTEP INIT;

if(disp_v2 = = 1 && disp_v4 = = 0) V/2 decimation is active */ if(UC_V//D[1] = = INTERLACE) iffVJ/D = = EVENJIELD)

C PHASEJNIT = 14336 + UC LSTEPJNIT; else

C_PHASEJNIT = 22528 + UC LSTEP INIT; else C PHASEJNIT = 10240 + UC LSTEP INIT;

if(disp_v2 = = 0 && d/sp_v4 = = 1)

/* V/4 decimation is active */ if(UC_VI/D[1] = = INTERLACE) iffVJ/D = = EVEN FIELD)

C PHASEJNIT = 15360 + UC LSTEPJNIT; else

C PHASEJNIT = 19456 + UC LSTEP INIT; else C PHASE INIT = 9216 + UC LSTEP INIT; else /* 4:2:2 input */ if(disp_v2 = = 0 && disp_v4 = = 0)

/* no vertical decimation is active*/ if(UC_V//D[1] = = INTERLACE) iffVJ/D = = EVEN FIELD)

C_PHASEJNIT = 8192 + UC LSTEPJNIT; else

C PHASEJNIT = UC LSTEP INIT; else C PHASEJNIT = UC LSTEP INIT;

if(disp_v2 == 1 && disp_v4 = = 0) /* V/2 decimation is active*/ ιf(UC_V//D[1] = = INTERLACE) iffVJ/D = = EVEN_F/ELD)

C PHASEJNIT = 8192 + UC LSTEPJNIT; else

C_PHASEJNIT = 12288 + UC LSTEPJNIT; else C PHASEJNIT = 6144 + UC LSTEPJNIT;

if(disp_v2 = = 0 && disp_v4 = = 1) /* V/4 decimation is active */ if(UC_V/ID[1] = = INTERLACE) iflV UD = = EVEN FIELD)

C PHASE INIT = 8192 + UC LSTEPJNIT; else

C PHASEJNIT = 10240 + UC LSTEPJNIT; else C PHASE INIT = 5120 + UC LSTEP INIT; Referring to FIG. 12, there is shown a block diagram 1200 illustrating further detail for VFC luma output line control block 918, which includes a line output counter 1202 for generating Y_LOC, a vertical zone detection 1204 for generating Y LDELTA, and an FSM (Finite State Machine) 1206 for generating control signals for luma.

For non linear zoom option, vertical active display size is divided into five zones. Each zone has a LDELTA value. The active zone is selected on the actual output line that is counted by Y LOC. The LDELTA value is the change of

LSTEP of one progressive output line as the following algorithm:

if (Y LOC < UC_VZONE1) Y DELTA = UCJDELTA1 else if(YJOC < UC /ZONE2) Y DELTA = UCJDELTA2 else if(Y_LOC < UC /ZONE3) Y DELTA = 0 else if (Y LOC < UC VZONE4) Y DELTA = UC LDELTA4 else

YJDELTA = UCJDELTA5

The structure for chroma output line control block 1018 is similar to that shown in FIG. 12. More specifically, a chroma line control block will include a chroma line output counter for generating C LOC, a vertical zone detection for generating C_LDELTA, and an FSM for generating the control signals and values for VFC chroma control 1000 as shown in FIG. 10.

Referring to FIG. 13, there is shown a state machine for FSM 1206. The inputs of the state machine are V RST DR, Y LOC, Y GO LINE, V OID, UC_VOID, YJNPUT EOL (end of line signal) and Y_OUTPUT_EOL (end of line signal). The outputs of the state machine are YJNIT VFC, Y_WMUX, Y RMUX, Y_H_PROG, Y_H_VFC, and Y NEW LINE. YJNIT VFC sets Y line detection block 912 and DTO1 and DT2 blocks into initial mode. Y WMUX and Y RMUX set the VFC filter multiplexers (shown in FIG.7) and Y H PROG indicates that a new output line is available. If it is in the correct raster, an Y H VFC pulse is also generated.

V RST DR resets FSM 1206. Y_LOC is the actual output line number (progressive count). Y GO LINE is the number of input lines that are necessary for the next Y H PROG pulse. V OID is vertical raster ID and UC VOID is output format ID (field or frame). YJNPUT EOL indicates the status of the input line transmission (1 -> transmission is ready). Y OUTPUT EOL indicates the status of output line transmission (1 -> transmission is ready). YJNIT VFC is high one clock after the first Y_H_PROG pulse.

FSM 1206 includes internal registers for counter, rmux and wmux. The count register is for loading the Y GO LINE value, and the FSM decrements it for each requested new line until it is zero. The FSM can only request an input line if the counter is greater than zero and VFC input source is ready with the previous line (YJNPUTJΞOL = 1). The rmux register is for the Y RMUX output, and the rmux value changes with a Y H PROG pulse. The mathematical function for rmux is rmux = (rmux + Y_GO_LINE)%4. The Y RMUX value equals rmux when output line is in correct raster. The wmux value changed with each new requested line. The mathematical function for wmux is wmux = (wmux + 1)%4. The Y WMUX output equals wmux.

The implementation of the state machine for chroma is in principle the same as that for luma. More specifically, the state machine for chroma will generates the control signals and values (i.e., C_RUMX, CJΛ/MUX, Y JNIT VFC, Y H PROG, Y_H_VFC and Y NEW LINE) for the chroma FSM. The state machine shown in FIG. 13 operates according to the following state tables:

Note: All states has a reset transition that is: Transition Name: V RST DR

Condition: V RST DR = = 1

Description: Go to start state

Assignments during transition:

State 1 : no active video:

Transition Name: Y INIT START

Condition:

Description: Set init mode and init values

Assignments during transition: count = 0; wmux = 0; rmux = 0;

YJNIT_VFC = 1 ;

Y WMUX = 0;

Y RMUX = 0,

Y_H_PROG = 0,

Y_H_VFC = 0;

Y NEW LINE = 0;

State 2: set init

Transition Name: Y FIRST LOAD

Condition: *

Description: Request the first line, read Y GO LINE, set mux and count values

Assignments during transition:

Y NEWJJNE = 1; wmux = 1 ;

Y WMUX = 1; count = Y GO LINE-1; rmux = Y GO LINE%4;

State 3: init line memory

Transition Name: Y REQUEST

Condition: ((YJNPUT_EOL == 1)&&(count > 0)&&(Y_NEW_LINE 0))

Description: The transmission of the input line is ready and we need more lines for the next output line

Assignments during transition:

Y NEWJJNE = 1; count --; wmux = (wmux +1)%4;

Y WMUX = wmux; Transition Name: Y CLR REQUEST

Condition: Y INPUT EOL = = 0

Description: The transmission of the input line is not ready - > clear the line request

Assignments during transition: Y NEW LINE = 0;

Transition Name: Y GEN H SYC

Condition: ((Y INPUT EOL = = 1 )&&(count = = 0))

Description: All lines are requested and transmitted for the next output line. The H-SYNC depends on the field raster. V OID is 0 for even fields

Assignments during transition: if(((Y_LOC(0) ! = V_OID) && (UC VOID = = INTERLACE)) | | (UC VOID = = PROGRESSIVE))

{ Y_H_PROG = 1 ; Y_H_VFC = 1 ; Y_RMUX = rmux;

} else

Y H PROG = 1

State 4: first gen. H SYC

Transition Name: Y INIT END

Condition: *

Description: Clear H-SYC and Y INIT VFC

Assignments during transition: Y_H_PROG = 0; Y_H_VFC = 0; Y INIT VFC = 0;

State 5: clear init Transition Name: Y SECOND LOAD

Condition: *

Description: Read the second Y GO LINE value

Assignments during transition: count = Y GOJJNE; rmux = (rmux + Y GO LINE)%4;

State 6: running

Transition Name: Y REQUEST2

Condition: ((Y JNPUT EOL = = 1 )&&(count > 0) && Y NEW LINE 0))

Description: The transmission of the input line is ready and we need more lines for the next output line which is inside the active video

Assignments during transition:

Y NEW LINE = 1 ; count wmux = (wmux + 1 )%4;

Y WMUX = wmux;

Transition Name: Y CLR REQUEST2

Condition: (Y INPUT EOL = = 0)

Description: The transmission of the input line is not ready and the next output line is inside the active video - > clear the line request

Assignments during transition: Y NEW LINE = 0; Transition Name: Y GEN H SYC

Condition: ((Y OUTPUT EOL = = 1 )&&(count = = 0))

Description: All lines are requested for the next output line which is inside the active video. The last line must only requested and not be transmitted. The H-SYNC depends on the field raster. V OID is 0 for even fields

Assignments during transition: if(((Y_LOC(0) ! = V_OID) && (UCJVOID = = INTERLACE)) | | (UC_VOID = = PROGRESSIVE))

{ Y_H_PROG = 1 ; Y H VFC = 1 ; Y RMUX = rmux;

} else

Y_H_PROG = 1 ; Y NEW LIN = 0;

State 7: load n

Transition Name: Y N LOAD

Condition: *

Description: Load the Y GO LINE, set rmux and clear H-SYC

Assignments during transition:

Y H PROG = 0;

YJH VFC = 0;

YJMEWJJNE = 0; count = YJ3O LINE; rmux = (rmux + Y GO LINE) %4;

Referring to FIG. 1 4, there is shown a block diagram 1 400 illustrating further detail for read/write protection and end of line detection block 91 6 for luma shown in FIG. 9. The read/write protection and end of line detection block includes a pixel overwrite protection block 1 402, an input line state block 1 404 and an output line state block 1 406.

In FIG. 1 4, RTR and RTS are handshaking signals. UC HSINL is horizontal size of an stored input video image, Y_NEW_LINE line is line request from the VFC luma output line control, YJNPUT EOL is the end of line signal from input lines, Y WR EN is write enable signal for the VFC line memories, Y PIC is pixel position of input line, Y POC is pixel position of output line, Y_OUTPUT_EOL is the end of line signal from output lines, UC HINP is horizontal write start position, UC YHINL is horizontal write length, Y H VFC is new horizontal output line signal, Y RD EN is enable signal for the VFC line memory reading. YJNPUT_ON signal is enable signal to overwrite actual write position in the VFC line memory and Y OUTPUT ON is enable signal to read out from the actual line memory positions.

Y JNPUT_ON is set to zero to stop writing of the line memories. Thus prior to initiating writing, it needs to detect whether the reading is active (active when Y OUTPUT EOL = = 0) . When the reading is active, it needs to continuously check the status of the reading until Y OUTPUT EOL goes to one (only for the actual output line), when the write position is lower than the read position. When Y OUTPUTJEOL becomes one, YJNPUT ON is set to zero. Y OUTPUT ON is set to zero to stop reading of the line memories. Thus, prior to initiating reading, it needs to detect whether the writing is active (active when YJNPUTPUT_EOL = = 0) . When the writing is active, it needs to continuously check the status of the writing until Y_INPUT_EOL goes to one (only for the actual input line), when the read position is lower than the write position. When Y JNPUT_EOL becomes one, Y OUTPUT ON is set to zero.

The further detail of the structure and operation of the read/write protection and end of line detection block 1 01 6 for chroma is in principle the same as that shown in FIG . 14.

For VFC luma control 900 shown in FIG. 9 and VFC chroma control 1000 shown in FIG. 1 0, run in and run out control block (91 4 or 1 01 4) performs initialization to VFC luma filter 71 4 or VFC chroma filter 81 4. The structure for luma and chroma is the same. This block needs a line input counter (Y LIC for luma and C LIC for chroma). The counter is set to zero with V_RST_DR. With each Y_H_PROG pulse the counter counts up the Y GO LINE input value for luma (counts up C GO LINE input for chroma). Y GO LINE (or C_GO_LINE) can differ if the number of requested lines is greater than the number of available lines.

For "filter run-in", Y RUN IN (or C RUNJN) is set during the first input line so that the first line is copied to all line memories (shown in FIG. 7 or FIG. 9).

For "filter run-out" for luma, it needs to detect how much Y LIC is greater than the number of available input lines. For interlace luma inputs, the number of input line is indicated by UC_VINL/2. For progressive luma inputs, the number of input lines is indicated by UC_VINL. The Y RUN OUT value is only updated with next Y H PROG pulse because the Y GO LINE value is for the next Y_H_PROG pulse. The function for Y RUN OUT is defined as:

For luma, the filter run out function (see run in and run out control block

914 shown in FIG. 9) also limits Y GO LINE input to Y GOJ NE output if necessary. Thus, Y GO LINE (output) equals YJ3OJJNE (input) when the number of input lines is greater than Y_LIC + Y GO LINE (input). The

Y GO LINE (output) is reduced by the difference (after this situation Y GO LINE (output) is set to 0 until V_RST_DR) when the number of input lines is less than

Y LIC + Y GO LINE (input) .

For "filter run-out" for chroma, it needs to detect how much C_LIC is greater than the number of available input lines. For 4:2:0 interlace chroma inputs, the number of input lines is UC VINL/4; for 4:2:0 progressive chroma inputs, the number of input lines is UC VINL/2. For 4:2:2 interlace chroma inputs, the number of available input lines is UC VINL/2; for 4:2:2 progressive chroma inputs, the number of available input lines is UC VINL. The C_RUN_OUT value is only updated with next C_H_PROG pulse because the C GO LINE value is for next C_H_PROG pulse. Thus, C RUN OUT is zero until C LIC is less than the vertical number of input lines, and C RUN OUT is 1 when C LIC is greater than the vertical number of input lines.

For chroma, the filter run out function (see run in and run out control block 1 014 shown in FIG. 1 0) also limits C_GO_LINE input to C_GO_LINE output. Thus, CJ3OJJNE (output) equals C GO LINE (input) when the number of input lines is greater than C LIC + CJ3O LINE (input) . C_GO_LINE (output )is reduced by the difference (after this situation C GO LINE output is set to 0 until V RSTJDR) when the number of input lines is greater than C LIC + C GO LINE input.

Referring to FIG. 1 5, there is shown a coefficient table for the VFC luma filter.

In the present invention, VFC luma filter 700 can be bypassed by a register. Specifically, if bit 0 of register UC_VFC_THRU is set to 0, the luma coefficients from the coefficient RAM are applied. If this bit is set to 1 , the luma coefficient bypass mode is activated and the following coefficients are used: Luminance CYO = 0 CY1 = 1 CY2 = 0

CY3 = 0

For chroma, if bit 1 of UC VFCJTHRU register is set to 0, the luma coefficient (CC1 ) is applied from block 1 008 (see FIG. 1 0) . If this bit is set to 1 , the luma coefficient (CC1 ) is 0.

While the present invention has been described with reference to the preferred embodiments, it is apparent that that various changes may be made in the embodiments without departing from the spirit and the scope of the invention, as defined by the appended claims.

Claims

1 . A method for processing pixel frames frame by frame for a display device, each of the pixel frames containing a plurality of pixel lines and having an end position, the method comprising the steps of: receiving (702) a plurality of pixel lines; processing (714) the received pixel lines; outputting (71 6) the processed pixel lines to the display device; detecting (91 4) an end position for a pixel frame; and eliminating (704) edge effects on the display device upon detection of the end position of the pixel frame.

2. The method of claim 1 , wherein the eliminating step further comprises the step of: repeatedly receiving at least one pixel line located on or preceding to the end position of the pixel frame.

3. The method of claim 2, wherein the repeatedly received pixel line is the last line of the pixel frame.

4. The method of claim 2, wherein the repeatedly received pixel line is the penultimate line of the pixel frame.

5. In using a system having a filter for processing pixel frames frame by frame for a display device, each of the pixel frames containing a plurality of pixel lines and having an end position, a method comprising the steps of: receiving (702) a plurality of pixel lines into the filter; processing (71 4) the received pixel lines in the filter; outputting (71 6) the processed pixel lines from the filter to the display device; detecting (91 4) an end position of a pixel frame; and eliminating (704) edge effects on the display device upon detection of the end position of the pixel frame.

6. The method of claim 5, wherein the eliminating step further comprises the step of: repeatedly receiving at least one pixel line from the filter, wherein the repeated pixel line is located on or preceding to the end position of the pixel frame.

7. The method of claim 6, wherein the repeatedly received pixel line is the last line of the pixel frame.

8. The method of claim 6, wherein the repeatedly received pixel line is the penultimate pixel line of the pixel frame.

9. The method of claim 6, wherein the filter includes a plurality of line memories, and the repeatedly receiving step receives the at least one pixel line from at least one of the line memories.

1 0. The method of claim 6, wherein the filter includes a first filter for processing chroma data and a second filter for processing luma data.

1 1 . An apparatus for processing pixel frames frame by frame for a display device, each of the pixel frames containing a plurality of pixel lines and having an end position, the apparatus comprising: filter means for receiving (702), processing (71 4) and outputting (71 6) a plurality of pixel lines; means for detecting (91 4) an end position of a pixel frame; and means for eliminating (704) edge effects on the display device upon detection of the end position of the pixel frame.

1 2. The apparatus of claim 1 1 , wherein the eliminating means further comprises: means for repeatedly receiving at least one pixel line from the filter, wherein the repeatedly received pixel line is located on or preceding to the end position of the pixel frame.

1 3. The apparatus of claim 1 2, wherein the repeatedly received pixel line is the last pixel line of the pixel frame.

1 4. The apparatus of claim 1 2, wherein the repeatedly received pixel line is the penultimate pixel line in the pixel frame.

1 5. The apparatus of claim 1 2, wherein the filter means includes a plurality of line memories, and the means for repeatedly receiving receives the at least one pixel line from at least one of the line memories.

1 6. The apparatus of claim 1 1 , wherein the filter means includes a first filter means for processing chroma data and a second filter means for processing luma data.