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WO2001026128A1 - Electron source, method of manufacture thereof, and display device - Google Patents

Electron source, method of manufacture thereof, and display device Download PDF

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Publication number
WO2001026128A1
WO2001026128A1 PCT/JP1999/005401 JP9905401W WO0126128A1 WO 2001026128 A1 WO2001026128 A1 WO 2001026128A1 JP 9905401 W JP9905401 W JP 9905401W WO 0126128 A1 WO0126128 A1 WO 0126128A1
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WO
WIPO (PCT)
Prior art keywords
film
electrode
thin
electron source
thick
Prior art date
Application number
PCT/JP1999/005401
Other languages
French (fr)
Japanese (ja)
Inventor
Masakazu Sagawa
Makoto Okai
Mutsumi Suzuki
Akitoshi Ishizaka
Toshiaki Kusunoki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1999/005401 priority Critical patent/WO2001026128A1/en
Priority to KR1020027003567A priority patent/KR20020030827A/en
Publication of WO2001026128A1 publication Critical patent/WO2001026128A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/312Cold cathodes, e.g. field-emissive cathode having an electric field perpendicular to the surface, e.g. tunnel-effect cathodes of metal-insulator-metal [MIM] type

Definitions

  • Electron source method of manufacturing electron source, and display device
  • the present invention relates to an electron source, a method of manufacturing the electron source, and a display device, and is particularly applied to a thin-film electron source having a three-layer structure of a lower electrode, an insulating layer, and an upper electrode and emitting electrons in a vacuum. And effective technology. Background art
  • FEDs field emission '' Displays
  • This FED is, for example, as described in Japanese Patent Application Laid-Open No. Hei 4-289644, after arranging an electron-emitting device for each pixel and accelerating the emitted electrons therefrom in a vacuum, The fluorescent material is irradiated, and the irradiated portion of the fluorescent material emits light.
  • Thin-film electron source matrix is known as an example of an electron source for FED o
  • a thin-film electron source is, for example, a device in which a voltage is applied between an upper electrode and a lower electrode in a three-layer thin film structure consisting of an upper electrode, an insulating layer and a lower electrode, and electrons are emitted from the surface of the upper electrode into vacuum. It is.
  • MIM Metal-Insulator-Metal
  • MIS metal-insulator-metal with metal-insulator-semiconductor electrode stacked
  • Insulator-semiconductor type a laminated film composed of a metal-insulator and a semiconductor, a metal, or a semiconductor electrode is known.
  • the MIM type thin film electron source is described in, for example, Japanese Patent Application Laid-Open No. 7-65710.
  • FIG. 24 is a diagram for explaining the operating principle of the thin-film electron source.
  • a driving voltage of Vd is applied between the upper electrode 13 and the lower electrode 11 from a driving voltage source to reduce the electric field in the tunnel insulating layer 12 to about 1 to 10 OMV / cm
  • the lower electrode 1 Electrons in the vicinity of the Fermi level in 1 pass through the barrier due to the tunnel phenomenon, and are injected into the conduction bands of the tunnel insulating layer 12 and the upper electrode 13 to become a hot electron.
  • a plurality of upper electrodes 13 and a plurality of lower electrodes 11 are provided, and the plurality of upper electrodes and the plurality of lower electrodes 11 are orthogonal to each other to form a thin-film electron source into a matrix.
  • an electron beam can be generated from any place, and can be used as an electron source of a display device.
  • the MIM thin-film electron source emits the hot electron, accelerated by the tunnel insulating layer 12, through the upper electrode 13 and into a vacuum.
  • the film thickness of the upper electrode 13 needs to be extremely thin, about several nm, in order to reduce scattering of the hot electron.
  • the sheet resistance of the upper electrode 13 is about 200 ⁇ / port, and the unit is
  • the wiring resistance per length can be as high as 7 kQ / cm.
  • the operating voltage of the thin-film electron emitter is 10 V and the current consumption is 1 mA, so the voltage drop due to the wiring resistance is 7 V / cm.
  • Such a large voltage drop is completely fatal when attempting to increase the size of the display screen of a display device using a thin-film electron source, and measures to prevent the voltage drop are indispensable.
  • the voltage drop can be compensated by the driving method, but it complicates the driving circuit and is not preferable in terms of the reliability of the ultra-thin wiring.
  • the power supply wiring (1) low resistance, (2) electric contact between the upper electrode 13 and the power supply wiring can be obtained, and (3) the upper electrode 13 does not break at the element step. (4) It is necessary to satisfy the four points that the formation of the power supply wiring does not affect the thin-film electron source device with the tunnel diode structure.
  • A1 alloy is conceivable as such a power supply wiring material.
  • Nd A1-neodymium (Nd; hereinafter, simply referred to as Nd) (2 atm%) alloy, which is also used as the lower electrode 11, is a low-resistance material having excellent heat resistance.
  • (2) and (3) have difficulty. That is, since a natural oxide film always intervenes on the surface of A1, contact resistance becomes a problem.
  • An object of the present invention is to reduce the resistance of a power supply bus electrode in an electron source and a method of manufacturing an electron source. Electrode of the electron source at the electron emission section It is an object of the present invention to provide a technology capable of preventing the disconnection of a step.
  • Another object of the present invention is to provide a technology that can prevent the occurrence of uneven brightness on a display screen by using the thin-film electron source in a display device. .
  • the present invention relates to an electron source comprising: a plurality of electron source elements; and a plurality of pass electrodes for applying a drive voltage to the electron source elements in a first direction among the plurality of electron source elements.
  • Each of the bus electrodes is electrically connected to an electrode of each of the electron source elements, and a thin film electrode having a thickness of 10 times or less the thickness of the electrode of the electron source element; It is characterized by comprising a thick-film electrode which is electrically connected to the electrode and has a larger thickness than the thin-film electrode.
  • the present invention has a structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and when a positive voltage is applied to the upper electrode, electrons are emitted from the upper electrode surface.
  • a thin-film electron source comprising: a plurality of electron source elements to be emitted; and a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements.
  • Each of the bus electrodes includes a thin-film electrode electrically connected to the upper electrode, and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode. And features.
  • the present invention has a structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and when a positive voltage is applied to the upper electrode, electrons are emitted from the upper electrode surface.
  • a thin-film electron source comprising: a plurality of electron source elements to be emitted; and a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements.
  • the bus electrodes each include a thin-film electrode provided integrally with the upper electrode, and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode. It is characterized by.
  • the present invention is characterized in that the thick film electrode is formed by using any one of electric plating, sputtering, vacuum evaporation, chemical vapor deposition, or printing.
  • the present invention is a display device using the thin-film electron source.
  • FIG. 1 is a diagram showing a structure of a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 2 is a view for explaining a method of manufacturing a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 1 is a diagram showing a structure of a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 2 is a view for explaining a method of manufacturing a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 1 is a diagram showing a structure of a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 2 is a view for explaining a method of manufacturing a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 3 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
  • FIG. 4 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
  • FIG. 5 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
  • FIG. 6 illustrates a method for manufacturing a thin-film electron source according to Embodiment 1 of the present invention.
  • FIG. 7 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
  • FIG. 8 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
  • FIG. 9 is a diagram for explaining a method of manufacturing the thin-film electron source according to the second embodiment of the present invention.
  • FIG. 10 is a diagram for explaining a method of manufacturing the thin-film electron source according to the second embodiment of the present invention.
  • FIG. 11 is a diagram for explaining a method of manufacturing a thin-film electron source according to Embodiment 2 of the present invention.
  • FIG. 12 is a view for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
  • FIG. 13 is a diagram for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
  • FIG. 14 is a diagram for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
  • FIG. 15 is a diagram for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention.
  • FIG. 16 is a view illustrating a method for manufacturing a thin-film electron source according to Embodiment 4 of the present invention.
  • FIG. 17 is a view for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention.
  • FIG. 18 is a view for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention.
  • FIG. 19 is a diagram showing a schematic configuration of a thin-film electron source array substrate of a display device according to Embodiment 5 of the present invention.
  • FIG. 20 is a diagram showing a schematic configuration of a fluorescent display panel of a display device according to Embodiment 5 of the present invention.
  • FIG. 21 is a cross-sectional view illustrating a schematic overall configuration of a display device according to Embodiment 5 of the present invention.
  • FIG. 22 is a schematic diagram showing a state where a drive circuit is connected to the display device according to the fifth embodiment of the present invention.
  • FIG. 23 is a timing chart showing an example of the waveform of the drive voltage output from each drive circuit shown in FIG.
  • FIG. 24 is a diagram showing the operating principle of the thin-film electron source. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a cross-sectional view showing a structure of one element of a thin-film electron source according to Embodiment 1 of the present invention.
  • the bus electrode serving as the power supply wiring has a bus electrode lower layer 15 electrically connected to the upper electrode 13, and a bus electrode upper layer lining the bus electrode lower layer 15. 16 and the upper layer 16 of the bus electrode is formed of a sputtering film.
  • FIG. 2A is a plan view
  • FIG. 2B is a cross-sectional view showing a cross-sectional structure taken along line AA ′ in FIG.
  • Figure (c) is a cross-sectional view showing the cross-sectional structure taken along the line BB of Figure (a).
  • an insulating substrate 10 made of glass or the like is prepared, and a metal film for a lower electrode is formed on the substrate 10.
  • A1 or A1 alloy is used as a material for the lower electrode.
  • an Al—Nd alloy in which Nd was doped at 2 atomic weight% was used.
  • the metal film was formed by, for example, sputtering, and the thickness was set to 300 nm.
  • a strip-shaped lower electrode 11 is formed by etching.
  • etching for example, wet etching using a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid was used.
  • a portion serving as an electron emitting portion on the lower electrode 11 is masked with a resist film 17, and a portion serving as an electron emitting portion on the lower electrode 11 is formed in a chemical conversion solution using the lower electrode 11 as an anode.
  • the other portions are selectively anodized thickly to form a protective insulating layer 14 as shown in FIG.
  • a protection insulating layer 14 having a thickness of about 13 nm is formed.
  • the resist film 17 is removed, and anodization is performed again in a chemical solution using the lower electrode 11 as an anode, and as shown in FIG. Next, a tunnel insulating film 12 is formed.
  • a tunnel insulating layer 12 having a thickness of about 10 nm is formed on the lower electrode 11.
  • a bus electrode film serving as a power supply line to the upper electrode 13 is formed by sputtering.
  • the bus electrode film a laminated film of a metal film to be the lower layer of the bus electrode (thin film electrode of the present invention) 15 and a metal film to be the upper layer of the bus electrode (thick film electrode of the present invention) 16 is used.
  • Tungsten (W) was used as a material for the lower layer of the bus electrode
  • an A1-Nd alloy was used as a material for the upper layer of the bus electrode.
  • the upper limit of the thickness of the metal film to be the bus electrode lower layer 15 is set so that the upper electrode 13 to be formed later is not disconnected by the step of the bus electrode lower layer 15. Set to 10 times the film thickness. More specifically, the thickness is reduced to about several nm to several hundred nm, and the metal film to be the upper layer 16 of the bus electrode is formed to be as thick as about several hundred nm in order to sufficiently supply power.
  • the lower limit of the thickness may be a thickness that functions as a conductor.
  • the thickness of the upper electrode 13 is preferably about 1/10.
  • the upper layer 16 of the bus electrode is striped in a direction orthogonal to the lower electrode 11 by a photolithography step and an etching step.
  • etching for example, a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid was used.
  • the bus electrode lower layer 15 is processed in the same photolithography step and etching step.
  • tungsten For the etching of tungsten (W), a mixed aqueous solution of ammonia and hydrogen peroxide is suitable. Finally, as shown in FIG. 8, an upper electrode 13 is formed. Thus, the thin-film electron source of the present embodiment is completed.
  • the upper electrode 13 was patterned by lift-off, and the upper electrode 13 was formed by sputtering.
  • the upper electrode 13 for example, a laminated film of iridium (Ir), platinum (Pt), and gold (Au) is used, each having a thickness of several nm, and formed as described above. We went by a spa ring.
  • the metal film to be the bus electrode upper layer 16 is formed by sputtering, but the present invention is not limited to this, and the metal film to be the bus electrode upper layer 16 is formed. May be formed by any of the following methods: electric plating, vacuum deposition, chemical vapor deposition, or printing.
  • the bus electrode upper layer 16 is formed to be as thick as several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13
  • the sheet resistance can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 ⁇ / port), and the resistance of the bus electrode can be reduced.
  • the lower layer 15 of the bus electrode is formed to have a thickness in the range of several nm to several 10 nm, it is possible to prevent the upper electrode 13 from breaking due to a step of the lower layer 15 of the bus electrode. .
  • the thin-film electron source according to the second embodiment of the present invention is characterized in that the upper electrode 13 also serves as the lower layer of the bus electrode, and the upper layer 16 of the bus electrode is formed on the upper electrode by sputtering.
  • FIG. 9A is a plan view and FIG. 9B is a plan view. Is a cross-sectional view showing a cross-sectional structure taken along the line A-A 'in FIG. (A), and FIG. (C) is a cross-sectional structure taken along the line BB in FIG. (A). It is sectional drawing.
  • a metal film to be the upper electrode 13 and a metal film to be the bus electrode upper layer 16 are formed by sputtering in this order.
  • the material of the metal film to be the upper electrode 13 is, for example, a laminated film of tungsten (W), platinum (Pt), and gold (Au), each having a thickness of 1 to 3 nm.
  • a 1 -Nd alloy is deposited on the material of the metal film to be the bus electrode upper layer 16 by several 100 nm.
  • a resist pattern is formed by a photolithography process, and the A 1 -Nd alloy other than the upper layer of the bus electrode is removed by wet etching, and as shown in FIG.
  • the upper electrode layer 16 is formed.
  • etching a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid described above is preferable.
  • the electron-emitting portion is covered with a resist pattern, the metal film for the upper electrode on the upper layer of the bus electrode is removed, and an upper electrode 13 is formed as shown in FIG.
  • the thin-film electron source of the present embodiment is completed.
  • aqua regia is preferably used for platinum (Pt) and gold (Au)
  • the above-described mixed aqueous solution of ammonia and hydrogen peroxide is preferably used for tungsten (W).
  • the metal film to be the bus electrode upper layer 16 is formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. ⁇ ⁇ It may be formed.
  • the upper layer 16 of the bus electrode is formed to be as thick as several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13
  • the sheet resistance can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 ⁇ / port), and the resistance of the bus electrode can be reduced.
  • the upper electrode 13 is also used as the lower layer of the bus electrode, the disconnection of the upper electrode 13 at the electron emission portion can be prevented.
  • the thin-film electron source according to Embodiment 3 of the present invention is characterized in that the upper electrode 13 also serves as the lower layer of the bus electrode, and the upper layer 16 of the bus electrode is formed on the upper electrode by electric plating. I do.
  • FIG. 12A is a plan view
  • FIG. 12B is a cross-sectional view showing a cross-sectional structure taken along the line AA ′ in FIG.
  • C is a cross-sectional view showing the cross-sectional structure taken along the line BB in FIG. (A).
  • a metal film to be the upper electrode 13 is formed by sputtering.
  • the material for the upper electrode is, for example, a laminated film of tungsten (W), platinum (Pt), and gold (Au), each having a thickness of 1 to 3 nm. Subsequently, a portion where the upper layer 16 of the bus electrode is not formed is covered with a resist pattern, and a gold (Au) film is grown as a backing electrode by an electrolytic gold plating. As shown in FIG. 13, an upper layer 16 of the bus electrode is formed.
  • the electron-emitting portion is covered with a resist pattern, the metal film for the upper electrode on the upper layer of the bus electrode is removed, and an upper electrode 13 is formed as shown in FIG.
  • the thin-film electron source of the present embodiment is completed.
  • aqua regia is preferable for platinum (Pt) and gold (Au)
  • the above-mentioned mixed aqueous solution of ammonia and hydrogen peroxide is preferable for tungsten (W).
  • the upper layer 16 of the bus electrode may be formed by any one of sputtering, vacuum evaporation, chemical vapor deposition, or printing.
  • the upper electrode 13 and the bus electrode upper layer 1 are formed. 6 and the thickness of the upper layer 16 of the bus electrode can be set arbitrarily, and the damage to the tunnel insulating layer 12 is reduced as compared with other processes. Can be.
  • the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13 It can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 ⁇ / port), and the resistance of the bus electrode can be reduced.
  • the upper electrode 13 is also used as the lower layer of the bus electrode, the disconnection of the upper electrode 13 at the electron emission portion can be prevented.
  • the upper electrode 13 is electrically connected to the lower bus electrode layer 15, and the upper electrode layer 15 is electrically connected to the lower bus electrode layer 15 by electric plating. 6 is formed.
  • a method of manufacturing the thin-film electron source of the present embodiment will be described with reference to FIGS. 15 to 18.
  • FIG. 15A is a plan view
  • FIG. 15B is a cross-sectional view showing a cross-sectional structure taken along line AA of FIG. (C) is a cross-sectional view showing a cross-sectional structure taken along the line BB of FIG. (A).
  • a metal film to be the lower layer 15 of the bus electrode is formed by sputtering.
  • the metal film to be the bus electrode lower layer 15 for example, a laminated film of tungsten (W) and gold (Au) is preferable, and the thickness of each is preferably about 10 nm.
  • a portion where the upper layer 16 of the bus electrode is not formed is covered with a resist pattern, and a gold (Au) film is grown as a backing electrode by an electrolytic gold plating. As shown in FIG. The upper layer 16 is formed.
  • the lower layer 15 of the bus electrode is processed by a photolithography step and an etching step.
  • the bus electrode lower layer 15 is processed so as to protrude from the bus electrode upper layer 16. is there.
  • an upper electrode 13 is formed.
  • the upper electrode 13 is patterned by lift-off, and the upper electrode 13 is formed by sputtering.
  • the upper electrode 13 for example, a laminated film of iridium (Ir), platinum (Pt), and gold (Au) is used, each having a thickness of several nm, and the film is formed by sputtering as described above. The ring was used.
  • the metal film to be the pass electrode upper layer 16 may be formed by any of sputtering, vacuum deposition, chemical vapor deposition, or printing.
  • the pass electrode upper layer 16 is formed to be as thick as about several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the sheet of the upper electrode 13.
  • the resistance can be reduced by about two digits compared to the resistance (about 200 ⁇ / port), and the resistance of the bus electrode can be reduced.
  • the lower layer 15 of the bus electrode is formed as thin as several nm to several 1 Onm, the disconnection of the upper electrode 13 at the step of the lower layer 15 of the bus electrode can be prevented.
  • FIG. 19 is a diagram showing a schematic configuration of a thin-film electron source array substrate of a display device according to Embodiment 5 of the present invention.
  • FIG. 19 (a) is a plan view of the thin-film type electron source array substrate of the present embodiment
  • FIG. 19 (b) is a cross-sectional structure taken along line AA shown in FIG.
  • FIG. 19 (c) show the cross-sectional structure along the line BB 'shown in (a). It is an important section sectional view shown.
  • the thin-film electron source of the first embodiment is used as the thin-film electron source array substrate.
  • the thin-film electron source of the second to fourth embodiments may be used. It may be.
  • the thin-film electron source array substrate of the present embodiment is formed by forming a thin-film electron source in a matrix on the substrate 10 according to the procedure described in the first embodiment.
  • FIG. 19 a (3 ⁇ 3) dot thin film type electron source matrix composed of three lower electrodes 11 and three upper electrode paths 17 is shown. In practice, a number of thin-film electron source matrices corresponding to the number of display dots are formed.
  • bus electrode is actually a laminated structure of the lower layer 15 of the bus electrode and the upper layer 16 of the bus electrode. However, in FIG. 19, they are collectively shown as the laminated pass electrode 18.
  • the electrode portions of the lower electrode 11 and the upper bus electrode 18 are electrodes for circuit connection. The surface must be exposed.
  • FIG. 20 is a diagram showing a schematic configuration of a fluorescent display panel of a display device according to Embodiment 5 of the present invention.
  • FIG. 20 (a) is a plan view of the fluorescent display panel of the present embodiment
  • FIG. 20 (b) is a cross-sectional structure taken along the line A--A shown in FIG.
  • FIG. (C) is a cross-sectional view of a main part showing a cross-sectional structure along the line BB ′ shown in FIG. (A).
  • the fluorescent display panel of the present embodiment includes a black matrix 120 formed on a substrate 110 such as a soda glass, and a groove of the black matrix 120. It consists of red (R) and green (G) 'blue (B) phosphors (111-1113) formed in the inside, and a mail-back film 114 formed on these Is done.
  • a method for manufacturing the fluorescent display panel of the present embodiment will be described.
  • a black matrix 120 is formed on the substrate 110 in order to increase the contrast of the display device.
  • the black matrix 120 is formed by applying a solution of a mixture of polyvinyl alcohol (PVA; hereinafter, simply referred to as PVA) and ammonium dichromate to the substrate 110 to form the black matrix 120 After exposing to light by irradiating ultraviolet rays to the part other than the part to be exposed, the unexposed part is removed, a solution in which graphite powder is dissolved is applied, and PVA is formed by lift-off.
  • PVA polyvinyl alcohol
  • the red phosphor 111 is formed by the following method.
  • the portion where the phosphor is to be formed is exposed to ultraviolet light, and then exposed, and the unexposed portion is flushed. To remove.
  • the red phosphor 111 is patterned.
  • the phosphor pattern is a stripe pattern shown in FIG. 20, but this stripe pattern is merely an example. Of course, an “R GB G” pattern in which one pixel is composed of four dots may be used.
  • a green phosphor 112 and a blue phosphor 113 are formed by the same method.
  • a phosphor for example, a red phosphor 1 1 1 Y 2 0 2 S: E u ( ⁇ 2 2 - R), green phosphor 1 1 2 Z n S: Cu, A l (P 2 2—G).
  • ZnS Ag (P22—B) may be used.
  • the substrate 11 A1 is deposited on the entire surface to a thickness of about 5 nm to form a metal back film 114.
  • This metal back film 114 works as an accelerating electrode.
  • the substrate 110 is heated to about 400 ° C. in the air to thermally decompose organic substances such as a film and a PVA.
  • FIG. 21 is a cross-sectional view illustrating a schematic overall configuration of a display device according to Embodiment 5 of the present invention.
  • the figure (a) shows the cross-sectional structure along the line AA shown in Figs. 19 and 20 (a), and the figure (B) shows the figures 19 and 20 (a).
  • 2) is a cross-sectional view of a main part showing a cross-sectional structure along the line BB shown in FIG.
  • the thin film type electron source array substrate manufactured by the above procedure, a fluorescent display panel, and a frame member 116 are assembled via a spacer 30. After erection, the frame member 116 is sealed using the flat glass 115. The height of the spacer 30 is set so that the distance between the thin film type electron source array substrate and the fluorescent display panel is about 1 to 3 mm.
  • the spacer 30 is, for example, a plate-shaped glass or ceramic sensor, and the spacer 30 is arranged between the laminated bus electrodes 18.
  • the spacer 30 since the spacer 30 is disposed below the black matrix 120 of the fluorescent display panel, the spacer 30 does not hinder light emission.
  • a pillar-shaped spacer is used as the spacer 30. Panels can be assembled using the same method even when using grids or grid-shaped spacers.
  • Sealed panels is evacuated to 1 0_ 7 T 0 rr about vacuum, after sealed sealing to (sealing, rodents evening scratch activated to maintain the vacuum in the panel.
  • a getter film can be formed by high-frequency induction heating or the like.
  • a non-evaporable gas containing zirconium (Zr) as a main component may be used.
  • the acceleration voltage applied to the metal back film 114 is set to 3 to 6 KV and high voltage.
  • a phosphor for a cathode ray tube can be used as the phosphor.
  • the pass electrode forming the power supply wiring Since the resistance of the thin film type electron source element can be operated without uneven brightness, it is possible to prevent uneven brightness on the display screen.
  • FIG. 22 is a schematic diagram showing a state where a drive circuit is connected to the display device of the present embodiment.
  • the lower electrode 11 is driven by a lower electrode drive circuit 40, and the laminated bus electrode 18 is driven by an upper electrode drive circuit 50.
  • each drive circuit (40, 50) and the thin film type electron source array substrate is performed, for example, by pressing a tape carrier package with an anisotropic conductive film.
  • the semiconductor chips constituting the components and the drive circuits (40, 50) are formed by chip-on-glass, which is directly mounted on a substrate (eg, glass) of a thin-film type electron source array substrate.
  • An acceleration voltage of about 3 to 6 KV is applied to the metal back film 114 from the acceleration voltage source 60 at all times.
  • FIG. 23 is a timing chart showing an example of the waveform of the drive voltage output from each drive circuit shown in FIG.
  • the m-th lower electrode 11 is Km
  • the n-th laminated pass electrode 18 is C n
  • the intersection of the m-th lower electrode 11 and the n-th laminated bus electrode 18 is (m, n ).
  • the driving voltage of ( ⁇ V 1) from the lower electrode driving circuit 40 is applied to the lower electrode 11 of K 1, and the upper electrode driving circuit is applied to the laminated bus electrode 18 of (C 1, C 2).
  • a driving voltage of 50 to (+ V 2) is applied.
  • V 1 + V 2 Since a voltage (V 1 + V 2) is applied between the lower electrode 11 and the upper electrode 13 at the intersections (1, 1) and (1, 2), the (V 1 + V 2) If the voltage is set to be equal to or higher than the electron emission start voltage, electrons are emitted from the thin-film electron source at the intersection of these two into a vacuum.
  • the emitted electrons are accelerated by an accelerating voltage from an accelerating voltage source 60 applied to the metal back film 114, and then enter the phosphors (111 to 113) to emit light.
  • a drive voltage (-VI) from the lower electrode drive circuit 40 is applied to the lower electrode 11 of K2, and the upper electrode drive circuit 50 is applied to the laminated bus electrode 18 of C1. (+ V 2) P
  • a desired image or information can be displayed by changing the signal applied to the laminated bus electrode 18.
  • the application of the inversion voltage for releasing the charges accumulated in the tunnel insulating layer 12 is performed by applying the driving voltage of ( ⁇ VI) from the lower electrode driving circuit 40 to all of the lower electrodes 11.
  • the driving voltage of (+ V 3) from the lower electrode driving circuit 40 is applied to all the lower electrodes 11, and the driving voltage of ( ⁇ V 3,) from the upper electrode driving circuit 50 to all the laminated bus electrodes 18 This was achieved by applying a drive voltage.
  • a power supply bus electrode for applying a drive voltage to the electron source element is formed of a thin film electrode and a low-resistance thick film electrode lined on the thin film electrode.
  • the thin-film electrode was formed thin enough to be about the thickness of the electrode of the electron source, It is possible to prevent disconnection of the electrode of the electron source at the electron emission portion.
  • the resistance of the bus electrode constituting the power supply wiring can be reduced even on a large screen of a 40-inch class, and it is possible to prevent the occurrence of uneven brightness on the display screen. It becomes possible.

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Abstract

A thin-film electron source comprises a plurality of electron source elements, each including a laminate of a lower electrode (11), an insulating layer (12) and an upper electrode (13) formed in that order; and a plurality of buses for applying driving voltage to the upper electrode (13) of those in a first direction of the electron source elements. Each of the buses is composed of a thin-film electrode (15) connected electrically with the upper electrode (13), and a thick-film electrode (16) provided on the thin-film electrode (15) and being thicker than the thin-film electrode (15). This structure prevents the increase in resistance of the power buses for applying driving voltage to the electronic source elements and the damage to the upper electrodes (13) in the electron emission part.

Description

明 細 書 電子源、 電子源の製造方法および表示装置 技術分野  Description Electron source, method of manufacturing electron source, and display device
本発明は、 電子源、 電子源の製造方法および表示装置に係わり、 特に、 下部電極、 絶縁層、 上部電極の 3層構造を有し、 真空中に電子を放出す る薄膜型電子源に適用して有効な技術に関する。 背景技術  The present invention relates to an electron source, a method of manufacturing the electron source, and a display device, and is particularly applied to a thin-film electron source having a three-layer structure of a lower electrode, an insulating layer, and an upper electrode and emitting electrons in a vacuum. And effective technology. Background art
互いに直交する電極群の交点を画素とし、 各画素への印加電圧を調整 することによって画像を表示するマ ト リクス型表示装置 (マ ト リ クス型 ディスプレイ) の 1つに、 フィール ドェミ ッショ ン ' ディスプレイ (以 下、 F E D と称する。 ) が知られている。  One of the matrix-type displays (matrix-type displays) that displays images by adjusting the voltage applied to each pixel at the intersection of the electrode groups that are orthogonal to each other is a field emission '' Displays (hereinafter referred to as FEDs) are known.
この F E Dは、 例えば、 特開平 4 一 2 8 9 6 4 4号公報に記載されて いるように、 各画素毎に電子放出素子を配置し、 そこからの放出電子を 真空中で加速した後、 蛍光体に照射し、 照射した部分の蛍光体を発光さ せるものである。  This FED is, for example, as described in Japanese Patent Application Laid-Open No. Hei 4-289644, after arranging an electron-emitting device for each pixel and accelerating the emitted electrons therefrom in a vacuum, The fluorescent material is irradiated, and the irradiated portion of the fluorescent material emits light.
F E D用の電子源の一例として、 薄膜型電子源マ ト リ クスが知られて いる o  Thin-film electron source matrix is known as an example of an electron source for FED o
薄膜型電子源とは、 例えば、 上部電極—絶縁層一下部電極の 3層薄膜 構造の上部電極と下部電極の間に電圧を印加して、 上部電極の表面から 真空中に電子を放出させるものである。  A thin-film electron source is, for example, a device in which a voltage is applied between an upper electrode and a lower electrode in a three-layer thin film structure consisting of an upper electrode, an insulating layer and a lower electrode, and electrons are emitted from the surface of the upper electrode into vacuum. It is.
例えば、 金属一絶縁体一金属を積層した M I M ( Metal - Insulator- Metal ) 型、 金属一絶縁体一半導体電極を積層した M I S ( Metal - Insulator-Semiconductor)型や、 金属一絶縁体と半導体の積層膜一金属 または半導体電極を積層したもの等が知られている。 For example, MIM (Metal-Insulator-Metal) type with metal-insulator-metal stacked, MIS (metal-insulator-metal with metal-insulator-semiconductor electrode stacked) Insulator-semiconductor type, a laminated film composed of a metal-insulator and a semiconductor, a metal, or a semiconductor electrode is known.
なお、 M I M型の薄膜電子源については、 例えば、 特開平 7— 6 5 7 1 0号に記載されている。  The MIM type thin film electron source is described in, for example, Japanese Patent Application Laid-Open No. 7-65710.
第 2 4図は、 薄膜型電子源の動作原理を説明するための図である。 上部電極 1 3 と下部電極 1 1 との間に駆動電圧源から V dの駆動電圧 を印加して、 トンネル絶縁層 1 2内の電界を 1〜 1 O MV/ c m程度に すると、 下部電極 1 1中のフェルミ準位近傍の電子は ト ンネル現象によ り障壁を透過し、 トンネル絶縁層 1 2、 上部電極 1 3の伝導帯へ注入さ れホッ トエレク トロンとなる。  FIG. 24 is a diagram for explaining the operating principle of the thin-film electron source. When a driving voltage of Vd is applied between the upper electrode 13 and the lower electrode 11 from a driving voltage source to reduce the electric field in the tunnel insulating layer 12 to about 1 to 10 OMV / cm, the lower electrode 1 Electrons in the vicinity of the Fermi level in 1 pass through the barrier due to the tunnel phenomenon, and are injected into the conduction bands of the tunnel insulating layer 12 and the upper electrode 13 to become a hot electron.
これらのホッ トエレク トロンのうち、 上部電極 1 3の仕事関数 (0) 以上のエネルギーを有するものは、 真空 2 0中に放出される。  Among these hot electrons, those having energy equal to or higher than the work function (0) of the upper electrode 13 are released into the vacuum 20.
ここで、 上部電極 1 3および下部電極 1 1 とを複数本設け、 これら複 数本の上部電極と、 複数本の下部電極 1 1 とを直交させて、 薄膜型電子 源をマ ト リクス状に形成すると、 任意の場所から電子線を発生させるこ とができるので、 表示装置の電子源に用いることができる。  Here, a plurality of upper electrodes 13 and a plurality of lower electrodes 11 are provided, and the plurality of upper electrodes and the plurality of lower electrodes 11 are orthogonal to each other to form a thin-film electron source into a matrix. When formed, an electron beam can be generated from any place, and can be used as an electron source of a display device.
これまで、 金 ( A u ) —酸化アルミニゥム (A 1203 ; 以下、 単に、 A 1203と称する。 ) 一アルミニウム (A 1 ; 以下、 単に、 A 1 と称す る。 ) 構造の M I M (Metal-Insulator-Metal) 構造などから電子放出 が観測されている。 Previously, gold (A u) - oxide Aruminiumu (A 1 2 0 3;. Hereinafter, simply referred to as A 1 2 0 3) one aluminum (. A 1; hereinafter simply that referred to as A 1) of the structure Electron emission has been observed from MIM (Metal-Insulator-Metal) structures.
M I M型の薄膜型電子源は、 ト ンネル絶縁層 1 2で加速したホッ トェ レク トロンを、 上部電極 1 3を透過させて真空中に放出させる。  The MIM thin-film electron source emits the hot electron, accelerated by the tunnel insulating layer 12, through the upper electrode 13 and into a vacuum.
したがって、 上部電極 1 3の膜厚はホッ トエレク トロンの散乱を少な くするために数 nm程度と非常に薄く する必要がある。  Therefore, the film thickness of the upper electrode 13 needs to be extremely thin, about several nm, in order to reduce scattering of the hot electron.
そのため、 上部電極 1 3のシー ト抵抗は約 2 0 0 Ω /口となり、 単位 長さあた りの配線抵抗は 7 k Q/cmにも達する。 Therefore, the sheet resistance of the upper electrode 13 is about 200 Ω / port, and the unit is The wiring resistance per length can be as high as 7 kQ / cm.
この場合に、 薄膜型電子源素子の動作電圧は 1 0 V、 消費電流は l m Aなので、 配線抵抗による電圧降下は 7 V/cmになる。  In this case, the operating voltage of the thin-film electron emitter is 10 V and the current consumption is 1 mA, so the voltage drop due to the wiring resistance is 7 V / cm.
このような大きな電圧降下は、 薄膜型電子源を用いる表示装置の表示 画面の大型化を図る場合全く致命的であ り、 電圧降下を防止する策が必 須となる。  Such a large voltage drop is completely fatal when attempting to increase the size of the display screen of a display device using a thin-film electron source, and measures to prevent the voltage drop are indispensable.
電圧降下は駆動法で補償する事も可能ではあるが、 駆動回路の複雑化 を招く と共に、 超薄膜配線の信頼性の面でも好ましくはない。  The voltage drop can be compensated by the driving method, but it complicates the driving circuit and is not preferable in terms of the reliability of the ultra-thin wiring.
本質的には給電用に新たな配線を導入する事が不可欠である。  In essence, it is essential to introduce new wiring for power supply.
そして、 給電用配線としては、 ( 1 ) 低抵抗であること、 ( 2 ) 上部 電極 1 3と給電配線との電気的接触が取れること、 ( 3 ) 上部電極 1 3 が素子段差で段切れしないこと、 ( 4 ) 給電用配線の形成が、 トンネル ダイォー ド構造の薄膜型電子源素子に影響を及ぼさないことの 4点を満 足する必要がある。  As the power supply wiring, (1) low resistance, (2) electric contact between the upper electrode 13 and the power supply wiring can be obtained, and (3) the upper electrode 13 does not break at the element step. (4) It is necessary to satisfy the four points that the formation of the power supply wiring does not affect the thin-film electron source device with the tunnel diode structure.
このような給電用配線材料としては、 A 1合金が考えられる。  A1 alloy is conceivable as such a power supply wiring material.
例えば、下部電極 1 1 としても採用されている A 1—ネオジム(N d ; 以下、 単に、 Ndと称する。 ) ( 2 a t m%) 合金は耐熱性に優れた低 抵抗材料であるが、 前記項目 ( 2 ) と ( 3 ) に難がある。 即ち、 A 1の 表面には常に自然酸化膜が介在するため接触抵抗が問題となる。  For example, A1-neodymium (Nd; hereinafter, simply referred to as Nd) (2 atm%) alloy, which is also used as the lower electrode 11, is a low-resistance material having excellent heat resistance. (2) and (3) have difficulty. That is, since a natural oxide film always intervenes on the surface of A1, contact resistance becomes a problem.
加えてウエッ トエツチングゃ反応性イオンエッチング (R I E) を用 いたテ一パ加工は、 段切れを防止する上で制御性が十分とはいえず、 ス ト ツパとなる ト ンネル絶縁膜 1 2へのダメージも無視できなかった。 本発明は、 前記従来技術の問題点を解決するためになされたものであ り、 本発明の目的は、 電子源および電子源の製造方法において、 給電用 のバス電極の抵抗を減少させるとともに、 電子放出部での電子源の電極 の段差切れ防止することが可能となる技術を提供することにある。 In addition, tape etching using wet etching / reactive ion etching (RIE) is not sufficiently controllable to prevent disconnection, and the tunnel insulating film 12 that becomes the stopper is removed. The damage of could not be ignored. An object of the present invention is to reduce the resistance of a power supply bus electrode in an electron source and a method of manufacturing an electron source. Electrode of the electron source at the electron emission section It is an object of the present invention to provide a technology capable of preventing the disconnection of a step.
ことができる。 be able to.
また、 本発明の他の目的は、 表示装置において、 前記薄膜型電子源を 使用することによ り、 表示画面に輝度むらが生じるのを防止することが 可能となる技術を提供することにある。  Another object of the present invention is to provide a technology that can prevent the occurrence of uneven brightness on a display screen by using the thin-film electron source in a display device. .
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述 及び添付図面によって明らかにする。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本願において開示される発明のうち、 代表的なものの概要を簡単に説 明すれば、 下記の通りである。  The following is a brief description of an outline of typical inventions disclosed in the present application.
即ち、 本発明は、 複数個の電子源素子と、 前記複数個の電子源素子の 中の第 1の方向の電子源素子に駆動電圧を印加する複数のパス電極とを 有する電子源であって、 前記各バス電極は、 前記各電子源素子の電極と 電気的に接続され、 かつ膜厚が前記電子源素子の電極の膜厚の 1 0倍以 下の厚さの薄膜電極と、 前記薄膜電極と電気的に接続され、 前記薄膜電 極に比して膜厚が厚い厚膜電極とで構成されることを特徴とする。  That is, the present invention relates to an electron source comprising: a plurality of electron source elements; and a plurality of pass electrodes for applying a drive voltage to the electron source elements in a first direction among the plurality of electron source elements. Each of the bus electrodes is electrically connected to an electrode of each of the electron source elements, and a thin film electrode having a thickness of 10 times or less the thickness of the electrode of the electron source element; It is characterized by comprising a thick-film electrode which is electrically connected to the electrode and has a larger thickness than the thin-film electrode.
また、 本発明は、 下部電極と、 絶縁層と、 上部電極とをこの順番に積 層した構造を有し、 前記上部電極に正極性の電圧を印加した際に、 前記 上部電極表面から電子を放出する複数個の電子源素子と、 前記複数個の 電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電圧を印加 する複数のバス電極とを有する薄膜型電子源であって、 前記各バス電極 は、 前記上部電極と電気的に接続される薄膜電極と、 前記薄膜電極上に 設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成されるこ とを特徴とする。 また、 本発明は、 下部電極と、 絶縁層と、 上部電極とをこの順番に積 層した構造を有し、 前記上部電極に正極性の電圧を印加した際に、 前記 上部電極表面から電子を放出する複数個の電子源素子と、 前記複数個の 電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電圧を印加 する複数のバス電極とを有する薄膜型電子源であって、 前記各バス電極 は、 前記上部電極と一体的に設けられる薄膜電極と、 前記薄膜電極上に 設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成されるこ とを特徴とする。 Further, the present invention has a structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and when a positive voltage is applied to the upper electrode, electrons are emitted from the upper electrode surface. A thin-film electron source comprising: a plurality of electron source elements to be emitted; and a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements. Each of the bus electrodes includes a thin-film electrode electrically connected to the upper electrode, and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode. And features. Further, the present invention has a structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and when a positive voltage is applied to the upper electrode, electrons are emitted from the upper electrode surface. A thin-film electron source comprising: a plurality of electron source elements to be emitted; and a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements. The bus electrodes each include a thin-film electrode provided integrally with the upper electrode, and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode. It is characterized by.
また、 本発明は、 前記厚膜電極を、 電気メ ツキ、 スパッタ リ ング、 真 空蒸着、 化学気相成長、 あるいは印刷法のいずれかの方法を用いて形成 することを特徴とする。  Further, the present invention is characterized in that the thick film electrode is formed by using any one of electric plating, sputtering, vacuum evaporation, chemical vapor deposition, or printing.
また、 本発明は、 前記薄膜電子源を使用する表示装置である。 図面の簡単な説明  Further, the present invention is a display device using the thin-film electron source. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の実施の形態 1の薄膜型電子源の構造を示す図であ 第 2図は、 本発明の実施の形態 1の薄膜型電子源の製造方法を説明す るための図である。  FIG. 1 is a diagram showing a structure of a thin-film electron source according to Embodiment 1 of the present invention. FIG. 2 is a view for explaining a method of manufacturing a thin-film electron source according to Embodiment 1 of the present invention. FIG.
第 3図は、 本発明の実施の形態 1の薄膜型電子源の製造方法を説明す るための図である。  FIG. 3 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
第 4図は、 本発明の実施の形態 1の薄膜型電子源の製造方法を説明す るための図である。  FIG. 4 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
第 5図は、 本発明の実施の形態 1 の薄膜型電子源の製造方法を説明す るための図である。  FIG. 5 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
第 6図は、 本発明の実施の形態 1 の薄膜型電子源の製造方法を説明す るための図である。 FIG. 6 illustrates a method for manufacturing a thin-film electron source according to Embodiment 1 of the present invention. FIG.
第 7図は、 本発明の実施の形態 1の薄膜型電子源の製造方法を説明す るための図である。  FIG. 7 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
第 8図は、 本発明の実施の形態 1の薄膜型電子源の製造方法を説明す るための図である。  FIG. 8 is a diagram for explaining a method of manufacturing the thin-film electron source according to the first embodiment of the present invention.
第 9図は、 本発明の実施の形態 2の薄膜型電子源の製造方法を説明す るための図である。  FIG. 9 is a diagram for explaining a method of manufacturing the thin-film electron source according to the second embodiment of the present invention.
第 1 0図は、 本発明の実施の形態 2の薄膜型電子源の製造方法を説明 するための図である。  FIG. 10 is a diagram for explaining a method of manufacturing the thin-film electron source according to the second embodiment of the present invention.
第 1 1図は、 本発明の実施の形態 2の薄膜型電子源の製造方法を説明 するための図である。  FIG. 11 is a diagram for explaining a method of manufacturing a thin-film electron source according to Embodiment 2 of the present invention.
第 1 2図は、 本発明の実施の形態 3の薄膜型電子源の製造方法を説明 するための図である。  FIG. 12 is a view for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
第 1 3図は、 本発明の実施の形態 3の薄膜型電子源の製造方法を説明 するための図である。  FIG. 13 is a diagram for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
第 1 4図は、 本発明の実施の形態 3の薄膜型電子源の製造方法を説明 するための図である。  FIG. 14 is a diagram for explaining a method of manufacturing the thin-film electron source according to the third embodiment of the present invention.
第 1 5図は、 本発明の実施の形態 4の薄膜型電子源の製造方法を説明 するための図である。  FIG. 15 is a diagram for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention.
第 1 6図は、 本発明の実施の形態 4の薄膜型電子源の製造方法を説明 するための図である。  FIG. 16 is a view illustrating a method for manufacturing a thin-film electron source according to Embodiment 4 of the present invention.
第 1 7図は、 本発明の実施の形態 4の薄膜型電子源の製造方法を説明 するための図である。  FIG. 17 is a view for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention.
第 1 8図は、 本発明の実施の形態 4の薄膜型電子源の製造方法を説明 するための図である。 第 1 9図は、 本発明の実施の形態 5の表示装置の薄膜型電子源ァレィ 基板の概略構成を示す図である。 FIG. 18 is a view for explaining a method of manufacturing the thin-film electron source according to the fourth embodiment of the present invention. FIG. 19 is a diagram showing a schematic configuration of a thin-film electron source array substrate of a display device according to Embodiment 5 of the present invention.
第 2 0図は、 本発明の実施の形態 5の表示装置の蛍光表示板の概略構 成を示す図である。  FIG. 20 is a diagram showing a schematic configuration of a fluorescent display panel of a display device according to Embodiment 5 of the present invention.
第 2 1図は、 本発明の実施の形態 5の表示装置の概略全体構成を示す 断面図である。  FIG. 21 is a cross-sectional view illustrating a schematic overall configuration of a display device according to Embodiment 5 of the present invention.
第 2 2図は、 本発明の実施の形態 5の表示装置に、 駆動回路を接続し た状態を示す模式図である。  FIG. 22 is a schematic diagram showing a state where a drive circuit is connected to the display device according to the fifth embodiment of the present invention.
第 2 3図は、 第 2 2図に示す各駆動回路から出力される駆動電圧の波 形の一例を示すタイ ミ ングチャートである。  FIG. 23 is a timing chart showing an example of the waveform of the drive voltage output from each drive circuit shown in FIG.
第 2 4図は、 薄膜型電子源の動作原理を示す図である。 発明を実施するための最良の形態  FIG. 24 is a diagram showing the operating principle of the thin-film electron source. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図面を参照して本発明の実施形態を詳細に説明する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
なお、 実施形態を説明するための全図において、 同一機能を有するも のは同一符号を付け、 その繰り返しの説明は省略する。  In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[実施の形態 1 ]  [Embodiment 1]
第 1図は、 本発明の実施の形態 1の薄膜型電子源の 1素子分の構造を 示す断面図である。  FIG. 1 is a cross-sectional view showing a structure of one element of a thin-film electron source according to Embodiment 1 of the present invention.
本実施の形態の薄膜型電子源は、 給電配線となるバス電極が、 上部電 極 1 3 と電気的に接続されるバス電極下層 1 5 と、 当該バス電極下層 1 5 を裏打ちするバス電極上層 1 6 とで構成され、 かつ、 バス電極上層 1 6がスパッタ リ ング膜によ り形成されていることを特徴とする。  In the thin-film electron source of the present embodiment, the bus electrode serving as the power supply wiring has a bus electrode lower layer 15 electrically connected to the upper electrode 13, and a bus electrode upper layer lining the bus electrode lower layer 15. 16 and the upper layer 16 of the bus electrode is formed of a sputtering film.
以下、 第 2図ないし第 8図を用いて、 本実施の形態の薄膜型電子源の 製造方法について説明する。 なお、 第 2図ないし第 8図において、 同図 ( a) は平面図、 同図 (b) は、 同図 ( a) の A— A' 切断線に沿った断面構造を示す断面図、 同図 ( c ) は、 同図 (a) の B— B, 切断線に沿った断面構造を示す断面図 である。 Hereinafter, a method for manufacturing the thin-film electron source of the present embodiment will be described with reference to FIGS. 2 to 8. 2A to 8, FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view showing a cross-sectional structure taken along line AA ′ in FIG. Figure (c) is a cross-sectional view showing the cross-sectional structure taken along the line BB of Figure (a).
先ず、 ガラス等の絶縁性の基板 1 0上を用意し、 この基板 1 0上に下 部電極用の金属膜を形成する。  First, an insulating substrate 10 made of glass or the like is prepared, and a metal film for a lower electrode is formed on the substrate 10.
下部電極用の材料としては、 A 1や A 1合金を用いる。  A1 or A1 alloy is used as a material for the lower electrode.
ここでは、 Ndを 2原子量% ド一プした A l—Nd合金を用いた。 また、 金属膜の形成には、 例えば、 スパッタ リ ングを用い、 その膜厚 は 3 0 0 n mとした。  Here, an Al—Nd alloy in which Nd was doped at 2 atomic weight% was used. The metal film was formed by, for example, sputtering, and the thickness was set to 300 nm.
金属膜形成後、 第 2図に示すように、 エッチングによ りス トライプ形 状の下部電極 1 1を形成する。  After forming the metal film, as shown in FIG. 2, a strip-shaped lower electrode 11 is formed by etching.
エッチングは、 例えば、 燐酸、 酢酸、 硝酸の混合水溶液によるゥエツ トエッチングを用いた。  For the etching, for example, wet etching using a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid was used.
次に、 下部電極 1 1上の電子放出部となる部分をレジス ト膜 1 7でマ スク し、 化成液中で下部電極 1 1を陽極として、 下部電極 1 1上の電子 放出部となる部分以外の部分を選択的に厚く陽極酸化し、 第 3図に示す ように、 保護絶縁層 1 4を形成する。  Next, a portion serving as an electron emitting portion on the lower electrode 11 is masked with a resist film 17, and a portion serving as an electron emitting portion on the lower electrode 11 is formed in a chemical conversion solution using the lower electrode 11 as an anode. The other portions are selectively anodized thickly to form a protective insulating layer 14 as shown in FIG.
このとき、 化成電圧を 1 0 0 Vとすれば、 厚さ約 1 3 6 nmの保護絶 縁層 1 4が形成される。  At this time, assuming that the formation voltage is 100 V, a protection insulating layer 14 having a thickness of about 13 nm is formed.
保護絶縁層 1 4を形成した後、 レジス ト膜 1 7を除去し、 化成液中で 再度下部電極 1 1を陽極として、 陽極酸化を行い、 第 4図に示すように、 下部電極 1 1上に ト ンネル絶縁膜 1 2を形成する。  After the formation of the protective insulating layer 14, the resist film 17 is removed, and anodization is performed again in a chemical solution using the lower electrode 11 as an anode, and as shown in FIG. Next, a tunnel insulating film 12 is formed.
このとき、 例えば、 化成電圧を 6 Vとすれば、 下部電極 1 1上に厚さ 約 1 0 nmの ト ンネル絶縁層 1 2が形成される。 次に、 第 5図に示すように、 上部電極 1 3への給電線となるバス電極 膜をスパッタ リ ングで形成する。 At this time, for example, if the formation voltage is 6 V, a tunnel insulating layer 12 having a thickness of about 10 nm is formed on the lower electrode 11. Next, as shown in FIG. 5, a bus electrode film serving as a power supply line to the upper electrode 13 is formed by sputtering.
ここでは、 このバス電極膜として、 バス電極下層 (本発明の薄膜電極) 1 5 となる金属膜と、 バス電極上層 (本発明の厚膜電極) 1 6 となる金 属膜との積層膜を用い、 バス電極下層用の材料としてはタングステン ( W ) を、 バス電極上層用の材料としては A 1— N d合金を用いた。 またその膜厚は、 バス電極下層 1 5 となる金属膜は、 後で形成する上 部電極 1 3がバス電極下層 1 5の段差で断線しないように、 厚さの上限 を上部電極 1 3の膜厚の 1 0倍に設定する。 具体的には、 数 n m〜数 1 O n m程度と薄く し、 バス電極上層 1 6 となる金属膜は給電を十分にす るために数 1 0 0 n m程度と厚く形成する。  Here, as the bus electrode film, a laminated film of a metal film to be the lower layer of the bus electrode (thin film electrode of the present invention) 15 and a metal film to be the upper layer of the bus electrode (thick film electrode of the present invention) 16 is used. Tungsten (W) was used as a material for the lower layer of the bus electrode, and an A1-Nd alloy was used as a material for the upper layer of the bus electrode. The upper limit of the thickness of the metal film to be the bus electrode lower layer 15 is set so that the upper electrode 13 to be formed later is not disconnected by the step of the bus electrode lower layer 15. Set to 10 times the film thickness. More specifically, the thickness is reduced to about several nm to several hundred nm, and the metal film to be the upper layer 16 of the bus electrode is formed to be as thick as about several hundred nm in order to sufficiently supply power.
厚さの下限は、 導体として機能する厚さであれば良い。 上部電極 1 3 の膜厚の 1 / 1 0程度あるのが好ましい。  The lower limit of the thickness may be a thickness that functions as a conductor. The thickness of the upper electrode 13 is preferably about 1/10.
続いて、 第 6図に示すように、 ホ ト リ ソ工程、 エッチング工程によ り、 バス電極上層 1 6 を、 下部電極 1 1 と直交する方向にス トライプ状に加 ェする。  Subsequently, as shown in FIG. 6, the upper layer 16 of the bus electrode is striped in a direction orthogonal to the lower electrode 11 by a photolithography step and an etching step.
ここで、 エッチングには、 例えば、 燐酸、 酢酸、 硝酸の混合水溶液を 使用した。  Here, for the etching, for example, a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid was used.
次に、 第 7図に示すように、 バス電極下層 1 5 を同じ く ホ ト リ ソ工程 とエッチング工程にて加工する。  Next, as shown in FIG. 7, the bus electrode lower layer 15 is processed in the same photolithography step and etching step.
この時留意するこ とは、 電子放出部において後から作られる上部電極 1 3 との電気的な接点を確保するため、 バス電極上層 1 6からはみ出す ようにバス電極下層 1 5 を加工することである。  At this time, it is important to process the lower bus electrode layer 15 so as to protrude from the upper bus electrode layer 16 in order to secure electrical contact with the upper electrode 13 to be formed later in the electron emission section. is there.
なお、 タングステン (W ) のエッチングには、 アンモニアと過酸化水 素の混合水溶液が適している。 最後に、 第 8図に示すように、 上部電極 1 3を形成する。 これによ り、 本実施の形態の薄膜型電子源が完成する。 For the etching of tungsten (W), a mixed aqueous solution of ammonia and hydrogen peroxide is suitable. Finally, as shown in FIG. 8, an upper electrode 13 is formed. Thus, the thin-film electron source of the present embodiment is completed.
この上部電極 1 3のパ夕一ニングはリ フ トオフによ り行い、 上部電極 1 3の形成はスパッ夕 リングで行った。  The upper electrode 13 was patterned by lift-off, and the upper electrode 13 was formed by sputtering.
上部電極 1 3 としては、 例えば、 イ リ ジウム ( I r ) 、 白金 ( P t ) 、 金 (A u ) の積層膜を用い、 それそれの膜厚は数 n mとし、 形成は前記 したようにスパッ夕 リ ングによ り行った。  As the upper electrode 13, for example, a laminated film of iridium (Ir), platinum (Pt), and gold (Au) is used, each having a thickness of several nm, and formed as described above. We went by a spa ring.
なお、 本実施の形態において、 バス電極上層 1 6 となる金属膜をスパ ッ夕 リ ングで形成したが、 本発明はこれに限定されるものではなく、 バ ス電極上層 1 6 となる金属膜を、 電気メ ツキ、 真空蒸着、 化学気相成長、 あるいは印刷法のいずれかの方法で形成するようにしてもよい。  In the present embodiment, the metal film to be the bus electrode upper layer 16 is formed by sputtering, but the present invention is not limited to this, and the metal film to be the bus electrode upper layer 16 is formed. May be formed by any of the following methods: electric plating, vacuum deposition, chemical vapor deposition, or printing.
本実施の形態の薄膜型電子源によれば、 バス電極上層 1 6 を数 1 0 0 n m程度と厚く形成したので、 給電配線を構成するバス電極のシ一 ト抵 抗を、 上部電極 1 3のシート抵抗 ( 2 0 0 Ω /口程度) に比べて、 2桁 程度小さ くでき、 バス電極の抵抗を減少させることができる。  According to the thin-film electron source of the present embodiment, the bus electrode upper layer 16 is formed to be as thick as several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13 The sheet resistance can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 Ω / port), and the resistance of the bus electrode can be reduced.
また、 バス電極下層 1 5 を数 n m〜数 1 0 n mの範囲の膜厚に成膜し たので、 上部電極 1 3がバス電極下層 1 5の段差で断線するのを防止す ることができる。  In addition, since the lower layer 15 of the bus electrode is formed to have a thickness in the range of several nm to several 10 nm, it is possible to prevent the upper electrode 13 from breaking due to a step of the lower layer 15 of the bus electrode. .
[実施の形態 2 ]  [Embodiment 2]
本発明の実施の形態 2の薄膜型電子源は、 上部電極 1 3がバス電極下 層を兼ねるとともに、 当該上部電極上にスパッ夕 リ ングによ りバス電極 上層 1 6 を形成したことを特徴とする。  The thin-film electron source according to the second embodiment of the present invention is characterized in that the upper electrode 13 also serves as the lower layer of the bus electrode, and the upper layer 16 of the bus electrode is formed on the upper electrode by sputtering. And
以下、 第 9図ないし第 1 1 図を用いて、 本実施の形態の薄膜型電子源 の製造方法について説明する。  Hereinafter, a method of manufacturing the thin-film electron source according to the present embodiment will be described with reference to FIGS. 9 to 11.
なお、 第 9図ないし第 1 1図において、 同図 ( a ) は平面図、 同図 ( b ) は、 同図 ( a) の A— A' 切断線に沿った断面構造を示す断面図、 同図 ( c ) は、 同図 ( a) の B— B, 切断線に沿った断面構造を示す断面図 である。 9 to 11, FIG. 9A is a plan view and FIG. 9B is a plan view. Is a cross-sectional view showing a cross-sectional structure taken along the line A-A 'in FIG. (A), and FIG. (C) is a cross-sectional structure taken along the line BB in FIG. (A). It is sectional drawing.
先ず、 前記実施の形態 1 と同様、 前記第 2図ないし第 4図に示す方法 によ り、 トンネル絶縁層 1 2までを形成する。  First, similarly to the first embodiment, up to the tunnel insulating layer 12 is formed by the method shown in FIGS.
次に、 第 9図に示すごと く、 上部電極 1 3となる金属膜と、 バス電極 上層 1 6となる金属膜をこの順序でスパッタ リ ングによ り形成する。 上部電極 1 3となる金属膜の材料としては、例えば、タングステン(W)、 白金 (P t ) 、 金 (Au) の積層膜とし、 それそれの膜厚は 1〜 3 nm とする。  Next, as shown in FIG. 9, a metal film to be the upper electrode 13 and a metal film to be the bus electrode upper layer 16 are formed by sputtering in this order. The material of the metal film to be the upper electrode 13 is, for example, a laminated film of tungsten (W), platinum (Pt), and gold (Au), each having a thickness of 1 to 3 nm.
バス電極上層 1 6となる金属膜の材料には、 前記した A 1 - N d合金 を数 1 0 0 nm堆積する。  The above-mentioned A 1 -Nd alloy is deposited on the material of the metal film to be the bus electrode upper layer 16 by several 100 nm.
つづいて、 ホ ト リ ソ工程によ り レジス トパターンを形成し、 ウエッ ト エッチングによ り、 バス電極上層以外の A 1— N d合金を除去し、 第 1 0図に示すように、 バス電極上層 1 6を形成する。  Subsequently, a resist pattern is formed by a photolithography process, and the A 1 -Nd alloy other than the upper layer of the bus electrode is removed by wet etching, and as shown in FIG. The upper electrode layer 16 is formed.
エッチングには、 前記した燐酸、 酢酸、 硝酸の混合水溶液が好適であ る  For etching, a mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid described above is preferable.
最後に、 電子放出部をレジス トパターンで覆い、 バス電極上層間の上 部電極用の金属膜を取り除いて、 第 1 1図に示すように、 上部電極 1 3 を形成する。 これによ り、 本実施の形態の薄膜型電子源が完成する。 エッチングには、 白金 (P t ) 、 金 (Au) については王水を、 また タングステン (W) に対しては前記したアンモニアと過酸化水素水の混 合水溶液が好適である。  Finally, the electron-emitting portion is covered with a resist pattern, the metal film for the upper electrode on the upper layer of the bus electrode is removed, and an upper electrode 13 is formed as shown in FIG. Thus, the thin-film electron source of the present embodiment is completed. For the etching, aqua regia is preferably used for platinum (Pt) and gold (Au), and the above-described mixed aqueous solution of ammonia and hydrogen peroxide is preferably used for tungsten (W).
なお、 本実施の形態においても、 バス電極上層 1 6となる金属膜を、 メ ツキ、 真空蒸着、 化学気相成長、 あるいは印刷法のいずれかの方法で 丄 形成するようにしてもよい。 Also in the present embodiment, the metal film to be the bus electrode upper layer 16 is formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. よ い It may be formed.
本実施の形態の薄膜型電子源によれば、 バス電極上層 1 6を数 1 0 0 nm程度と厚く形成したので、 給電配線を構成するバス電極のシ一ト抵 抗を、 上部電極 1 3のシート抵抗 ( 2 0 0 Ω /口程度) に比べて、 2桁 程度小さ くでき、 バス電極の抵抗を減少させることができる。  According to the thin-film electron source of the present embodiment, the upper layer 16 of the bus electrode is formed to be as thick as several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13 The sheet resistance can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 Ω / port), and the resistance of the bus electrode can be reduced.
また、 上部電極 1 3でバス電極下層を兼用させるようにしたので、 電 子放出部での上部電極 1 3の段差切れを防止することができる。  In addition, since the upper electrode 13 is also used as the lower layer of the bus electrode, the disconnection of the upper electrode 13 at the electron emission portion can be prevented.
[実施の形態 3 ]  [Embodiment 3]
本発明の実施の形態 3の薄膜型電子源は、 上部電極 1 3がバス電極下 層を兼ねるとともに、 当該上部電極上に電気メ ツキによ りバス電極上層 1 6を形成したことを特徴とする。  The thin-film electron source according to Embodiment 3 of the present invention is characterized in that the upper electrode 13 also serves as the lower layer of the bus electrode, and the upper layer 16 of the bus electrode is formed on the upper electrode by electric plating. I do.
以下、 第 1 2図ないし第 1 4図を用いて、 本実施の形態の薄膜型電子 源の製造方法について説明する。  Hereinafter, a method of manufacturing the thin-film electron source of the present embodiment will be described with reference to FIGS. 12 to 14.
なお、 第 1 2図ないし第 1 4図において、 同図 ( a ) は平面図、 同図 ( b ) は、 同図 ( a) の A— A' 切断線に沿った断面構造を示す断面図、 同図 ( c ) は、 同図 ( a ) の B— B, 切断線に沿った断面構造を示す断 面図である。  In FIGS. 12 to 14, FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view showing a cross-sectional structure taken along the line AA ′ in FIG. (C) is a cross-sectional view showing the cross-sectional structure taken along the line BB in FIG. (A).
先ず、 前記実施の形態 1 と同様、 前記第 2図ないし第 4図に示す方法 によ り、 ト ンネル絶縁層 1 2までを形成する。  First, similarly to the first embodiment, up to the tunnel insulating layer 12 is formed by the method shown in FIGS.
次に、 第 1 2図に示すごと く、 上部電極 1 3 となる金属膜をスパッ夕 リ ングによ り形成する。  Next, as shown in FIG. 12, a metal film to be the upper electrode 13 is formed by sputtering.
上部電極用の材料としては、 例えば、 タ ングステン (W) 、 白金 ( P t ) 、 金 (Au ) の積層膜とし、 それそれの膜厚は 1〜 3 nmとする。 つづいて、 バス電極上層 1 6が形成されない部分をレジス トパターン で覆い、 電解金メ ッキによ り金 (A u )膜を裏打ち電極と して成長させ、 第 1 3図に示すように、 バス電極上層 1 6 を形成する。 The material for the upper electrode is, for example, a laminated film of tungsten (W), platinum (Pt), and gold (Au), each having a thickness of 1 to 3 nm. Subsequently, a portion where the upper layer 16 of the bus electrode is not formed is covered with a resist pattern, and a gold (Au) film is grown as a backing electrode by an electrolytic gold plating. As shown in FIG. 13, an upper layer 16 of the bus electrode is formed.
最後に、 電子放出部をレジス トパターンで覆い、 バス電極上層間の上 部電極用の金属膜を取り除いて、 第 1 4図に示すように、 上部電極 1 3 を形成する。 これにより、 本実施の形態の薄膜型電子源が完成する。 エッチングには、 白金 ( P t ) 、 金 (A u ) については王水を、 また タングステン (W ) に対しては前記したアンモニアと過酸化水素水の混 合水溶液が好適である。  Finally, the electron-emitting portion is covered with a resist pattern, the metal film for the upper electrode on the upper layer of the bus electrode is removed, and an upper electrode 13 is formed as shown in FIG. Thus, the thin-film electron source of the present embodiment is completed. For etching, aqua regia is preferable for platinum (Pt) and gold (Au), and the above-mentioned mixed aqueous solution of ammonia and hydrogen peroxide is preferable for tungsten (W).
なお、 本実施の形態においては、 バス電極上層 1 6を、 スパッタ リ ン グ、 真空蒸着、 化学気相成長、 あるいは印刷法のいずれかの方法で形成 するようにしてもよい。  In this embodiment, the upper layer 16 of the bus electrode may be formed by any one of sputtering, vacuum evaporation, chemical vapor deposition, or printing.
但し、 本実施の形態のように、 電解金メ ツキによ り金 (A u ) 膜を裏 打ち電極として成長させバス電極上層 1 6 を形成する場合は、 上部電極 1 3 とバス電極上層 1 6 との間の接着性が良好となり、 また、 バス電極 上層 1 6の膜厚が任意に設定でき、 さらに、 ト ンネル絶縁層 1 2へのダ メージを他のプロセスに比して少なく することができる。  However, when a gold (Au) film is grown as a backing electrode by electrolysis gold plating to form the bus electrode upper layer 16 as in the present embodiment, the upper electrode 13 and the bus electrode upper layer 1 are formed. 6 and the thickness of the upper layer 16 of the bus electrode can be set arbitrarily, and the damage to the tunnel insulating layer 12 is reduced as compared with other processes. Can be.
本実施の形態の薄膜型電子源によれば、 バス電極上層 1 6 を数 1 0 0 n m程度と厚く形成したので、 給電配線を構成するバス電極のシ一 ト抵 抗を、 上部電極 1 3のシー ト抵抗 ( 2 0 0 Ω /口程度) に比べて、 2桁 程度小さ くでき、 バス電極の抵抗が減少させることができる。  According to the thin-film electron source of the present embodiment, since the upper layer 16 of the bus electrode is formed to be as thick as several hundred nm, the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the upper electrode 13 It can be reduced by about two orders of magnitude compared to the sheet resistance (about 200 Ω / port), and the resistance of the bus electrode can be reduced.
また、 上部電極 1 3でバス電極下層を兼用させるようにしたので、 電 子放出部での上部電極 1 3の段差切れを防止することができる。  In addition, since the upper electrode 13 is also used as the lower layer of the bus electrode, the disconnection of the upper electrode 13 at the electron emission portion can be prevented.
[実施の形態 4 ]  [Embodiment 4]
本発明の実施の形態 4の薄膜型電子源は、 上部電極 1 3がバス電極下 層 1 5 と電気的に接続され、 かつバス電極下層 1 5上に電気メ ツキによ りバス電極上層 1 6 を形成したこ とを特徴とする。 以下、 第 1 5図ないし第 1 8図を用いて、 本実施の形態の薄膜型電子 源の製造方法について説明する。 In the thin-film electron source according to the fourth embodiment of the present invention, the upper electrode 13 is electrically connected to the lower bus electrode layer 15, and the upper electrode layer 15 is electrically connected to the lower bus electrode layer 15 by electric plating. 6 is formed. Hereinafter, a method of manufacturing the thin-film electron source of the present embodiment will be described with reference to FIGS. 15 to 18.
なお、 第 1 5図ないし第 1 8図において、 同図 ( a) は平面図、 同図 ( b ) は、 同図 (a) の A— A, 切断線に沿った断面構造を示す断面図、 同図 ( c ) は、 同図 (a) の B— B, 切断線に沿った断面構造を示す断 面図である。  15A to 18, FIG. 15A is a plan view, and FIG. 15B is a cross-sectional view showing a cross-sectional structure taken along line AA of FIG. (C) is a cross-sectional view showing a cross-sectional structure taken along the line BB of FIG. (A).
先ず、 前記実施の形態 1と同様、 前記第 2図ないし第 4図に示す方法 によ り、 ト ンネル絶縁層 1 2までを形成する。  First, similarly to the first embodiment, up to the tunnel insulating layer 12 is formed by the method shown in FIGS. 2 to 4.
次に、 第 1 5図に示すごと く、 バス電極下層 1 5となる金属膜をスパ ッタ リ ングによ り形成する。  Next, as shown in FIG. 15, a metal film to be the lower layer 15 of the bus electrode is formed by sputtering.
バス電極下層 1 5となる金属膜の材料としては、 例えば、 タングステ ン (W) 、 金 (Au) の積層膜とし、 それそれの膜厚は 1 0 nm程度 が 好ましい。  As a material of the metal film to be the bus electrode lower layer 15, for example, a laminated film of tungsten (W) and gold (Au) is preferable, and the thickness of each is preferably about 10 nm.
つづいて、 バス電極上層 1 6が形成されない部分をレジス トパターン で覆い、 電解金メ ッキによ り金 (Au)膜を裏打ち電極として成長させ、 第 1 6図に示すように、 バス電極上層 1 6を形成する。  Subsequently, a portion where the upper layer 16 of the bus electrode is not formed is covered with a resist pattern, and a gold (Au) film is grown as a backing electrode by an electrolytic gold plating. As shown in FIG. The upper layer 16 is formed.
次に、 第 1 7図に示すように、 バス電極下層 1 5をホ ト リ ソ工程とェ ツチング工程にて加工する。  Next, as shown in FIG. 17, the lower layer 15 of the bus electrode is processed by a photolithography step and an etching step.
この時留意することは、 電子放出部において後から作られる上部電極 1 3との電気的な接点を確保するため、 バス電極上層 1 6からはみ出す ようにバス電極下層 1 5を加工するこ とである。  At this time, it should be noted that, in order to secure an electrical contact with the upper electrode 13 to be formed later in the electron-emitting portion, the bus electrode lower layer 15 is processed so as to protrude from the bus electrode upper layer 16. is there.
金 ( A u ) のエッチングには王水を、 またタングステン ( W ) のェヅ チングには前記したアンモニアと過酸化水素の混合水溶液を用いる。 最後に、 第 1 8図に示すように、 上部電極 1 3を形成する。 これによ り、 本実施の形態の薄膜型電子源が完成する。 上部電極 1 3のパターニングはリフ トオフで行い、 上部電極 1 3の形 成はスパッ夕 リ ングで行う。 Refined water is used for etching gold (Au), and the above-mentioned mixed aqueous solution of ammonia and hydrogen peroxide is used for etching tungsten (W). Finally, as shown in FIG. 18, an upper electrode 13 is formed. Thus, the thin-film electron source of the present embodiment is completed. The upper electrode 13 is patterned by lift-off, and the upper electrode 13 is formed by sputtering.
上部電極 1 3としては、 例えば、 イ リジウム ( I r ) 、 白金 ( P t ) 、 金 (Au) の積層膜を用い、 それそれの膜厚は数 nmとし、 成膜は前記 したようにスパッタ リ ングによ り行った。  As the upper electrode 13, for example, a laminated film of iridium (Ir), platinum (Pt), and gold (Au) is used, each having a thickness of several nm, and the film is formed by sputtering as described above. The ring was used.
なお、 本実施の形態においても、 パス電極上層 1 6となる金属膜を、 スパッタ リ ング、 真空蒸着、 化学気相成長、 あるいは印刷法のいずれか の方法で形成するようにしてもよい。  Also in the present embodiment, the metal film to be the pass electrode upper layer 16 may be formed by any of sputtering, vacuum deposition, chemical vapor deposition, or printing.
本実施の形態の薄膜型電子源によれば、 パス電極上層 1 6を数 1 00 nm程度と厚く形成したので、 給電配線を構成するバス電極のシー ト抵 抗を、 上部電極 1 3のシート抵抗 ( 2 0 0 Ω/口程度) に比べて、 2桁 程度小さ くでき、 バス電極の抵抗を減少させることができる。  According to the thin-film type electron source of the present embodiment, the pass electrode upper layer 16 is formed to be as thick as about several hundred nm, so that the sheet resistance of the bus electrode constituting the power supply wiring is reduced by the sheet of the upper electrode 13. The resistance can be reduced by about two digits compared to the resistance (about 200 Ω / port), and the resistance of the bus electrode can be reduced.
また、 バス電極下層 1 5を数 nm〜数 1 O n m程度と薄く形成したの で、 上部電極 1 3がバス電極下層 1 5の段差で断線する段差切れを防止 することができる。  In addition, since the lower layer 15 of the bus electrode is formed as thin as several nm to several 1 Onm, the disconnection of the upper electrode 13 at the step of the lower layer 15 of the bus electrode can be prevented.
なお、 前記各実施の形態では、 本発明を、 薄膜型電子源に適用した実 施の形態について説明したが、本発明はこれに限定されるものではなく、 本発明は、 例えば、 表面伝導型の電子源にも適用可能であることはいう までもない。  In each of the above embodiments, an embodiment in which the present invention is applied to a thin-film electron source has been described. However, the present invention is not limited to this. Needless to say, the present invention can be applied to other electron sources.
[実施の形態 5 ]  [Embodiment 5]
第 1 9図は、 本発明の実施の形態 5の表示装置の薄膜型電子源アレイ 基板の概略構成を示す図である。  FIG. 19 is a diagram showing a schematic configuration of a thin-film electron source array substrate of a display device according to Embodiment 5 of the present invention.
第 1 9図 ( a ) は、 本実施の形態の薄膜型電子源ァレィ基板の平面図 であり、 同図 (b) は、 同図 ( a) に示す A— A, 線に沿った断面構造、 および同図 ( c ) は、 同図 ( a) に示す B— B ' 線に沿った断面構造を 示す要部断面図である。 FIG. 19 (a) is a plan view of the thin-film type electron source array substrate of the present embodiment, and FIG. 19 (b) is a cross-sectional structure taken along line AA shown in FIG. , And (c) show the cross-sectional structure along the line BB 'shown in (a). It is an important section sectional view shown.
本実施の形態では、 薄膜型電子源アレイ基板として、 前記実施の形態 1の薄膜型電子源を用いる場合について説明するが、 前記実施の形態 2 ないし実施の形態 4の薄膜型電子源を用いるようにしてもよい。  In this embodiment, the case where the thin-film electron source of the first embodiment is used as the thin-film electron source array substrate will be described. However, the thin-film electron source of the second to fourth embodiments may be used. It may be.
本実施の形態の薄膜型電子源アレイ基板は、 前記実施の形態 1で説明 した手順にしたがって、 基板 1 0上に、 薄膜型電子源がマ ト リクス状に 形成されて構成される。  The thin-film electron source array substrate of the present embodiment is formed by forming a thin-film electron source in a matrix on the substrate 10 according to the procedure described in the first embodiment.
なお、 第 1 9図では、 3本の下部電極 1 1 と 3本の上部電極パスラィ ン 1 7からなる ( 3 x 3 ) ドッ 卜の薄膜型電子源マ ト リ クスを図示して いるが、 実際には、 表示 ドッ ト数に対応した数の薄膜型電子源マ ト リ ク スを形成する。  In FIG. 19, a (3 × 3) dot thin film type electron source matrix composed of three lower electrodes 11 and three upper electrode paths 17 is shown. In practice, a number of thin-film electron source matrices corresponding to the number of display dots are formed.
また、 実際には、 バス電極は、 バス電極下層 1 5 と、 バス電極上層 1 6 との積層構造であるが、 第 1 9図では積層パス電極 1 8 としてまとめ て表示している。  In addition, the bus electrode is actually a laminated structure of the lower layer 15 of the bus electrode and the upper layer 16 of the bus electrode. However, in FIG. 19, they are collectively shown as the laminated pass electrode 18.
なお、 前記各実施の形態では説明しなかったが、 薄膜型電子源マ ト リ クスを表示装置に使用する場合、 下部電極 1 1、 上部バス電極 1 8の電 極端部は回路接続のため電極面を露出しておかなければならない。  Although not described in the above embodiments, when the thin film type electron source matrix is used for a display device, the electrode portions of the lower electrode 11 and the upper bus electrode 18 are electrodes for circuit connection. The surface must be exposed.
第 2 0図は、 本発明の実施の形態 5の表示装置の蛍光表示板の概略構 成を示す図である。  FIG. 20 is a diagram showing a schematic configuration of a fluorescent display panel of a display device according to Embodiment 5 of the present invention.
第 2 0図 ( a ) は、 本実施の形態の蛍光表示板の平面図であり、 同図 ( b ) は、 同図 ( a ) に示す A— A, 線に沿った断面構造、 および同図 ( c ) は、 同図 ( a ) に示す B— B ' 線に沿った断面構造を示す要部断 面図である。  FIG. 20 (a) is a plan view of the fluorescent display panel of the present embodiment, and FIG. 20 (b) is a cross-sectional structure taken along the line A--A shown in FIG. FIG. (C) is a cross-sectional view of a main part showing a cross-sectional structure along the line BB ′ shown in FIG. (A).
本実施の形態の蛍光表示板は、 ソーダガラス等の基板 1 1 0に形成さ れるブラ ックマ ト リ クス 1 2 0 と、 このブラ ックマ ト リ クス 1 2 0の溝 内に形成される赤 (R) · 緑 (G) ' 青 (B) の蛍光体 ( 1 1 1〜 1 1 3 ) と、 これらの上に形成されるメ夕ルバック膜 1 1 4とで構成される。 以下、 本実施の形態の蛍光表示板の作成方法について説明する。 The fluorescent display panel of the present embodiment includes a black matrix 120 formed on a substrate 110 such as a soda glass, and a groove of the black matrix 120. It consists of red (R) and green (G) 'blue (B) phosphors (111-1113) formed in the inside, and a mail-back film 114 formed on these Is done. Hereinafter, a method for manufacturing the fluorescent display panel of the present embodiment will be described.
まず、 表示装置のコン トラス トを上げる目的で、 基板 1 1 0上に、 ブ ラックマ ト リ クス 1 2 0を形成する。  First, a black matrix 120 is formed on the substrate 110 in order to increase the contrast of the display device.
ブラックマ ト リクス 1 2 0は、 ポリ ビニルアルコール ( P V A;以下、 単に、 PVAと称する。 ) と重クロム酸アンモニゥムとを混合した溶液 を基板 1 1 0に塗布し、 ブラックマ ト リクス 1 2 0を形成したい部分以 外に紫外線を照射して感光させた後、 未感光部分を除去し、 そこに黒鉛 粉末を溶かした溶液を塗布し、 P V Aを リ フ トオフすることによ り形成 する。  The black matrix 120 is formed by applying a solution of a mixture of polyvinyl alcohol (PVA; hereinafter, simply referred to as PVA) and ammonium dichromate to the substrate 110 to form the black matrix 120 After exposing to light by irradiating ultraviolet rays to the part other than the part to be exposed, the unexposed part is removed, a solution in which graphite powder is dissolved is applied, and PVA is formed by lift-off.
次に、 以下の方法によ り赤色蛍光体 1 1 1を形成する。  Next, the red phosphor 111 is formed by the following method.
赤色蛍光体粒子に PVAと重クロム酸アンモニゥムとを混合した水溶 液を基板 1 1 0上に塗布した後、 蛍光体を形成する部分に紫外線を照射 して感光させた後、 未感光部分を流水で除去する。  After applying an aqueous solution of a mixture of PVA and ammonium bichromate to the red phosphor particles on the substrate 110, the portion where the phosphor is to be formed is exposed to ultraviolet light, and then exposed, and the unexposed portion is flushed. To remove.
このようにして、 赤色蛍光体 1 1 1をパターン化する。  Thus, the red phosphor 111 is patterned.
なお、 蛍光体パターンは、 第 2 0図に示すス トライ プ状のパターンで あるが、 このス トライ プパターンは一例であって、 それ以外にも、 ディ スプレイの設計に応じて、 たとえば、 近接する 4 ドッ トで一画素を構成 させた 「R GB G」 パターンでももちろん構わない。  The phosphor pattern is a stripe pattern shown in FIG. 20, but this stripe pattern is merely an example. Of course, an “R GB G” pattern in which one pixel is composed of four dots may be used.
同様の方法によ り、緑色蛍光体 1 1 2と青色蛍光体 1 1 3を形成する。 ここで、 蛍光体として、 例えば、 赤色蛍光体 1 1 1は Y 202 S : E u ( Ρ 2 2 - R )、 緑色蛍光体 1 1 2は Z n S : Cu, A l (P 2 2— G) . 青色蛍光体 1 1 3は Z n S : A g (P 2 2— B) を用いればよい。 A green phosphor 112 and a blue phosphor 113 are formed by the same method. Here, as a phosphor, for example, a red phosphor 1 1 1 Y 2 0 2 S: E u (Ρ 2 2 - R), green phosphor 1 1 2 Z n S: Cu, A l (P 2 2—G). As the blue phosphor 1 13, ZnS: Ag (P22—B) may be used.
次いで、 ニ ト ロセルロースなどの膜でフィルミ ングした後、 基板 1 1 0全体に A 1を、 膜厚 Ί 5 n m程度蒸着してメタルバック膜 1 1 4 とす る。 このメ タルバック膜 1 1 4が、 加速電極として働く。 Next, after filming with a film such as nitrocellulose, the substrate 11 A1 is deposited on the entire surface to a thickness of about 5 nm to form a metal back film 114. This metal back film 114 works as an accelerating electrode.
その後、 基板 1 1 0 を大気中 4 0 0 °C程度に加熱してフィルミ ング膜 や P V Aなどの有機物を加熱分解する。  After that, the substrate 110 is heated to about 400 ° C. in the air to thermally decompose organic substances such as a film and a PVA.
このようにして、 蛍光表示板が完成する。  Thus, the fluorescent display panel is completed.
第 2 1図は、 本発明の実施の形態 5の表示装置の概略全体構成を示す 断面図である。  FIG. 21 is a cross-sectional view illustrating a schematic overall configuration of a display device according to Embodiment 5 of the present invention.
なお、 同図 ( a ) は、 第 1 9、 2 0図 ( a ) に示す A— A, 線に沿つ た断面構造、 および同図 ( B ) は、 第 1 9、 2 0図 ( a ) に示す B— B, 線に沿った断面構造を示す要部断面図である。  The figure (a) shows the cross-sectional structure along the line AA shown in Figs. 19 and 20 (a), and the figure (B) shows the figures 19 and 20 (a). 2) is a cross-sectional view of a main part showing a cross-sectional structure along the line BB shown in FIG.
第 2 1図に示すように、 前記手順によ り製作された薄膜型電子源ァレ ィ基板と、 蛍光表示板と、 枠部材 1 1 6 とを、 スぺ一サ 3 0を介して組 み立て後、 枠部材 1 1 6 をフ リ ツ トガラス 1 1 5 を用いて封着する。 薄膜型電子源ァレィ基板と蛍光表示板との間の距離は、 1 ~ 3 m m程 度になるようにスベーサ 3 0の高さを設定する。  As shown in FIG. 21, the thin film type electron source array substrate manufactured by the above procedure, a fluorescent display panel, and a frame member 116 are assembled via a spacer 30. After erection, the frame member 116 is sealed using the flat glass 115. The height of the spacer 30 is set so that the distance between the thin film type electron source array substrate and the fluorescent display panel is about 1 to 3 mm.
スぺ一サ 3 0は、 例えば、 板状のガラス製またはセラ ミ ックス製のス ぺ一サであり、 このスぺ一サ 3 0を積層バス電極 1 8間に配置する。  The spacer 30 is, for example, a plate-shaped glass or ceramic sensor, and the spacer 30 is arranged between the laminated bus electrodes 18.
この場合、 スぺ一サ 3 0が蛍光表示板のブラ ックマ ト リ クス 1 2 0の 下に配置されるため、 スぺーサ 3 0が発光を阻害しない。  In this case, since the spacer 30 is disposed below the black matrix 120 of the fluorescent display panel, the spacer 30 does not hinder light emission.
したがって、 スぺ一サ 3 0の存在による画質の劣化が生じに く い。 ここでは、 説明のため、 R (赤) 、 G (緑) 、 B (青) に発光する ド ッ ト毎、 即ち、 積層バス電極 1 8の間に全てスぺ一サ 3 0を立てている が、 実際は機械強度が耐える範囲で、 スぺーサ 3 0の枚数 (密度) を減 ら し、 大体 1 c mおきに立てればよい。  Therefore, deterioration of the image quality due to the presence of the spacer 30 is unlikely to occur. Here, for the sake of explanation, all the dots 30 emitting light for R (red), G (green), and B (blue), that is, all the spacers 30 are provided between the stacked bus electrodes 18. However, in practice, the number of spacers 30 (density) should be reduced and set approximately every 1 cm as long as the mechanical strength can withstand.
また、 本実施の形態において、 スぺ一サ 3 0 と して、 支柱状のスぺー サ、 格子状のスぺ一サを使用する場合でも同様な手法によ りパネル組み 立てが可能である。 In the present embodiment, a pillar-shaped spacer is used as the spacer 30. Panels can be assembled using the same method even when using grids or grid-shaped spacers.
封着したパネルは、 1 0_7 T 0 r r程度の真空に排気して、 封止する ( 封止した後、 ゲッ夕一を活性化し、 パネル内の真空を維持する。 Sealed panels is evacuated to 1 0_ 7 T 0 rr about vacuum, after sealed sealing to (sealing, rodents evening scratch activated to maintain the vacuum in the panel.
例えば、 ノ リ ゥム (B a) を主成分とするゲッ夕ー材の場合、 高周波 誘導加熱等によ りゲッ夕一膜を形成できる。  For example, in the case of a getter material mainly containing norm (Ba), a getter film can be formed by high-frequency induction heating or the like.
また、 ジルコニウム ( Z r) を主成分とする非蒸発型ゲッ夕一を用い てもよい。  Alternatively, a non-evaporable gas containing zirconium (Zr) as a main component may be used.
このようにして、 本実施の形態の表示装置が完成する。  Thus, the display device of the present embodiment is completed.
本実施の形態の表示装置では、 薄膜型電子源アレイ基板と蛍光表示板 との間の距離が、 1〜 3 mm程度と長いので、 メタルバック膜 1 1 4に 印加する加速電圧を 3〜 6 K Vと高電圧にできる。  In the display device of the present embodiment, since the distance between the thin film type electron source array substrate and the fluorescent display plate is as long as about 1 to 3 mm, the acceleration voltage applied to the metal back film 114 is set to 3 to 6 KV and high voltage.
したがって、 前記したように、 蛍光体には、 陰極線管 ( CR T) 用の 蛍光体を使用することができる。  Therefore, as described above, a phosphor for a cathode ray tube (CRT) can be used as the phosphor.
本実施の形態の表示装置によれば、 薄膜型電子源をアレイ状に多数配 列して 40ィ ンチクラスの大画面の冷陰極型蛍光表示装置を構成しても, 給電配線を構成するパス電極の抵抗を減少させることができ、 各薄膜型 電子源素子を輝度むらなく動作させることができるので、 表示画面い輝 度むらが生じるのを防止することが可能となる。  According to the display device of the present embodiment, even when a large number of thin-film electron sources are arranged in an array to form a 40-inch class large-screen cold-cathode fluorescent display device, the pass electrode forming the power supply wiring Since the resistance of the thin film type electron source element can be operated without uneven brightness, it is possible to prevent uneven brightness on the display screen.
第 2 2図は、 本実施の形態の表示装置に、 駆動回路を接続した状態を 示す模式図である。  FIG. 22 is a schematic diagram showing a state where a drive circuit is connected to the display device of the present embodiment.
下部電極 1 1は下部電極駆動回路 40で駆動され、 積層バス電極 1 8 は上部電極駆動回路 5 0で駆動される。  The lower electrode 11 is driven by a lower electrode drive circuit 40, and the laminated bus electrode 18 is driven by an upper electrode drive circuit 50.
ここで、 各駆動回路 ( 40, 5 0 ) と、 薄膜型電子源アレイ基板との 接続は、 例えば、 テープキャ リアパッケージを異方性導電膜で圧着した ものや、 各駆動回路 ( 40 , 5 0) を構成する半導体チップを、 薄膜型 電子源アレイ基板の基板 (例えば、 ガラス) 上に直接実装するチップォ ングラス等によって行う。 Here, the connection between each drive circuit (40, 50) and the thin film type electron source array substrate is performed, for example, by pressing a tape carrier package with an anisotropic conductive film. The semiconductor chips constituting the components and the drive circuits (40, 50) are formed by chip-on-glass, which is directly mounted on a substrate (eg, glass) of a thin-film type electron source array substrate.
メタルバック膜 1 1 4には、 加速電圧源 6 0から 3〜 6 KV程度の加 速電圧を常時印加する。  An acceleration voltage of about 3 to 6 KV is applied to the metal back film 114 from the acceleration voltage source 60 at all times.
第 2 3図は、 第 2 2図に示す各駆動回路から出力される駆動電圧の波 形の一例を示すタイ ミ ングチャートである。  FIG. 23 is a timing chart showing an example of the waveform of the drive voltage output from each drive circuit shown in FIG.
ここで、 m番目の下部電極 1 1を Km、 n番目の積層パス電極 1 8を C n、 m番目の下部電極 1 1と、 n番目の積層バス電極 1 8との交点を ( m、 n ) で表すことにする。  Here, the m-th lower electrode 11 is Km, the n-th laminated pass electrode 18 is C n, and the intersection of the m-th lower electrode 11 and the n-th laminated bus electrode 18 is (m, n ).
時刻 t 0ではいずれの電極も駆動電圧がゼロであるので電子は放出さ れず、 したがって、 蛍光体は発光しない。  At time t 0, no driving voltage is applied to any of the electrodes, so that no electrons are emitted, and thus the phosphor does not emit light.
時刻 t 1において、 K 1の下部電極 1 1に、 下部電極駆動回路 40か ら (—V 1 ) なる駆動電圧を、 ( C 1 , C 2 ) の積層バス電極 1 8に、 上部電極駆動回路 5 0から ( + V 2 ) なる駆動電圧を印加する。  At time t 1, the driving voltage of (−V 1) from the lower electrode driving circuit 40 is applied to the lower electrode 11 of K 1, and the upper electrode driving circuit is applied to the laminated bus electrode 18 of (C 1, C 2). A driving voltage of 50 to (+ V 2) is applied.
交点 ( 1 , 1 ) 、 ( 1, 2 ) の下部電極 1 1 と上部電極 1 3との間に は (V 1 +V 2 ) なる電圧が印加されるので、 (V 1 +V 2 ) の電圧を 電子放出開始電圧以上に設定しておけば、 この 2つの交点の薄膜型電子 源からは電子が真空中に放出される。  Since a voltage (V 1 + V 2) is applied between the lower electrode 11 and the upper electrode 13 at the intersections (1, 1) and (1, 2), the (V 1 + V 2) If the voltage is set to be equal to or higher than the electron emission start voltage, electrons are emitted from the thin-film electron source at the intersection of these two into a vacuum.
放出された電子はメタルバック膜 1 1 4に印加される加速電圧源 6 0 からの加速電圧によ り加速された後、 蛍光体 ( 1 1 1〜 1 1 3 ) に入射 し、 発光させる。  The emitted electrons are accelerated by an accelerating voltage from an accelerating voltage source 60 applied to the metal back film 114, and then enter the phosphors (111 to 113) to emit light.
時刻 t 2において、 K 2の下部電極 1 1に、 下部電極駆動回路 4 0か ら (— V I ) なる駆動電圧を印加し、 C 1の積層バス電極 1 8に、 上部 電極駆動回路 5 0から ( + V 2 ) なる駆動電圧を印加すると、 同様に交 P At time t2, a drive voltage (-VI) from the lower electrode drive circuit 40 is applied to the lower electrode 11 of K2, and the upper electrode drive circuit 50 is applied to the laminated bus electrode 18 of C1. (+ V 2) P
21 点 ( 2、 1 ) が点灯する。  21 points (2, 1) light up.
このようにして、 積層バス電極 1 8 に印加する信号を変えることによ り所望の画像または情報を表示することができる。  Thus, a desired image or information can be displayed by changing the signal applied to the laminated bus electrode 18.
また、 積層バス電極 1 8に印加する駆動電圧 ( + V 2 ) の大きさを適 宜変えることによ り、 階調のある画像を表示することができる。  Further, by appropriately changing the magnitude of the driving voltage (+ V 2) applied to the laminated bus electrode 18, an image with gradation can be displayed.
なお、 ト ンネル絶縁層 1 2 中に蓄積される電荷を開放するための反転 電圧の印加は、 ここでは下部電極 1 1の全てに、 下部電極駆動回路 4 0 から (— V I ) の駆動電圧を印加した後、 全下部電極 1 1 に下部電極駆 動回路 4 0から ( + V 3 ) の駆動電圧を、 全積層バス電極 1 8に、 上部 電極駆動回路 5 0から (― V 3, ) の駆動電圧を印加することによ り行 つた。  Here, the application of the inversion voltage for releasing the charges accumulated in the tunnel insulating layer 12 is performed by applying the driving voltage of (−VI) from the lower electrode driving circuit 40 to all of the lower electrodes 11. After the application, the driving voltage of (+ V 3) from the lower electrode driving circuit 40 is applied to all the lower electrodes 11, and the driving voltage of (−V 3,) from the upper electrode driving circuit 50 to all the laminated bus electrodes 18 This was achieved by applying a drive voltage.
以上、 本発明者によってなされた発明を、 前記実施の形態に基づき具 体的に説明したが、 本発明は、 前記実施の形態に限定されるものではな く、 その要旨を逸脱しない範囲において種々変更可能であることは勿論 である。 産業上の利用可能性  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. Of course, it can be changed. Industrial applicability
本願において開示される発明のう ち代表的なものによって得られる効 果を簡単に説明すれば、 下記の通りである。  The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
( 1 ) 本発明の電子源によれば、 電子源素子に駆動電圧を印加する給電 用のバス電極を、 薄膜電極と、 この薄膜電極上に裏打ちされた低抵抗な 厚膜電極とから成る積層構造としたので、 バス電極のシー ト抵抗を、 上 部電極のシー ト抵抗に比べて 2桁程度小さ く でき、 バス電極の抵抗を低 減させることが可能となる。  (1) According to the electron source of the present invention, a power supply bus electrode for applying a drive voltage to the electron source element is formed of a thin film electrode and a low-resistance thick film electrode lined on the thin film electrode. With this structure, the sheet resistance of the bus electrode can be reduced by about two orders of magnitude compared to the sheet resistance of the upper electrode, and the resistance of the bus electrode can be reduced.
また、 薄膜電極を、 電子源の電極の膜厚程度に薄く形成したので、 電 子放出部での電子源の電極の段差切れ防止することができる。 In addition, since the thin-film electrode was formed thin enough to be about the thickness of the electrode of the electron source, It is possible to prevent disconnection of the electrode of the electron source at the electron emission portion.
( 2 ) 本発明の表示装置によれば、 4 0イ ンチクラスの大画面でも、 給 電配線を構成するバス電極の抵抗を減少させることができ、 表示画面に 輝度むら生じるのを防止することが可能となる。  (2) According to the display device of the present invention, the resistance of the bus electrode constituting the power supply wiring can be reduced even on a large screen of a 40-inch class, and it is possible to prevent the occurrence of uneven brightness on the display screen. It becomes possible.

Claims

請 求 の 範 囲 1 . 複数個の電子源素子と、 Scope of Claim 1. Multiple electron source devices,
前記複数個の電子源素子の中の第 1の方向の電子源素子に駆動電圧を 印加する複数のバス電極とを有する電子源であって、  A plurality of bus electrodes for applying a driving voltage to the electron source element in a first direction among the plurality of electron source elements,
前記各バス電極は、 前記各電子源素子の電極と電気的に接続され、 か つ膜厚が前記電子源素子の電極の膜厚以下の厚さの薄膜電極と、  Each of the bus electrodes is electrically connected to an electrode of each of the electron source elements, and a thin film electrode having a thickness equal to or less than the thickness of the electrode of the electron source element;
前記薄膜電極と電気的に接続され、 前記薄膜電極に比して膜厚が厚い 厚膜電極とで構成されることを特徴とする電子源。  An electron source, comprising: a thick-film electrode that is electrically connected to the thin-film electrode and has a larger thickness than the thin-film electrode.
2 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印刷 法のいずれかの方法によ り形成される金属層であることを特徴とする請 求の範囲第 1項の電子源。  2. The electronic device according to claim 1, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, and printing. source.
3 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造を 有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表面 から電子を放出する複数個の電子源素子と、  3. It has a structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. An electron source element;
前記複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に 駆動電圧を印加する複数のバス電極とを有する薄膜型電子源であって、 前記各バス電極は、 前記上部電極と電気的に接続される薄膜電極と、 前記薄膜電極上に設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電 極とで構成されることを特徴とする薄膜型電子源。  A thin-film electron source having a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements; A thin-film electron source, comprising: a thin-film electrode electrically connected to an electrode; and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode.
4 . 前記薄膜電極は、 その膜厚が前記上部電極の膜厚 1 0倍以下の厚 さであることを特徴とする請求の範囲第 3項に記載の薄膜型電子源。  4. The thin-film electron source according to claim 3, wherein said thin-film electrode has a thickness not more than 10 times the thickness of said upper electrode.
5 . 前記薄膜電極および厚膜電極は、 それそれ前記絶縁層が露出する 開口部を有し、 かつ、 前記厚膜電極に設けられる開口部は、 前記薄膜電 極に設けられる開口部よ り大き く、 前記上部電極は、 前記厚膜電極に設けられる開口部内に露出する前記 薄膜電極を覆うように設けられていることを特徴とする請求の範囲第 3 項または請求の範囲第 4項に記載の薄膜型電子源。 5. The thin-film electrode and the thick-film electrode each have an opening through which the insulating layer is exposed, and the opening provided in the thick-film electrode is larger than the opening provided in the thin-film electrode. And The thin film according to claim 3, wherein the upper electrode is provided so as to cover the thin film electrode exposed in an opening provided in the thick film electrode. Type electron source.
6 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印刷 法のいずれかの方法によ り形成される金属層であることを特徴とする請 求の範囲第 3項ないし請求の範囲第 5項のいずれか 1項に記載の薄膜型 電子源。  6. The claim according to claim 3, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. 6. The thin-film electron source according to any one of paragraphs 5 to 5.
7 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造を 有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表面 から電子を放出する複数個の電子源素子と、  7. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. An electron source element;
前記複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に 駆動電圧を印加する複数のバス電極とを有する薄膜型電子源であって、 前記各バス電極は、 前記上部電極と一体的に設けられる薄膜電極と、 前記薄膜電極上に設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電 極とで構成されることを特徴とする薄膜型電子源。  A thin-film electron source having a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements; A thin-film electron source, comprising: a thin-film electrode provided integrally with an electrode; and a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode.
8 . 前記厚膜電極は、 それそれ前記絶縁層が形成される領域に設けら れる開口部を有することを特徴とする請求の範囲第 7項に記載の薄膜型 電子源。  8. The thin-film electron source according to claim 7, wherein each of said thick film electrodes has an opening provided in a region where said insulating layer is formed.
9 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印刷 法のいずれかの方法によ り形成される金属層であることを特徴とする請 求の範囲第 7項または請求の範囲第 8項に記載の薄膜型電子源。  9. The claim 7 or claim, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. 9. The thin-film electron source according to item 8, wherein
1 0 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、  10. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. Electron source elements,
前記上部電極と電気的に接続される薄膜電極と、 前記薄膜電極上に設 けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成され、 前記 複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電 圧を印加する複数のパス電極とを有する薄膜型電子源の製造方法であつ て、 A thin film electrode electrically connected to the upper electrode; And a driving voltage is applied to an upper electrode of the electron source element in a first direction among the plurality of electron source elements. A method for manufacturing a thin-film electron source having a plurality of pass electrodes, comprising:
前記下部電極を形成する工程 1 と、  Step 1 of forming the lower electrode;
前記絶縁層を形成する工程 2 と、  Step 2 of forming the insulating layer;
前記下部電極および前記絶縁層上に薄膜導電膜を形成する工程 3 と、 前記薄膜導電膜上に厚膜導電膜を形成する工程 4と、  A step 3 of forming a thin film conductive film on the lower electrode and the insulating layer, and a step 4 of forming a thick film conductive film on the thin film conductive film,
前記厚膜導電膜を選択的にパターンニングして前記厚膜電極を形成す る工程 5 と、  Step 5 of selectively patterning the thick-film conductive film to form the thick-film electrode;
前記薄膜導電膜を選択的にパターンニングして前記薄膜電極を形成す る工程 6、  Step 6 of selectively patterning the thin film conductive film to form the thin film electrode,
前記薄膜電極と電気的に接続される上部電極を形成する工程 7 とを有 することを特徴とする薄膜型電子源の製造方法。  Forming a top electrode electrically connected to the thin-film electrode. 7. A method for manufacturing a thin-film electron source, comprising:
1 1 . 前記薄膜導電膜を形成する工程 3 において、 前記薄膜導電膜の 膜厚が、 前記上部電極の膜厚の 1 0倍以下の厚さになるように、 前記薄 膜導電膜を形成することを特徴とする請求の範囲第 1 0項に記載の薄膜 型電子源の製造方法。  11. In the step 3 of forming the thin-film conductive film, the thin-film conductive film is formed such that the thickness of the thin-film conductive film is 10 times or less the thickness of the upper electrode. 10. The method for manufacturing a thin-film electron source according to claim 10, wherein:
1 2 .前記厚膜導電膜を選択的にパターンニングする工程 5 において、 前記厚膜電極に前記絶縁層が露出する開口部を形成し、  12.In step 5 of selectively patterning the thick film conductive film, an opening is formed in the thick film electrode so that the insulating layer is exposed,
また、前記薄膜導電膜を選択的にパターンニングする工程 6 において、 前記厚膜電極に形成した開口部の内部の前記薄膜電極に、 前記絶縁層が 露出する開口部を形成し、  In step 6 of selectively patterning the thin-film conductive film, an opening is formed in the thin-film electrode inside the opening formed in the thick-film electrode to expose the insulating layer;
さらに、 前記上部電極を形成する工程 7 において、 前記厚膜電極に設 けられる開口部内に露出する前記薄膜電極を覆う ように、 前記上部電極 を形成することを特徴とする請求の範囲第 1 0項または請求の範囲第 1 1項に記載の薄膜型電子源の製造方法。 Further, in the step 7 of forming the upper electrode, the upper electrode is covered so as to cover the thin-film electrode exposed in an opening formed in the thick-film electrode. 12. The method of manufacturing a thin-film electron source according to claim 10 or claim 11, wherein:
1 3 . 前記厚膜導電膜を形成する工程 4において、 前記厚膜導電膜を、 メ ツキ、 スパッタ リ ング、 真空蒸着、 化学気相成長あるいは印刷法のい ずれかの方法によ り形成することを特徴とする請求の範囲第 1 0項ない し請求の範囲第 1 2項のいずれか 1項に記載の薄膜型電子源の製造方法。  13. In the step 4 of forming the thick film conductive film, the thick film conductive film is formed by any one of plating, sputtering, vacuum deposition, chemical vapor deposition, or printing. The method for manufacturing a thin-film electron source according to any one of claims 10 to 12, characterized by the above-mentioned.
1 4 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、  14. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. Electron source elements,
前記上部電極と電気的に接続される薄膜電極と、 前記薄膜電極上に設 けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成され、 前記 複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電 圧を印加する複数のバス電極とを有する薄膜型電子源の製造方法であつ て、  A thin-film electrode electrically connected to the upper electrode; and a thick-film electrode provided on the thin-film electrode and having a thickness greater than that of the thin-film electrode. A method of manufacturing a thin-film electron source, comprising: a plurality of bus electrodes for applying a driving voltage to an upper electrode of an electron source element in a first direction inside;
前記下部電極を形成する工程 1 と、  Step 1 of forming the lower electrode;
前記絶縁層を形成する工程 2 と、  Step 2 of forming the insulating layer;
前記下部電極および前記絶縁層上に薄膜導電膜を形成する工程 3 と、 前記薄膜導電膜上に選択的に厚膜電極を形成する工程 4 と、  A step 3 of forming a thin film conductive film on the lower electrode and the insulating layer; and a step 4 of selectively forming a thick film electrode on the thin film conductive film.
前記薄膜導電膜を選択的にパターンニングして前記薄膜電極を形成す る工程 5、  Forming the thin film electrode by selectively patterning the thin film conductive film, 5.
前記薄膜電極と電気的に接続される上部電極を形成する工程 6 とを有 することを特徴とする薄膜型電子源の製造方法。  Forming a top electrode electrically connected to the thin-film electrode. 6. A method for manufacturing a thin-film electron source.
1 5 . 前記薄膜導電膜を形成する工程 3 において、 前記薄膜導電膜の 膜厚が、 前記上部電極の膜厚の 1 0倍以下の厚さになるように、 前記薄 膜導電膜を形成することを特徴とする請求の範囲第 1 4項に記載の薄膜 型電子源の製造方法。 15. In the step 3 of forming the thin-film conductive film, the thin-film conductive film is formed such that the thickness of the thin-film conductive film is 10 times or less the thickness of the upper electrode. 15. The thin film according to claim 14, wherein Method of manufacturing a type electron source.
1 6 . 前記選択的に厚膜電極を形成する工程 4において、 前記厚膜電 極に前記絶縁層が露出する開口部を形成し、  16. In the step 4 of selectively forming the thick film electrode, an opening is formed in the thick film electrode so that the insulating layer is exposed,
また、前記薄膜導電膜を選択的にパターンニングする工程 5 において、 前記薄膜電極に前記絶縁層が露出する開口部を形成し、  In step 5 of selectively patterning the thin film conductive film, an opening is formed in the thin film electrode so that the insulating layer is exposed,
さらに、 前記上部電極を形成する工程 6 において、 前記厚膜電極に設 けられる開口部内に露出する前記薄膜電極を覆うように、 前記上部電極 を形成することを特徴とする請求の範囲第 1 4項または請求の範囲第 1 5項に記載の薄膜型電子源の製造方法。  Further, in the step (6) of forming the upper electrode, the upper electrode is formed so as to cover the thin film electrode exposed in an opening provided in the thick film electrode. 16. The method for producing a thin-film electron source according to claim 15 or claim 15.
1 7 . 前記選択的に厚膜電極を形成する工程 4において、 前記厚膜電 極を、 メ ツキ、 スパッタ リ ング、 真空蒸着、 化学気相成長あるいは印刷 法のいずれかの方法によ り形成することを特徴とする請求の範囲第 1 4 項ないし請求の範囲第 1 6項のいずれか 1項に記載の薄膜型電子源の製 造方法。  17. In the step 4 of selectively forming a thick film electrode, the thick film electrode is formed by any one of plating, sputtering, vacuum deposition, chemical vapor deposition, or printing. The method for producing a thin-film electron source according to any one of claims 14 to 16, wherein the method comprises:
1 8 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、  18. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. Electron source elements,
前記上部電極と一体的に設けられる薄膜電極と、 前記薄膜電極上に設 けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成され、 前記 複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電 圧を印加する複数のバス電極とを有する薄膜型電子源の製造方法であつ て、  A thin film electrode provided integrally with the upper electrode; and a thick film electrode provided on the thin film electrode and having a larger thickness than the thin film electrode. A method of manufacturing a thin-film electron source, comprising: a plurality of bus electrodes for applying a driving voltage to an upper electrode of an electron source element in a first direction of the first direction.
前記下部電極を形成する工程 1 と、  Step 1 of forming the lower electrode;
前記絶縁層を形成する工程 2 と、  Step 2 of forming the insulating layer;
前記下部電極および前記絶縁層上に簿膜導電膜を形成する工程 3 と、 前記薄膜導電膜上に厚膜導電膜を形成する工程 4 と、 Step 3 of forming a thin film conductive film on the lower electrode and the insulating layer; Step 4 of forming a thick conductive film on the thin conductive film;
前記厚膜導電膜を選択的にパターンニングして前記厚膜電極を形成す る工程 5 と、  Step 5 of selectively patterning the thick-film conductive film to form the thick-film electrode;
前記薄膜導電膜を選択的にパターンニングして前記薄膜電極および前 記上部電極を形成する工程 6 とを有することを特徴とする薄膜型電子源 の製造方法。  A step 6 of selectively patterning the thin-film conductive film to form the thin-film electrode and the upper electrode.
1 9 .前記厚膜導電膜を選択的にパターンニングする工程 5 において、 前記厚膜電極に前記絶縁層が露出する開口部を形成することを特徴とす る請求の範囲第 1 8項に記載の薄膜型電子源の製造方法。  19. The method according to claim 18, wherein in the step 5 of selectively patterning the thick film conductive film, an opening for exposing the insulating layer is formed in the thick film electrode. Of manufacturing a thin film type electron source.
2 0 . 前記厚膜導電膜を形成する工程 4において、 前記厚膜導電膜を、 メ ツキ、 スパッタ リング、 真空蒸着、 化学気相成長あるいは印刷法のい ずれかの方法により形成することを特徴とする請求の範囲第 1 8項また は請求の範囲第 1 9項に記載の薄膜型電子源の製造方法。  20. In the step 4 of forming the thick-film conductive film, the thick-film conductive film is formed by any one of plating, sputtering, vacuum deposition, chemical vapor deposition, or printing. 10. The method of manufacturing a thin-film electron source according to claim 18 or claim 19.
2 1 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、  21. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the upper electrode surface when a positive voltage is applied to the upper electrode. Electron source elements,
前記上部電極と一体的に設けられる薄膜電極と、 前記薄膜電極上に設 けられ、 前記薄膜電極に比して膜厚が厚い厚膜電極とで構成され、 前記 複数個の電子源素子の中の第 1の方向の電子源素子の上部電極に駆動電 圧を印加する複数のバス電極とを有する薄膜型電子源の製造方法であつ て、  A thin film electrode provided integrally with the upper electrode; and a thick film electrode provided on the thin film electrode and having a larger thickness than the thin film electrode. A method of manufacturing a thin-film electron source, comprising: a plurality of bus electrodes for applying a driving voltage to an upper electrode of an electron source element in a first direction of the first direction.
前記下部電極を形成する工程 1 と、  Step 1 of forming the lower electrode;
前記絶縁層を形成する工程 2 と、  Step 2 of forming the insulating layer;
前記下部電極および前記絶縁層上に薄膜導電膜を形成する工程 3 と、 前記薄膜導電膜上に選択的に厚膜電極を形成する工程 4 と、 前記薄膜導電膜を選択的にパターンニングして前記薄膜電極および前 記上部電極を形成する工程 5 とを有することを特徴とする薄膜型電子源 の製造方法。 A step 3 of forming a thin film conductive film on the lower electrode and the insulating layer; and a step 4 of selectively forming a thick film electrode on the thin film conductive film. A step 5 of selectively patterning the thin-film conductive film to form the thin-film electrode and the upper electrode.
2 2 . 前記選択的に厚膜電極を形成する工程 4において、 前記厚膜電 極に前記絶縁層が露出する開口部を形成することを特徴とする請求の範 囲第 2 1項に記載の薄膜型電子源の製造方法。  22. The method according to claim 21, wherein in the step 4 of selectively forming a thick film electrode, an opening is formed in the thick film electrode so that the insulating layer is exposed. A method for manufacturing a thin-film electron source.
2 3 . 前記選択的に厚膜導電膜を形成する工程 4において、 前記厚膜 導電膜を、 メ ツキ、 スパッタ リ ング、 真空蒸着、 化学気相成長あるいは 印刷法のいずれかの方法によ り形成することを特徴とする請求の範囲第 2 1項または請求の範囲第 2 2項に記載の薄膜型電子源の製造方法。  23. In the step 4 for selectively forming the thick film conductive film, the thick film conductive film is formed by any one of plating, sputtering, vacuum deposition, chemical vapor deposition, or printing. The method for producing a thin-film electron source according to claim 21 or claim 22, wherein the electron source is formed.
2 4 . 複数個の電子源素子と、 前記複数個の電子源素子の中の第 1の 方向の電子源素子に駆動電圧を印加する複数のパス電極とを有する第 1 の基板と、  24. A first substrate having a plurality of electron source elements, and a plurality of pass electrodes for applying a drive voltage to the electron source elements in a first direction among the plurality of electron source elements,
枠部材と、  A frame member;
蛍光体を有する第 2の基板とを備え、 前記第 1 の基板、 前記枠部材ぉ よび前記第 2の基板とで囲まれる空間が真空雰囲気とされる表示装置で あって、  A display device comprising: a second substrate having a phosphor, wherein a space surrounded by the first substrate, the frame member, and the second substrate is a vacuum atmosphere,
前記第 1の基板の各バス電極は、 前記各電子源素子の電極と電気的に 接続され、 かつ膜厚が前記電子源素子の電極の膜厚以下の厚さの薄膜電 極と、  Each bus electrode of the first substrate is electrically connected to an electrode of each of the electron source elements, and a thin film electrode having a thickness equal to or less than the thickness of the electrode of the electron source element;
前記薄膜電極と電気的に接続され、 前記薄膜電極に比して膜厚が厚い 厚膜電極とで構成されることを特徴とする表示装置。  A display device comprising: a thick-film electrode that is electrically connected to the thin-film electrode and has a larger thickness than the thin-film electrode.
2 5 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印 刷法のいずれかの方法によ り形成される金属層であることを特徴とする 請求の範囲第 2 4項に記載の表示装置。 25. The method according to claim 24, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. The display device according to claim 1.
2 6 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、 前記複数個の電子源素子 の中の第 1の方向の電子源素子の上部電極に駆動電圧を印加する複数の バス電極とを有する第 1の基板と、 26. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. A first substrate having: a plurality of electron source elements; and a plurality of bus electrodes for applying a drive voltage to an upper electrode of the electron source element in a first direction among the plurality of electron source elements.
枠部材と、  A frame member;
蛍光体を有する第 2の基板とを備え、 前記第 1の基板、 前記枠部材ぉ よび前記第 2の基板とで囲まれる空間が真空雰囲気とされる表示装置で あって、  A second substrate having a phosphor, wherein a space surrounded by the first substrate, the frame member, and the second substrate is a vacuum atmosphere,
前記第 1の基板の各バス電極は、 前記上部電極と電気的に接続される 薄膜電極と、  Each bus electrode of the first substrate, a thin film electrode electrically connected to the upper electrode,
前記薄膜電極上に設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電 極とで構成されることを特徴とする表示装置。  A display device, comprising: a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode.
2 7 . 前記薄膜電極は、 その膜厚が前記上部電極の膜厚の 1 0倍以下 の厚さであることを特徴とする請求の範囲第 2 6項に記載の表示装置。  27. The display device according to claim 26, wherein said thin-film electrode has a thickness not more than 10 times the thickness of said upper electrode.
2 8 . 前記薄膜電極および厚膜電極は、 それそれ前記絶縁層が露出す す開口部を有し、 かつ、 前記厚膜電極に設けられる開口部は、 前記薄膜 電極に設けられる開口部より大きく、  28. The thin-film electrode and the thick-film electrode each have an opening through which the insulating layer is exposed, and the opening provided in the thick-film electrode is larger than the opening provided in the thin-film electrode. ,
前記上部電極は、 前記厚膜電極に設けられる開口部内に露出する前記 薄膜電極を覆うように設けられていることを特徴とする請求の範囲第 2 6項または請求の範囲第 2 7項に記載の表示装置。  The said upper electrode is provided so that the said thin film electrode exposed in the opening part provided in the said thick film electrode may be provided, The Claim 26 or Claim 27 characterized by the above-mentioned. Display device.
2 9 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印 刷法のいずれかの方法により形成される金属層であることを特徴とする 請求の範囲第 2 6項ないし請求の範囲第 2 8項のいずれか 1項に記載の 表示装置。 29. The method according to claim 26, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. The display device according to any one of Items 28 to 28.
3 0 . 下部電極と、 絶縁層と、 上部電極とをこの順番に積層した構造 を有し、 前記上部電極に正極性の電圧を印加した際に、 前記上部電極表 面から電子を放出する複数個の電子源素子と、 前記複数個の電子源素子 の中の第 1の方向の電子源素子の上部電極に駆動電圧を印加する複数の パス電極とを有する第 1の基板と、 30. A structure in which a lower electrode, an insulating layer, and an upper electrode are laminated in this order, and a plurality of electrodes that emit electrons from the surface of the upper electrode when a positive voltage is applied to the upper electrode. A first substrate having a plurality of electron source elements, and a plurality of pass electrodes for applying a drive voltage to an upper electrode of the electron source elements in a first direction among the plurality of electron source elements;
枠部材と、  A frame member;
蛍光体を有する第 2の基板とを備え、 前記第 1の基板、 前記枠部材ぉ よび前記第 2の基板とで囲まれる空間が真空雰囲気とされる表示装置で あって、  A second substrate having a phosphor, wherein a space surrounded by the first substrate, the frame member, and the second substrate is a vacuum atmosphere,
前記第 1 の基板の各バス電極は、 前記上部電極と一体的に設けられる 簿膜電極と、  Each bus electrode of the first substrate,
前記薄膜電極上に設けられ、 前記薄膜電極に比して膜厚が厚い厚膜電 極とで構成されることを特徴とする表示装置。  A display device comprising: a thick-film electrode provided on the thin-film electrode and having a larger thickness than the thin-film electrode.
3 1 . 前記厚膜電極は、 それそれ前記絶縁層が形成される領域に設け られる開口部を有することを特徴とする請求の範囲第 3 0項に記載の表 示装置。  31. The display device according to claim 30, wherein the thick-film electrode has an opening provided in a region where the insulating layer is formed.
3 2 . 前記厚膜電極は、 メ ツキ、 真空蒸着、 化学気相成長あるいは印 刷法のいずれかの方法によ り形成される金属層であることを特徴とする 請求の範囲第 3 0項または請求の範囲第 3 1項に記載の表示装置。  32. The method according to claim 30, wherein the thick film electrode is a metal layer formed by any one of plating, vacuum deposition, chemical vapor deposition, or printing. Alternatively, the display device according to claim 31.
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