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WO2001016697A3 - Local register instruction for micro engine used in multithreadedparallel processor architecture - Google Patents

Local register instruction for micro engine used in multithreadedparallel processor architecture Download PDF

Info

Publication number
WO2001016697A3
WO2001016697A3 PCT/US2000/024054 US0024054W WO0116697A3 WO 2001016697 A3 WO2001016697 A3 WO 2001016697A3 US 0024054 W US0024054 W US 0024054W WO 0116697 A3 WO0116697 A3 WO 0116697A3
Authority
WO
WIPO (PCT)
Prior art keywords
multithreadedparallel
processor architecture
engine used
local register
register instruction
Prior art date
Application number
PCT/US2000/024054
Other languages
French (fr)
Other versions
WO2001016697A2 (en
WO2001016697A9 (en
Inventor
Gilbert Wolrich
Matthew J Adiletta
William Wheeler
Debra Bernstein
Donald Hooper
Original Assignee
Intel Corp
Gilbert Wolrich
Matthew J Adiletta
William Wheeler
Debra Bernstein
Donald Hooper
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Gilbert Wolrich, Matthew J Adiletta, William Wheeler, Debra Bernstein, Donald Hooper filed Critical Intel Corp
Priority to PCT/US2000/024054 priority Critical patent/WO2001016697A2/en
Priority to AU71012/00A priority patent/AU7101200A/en
Publication of WO2001016697A2 publication Critical patent/WO2001016697A2/en
Priority to US09/811,995 priority patent/US20020053017A1/en
Publication of WO2001016697A3 publication Critical patent/WO2001016697A3/en
Publication of WO2001016697A9 publication Critical patent/WO2001016697A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A method of operating a processor (12) including loading one or more bytes of data within a register associated with microengines (22 a-f) with a shifted value of an operand and preserving or cleaning the bytes of data that are not loaded. The method further includes providing a bit mask that specifies which of the one or more bytes of data within the register are affected.
PCT/US2000/024054 1999-09-01 2000-09-01 Local register instruction for micro engine used in multithreadedparallel processor architecture WO2001016697A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US2000/024054 WO2001016697A2 (en) 1999-09-01 2000-09-01 Local register instruction for micro engine used in multithreadedparallel processor architecture
AU71012/00A AU7101200A (en) 1999-09-01 2000-09-01 Local register instruction for micro engine used in multithreaded parallel processor architecture
US09/811,995 US20020053017A1 (en) 2000-09-01 2001-03-19 Register instructions for a multithreaded processor

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15196199P 1999-09-01 1999-09-01
US60/151,961 1999-09-01
PCT/US2000/024054 WO2001016697A2 (en) 1999-09-01 2000-09-01 Local register instruction for micro engine used in multithreadedparallel processor architecture

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/811,995 Continuation US20020053017A1 (en) 2000-09-01 2001-03-19 Register instructions for a multithreaded processor

Publications (3)

Publication Number Publication Date
WO2001016697A2 WO2001016697A2 (en) 2001-03-08
WO2001016697A3 true WO2001016697A3 (en) 2002-02-14
WO2001016697A9 WO2001016697A9 (en) 2002-09-12

Family

ID=35788086

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/024054 WO2001016697A2 (en) 1999-09-01 2000-09-01 Local register instruction for micro engine used in multithreadedparallel processor architecture

Country Status (1)

Country Link
WO (1) WO2001016697A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US6002881A (en) * 1997-06-10 1999-12-14 Arm Limited Coprocessor data access control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487159A (en) * 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US6002881A (en) * 1997-06-10 1999-12-14 Arm Limited Coprocessor data access control

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WALDSPURGER ET AL.: "Register relocation: Flexible contexts for multithreading", PROCEEDINGS OF THE 20TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 1993, pages 120 - 130, XP002943962 *

Also Published As

Publication number Publication date
WO2001016697A2 (en) 2001-03-08
WO2001016697A9 (en) 2002-09-12

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