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WO2000019514A1 - Semiconductor package and flip-chip bonding method therefor - Google Patents

Semiconductor package and flip-chip bonding method therefor Download PDF

Info

Publication number
WO2000019514A1
WO2000019514A1 PCT/JP1998/004337 JP9804337W WO0019514A1 WO 2000019514 A1 WO2000019514 A1 WO 2000019514A1 JP 9804337 W JP9804337 W JP 9804337W WO 0019514 A1 WO0019514 A1 WO 0019514A1
Authority
WO
WIPO (PCT)
Prior art keywords
bonding
chip
substrate
bumps
semiconductor chip
Prior art date
Application number
PCT/JP1998/004337
Other languages
French (fr)
Japanese (ja)
Inventor
Ryouichi Kajiwara
Masahiro Koizumi
Toshiaki Morita
Kazuya Takahashi
Asao Nishimura
Kunihiro Tsubosaki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/004337 priority Critical patent/WO2000019514A1/en
Priority to KR1020007003151A priority patent/KR20010030703A/en
Priority to CN98814031A priority patent/CN1299518A/en
Publication of WO2000019514A1 publication Critical patent/WO2000019514A1/en

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    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Definitions

  • the present invention relates to a semiconductor package having a structure in which a semiconductor chip such as an LSI chip is mounted on a carrier substrate made of an organic material.
  • solder bumps are formed on the A1 electrode pad on the chip side via a barrier metal, and the connection terminals on the board side are plated with Au with good solder wettability to achieve a fluxless, non-oxidizing atmosphere. This is a method in which solder is reflowed and joined. If the substrate is a ceramic substrate, use it in a hermetically sealed state.If the substrate is an organic substrate, fill it with a resin and silicon compound whose thermal expansion coefficient is adjusted between the chip and resin. Used with increased reliability of solder joints.
  • thermocompression bonding and thermocompression bonding using ultrasonic waves have been known as flip chip bonding of Au bumps and Au pads without using solder.
  • Conventional thermocompression bonding conditions are a heating temperature of 350 ° C, a load of 150 to 250 g Z bumps, and chips with less than 50 bumps are bonded.
  • a chip having a heating temperature of 200 ° C., a load of 300 g and approximately 6 bumps is bonded.
  • the carrier substrate is made of ceramic.
  • the load is reduced by increasing the heating temperature, but it still requires 150 g Z bumps.
  • the heating temperature is reduced to 200 ° C in thermocompression bonding with ultrasonic waves.
  • the load is as high as 300 g Z bump. This is a condition that has been studied and found in order to reliably join AuZAu in the atmosphere.Because the joining becomes unstable at lower temperatures and load conditions, it is not suitable for actual product assembly. Not applicable.
  • the crimped shape of the Au bump is a junction having a shape that is largely crushed with a typical size of 15 to 25 tm in thickness and a diameter of 15 O ⁇ m or more.
  • connection method As another conventional Au bump connection method, there is also known a connection method in which a conductive resin is used as an adhesive and heated and pressed between the two. In this method, a predetermined long-term reliability is obtained by filling and solidifying the resin between the chip and the substrate.
  • a method to cope with this is to mount the electrode terminals of the chip by arranging them in an elliptical manner over the entire surface of the chip.
  • the solder bump bonding method (C 4) which has already been adopted in the field of conventional large computers, can solve the above two problems, but when applied to semiconductor packages, there is a problem in terms of soldering temperature. appear.
  • large-scale computers use high-melting-point solder (95 Pb-15Sn solder with a melting point of 300 ° C) because of the necessity of performing subsequent layer soldering for the chip soldering material.
  • the soldering temperature is higher than the melting point of the solder.
  • solder having a solidus temperature in the range of 200 ° C to 240 ° C the solder joints inside the package will be partially removed during the eutectic soldering process of mounting the semiconductor package on the wiring board. Problems such as re-melting and defective disconnection occur. In other words, in the internal connection of the semiconductor package, a connection part having a heat resistance of 250 ° C. or more must be realized at a low connection temperature of 250 ° C. or less.
  • This bonding method is a method in which Au, which has a high melting point and excellent bonding properties, is formed into a bump shape and pressed in a solid phase using heating or ultrasonic waves. You can get it.
  • the conventional Au bump bonding method requires a bonding load of 300 g per bump, and a chip of about 100 to 2000 bumps is actually considered.
  • the load applied to the tool is 30 to 600 kg, and chipping or cracking of the chip due to one-sided contact of the press tool becomes a serious problem.
  • the maximum load that can be applied to the chip is empirically estimated to be about 20 to 40 kg, reliable bonding must be performed under the condition that the bonding load per bump is 20 to 80 g. If so, practical application is difficult.
  • the bonding temperature can be increased by the conventional thermocompression bonding method, reliable bonding can be achieved under low load conditions. The temperature cannot be raised to more than 250 ° C even for mid-air and 200 ° C for epoxy.
  • Ultrasonic thermocompression bonding which enables reliable bonding with low heating temperature and relatively low load, requires high ultrasonic energy to obtain a reliable joint. Therefore, there is a problem that the chip is damaged.
  • the method using the Au bump and the conductive resin is a method of performing pressure bonding with a low heating temperature and a low bonding load as connection conditions, so that the connection can be performed with a small deformation of the bump.
  • a resin is filled between the chip and the substrate in advance in the connection step and then pressure-bonded, it is possible to assemble a good package free of voids and the like.
  • a conductive resin there is a reliability problem that the contact state of the conductive particles deteriorates due to volume expansion due to moisture absorption, and the resistance increases with time.
  • the bonding temperature in the conventional technology is 70 ° C or more in view of the improvement of the bonding property by desorption of adsorbed molecules and interface diffusion, and 200 ° C
  • the shape after crimping is used as the aspect ratio (height Z diameter ratio).
  • the thermal strain of the joined body when the joining temperature is assumed to be 70 ° C is roughly estimated.
  • the Young's modulus of each member is as follows: Si: 190 GPa, Au pump: 88 GPa, polyimide substrate
  • the bump height when the bonding temperature is 70 ° C, the bump height must be 50 m or more even if the bump has sufficient bonding strength. A height of at least 8 O zm is required. If the bonding strength between the Au bump and the chip or substrate is weak, a higher bump height is required. For this reason, the Au bump height is the minimum height at which the Au bump is not damaged by thermal contraction after bonding, that is, the crimping diameter when the bump height is 50 ⁇ m when the bonding temperature is 70 ° C. : 500 ⁇ m or more, and when the bonding temperature is 200 ° C. and the bump height is 80 tm, the pressure bonding diameter is 400 im or more. For this reason, it has been difficult to reduce the bump pitch to 500 ⁇ m or less in consideration of the variation in the crimping diameter and the variation in the shape. Disclosure of the invention
  • Another object of the present invention is to provide a mounting structure which does not cause a problem of joint damage due to thermal strain in a cooling process after bonding the organic carrier substrate to the substrate when mounting at an wafer level. Providing a mounting structure that can reduce the pitch, and providing a low-cost package mounting method at the wafer stage. To provide.
  • the substrate and the chip are formed by using Au bumps arranged in an area as an intermediate material.
  • the structure is such that metal is firmly joined and the gap between the two is filled with resin.
  • the material composition of the flip chip bonding surface is assumed to be AuZAu, the cleanliness of the bonding surface is specified, and the water content is determined by the water vapor partial pressure: l OOP Heat-weld or heat-weld by applying scrubbing or weak ultrasonic vibration in a dry atmosphere of a or less. According to this bonding method, the semiconductor package according to the present invention can be manufactured.
  • Au has a strength of about 14 to 25 kg / 2 and is a material that does not harden due to work, so its fatigue life is at least one order of magnitude longer than that of solder materials. Bonding improves the package's temperature cycle reliability. However, if the Au bumps are not severely crushed, a reliable joint with sufficient joint strength cannot be obtained.Therefore, there is the problem of chip damage due to joining load and ultrasonic vibration, There is a problem when the gap between the holes becomes too narrow and the resin cannot be sufficiently filled. For this reason, it is difficult to apply Au bumps to a semiconductor package using an organic substrate.
  • FIG. 12 shows the bonding results when the Au pole was ultrasonically bonded to the Au deposited film at a heating temperature of 100 ° C. in the case where the bonding atmosphere was in the air or in nitrogen.
  • the joining load is 50 g.
  • the horizontal axis indicates the ultrasonic output, and the vertical axis indicates the ratio at which the bonding strength becomes 16 g or more.
  • Bonding success rate 100% ultrasonic output is obtained.
  • the ultrasonic output is 0 mW, that is, bonding can be performed only with load, and it cannot be cleaned in nitrogen. At least at 1.4 mW, it reaches 100%.
  • a bonding success rate of 100% can be obtained even with purification at 15 mW, and if not, 151 mW is required.
  • bonding in a nitrogen atmosphere to a surface that is not cleaned has better re-bonding properties than cleaning and bonding in the air.
  • Figure 13 shows the results of an Auger analysis of the surface contamination. The untreated sample is clearly contaminated with organic matter and S, and the Au concentration on the surface is as low as 33 atomic%.
  • the sample subjected to the surface cleaning treatment has a low contamination level even when exposed to nitrogen or the atmosphere, and maintains a high Au concentration of 55 to 61 atomic% on the surface as compared with the untreated one. ing.
  • a u In welding the bonding properties are not determined only by the surface contamination level, and the influence of the atmospheric gas is large.
  • Fig. 14 shows the gas composition of the atmosphere (air). Oxygen and moisture can be considered as gases that affect the bondability. Therefore, an atmosphere containing these gases was created and bonding was performed in the atmosphere, and the bonding properties were compared.
  • Fig. 15 shows the results of bonding when Ar gas was bonded to a gas containing oxygen or moisture in an atmosphere of air and nitrogen. The shaded area is the ultrasonic output area where the bonding success rate: 100% can be obtained. Oxygen did not affect the bonding at all, indicating that the moisture was poor. Fig.
  • 16 shows the relationship between the water content in the atmospheric gas and the minimum ultrasonic output that gives a bonding success rate of 100%.
  • the water content is in the range of about 0.03 to 0.1 vo 1%, and the bondability rapidly deteriorates. That is, if the moisture content in the atmosphere is 0.03 to 0.1 vol% or less, a surface cleaning treatment is performed to obtain a bonding temperature of 100 ° C and a bonding load of 50 ° C. Under low temperature and low load conditions of g, the Au pole and Au pad can be crimped to a joint strength of 16 g or more. From these results, it is clear that control of moisture in the bonding atmosphere is very important in Au bonding. If the moisture control is sufficient, sufficient bonding strength can be obtained by cleaning the Au bonding surface so that the Au concentration becomes 20 atomic% or more.
  • the chip on which the Au bump is formed can be used as the Au pad or Au bump on the organic substrate.
  • Load ⁇ 50 bumps, Bonding temperature: 100 to 200 ° C suppresses bump deformation and provides high strength It becomes possible to join to.
  • an Au bump ZA u pad bonding method with controlled surface cleaning and atmosphere it is possible to house ultra-high pin count or high speed operation LSI chips and maximize their chip performance. And a package structure with high long-term reliability of the joint can be realized.
  • the semiconductor package can be assembled with good productivity and a good yield.
  • Figures 17 and 18 show the results of a reliability test conducted by assembling a semiconductor package using this method.
  • Fig. 17 shows the temperature cycle test results of packages with various Au bump heights. The tip size ranges from 5 thighs to 10 mm square. There is clearly a correlation between the bump height and the rupture life, and the practically required life of more than 100 times is about 5 ⁇ or more in bump height.
  • Fig. 18 shows the results of examining the relationship between the bump joint strength and the rate of breakage when solder reflow is repeated. At a bump strength of 20 g, fracture is observed with a small probability. Therefore, from the viewpoint of package reliability, it is desirable that the bump height is 5 or more and the bump strength is 30 g or more.
  • joining can be performed at a joining temperature of 70 ° C. to 100 ° C. with a small crushing rate as shown in FIG.
  • the strain between the Si wafer and the carrier substrate is about 60 m under the model conditions in FIG. 19, and there is a relationship between the bump height and the main strain as shown in FIG.
  • the bonding temperature is 70 ° C. and the bump height is 50 m
  • the main strain is about 3%, and a stress of 13 to 20 kg / mm 2 is generated. If the bonding interface strength of the Au bump is lower than this value, it will break at the interface, so the bonding strength must be sufficiently high.
  • the bump crush rate must be increased to 50% or more.
  • the bump diameter becomes 420 ⁇ m, making it difficult to achieve a pitch of 500 ⁇ m or less.
  • bonding can be achieved with a crush ratio of 22% and an aspect ratio of 0.52.
  • a bump height of 50 m can be realized with a crimping diameter of 10 ⁇ m ⁇ . That is, bonding at a pitch of 200 ⁇ m is possible.
  • the bump diameter to 200 ⁇ and the bump height to 100 >> 1
  • the distortion can be reduced to 0.3% and the stress generated in the bump is 2.6.
  • kg / mm 2 suppresses deformation within the elastic range, so there is no risk of breakage of the joint.
  • the present invention has been made on a cleaning method for the Au surface and a bonding atmosphere in consideration of the water content of the bonding atmosphere, which will be described later in detail. Then, according to the bonding method of the present invention, the following novel semiconductor packages can be obtained.
  • the electrode terminals of the semiconductor chip and the internal connection terminals of the organic substrate are connected via an Au bump with a diameter of 300 ⁇ or less, a height of 50 ⁇ or more and a height ratio of 1/5 or more.
  • Au bump with a diameter of 300 ⁇ or less, a height of 50 ⁇ or more and a height ratio of 1/5 or more.
  • the semiconductor chip and the plurality of internal connection terminals of the organic substrate are flip-chip bonded via Au bumps with a pitch of 400 m or less, and the area of the external connection terminal and the internal connection terminal on the organic substrate are connected.
  • the area is divided by slits, and the external connection terminal and the internal connection terminal are connected by wiring passing through the slit Semiconductor package.
  • the semiconductor chip and the plurality of internal connection terminals arranged in an area on the organic substrate are joined face-down via Au bumps, and the area of the internal connection terminal and the area of the external connection terminal are connected. Is a semiconductor package that overlaps on the projection surface.
  • a plurality of semiconductor chips having electrode terminals and arranged with a gap of 1 mm or less and a plurality of internal connection terminals of the organic substrate are connected via Au bumps, and the external connection terminals of the organic substrate are connected to the liquid.
  • FIG. 1 is an embodiment of a sectional structure of a semiconductor package according to the present invention.
  • FIG. 2 is a diagram showing an Au bump shape.
  • FIG. 3 is another embodiment of the sectional structure of the semiconductor package according to the present invention.
  • FIG. 4 is another embodiment of the sectional structure of the semiconductor package according to the present invention.
  • FIG. 5 is a plan view of an organic carrier substrate used for the semiconductor package of FIG.
  • FIG. 6 is an embodiment of a cross-sectional structure of a multi-chip semiconductor package according to the present invention.
  • FIG. 7 is an example of a joining procedure showing a joining method of a chip and a carrier substrate according to the present invention.
  • FIG. 8 is an embodiment of an apparatus configuration for realizing the joining method of FIG.
  • FIG. 9 shows another joining method of a chip and a carrier substrate according to the present invention. Example procedure.
  • FIG. 10 is an embodiment of an apparatus configuration for realizing the joining method of FIG. 9.
  • FIG. 11 is an embodiment of an apparatus configuration of the pretreatment chamber and the joining chamber of FIG. Figure 12 shows the experimental results showing the effect of the nitrogen and atmospheric bonding atmosphere on the bonding results.
  • Fig. 13 shows Auger analysis results showing the contamination on the joint surface.
  • Fig. 14 shows the gas composition in the atmosphere.
  • Fig. 15 shows the experimental results showing the effect of various bonding atmospheres on the bonding results.
  • Fig. 16 shows the experimental results showing the effect of the moisture content of the bonding atmosphere on the bonding results.
  • FIG. 17 is a result of a temperature cycle test of the semiconductor package according to the present invention.
  • FIG. 18 is a result of a repeated solder reflow test of the semiconductor package according to the present invention.
  • Figure 19 shows a model of a semiconductor package.
  • Figure 20 shows the relationship between bump height and distortion.
  • Fig. 21 shows the relationship between the crushing rate and the joint strength.
  • FIG. 1 shows a sectional structure of a semiconductor package according to the present invention.
  • Au bumps 7 are formed on A 1 or Au electrode pads 2 of semiconductor chip 1 (hereinafter referred to as chip 1) by pole bonding.
  • the organic carrier substrate includes an organic insulating plate 3, an internal connection terminal 4 provided on one surface of the organic insulating plate 3, an external connection terminal 5 provided on the back surface of one surface, and an external connection terminal 5
  • the plating resist covering the insulating plate surface around the It is composed of
  • the internal connection terminals 4 and the external connection terminals 5 are formed by Cu plating or a method of attaching and etching Cu foil, and the connection terminals are electrically connected by through holes provided in the organic insulating plate 3 and wiring. It is connected to.
  • connection terminal is provided with Ni or Pd plating on the base and then Au plating on the outermost surface.
  • the Au bumps 8 are formed on the internal connection terminals 4 of the carrier board by pole bonding, and are aligned with the Au bumps 6 of the chip 1 so that the Au bumps come into contact with each other.
  • the atmosphere is evacuated to 1 Pa or less and heated to 15 O to 250 ° C to perform pressure bonding.
  • the load is 30 to 80 g Z bump, and the joining is performed by controlling the amount of displacement so that the bump is not crushed too much.
  • Fig. 2 shows the initial Au bump shape formed by pole bonding.
  • the tip-side pole bump shape (A) has a crimp diameter D c of 110 soil 10 m, a shoulder height H c at which the tip surface of the kyecuring tool is in contact is 25 ⁇ 5 ⁇ , Select the discharge and bonding conditions and the shape of the drilling tool so that the height Dh of the raised part at the center of the bump is 50 m and the height Hh of that part is 50 m at 10 m. ing.
  • the bonding strength is 80 g or more in shear strength.
  • the shape of the pole bump on the substrate side (B) is such that the deformation of the pole is smaller than on the chip side and the shoulder height Hk is as high as about 40 ⁇ 10 m. I have.
  • pole bonding in this case, the bonding terminal surface of the board is sputter-cleaned immediately before bonding in order to improve the bondability.
  • the bonding strength is 50 g or more in shear strength.
  • the shape of both bumps after crimping is controlled by controlling the amount of crushing of the bumps by controlling the amount of displacement so that the bumps are metallically joined at the raised portion at the center of the bumps. ing.
  • the most constricted part of the joined bump pillars is formed at the joint between the bumps, and in terms of strength, The bonding interface is the lowest.
  • the height H between the chip and the substrate is about 70 ⁇ 10 m.
  • the resin 9 with high fluidity is removed. It is poured and cured, and finally, solder bumps 10 are formed on the external connection terminals to complete the package.
  • the following effects are obtained. 1) Since the A1 electrode pad of the chip and the internal connection terminal of the organic carrier substrate are connected by the flip-chip bonding method, the pads are arranged in an area even for multi-pin LSI chips.
  • the pad pitch can be reduced and bonding can be performed, and it can be mounted on a semiconductor package.
  • the chip and the organic carrier substrate are electrically connected at the shortest distance, a package with a high transmission speed can be configured, and a package that can fully exploit the performance of high-speed processing LSI chips can be realized. .
  • the connection is completed within the chip projection area by the face down, a plurality of chips can be mounted close to each other. Therefore, in a multi-chip package, the knock size can be significantly reduced. Also, since the heat resistance of the joints in the package is the same as that of the conventional Au wire bonding type package, it can be mounted on a wiring board with the same solder reflow opening as before.
  • FIG. 3 shows a cross-sectional structure of a semiconductor package according to another embodiment of the present invention.
  • the organic carrier substrate is patterned with polyimide tape 13 with openings, and the internal and external connection terminals 14 are used as internal and external connection terminals on the front and back surfaces of the same Cu land.
  • a tape substrate is used.
  • Ni plating is applied to the base and Au plating is applied to the outermost surface.
  • Au bumps 16 are formed on the internal connection terminals on the opening side, and are joined to Au bumps 15 formed on A 1 or Au electrodes 12 of the LSI chip 11. .
  • the method of joining Au bumps is as follows.
  • the Au bump surface on the substrate side is cleaned by an Ar sputter, and the substrate is carried into a bonding chamber in a dry atmosphere having a water vapor partial pressure of 100 Pa or less without being exposed to the air.
  • the chip on which the Au bumps are formed is heated in a vacuum chamber to remove adsorbed moisture, and then carried into the bonding chamber.
  • the two Au bumps are aligned in the joining chamber, the chip is mounted on the substrate with a face-down, and heated and pressed with a joining tool from the chip side, and several scrubs or ultrasonic waves of 5 to 10 m are performed. Join by applying vibration.
  • the chip and the tape substrate have the same dimensions, and the joining portion is entirely housed inside the chip surface on the projection surface.
  • the present embodiment is suitable for the case of 200 pins or less.
  • FIG. 4 shows a cross-sectional structure of another semiconductor package according to the present invention.
  • FIG. 5 is a plan view of the organic carrier substrate used in FIG.
  • the organic carrier substrate is a tape substrate composed of a polyimide tape 23 and a Cu foil pattern adhered to the tape and etched.
  • the polyimide tape has an opening at the boundary between the external connection terminal area and the internal connection terminal area 24 and the external connection terminal area 25.
  • the slit 29, which is the latter opening, is large enough that the distortion of the tape in the internal connection area is not transmitted to the external connection area.
  • the Cu foil pattern is composed of internal and external connection terminals 26 and 27 and a wiring portion 28 passing through a slit 29.
  • the Au bumps 30 formed on the Au-plated internal connection terminals 26 and the electrode terminals 22 of the chip 21 are metallically joined.
  • the bonding method is as follows. First, the surface of the internal connection terminals of the tape substrate is cleaned by sputtering with Ar ions, the chip is positioned and mounted in a dry atmosphere with a water vapor partial pressure of 100 Pa or less, and the overall temperature is reduced. Heating is performed at 200 ° C, and pressure is applied from the chip side and ultrasonic vibration is applied to perform pressure bonding. On the chip mounting side of the external connection terminal area, a reinforcing plate 31 having the same thermal expansion coefficient as the wiring board on which the package is mounted is adhered with an adhesive 32.
  • Highly fluid resin 33 is poured between the chip and the substrate and solidified.
  • an underlining material is used so that the resin does not leak from the slit portion 29, and the slit portion is also solidified with the resin. Therefore, the wiring passing through the slit is covered and protected by the resin.
  • an ultra-high number of electrode terminals having more than 150 pins are used, and the SI chip is securely connected to the terminals of the tape substrate with a material having a high melting point, a long fatigue life and a high environmental resistance. Because it can be rip-chip bonded, it is possible to assemble an ultra-high-pin-count, ultra-high-speed processing LSI chip into a plastic package with low cost and high reliability when mounted on a wiring board. Further, when the package according to the present embodiment is mounted on a wiring board, thermal distortion due to a difference in thermal expansion between the chip and the carrier board is cut off by the slit portion, and thermal expansion of the external connection terminal area is prevented. The rate is almost the same as the coefficient of thermal expansion of the wiring board. Therefore, no large thermal stress is generated in the solder bump connection part, and the temperature cycle life of the solder bump connection part becomes very long.
  • FIG. 6 shows a cross-sectional structure of an embodiment in which the present invention is applied to a multi-chip package in which a plurality of chips are closely arranged with a gap of 1 mm or less.
  • an internal connection terminal 44, an external connection terminal 45, and a wiring pattern are formed on each surface of the module substrate 43.
  • Internal connection terminals Au bumps are made by applying thick Ni plating 47 on the ground and forming Au plating 48 on it.
  • Au stud bumps 46 are formed on the A1 electrode pads 42 of the chip 41 by a wire bonding method.
  • the bonding of Au bumps is performed by cleaning the surface of the Au bumps on the substrate side by sputter cleaning, transporting it to a bonding chamber filled with an air-tight and dry atmosphere gas without exposing it to the air, Au bumps are heat-treated in vacuum to remove adsorbed moisture and organic matter, are aligned and faced, and are joined by applying heat, pressure and scrub vibration. A plurality of chips are joined to the module substrate, and a resin 49 is filled between the chip substrates. Solder bumps 50 with a liquidus temperature of 190 ° C. or higher are formed on the back surface of the module substrate for connection to the motherboard. As an external connection mechanism, a structure in which a lead terminal is used instead of a solder bump and the lead terminal is soldered to a mother board may be used.
  • connection between the module substrate and the chip is a metal joint between Au bumps having high strength, the temperature cycle reliability of the internal connection portion is high, and the connection portion having heat resistance is used. Therefore, there is an effect that there is no restriction on a heating temperature in soldering to a mother node.
  • FIG. 7 shows a joining procedure of the joining method according to the present invention.
  • Au bumps formed by the pole wire bonding method are characterized by high Au purity of the bump material, softness, and high cleanliness of the bump surface because bumps can be formed in the process immediately before flip chip bonding. For this reason, the surface cleaning treatment of both can be omitted, and the chip is placed on the carrier substrate under atmospheric pressure. Then, the surrounding atmosphere is evacuated to a vacuum of 100 Pa or less and heated, and moisture and organic substances adsorbed on the bump surface are separated and pressure-bonded. At this time, the bonding strength can be easily improved by performing scrubbing with an amplitude: several to several tens ⁇ m a plurality of times together with the pressurization, or by applying ultrasonic vibration.
  • the chip is positioned by setting the substrate and chip in a bonding apparatus in the atmosphere, and after positioning, a load of about several g or less per bump is applied to the chip with a pressing jig. By doing so, displacement between the chip and the substrate during pressurization can be prevented, and the bonded area exposed to the vacuum atmosphere can be increased as much as possible to promote the detachment of the adsorbed material.
  • the substrate with the chips is taken out into the atmosphere, liquid resin is allowed to penetrate between the chip substrates, bubbles are removed, and the resin is cured by heating. After that, apply flux to the Au-plated external connection terminals on the back of the carrier board, mount the solder poles, and reflow the solder by heating to form solder bumps.
  • FIG. 8 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG.
  • the upper chamber 54 and the lower chamber 51 for evacuation closely contact each other via the 0-ring 61.
  • a pressing jig / vacuum flange 55 for applying pressure to the chip 68 is hermetically integrated via a bellows 56.
  • a cylinder 62 fixed to a support arm 53 is disposed above the flange, and the piston 75 is attached to the flange to control the vertical movement of the flange.
  • the upper chamber can move up and down independently of the movement of the flange, and is controlled by a drive mechanism 63 attached to the support arm.
  • the relative movement distance between the upper chamber and the flange is designed to be 20 mm or more.
  • the structure is such that the upper chamber can be pulled up while a low load is applied to it, and the position confirmation force camera can be inserted into the chamber.
  • the heat stage 57 for supplying and setting the semiconductor chip 68 and the carrier substrate 70 in a state where the Au bump 69 and the Au pad 71 are in contact with each other has a heater 60 inside. Further, a stage drive mechanism 59 is provided for driving the stage left and right by a small amount.
  • the heat stage is supported by a pairing 58 that has the role of supporting movement and joining load.
  • the size of the space to be evacuated is designed to be the smallest size that can accommodate the chip and the substrate, and the evacuation pump 64 is designed so that the evacuation time to 10 to rr or less is 20 seconds or less. Is selected. N 2 gas 66 is used as the leak gas for returning the chamber to atmospheric pressure.
  • the joining mechanism is arranged outside the vacuum chamber so that only the periphery of the joining sample can be evacuated, so that it is necessary for the joining to be performed under atmospheric pressure before joining.
  • the time required to obtain a vacuum atmosphere is greatly reduced, and a single bonding process such as alignment of substrate and chip ⁇ evacuation ⁇ pressure bonding ⁇ atmospheric leak can be performed in less than one minute.
  • the joining method according to the present invention can be applied to mass production.
  • a scrub of several ⁇ can be applied from the substrate side during the pressure bonding process, the bonding strength can be increased with a low load, and the possibility of chip damage can be further reduced. There is also an effect.
  • FIG. 9 shows another joining procedure of the joining method according to the present invention.
  • the Au pad or Au bump formed by plating is expensive in terms of cost if it is formed thicker than several ims, and must be manufactured with a thickness of 1 ⁇ or less. is there.
  • the Au plating is thin, the Au deformation of the pad is so small that the surface contamination level has a large effect on the bonding. This Therefore, in the procedure shown in the figure, the Au pad surface on the substrate side is cleaned by sputter cleaning, and the Au bump surface on the chip side is only heated in vacuum to remove adsorbed moisture.
  • FIG. 10 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG.
  • the basic configuration of the equipment consists of a pretreatment chamber 81 for cleaning the pad surface of the substrate, a chip supply chamber 83 for supplying a semiconductor chip with vacuum heating and supplying it to the bonding chamber described later, and aligning the substrate and the chip.
  • a substrate unloading room 86 to take out a substrate with chips from the bonding room 86, airtight pretreatment room, bonding room, and chip supply room
  • a dry gas supply mechanism 85 for supplying dry gas to the substrate unloading chamber
  • a vacuum exhaust system 64 for evacuating each chamber to a vacuum
  • a substrate supply mechanism 87 for supplying substrates to the pretreatment chamber.
  • the chambers are connected by gate valves 88, 89, 90 to transfer substrates or chips.
  • the drying gas may be any gas such as air, nitrogen and argon, as long as the partial pressure of water vapor is 100 Pa or less, regardless of oxidizing or non-oxidizing.
  • FIG. 11 is an embodiment showing an apparatus configuration of the pretreatment chamber and the bonding chamber in FIG. 10. It is.
  • the pretreatment chamber 100 is provided with a mechanism for sputtering the carrier substrate 129 with Ar ions.
  • the cathode electrode 107 is electrically insulated from the device by an insulating member 108, and a cathode electrode 106 having the same potential as the ground is arranged on the upper portion.
  • the substrate is set on a force source electrode, the chamber is evacuated to a vacuum, then Ar gas is introduced, and a high frequency voltage superimposed with a DC component is applied between the electrodes from a high frequency power source 109. To generate a glow discharge between the electrodes.
  • the bonding chamber contains a substrate transfer mechanism 127, a camera 125, its drive system 126, an XY movable stage 124, a positioning mechanism consisting of a controller 123, and a pressurizing mechanism 118.
  • a joining mechanism consisting of a support arm 121, an ultrasonic vibration mechanism 1 19, a joining tool 120, and a controller 122, a chip supply (not shown) that transports the chip 13 1 to the joining tool A mechanism is provided.
  • the bonding chamber is evacuated once, and dried nitrogen gas is introduced to near atmospheric pressure to maintain a dry atmosphere at normal pressure.
  • the substrate 130 is mounted on a heat stage 128 having a built-in heating mechanism.
  • the tip 13 1 is chucked to the joining tool by vacuum suction.
  • the camera is inserted between the chip and the substrate, and the position of the Au bump on the chip and the Au pad on the substrate are checked while aligning with the XY movable stage.After moving the camera, the chip is lowered by the pressure mechanism. It moves and joins by applying pressure and ultrasonic waves.
  • the surface is physically etched with Ar ions.
  • Chip side This greatly improves the bondability with the Au bump, and provides a highly reliable, high-strength joint.
  • the atmosphere in the joining chamber is a dry, normal-pressure nitrogen gas atmosphere with a low water content, the joining performance is not impaired, and the chips can be chucked by the vacuum suction method. Since they can be used for a long life without causing adhesion, mass-produced processes and equipment can be realized, and highly reliable bonding between the chip and the carrier substrate can be achieved.
  • an ultra-high pin count or high-speed LSI chip can be housed in a compact, and the chip performance can be maximized.
  • a semiconductor package having a highly reliable connection portion can be provided by using a low-cost organic carrier substrate.
  • the present invention provides an Au bump / Au pad or an Au bump, a flip-chip bonding method of an Au bump capable of producing the semiconductor package by a process with high productivity, and a bonding apparatus for realizing the method. can do.

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Abstract

A semiconductor chip is firmly bonded to an organic substrate through cleaned Au bumps in an atmosphere where moisture is little. Each Au bump has a diameter of 300 νm or less, a height of 50 νm or above and a ratio of the height to the diameter of 1/5 or above, and is reduced in strain.

Description

明 細 書  Specification
半導体パッケージ及びそれにおけるフ リ ップチップ接合方法 技術分野  Semiconductor package and flip-chip bonding method therefor
本発明は、 L S I チップ等の半導体チップを有機材料のキャ リ ア基板 に搭載した構造の半導体パッケージに関する。 背景技術  The present invention relates to a semiconductor package having a structure in which a semiconductor chip such as an LSI chip is mounted on a carrier substrate made of an organic material. Background art
従来において、 半導体チップをフ リ ップチップ方式で基板に接続する 方式と して、 半田バンプを使う方式が C 4技術と して知られている。 チ ップ側の A 1 電極パッ ド上にバリ アメタルを介して半田バンプを形成し 基板側の接続端子には半田ぬれ性のよい A uめっ きを施し、 フラ ックス レスで非酸化性雰囲気中で半田を リ フ ローして接合する方法である。 基 板がセラ ミ ックの場合は気密封止して使用 し、 基板が有機基板の場合は チップと樹脂の間に熱膨張率を調整した樹脂とシリ コ ンのコ ンパゥン ド を充填して半田接合部の信頼性を上げて使用 している。  Conventionally, as a method of connecting a semiconductor chip to a substrate by a flip chip method, a method using solder bumps is known as C4 technology. Solder bumps are formed on the A1 electrode pad on the chip side via a barrier metal, and the connection terminals on the board side are plated with Au with good solder wettability to achieve a fluxless, non-oxidizing atmosphere. This is a method in which solder is reflowed and joined. If the substrate is a ceramic substrate, use it in a hermetically sealed state.If the substrate is an organic substrate, fill it with a resin and silicon compound whose thermal expansion coefficient is adjusted between the chip and resin. Used with increased reliability of solder joints.
一方、 半田を使わない A uバンプ A uパッ ドのフ リ ップチップ接合 と して、 以前から熱圧着法や超音波併用熱圧着法が知られている。 従来 から行われている熱圧着の条件は、 加熱温度 3 5 0 °C, 荷重 1 5 0 〜 2 5 0 g Zバンプで、 バンプ数 5 0個未満レベルのチップが接合されて いる。 ま た、 超音波併用熱圧着法においては、 加熱温度が 2 0 0 °C , 荷 重 3 0 0 gで、 6バンプ程度のチップが接合されている。 いずれの場合 も、 キャ リ ア基板はセラ ミ ック製である。 熱圧着法では、 加熱温度を上 げることで荷重を下げているが、 それでも 1 5 0 g Zバンプを必要と し ている。 ま た、 超音波併用熱圧着では加熱温度を 2 0 0 °Cに下げている が、 荷重が 3 0 0 g Zバンプと高い。 これは、 A u Z A u を大気中で確 実に接合するために種々検討されて見出された条件で、 これ以下の温度 や荷重条件では接合が不安定になるため、 実際の製品組立てには適用で きない。 上記の両圧着法では、 A uバンプの圧着形状が、 代表的な寸法 と して厚さ 1 5 ~ 2 5 t m , 直径 1 5 O ^ m以上の大き く 潰れた形状の 接合部となる。 On the other hand, thermocompression bonding and thermocompression bonding using ultrasonic waves have been known as flip chip bonding of Au bumps and Au pads without using solder. Conventional thermocompression bonding conditions are a heating temperature of 350 ° C, a load of 150 to 250 g Z bumps, and chips with less than 50 bumps are bonded. In addition, in the thermocompression bonding method using ultrasonic waves, a chip having a heating temperature of 200 ° C., a load of 300 g and approximately 6 bumps is bonded. In each case, the carrier substrate is made of ceramic. In the thermocompression bonding method, the load is reduced by increasing the heating temperature, but it still requires 150 g Z bumps. In addition, the heating temperature is reduced to 200 ° C in thermocompression bonding with ultrasonic waves. However, the load is as high as 300 g Z bump. This is a condition that has been studied and found in order to reliably join AuZAu in the atmosphere.Because the joining becomes unstable at lower temperatures and load conditions, it is not suitable for actual product assembly. Not applicable. In both of the above crimping methods, the crimped shape of the Au bump is a junction having a shape that is largely crushed with a typical size of 15 to 25 tm in thickness and a diameter of 15 O ^ m or more.
ま た、 従来の他の A uバンプノ A uパッ ド接続法と して、 両者の間に 導電性樹脂を接着剤に用いて加熱圧着する接続方法が知られている。 こ の方法では、 チップと基板間に樹脂を充填して固める こ と によ り 、 所定 の長期信頼性を得る構造となっている。  As another conventional Au bump connection method, there is also known a connection method in which a conductive resin is used as an adhesive and heated and pressed between the two. In this method, a predetermined long-term reliability is obtained by filling and solidifying the resin between the chip and the substrate.
最近の L S I チップは超微細配線技術の開発によ リ高集積化が進み、 チップの多ピン化あるいはチップシユ リ ンク に伴う狭パッ ドピッチ化が 急速に進んでいる。 これらのチップをパッケージに実装する場合、 従来 の周辺パッ ドの接合技術では 2 つの問題が発生する。 すなわち、 T A B やワイヤボンディ ング等では接合可能なパッ ドピッチが 4 0 mレべル に限界がある こと、 チップの端子からパッケージの外部端子までの配線 を最短ルー 卜で結線できないため、 配線イ ンダクタ ンスが増加して信号 伝送に遅れを生じ、 処理速度が低下することの 2 つである。  Recent LSI chips are becoming more highly integrated due to the development of ultra-fine wiring technology, and the number of pins in the chip and the narrower pad pitch associated with the chip link are rapidly progressing. When mounting these chips in a package, there are two problems with the conventional peripheral pad bonding technology. In other words, in the case of TAB or wire bonding, the bondable pad pitch is limited to a level of 40 m, and the wiring from the chip terminal to the external terminal of the package cannot be connected with the shortest route. And delay in signal transmission due to the increase in the speed, resulting in a decrease in processing speed.
これに対処する方法が、 チップの電極端子をチップ全面にェリ ァ状に 配置して実装する方法である。 従来の大型計算機などの分野で既に採用 されている半田バンプ接合法(C 4 )は、 上記 2 つの問題を解決できるも のの、 半導体パッケージに適用する場合には半田付け温度の点で問題が 発生する。 すなわち、 大型計算機ではチップの半田付け材料に、 その後 の階層半田付けを行う必要性から高融点半田 (融点 3 0 0 °Cの 9 5 P b 一 5 S n半田) を用いている。 一般に半田付け温度は、 半田の融点よ り 約 5 0 °C程度高い温度が適するため、 基板材料がセラ ミ ッ クではなく 有 機材料の場合には、 基板の熱劣化のためにこの高融点半田を使う ことが できない。 も し 2 0 0 °C〜 2 4 0 °Cの範囲に固相温度をもつ半田を用い た場合、 半導体パッケージを配線基板に搭載する共晶半田付け工程で、 パッケージ内部の半田接合部が部分的に再溶融して断線不良が発生する といった問題が発生する。 すなわち、 半導体パッケージの内部接続では、 2 5 0 °C以下の低い接続温度で、 2 5 0 °C以上の耐熱性を持つ接続部が 実現されなければならないのである。 A method to cope with this is to mount the electrode terminals of the chip by arranging them in an elliptical manner over the entire surface of the chip. The solder bump bonding method (C 4), which has already been adopted in the field of conventional large computers, can solve the above two problems, but when applied to semiconductor packages, there is a problem in terms of soldering temperature. appear. In other words, large-scale computers use high-melting-point solder (95 Pb-15Sn solder with a melting point of 300 ° C) because of the necessity of performing subsequent layer soldering for the chip soldering material. Generally, the soldering temperature is higher than the melting point of the solder. Since a temperature as high as about 50 ° C is suitable, if the substrate material is not ceramic but an organic material, the high melting point solder cannot be used due to thermal deterioration of the substrate. If solder having a solidus temperature in the range of 200 ° C to 240 ° C is used, the solder joints inside the package will be partially removed during the eutectic soldering process of mounting the semiconductor package on the wiring board. Problems such as re-melting and defective disconnection occur. In other words, in the internal connection of the semiconductor package, a connection part having a heat resistance of 250 ° C. or more must be realized at a low connection temperature of 250 ° C. or less.
この要求に適する接合法と して、 A uバンプを用いるフ リ ップチップ 接合法がある。 この接合法は、 高融点で接合性に優れる A u をバンプ形 状に して加熱あるいは超音波を併用 して固相で圧着する方法であるため、 低い接合温度で耐熱性のある接合部を得る ことが可能なのである。 しか し、 従来の A uバンプ接合法は 1 バンプ当 り の接合荷重が 3 0 0 gも必 要であ り 、 実際に 1 0 0 から 2 0 0 0バンプ程度のチップを考えるとチ ップに加える荷重が 3 0 〜 6 0 0 k g とな り 、 加圧ツールの片当 り等に よるチップの欠けや割れの発生が大きな問題となる。 チップに印加可能 な最大荷重は経験的に約 2 0 〜 4 0 k g程度と考え られるため、 1 バン プ当 り の接合荷重が 2 0 〜 8 0 gの条件で信頼性の高い接合を行えなけ れば、 実際の適用が困難である。 従来の熱圧着法で接合温度を上げられ れば低い荷重条件で信頼性のある接合が可能であるが、 基板が有機材料 であるため熱損傷の観点から、 加熱温度を耐熱性のあるポリ イ ミ ドでも 2 5 0 °C、 エポキシ系では 2 0 0 °C以上に上げられない。 低い加熱温度 と比較的低い荷重で信頼性のある接合を行える超音波併用熱圧着法では、 信頼性のある接合部を得るためには高い超音波エネルギーが必要であ り 、 超音波振動によ ってチップを損傷するという問題がある。 ま た、 加熱圧 着と超音波圧着のいずれも接合後のバンプ圧着形状が著し く 潰れた形状 となるため、 チップシュ リ ンク によ リノ ッ ドピッチが 2 0 0 μ m程度ま で狭ピッチ化して く ると、 バンプ変形によ る隣接パッ ドとの短絡が問題 となる。 同時に、 バンプ間の空隙が高さ 2 0 μ m程度で隣接間隔が 5 0 μ m程度となるため、 樹脂を充填する場合にボイ ドが発生し易く なつて アンダーフ ィルの充填が難し く な リ 、 パッケージと しての信頼性が低下 するという問題もある。 As a bonding method suitable for this requirement, there is a flip-chip bonding method using Au bumps. This bonding method is a method in which Au, which has a high melting point and excellent bonding properties, is formed into a bump shape and pressed in a solid phase using heating or ultrasonic waves. You can get it. However, the conventional Au bump bonding method requires a bonding load of 300 g per bump, and a chip of about 100 to 2000 bumps is actually considered. The load applied to the tool is 30 to 600 kg, and chipping or cracking of the chip due to one-sided contact of the press tool becomes a serious problem. Since the maximum load that can be applied to the chip is empirically estimated to be about 20 to 40 kg, reliable bonding must be performed under the condition that the bonding load per bump is 20 to 80 g. If so, practical application is difficult. If the bonding temperature can be increased by the conventional thermocompression bonding method, reliable bonding can be achieved under low load conditions. The temperature cannot be raised to more than 250 ° C even for mid-air and 200 ° C for epoxy. Ultrasonic thermocompression bonding, which enables reliable bonding with low heating temperature and relatively low load, requires high ultrasonic energy to obtain a reliable joint. Therefore, there is a problem that the chip is damaged. Heating pressure Both the bonding and the ultrasonic pressure bonding have a markedly crushed bump compression shape after bonding, so if the tip pitch is reduced to about 200 μm by chip shrink, A short circuit between adjacent pads due to bump deformation is a problem. At the same time, the gap between the bumps is about 20 μm in height and the adjacent space is about 50 μm, so that when filling with resin, voids are easily generated, and it is difficult to fill the underfill. Another problem is that the reliability of the package is reduced.
これに対して A uバンプと導電性樹脂を用いる方法は、 接続条件と し て低い加熱温度 · 低い接合荷重で圧着する方法であるため、 バンプの変 形を小さ く して接続できる。 ま た、 接続工程でチップと基板間に予め樹 脂を充填してから圧着する方法であるため、 ボイ ド等の発生が無い良好 なパッケージを組み立てる ことが可能である。 しかし、 導電性樹脂の場 合は吸湿による体積膨張によつて導電性粒子の接触状態が悪く なり 、 抵 抗が経時的に増加するという信頼性上の問題がある。  On the other hand, the method using the Au bump and the conductive resin is a method of performing pressure bonding with a low heating temperature and a low bonding load as connection conditions, so that the connection can be performed with a small deformation of the bump. In addition, since a resin is filled between the chip and the substrate in advance in the connection step and then pressure-bonded, it is possible to assemble a good package free of voids and the like. However, in the case of a conductive resin, there is a reliability problem that the contact state of the conductive particles deteriorates due to volume expansion due to moisture absorption, and the resistance increases with time.
一方、 最近のパッケージコス ト低減策と して、 ゥ ェ一ハ段階でパッケ —ジに組み立てる方式のチップスケールパッケージが提案されている。 配線基板へのパッケージの実装は半田ポールバンプを介して接合する構 造が一般に採用されるが、 その半田接合部をアンダーフ ィルによる樹脂 補強なしで信頼性を確保する ことが、 パッケージの搭載実装コス トゃリ ペア性を確保する上で重要である。 そのためには、 S i チップの熱膨張 率と配線基板の熱膨張率の差によ って発生する熱歪みが半田接合部に集 中するのを防ぐため、 半田部以外で熱歪みが緩和される構造とする必要 がある。 このため、 B G Aパッケージでは有機キャ リ ア基板を用いる構 造が一般に採用されている。 しかし、 ゥェ一ハ状態でキャ リ ア基板と接 合すると、 キャ リ ア基板の熱膨張と S i ゥエーハとの熱膨張の差によ り ゥエーハ周辺の接合部にはゥエーハサイ ズに比例した大きな歪が発生す る。 発生する歪の大き さは接合温度に比例し、 バンプ高さ に反比例する。 従来の半田を介した接合では、 配線基板への実装における耐半田付け性 の観点からパッケージ組み立ての半田付け温度が必然的に高く な り 、 そ のため歪みが大き く なる ことと半田強度が弱いこ との理由から、 接合後 にワーク を室温に冷却 したと きにゥエ一ハ周辺の半田接合部に大きな歪 みが発生して破損して しま う という問題がある。 一方、 A uバンプを用 いた接合構造では、 吸着分子の離脱と界面拡散による接合性改善の点か ら従来技術における接合可能な加熱温度が 7 0 °C以上であ り 、 ま た 200 °C以下の低温では A uバンプの大幅な塑性変形が接合に不可欠な要素で ある ことから、 圧着後の形状をアスペク ト比 (高さ Z直径の比) と してOn the other hand, as a recent package cost reduction measure, a chip scale package that is assembled into a package at the wafer stage has been proposed. In general, a structure in which a package is mounted on a wiring board by bonding via a solder pole bump is adopted.However, it is necessary to ensure the reliability without reinforcing the solder joints with resin by underfill. It is important for ensuring cost repairability. To prevent this, the thermal strain generated by the difference between the coefficient of thermal expansion of the Si chip and the coefficient of thermal expansion of the wiring board is prevented from concentrating on the solder joint, so that the thermal distortion is reduced outside the solder. It is necessary to make the structure. For this reason, a structure using an organic carrier substrate is generally adopted for the BGA package. However, if the wafer is in contact with the carrier substrate in the wafer state, the difference between the thermal expansion of the carrier substrate and the thermal expansion of the Si substrate will occur. A large strain proportional to the size of the eaves is generated at the joint around the eaves. The magnitude of the generated strain is proportional to the junction temperature and inversely proportional to the bump height. With conventional soldering, the soldering temperature of the package assembly is inevitably high from the viewpoint of soldering resistance in mounting on the wiring board, which results in high distortion and low solder strength. For this reason, when the work is cooled to room temperature after joining, there is a problem that a large distortion is generated in the solder joints around the wafer and the solder joints are damaged. On the other hand, in the bonding structure using Au bumps, the bonding temperature in the conventional technology is 70 ° C or more in view of the improvement of the bonding property by desorption of adsorbed molecules and interface diffusion, and 200 ° C At the following low temperatures, large plastic deformation of Au bumps is an indispensable element for joining, so the shape after crimping is used as the aspect ratio (height Z diameter ratio).
1 Z 5以上に上げる ことが困難であった。 特に接合温度が 1 3 0 °C以下 では、 アスペク ト比が 1 ノ 1 0以下と著し く 低かった。 接合温度を仮に 7 0 °Cと した場合の接合体の熱歪みを第 1 9 図に示す構造モデルを用い て概算すると、 ゥエーハサイズが 8 イ ンチの場合、 S i の熱膨張率 α = 3 X 1 0— 6 Ζ Κとキャ リ アテープ基板の熱膨張率 α = 1 5 X 1 0 / Κ の差から、 ゥェ一ハ周辺のバンプ接合部に 0. 0 6 O mm のずれの発生が 確認できる。 このずれをバンプの変形と基板の変形と S i ゥエーハの変 形で吸収する こ とになる。 そこで、 この時の S i ゥエーハとキャ リ ア基 板間の歪みの分担は各部材の応力バランスから概算する。 各部材のヤン グ率は S i : 1 9 0 G p a , A uノ ンプ : 8 8 G P a , ポリ イ ミ ド基板It was difficult to increase to 1 Z 5 or more. In particular, when the junction temperature was 130 ° C. or lower, the aspect ratio was remarkably low, ie, 1-10. Using the structural model shown in Fig. 19, the thermal strain of the joined body when the joining temperature is assumed to be 70 ° C is roughly estimated.When the wafer size is 8 inches, the thermal expansion coefficient of Si is α = 3 X from 1 0- 6 Zeta kappa and calibration re Atepu difference in the thermal expansion coefficient α = 1 5 X 1 0 → / Κ substrate, the occurrence of deviation of 0. 0 6 O mm bump junction near © E one tooth You can check. This displacement is absorbed by the deformation of the bump, the deformation of the substrate, and the deformation of the Si / E wafer. Therefore, the strain sharing between the Si wafer and the carrier substrate at this time is roughly estimated from the stress balance of each member. The Young's modulus of each member is as follows: Si: 190 GPa, Au pump: 88 GPa, polyimide substrate
: 9 G p aであ り 、 断面比率は部材の厚みと A uバンプの空間体積比率 で決ま るから、 バンプ高さ を H、 A uバンプの上下の剪断方向のずれを Δとすると、 バンプの引張方向の主歪み ( ε ) は 2次元モデルで ε = ((Η2 + Δ2) 1 /2 - Η ) Ζ Ηと表わされ、 バンプ高さ と主歪みの関係は第 2 0図に示すよ う な曲線となる。 一方、 A uバンプの伸びは材質に依存 するものの、 めっ きあるいはポールボンディ ングで形成する場合には 3 ~ 6 %であ り 、 主歪みがこの値を超える条件では A uバンプが破断して しま う 。 すなわち、 接合温度 7 0 °Cの場合には、 十分な接合強度を有し ているバンプでも、 バンプ高さ 5 0 m以上が必要であ り 、 接合温度 2 0 0 °Cの場合にはバンプ高さ 8 O z m以上が必要である。 も しチップ や基板と A uバンプの接合強度が弱い場合には、 さ らに高いバンプ高さ が必要となる。 このため、 A uバンプ高さ を接合後の熱収縮で A uバン プが破損しない最小の高さ、 すなわち接合温度 7 0 °Cの場合でバンプ高 さ 5 0 μ mに した場合で圧着径 : 5 0 0 μ m以上となり 、 接合温度 200 °Cの場合でバンプ高さ 8 0 t mに した場合、 圧着径が 4 0 0 i m以上と なる。 このため、 圧着径のバラツキや形状のバラツキを考慮すると、 バ ンプピッチを 5 0 0 μ m以下に狭ピッチ化する こ とが困難であった。 発明の開示 : 9 Gpa, and the cross-sectional ratio is determined by the thickness of the member and the space-volume ratio of the Au bump. Therefore, if the height of the bump is H, and the shift in the shear direction above and below the Au bump is Δ, The principal strain in the tensile direction (ε) is expressed as ε = ((Η 2 + Δ 2 ) 1/2 -Η) Η で in the two -dimensional model, and the relationship between the bump height and the principal strain is The curve is as shown in Fig. 20. On the other hand, although the elongation of the Au bump depends on the material, it is 3 to 6% when it is formed by plating or pole bonding, and the Au bump breaks when the main strain exceeds this value. I will. In other words, when the bonding temperature is 70 ° C, the bump height must be 50 m or more even if the bump has sufficient bonding strength. A height of at least 8 O zm is required. If the bonding strength between the Au bump and the chip or substrate is weak, a higher bump height is required. For this reason, the Au bump height is the minimum height at which the Au bump is not damaged by thermal contraction after bonding, that is, the crimping diameter when the bump height is 50 μm when the bonding temperature is 70 ° C. : 500 μm or more, and when the bonding temperature is 200 ° C. and the bump height is 80 tm, the pressure bonding diameter is 400 im or more. For this reason, it has been difficult to reduce the bump pitch to 500 μm or less in consideration of the variation in the crimping diameter and the variation in the shape. Disclosure of the invention
本発明の目的は、 超多ピンあるいは高速動作の L S I チップ等の半導 体チップを収納してそのチップ性能を最大限に引 き出すこ とが可能で、 しかも内部接続部の耐熱性と信頼性の高い半導体パッケージを提供する ことにある。 ま た、 その半導体パッケージを実現するために必要な、 低 温プロセスと量産性と良好な歩留ま り を合わせ持つチップ Z基板間のフ リ ップチップ接合方法及び装置を提供する ことにある。  SUMMARY OF THE INVENTION It is an object of the present invention to accommodate a semiconductor chip such as an ultra-high-pin-count or high-speed LSI chip, and to maximize the performance of the chip. Another object of the present invention is to provide a highly reliable semiconductor package. Another object of the present invention is to provide a flip chip bonding method and apparatus between chip Z substrates which has a low temperature process, mass productivity, and a good yield, which are necessary for realizing the semiconductor package.
本発明の他の目的は、 ゥエーハレベルで実装する場合に、 ゥエー八と 有機キャ リ ア基板を接合した後の冷却過程で熱歪みによる接合部損傷の 問題を起さない実装構造であって しかもバンプピッチを小さ く できる実 装構造を提供し、 ゥエーハ段階での低コス 卜のパッケージ実装方法を提 供する こ と にある。 Another object of the present invention is to provide a mounting structure which does not cause a problem of joint damage due to thermal strain in a cooling process after bonding the organic carrier substrate to the substrate when mounting at an wafer level. Providing a mounting structure that can reduce the pitch, and providing a low-cost package mounting method at the wafer stage. To provide.
本発明による半導体パッケージの構造においては、 有機キヤ リ ア基板 と半導体チップが 5 0 μ m以上離れた状態で、 基板とチップが、 エリ ア 状に配置された A uバンプを中間材と して金属的に強固に接合され、 両 者の間隙に樹脂を充填した構造とする。 ま た、 本発明による接合方法に おいては、 フ リ ップチップ接合面の材料構成を A u Z A u と し、 その接 合表面の清浄度を規定し、 水分含有量が水蒸気分圧 : l O O P a以下で ある乾燥雰囲気中で加熱圧接あるいはスクラブや弱い超音波振動を加え て加熱圧接する。 この接合方法によ って、 上記本発明による半導体パッ ケージを製造する ことができる。  In the structure of the semiconductor package according to the present invention, with the organic carrier substrate and the semiconductor chip being separated by 50 μm or more, the substrate and the chip are formed by using Au bumps arranged in an area as an intermediate material. The structure is such that metal is firmly joined and the gap between the two is filled with resin. Further, in the bonding method according to the present invention, the material composition of the flip chip bonding surface is assumed to be AuZAu, the cleanliness of the bonding surface is specified, and the water content is determined by the water vapor partial pressure: l OOP Heat-weld or heat-weld by applying scrubbing or weak ultrasonic vibration in a dry atmosphere of a or less. According to this bonding method, the semiconductor package according to the present invention can be manufactured.
以下、 本発明の基となった本発明者の検討結果等について、 若干具体 的に述べる。  Hereinafter, the results of the study by the present inventors, which are the basis of the present invention, will be described in some detail.
一般に、 A uは強度が 1 4 〜 2 5 kg / 2 程度あ り 、 ま た加工硬化し ない材料であるため疲労寿命が半田材に比べて 1 桁以上長く 、 A uバン プでフ リ ップチップ接合できればパッケージの温度サイ クル信頼性が向 上する。 しかし、 A uバンプを著し く 潰さなければ十分な接合強度を持 つた信頼性のある接合部を得る ことができないため、 接合荷重や超音波 振動によるチップの損傷の問題や、 チップと基板間の間隙が狭く な り過 ぎるため樹脂の充填が十分に行えな く なるといつた問題がある。 このた め、 有機基板を用いる半導体パッケージでは A uバンプの適用が難しい。 一方、 A uや A g等の貴金属の接合においては、 超高真空中で表面を清 浄化すれば、 常温かつ低荷重の条件でバンプの変形を小さ く 抑えて圧着 できる。 しかし半導体パッケージの量産ライ ンに適用するには、 真空中 で清浄化後にチップと基板を位置合わせするハン ドリ ング機構とそのプ 口セスのタ ク 卜に問題があ り 、 量産性と生産コス トの点で実製品に適用 困難である。 問題となる理由は、 チップや基板を真空中でチヤ ッキング する手段が難しいことや、 位置合わせする機構部を真空排気可能な材料 で構成した場合の装置コス トが高いこと、 真空中で高速駆動すると可動 部が摩耗や凝着を起こ し易く 装置寿命が短いこと等である。 も し、 常圧 下という条件で真空中と同等な接合性を得る接合方法があれば、 上記問 題を解決できて、 チップと基板のハン ドリ ングを容易に行え、 各機構部 の駆動を高速で動作可能となる。 In general, Au has a strength of about 14 to 25 kg / 2 and is a material that does not harden due to work, so its fatigue life is at least one order of magnitude longer than that of solder materials. Bonding improves the package's temperature cycle reliability. However, if the Au bumps are not severely crushed, a reliable joint with sufficient joint strength cannot be obtained.Therefore, there is the problem of chip damage due to joining load and ultrasonic vibration, There is a problem when the gap between the holes becomes too narrow and the resin cannot be sufficiently filled. For this reason, it is difficult to apply Au bumps to a semiconductor package using an organic substrate. On the other hand, in the bonding of precious metals such as Au and Ag, if the surface is purified in an ultra-high vacuum, the bumps can be crimped under normal temperature and low load conditions with a small deformation of the bumps. However, when applied to mass production lines of semiconductor packages, there is a problem with the soldering mechanism that aligns the chip with the substrate after cleaning in a vacuum and the process of the process. Applied to actual products in terms of Have difficulty. Reasons for the problem are that it is difficult to check chips and substrates in vacuum, the cost of equipment is high when the alignment mechanism is made of a material that can be evacuated, and high-speed operation in vacuum Then, the moving parts are prone to wear and adhesion, and the life of the equipment is short. If there is a bonding method that achieves the same bonding properties as in a vacuum under normal pressure, the above problem can be solved, the chip and the substrate can be easily handled, and the driving of each mechanism is performed It can operate at high speed.
我々はこのよ う な考え方に基づき、 表面清浄状態と接合状態について、 種々の検討を行った。 第 1 2 図は、 接合雰囲気が大気中及び窒素中の場 合で、 A u蒸着膜に A uポールを 1 0 0 °Cの加熱温度で超音波接合した 時の接合結果を示す。 接合荷重は 5 0 gである。 横軸は超音波出力で、 縦軸は接合強度が 1 6 g以上となる割合を示す。 A u膜表面の処理は、 各雰囲気の場合とも、 未処理の場合とイオン照射して清浄化した場合の 接合結果をプロ ッ ト している。 ボンディ ング成功率 : 1 0 0 %が得られ る超音波出力は、 表面清浄化して窒素中で接合した場合に超音波出力 0 m Wすなわち荷重のみで接合できており 、 窒素中では清浄化しな く ても 1 . 4 m W で 1 0 0 %に達している。 一方、 大気中の場合は、 清浄化し てもボンディ ング成功率 : 1 0 0 %が得られるのは 1 5 m Wで、 清浄化 しない場合は 1 5 1 m Wが必要である。 すなわち、 清浄化しない面に窒 素中で接合する方が、 清浄化して大気中で接合するよ リ接合性が良い。 第 1 3 図は、 表面の汚れ状態をォージェ分析で調べた結果を示す。 未処 理の試料では明らかに有機物汚染や S汚染が顕著で、 表面の A u濃度も 3 3原子%と低い。 一方、 表面清浄化処理を施した試料は、 窒素あるい は大気に曝しても汚染レベルが未処理に比べて低く 、 表面の A u濃度も 5 5 〜 6 1 原子%と高いレベルを維持している。 以上のよ う に、 A u同 士の接合においては表面の汚染レベルだけで接合性が決ま るわけではな く 、 雰囲気ガスの影響が大きい。 We conducted various studies on the surface clean state and the bonding state based on this concept. FIG. 12 shows the bonding results when the Au pole was ultrasonically bonded to the Au deposited film at a heating temperature of 100 ° C. in the case where the bonding atmosphere was in the air or in nitrogen. The joining load is 50 g. The horizontal axis indicates the ultrasonic output, and the vertical axis indicates the ratio at which the bonding strength becomes 16 g or more. Regarding the treatment of the Au film surface, the bonding results are plotted for both the untreated and the cleaned by irradiation with ions in each atmosphere. Bonding success rate: 100% ultrasonic output is obtained. When the surface is cleaned and bonded in nitrogen, the ultrasonic output is 0 mW, that is, bonding can be performed only with load, and it cannot be cleaned in nitrogen. At least at 1.4 mW, it reaches 100%. On the other hand, in the atmosphere, a bonding success rate of 100% can be obtained even with purification at 15 mW, and if not, 151 mW is required. In other words, bonding in a nitrogen atmosphere to a surface that is not cleaned has better re-bonding properties than cleaning and bonding in the air. Figure 13 shows the results of an Auger analysis of the surface contamination. The untreated sample is clearly contaminated with organic matter and S, and the Au concentration on the surface is as low as 33 atomic%. On the other hand, the sample subjected to the surface cleaning treatment has a low contamination level even when exposed to nitrogen or the atmosphere, and maintains a high Au concentration of 55 to 61 atomic% on the surface as compared with the untreated one. ing. As above, A u In welding, the bonding properties are not determined only by the surface contamination level, and the influence of the atmospheric gas is large.
そこで次に、 雰囲気ガスの何が接合性を悪く しているかを調べるため 大気のガス分析を行い、 窒素以外の含有ガスの接合性に与える影響を検 討した。 第 1 4図は、 大気(空気)のガス組成を示す。 接合性に影響を与 えるガスと しては酸素及び水分が考え られる。 そこで、 これらのガスを 含む雰囲気を作製してその中で接合を行い、 接合性を比較した。 第 1 5 図は、 A r ガスに酸素や水分を含むガスと空気及び窒素雰囲気中で接合 した時の接合結果を示す。 斜線の部分がボンディ ング成功率 : 1 0 0 % が得られる超音波出力領域である。 酸素は全く 接合性に影響を与えてお らず、 水分が悪いことが分かる。 第 1 6 図は、 雰囲気ガス中の水分含有 量とボンディ ング成功率 1 0 0 %が得られる最小超音波出力の関係を示 す。 両者の間には明らかに相関関係が認められ、 水分含有量が 0 . 0 3 ~ 0 . 1 vo 1 %辺りから接合性が急速に悪く なつている。 すなわち、 雰囲 気中の水分含有量が 0 . 0 3 〜 0 . 1 vo l % 以下であれば、 表面清浄化処 理を行う こ とで、 接合温度 1 0 0 °C, 接合荷重 5 0 gの低温 · 低荷重条 件で、 A uポールと A uパッ ドを接合強度 1 6 g以上に圧着できる。 こ れらの結果から、 A uの接合においては、 接合雰囲気中の水分の管理が 非常に重要である ことが明らかである。 なお、 水分管理が十分ならば、 A u接合表面を A u濃度が 2 0原子%以上となるよ う に清浄化処理すれ ば十分な接合強度が得られる。  Therefore, next, we conducted atmospheric gas analysis to determine what atmospheric gas was deteriorating the bondability, and examined the effect of non-nitrogen-containing gases on the bondability. Fig. 14 shows the gas composition of the atmosphere (air). Oxygen and moisture can be considered as gases that affect the bondability. Therefore, an atmosphere containing these gases was created and bonding was performed in the atmosphere, and the bonding properties were compared. Fig. 15 shows the results of bonding when Ar gas was bonded to a gas containing oxygen or moisture in an atmosphere of air and nitrogen. The shaded area is the ultrasonic output area where the bonding success rate: 100% can be obtained. Oxygen did not affect the bonding at all, indicating that the moisture was poor. Fig. 16 shows the relationship between the water content in the atmospheric gas and the minimum ultrasonic output that gives a bonding success rate of 100%. There is a clear correlation between the two, and the water content is in the range of about 0.03 to 0.1 vo 1%, and the bondability rapidly deteriorates. That is, if the moisture content in the atmosphere is 0.03 to 0.1 vol% or less, a surface cleaning treatment is performed to obtain a bonding temperature of 100 ° C and a bonding load of 50 ° C. Under low temperature and low load conditions of g, the Au pole and Au pad can be crimped to a joint strength of 16 g or more. From these results, it is clear that control of moisture in the bonding atmosphere is very important in Au bonding. If the moisture control is sufficient, sufficient bonding strength can be obtained by cleaning the Au bonding surface so that the Au concentration becomes 20 atomic% or more.
この結果を応用すれば、 表面清浄化処理と水分を管理した雰囲気中で 接合する方法を組み合わせる ことによ り 、 A uバンプを形成したチップ を有機基板上の A uパッ ドあるいは A uバンプに、 荷重≤ 5 0 バン プ, 接合温度 : 1 0 0 〜 2 0 0 °Cの条件でバンプの変形を抑えて高強度 に接合する こ とが可能になる。 換言すれば、 表面清浄化と雰囲気を制御 した A uバンプ Z A uパッ ドの接合方法を適用する こと によって、 超多 ピンあるいは高速動作の L S I チップを収納してそのチップ性能を最大 限に引き出すことが可能で、 しかも接合部の長期信頼性が高いパッケ一 ジ構造を実現できる。 しかも、 その半導体パッケージを量産性よ く かつ 良好な歩留ま り で組立てることができる。 Applying this result, by combining the surface cleaning treatment and the bonding method in an atmosphere where moisture is controlled, the chip on which the Au bump is formed can be used as the Au pad or Au bump on the organic substrate. , Load ≤ 50 bumps, Bonding temperature: 100 to 200 ° C, suppresses bump deformation and provides high strength It becomes possible to join to. In other words, by applying an Au bump ZA u pad bonding method with controlled surface cleaning and atmosphere, it is possible to house ultra-high pin count or high speed operation LSI chips and maximize their chip performance. And a package structure with high long-term reliability of the joint can be realized. In addition, the semiconductor package can be assembled with good productivity and a good yield.
この方法によ って半導体パッケージを組立てて信頼性試験を行った結 果を第 1 7 図, 第 1 8図に示す。 第 1 7 図は、 A uバンプ高さ を種々変 えたパッケージの温度サイ クル試験結果を示す。 チップサイズは 5腿〜 1 0 mm角である。 バンプ高さ と破断寿命の間には明らかに相関が有り 、 実用上必要な寿命 1 0 0 0 回を超えるのはバンプ高さ約 5 Ο πι以上で ある。 ま た、 第 1 8 図は、 半田リ フ ローを繰り返 した場合のバンプ接合 強度と破断発生率の関係を調べた結果を示す。 バンプ強度が 2 0 gでは、 少ない確率ながら破断の発生が見られる。 従って、 パッケージの信頼性 の点から、 バンプ高さ : 5 以上、 バンプ強度 : 3 0 g以上が望ま しい。  Figures 17 and 18 show the results of a reliability test conducted by assembling a semiconductor package using this method. Fig. 17 shows the temperature cycle test results of packages with various Au bump heights. The tip size ranges from 5 thighs to 10 mm square. There is clearly a correlation between the bump height and the rupture life, and the practically required life of more than 100 times is about 5 Οπι or more in bump height. Fig. 18 shows the results of examining the relationship between the bump joint strength and the rate of breakage when solder reflow is repeated. At a bump strength of 20 g, fracture is observed with a small probability. Therefore, from the viewpoint of package reliability, it is desirable that the bump height is 5 or more and the bump strength is 30 g or more.
次に、 ゥェ一ハレベルでのキャ リ ア基板の接合を考える。 本発明によ る接合方法を適用すれば、 接合温度 7 0 °C〜 1 0 0 °Cにおいて、 第 2 1 図に示すよ う な小さな圧壊率で接合できる。 S i ゥエーハとキャ リ ア基 板間の歪みは、 第 1 9 図のモデル条件において約 6 0 mであ り 、 第 2 0図に示すよ う なバンプ高さ と主歪みの関係がある。 接合温度を 7 0 °Cと してバンプ高さ を 5 0 mとすると主歪みが約 3 %となり 、 1 3 〜 2 0 kg / mm2 の応力が発生する。 も し、 A uバンプの接合界面強度がこ の値よ り弱いと界面で破断して しま う ため、 接合強度は十分に高く して おく 必要がある。 従来では、 バンプ圧潰率を 5 0 %以上に上げないと十 分な接合強度が得られないため、 ノ ンプ高さ を 5 0 mにするためには、 バンプ径が 4 2 0 μ mとな り 5 0 0 μ mピッチ以下の実現が難しいが、 表面を清浄化して ドライ な雰囲気中でボンディ ングする方式を採用する ことで圧壊率 2 2 %, アスペク ト比 0. 5 2 で接合する ことができる。 このため、 バンプ高さ 5 0 mを圧着径 1 0 Ο μ ηιで実現することがで きるよ う になる。 すなわち、 2 0 0 μ mピッチのボンディ ングが可能と なる。 ま た逆に、 ノ ンプ径を 2 0 0 μ ηιと してバンプ高さ を 1 0 0 》1 とする ことで、 歪みを 0. 3 %に低減でき、 バンプ内の発生応力が 2. 6 kg/mm2 で弾性範囲の変形に抑え られるため、 接合部の破損の恐れが全 く 無く なる。 Next, consider the bonding of the carrier substrate at the wafer level. If the joining method according to the present invention is applied, joining can be performed at a joining temperature of 70 ° C. to 100 ° C. with a small crushing rate as shown in FIG. The strain between the Si wafer and the carrier substrate is about 60 m under the model conditions in FIG. 19, and there is a relationship between the bump height and the main strain as shown in FIG. When the bonding temperature is 70 ° C. and the bump height is 50 m, the main strain is about 3%, and a stress of 13 to 20 kg / mm 2 is generated. If the bonding interface strength of the Au bump is lower than this value, it will break at the interface, so the bonding strength must be sufficiently high. Conventionally, the bump crush rate must be increased to 50% or more. In order to obtain a bump height of 50 m, the bump diameter becomes 420 μm, making it difficult to achieve a pitch of 500 μm or less. By adopting a method of bonding in a clean and dry atmosphere, bonding can be achieved with a crush ratio of 22% and an aspect ratio of 0.52. For this reason, a bump height of 50 m can be realized with a crimping diameter of 10 μm μηι. That is, bonding at a pitch of 200 μm is possible. Conversely, by setting the bump diameter to 200 μηι and the bump height to 100 >> 1, the distortion can be reduced to 0.3% and the stress generated in the bump is 2.6. kg / mm 2 suppresses deformation within the elastic range, so there is no risk of breakage of the joint.
上記のよ う な検討に基づいて、 後で詳述するよ う な A u表面の清浄化 及び接合雰囲気の水分量に配慮した接合方法に係る本発明がなされた。 そ して、 本発明による接合方法によ って、 次のよ う な新規な各半導体パ ッケージが得られる。  Based on the above-described studies, the present invention has been made on a cleaning method for the Au surface and a bonding atmosphere in consideration of the water content of the bonding atmosphere, which will be described later in detail. Then, according to the bonding method of the present invention, the following novel semiconductor packages can be obtained.
1 ) 半導体チップの電極端子と有機基板の内部接続端子とが、 直径 300 μ ιη以下で高さ 5 0 μ ιη以上かつ高さ Ζ直径の比が 1 / 5以上である A uバンプを介して接合される半導体パッケージ。  1) The electrode terminals of the semiconductor chip and the internal connection terminals of the organic substrate are connected via an Au bump with a diameter of 300 μιη or less, a height of 50 μιη or more and a height ratio of 1/5 or more. Semiconductor package to be joined.
2 ) 半導体チップの複数の電極端子と、 有機基板においてこれら電極端 子と寸法的に同一に配列される複数の内部接続端子とが、 A uバンプを 介して接続され、 かつ有機基板の複数の外部接続端子が液相温度 1 9 0 °C以上の半田バンプで構成される半導体パッケージ。  2) The plurality of electrode terminals of the semiconductor chip and the plurality of internal connection terminals that are dimensionally identical to the electrode terminals on the organic substrate are connected via Au bumps, and the plurality of A semiconductor package whose external connection terminals are composed of solder bumps with a liquidus temperature of 190 ° C or higher.
3 ) 半導体チップと有機基板の複数の内部接続端子とが、 ピッチ 4 0 0 m以下の A uバンプを介してフ リ ップチップ接合され、 有機基板にお いて外部接続端子の領域と内部接続端子の領域がス リ ッ トによ って分割 され、 外部接続端子と内部接続端子がス リ ッ トを通る配線で結線される 半導体パッケージ。 3) The semiconductor chip and the plurality of internal connection terminals of the organic substrate are flip-chip bonded via Au bumps with a pitch of 400 m or less, and the area of the external connection terminal and the internal connection terminal on the organic substrate are connected. The area is divided by slits, and the external connection terminal and the internal connection terminal are connected by wiring passing through the slit Semiconductor package.
4 ) 半導体チップと、 有機基板においてエリ ア状に配置される複数の内 部接続端子とが、 A uバンプを介してフ ェイ スダウンで接合され、 内部 接続端子の領域と外部接続端子の領域が投影面上で重なる半導体パッケ ージ。  4) The semiconductor chip and the plurality of internal connection terminals arranged in an area on the organic substrate are joined face-down via Au bumps, and the area of the internal connection terminal and the area of the external connection terminal are connected. Is a semiconductor package that overlaps on the projection surface.
5 ) 電極端子を有し、 1 mm以下の間隙で配置される複数の半導体チップ と、 有機基板の複数の内部接続端子とが A uバンプを介して接続され、 有機基板の外部接続端子が液相温度 1 9 0 °C以上の半田バンプで構成さ れる半導体パッケージ。  5) A plurality of semiconductor chips having electrode terminals and arranged with a gap of 1 mm or less and a plurality of internal connection terminals of the organic substrate are connected via Au bumps, and the external connection terminals of the organic substrate are connected to the liquid. A semiconductor package composed of solder bumps with a phase temperature of 190 ° C or higher.
なお、 上記各半導体パッケージにおいては、 半導体チップと有機基板 の間に樹脂が充填される ことが好ま しい。 図面の簡単な説明  In each of the above semiconductor packages, it is preferable that a resin is filled between the semiconductor chip and the organic substrate. BRIEF DESCRIPTION OF THE FIGURES
第 1 図は、 本発明による半導体パッケージの断面構造の一実施例。 第 2 図は、 A uバンプ形状を示す図。  FIG. 1 is an embodiment of a sectional structure of a semiconductor package according to the present invention. FIG. 2 is a diagram showing an Au bump shape.
第 3 図は、 本発明による半導体パッケージの断面構造の他の実施例。 第 4図は、 本発明による半導体パッケージの断面構造の他の実施例。 第 5 図は、 第 4図の半導体パッケージに用いる有機キャ リ ア基板の平 面図。  FIG. 3 is another embodiment of the sectional structure of the semiconductor package according to the present invention. FIG. 4 is another embodiment of the sectional structure of the semiconductor package according to the present invention. FIG. 5 is a plan view of an organic carrier substrate used for the semiconductor package of FIG.
第 6 図は、 本発明によるマルチチップ半導体パッケージの断面構造の 一実施例。  FIG. 6 is an embodiment of a cross-sectional structure of a multi-chip semiconductor package according to the present invention.
第 7 図は、 本発明によるチップとキャ リ ア基板の接合方法を示す一接 合手順例。  FIG. 7 is an example of a joining procedure showing a joining method of a chip and a carrier substrate according to the present invention.
第 8図は、 第 7 図の接合方法を実現するための装置構成の一実施例。 第 9 図は、 本発明によるチップとキャ リ ア基板の接合方法の他の接合 手順例。 FIG. 8 is an embodiment of an apparatus configuration for realizing the joining method of FIG. FIG. 9 shows another joining method of a chip and a carrier substrate according to the present invention. Example procedure.
第 1 0図は、 第 9 図の接合方法を実現するための装置構成の一実施例 第 1 1 図は、 第 1 0 図の前処理室と接合室の装置構成の一実施例。 第 1 2 図は、 窒素及び大気の接合雰囲気が接合結果に与える影響を示 す実験結果。  FIG. 10 is an embodiment of an apparatus configuration for realizing the joining method of FIG. 9. FIG. 11 is an embodiment of an apparatus configuration of the pretreatment chamber and the joining chamber of FIG. Figure 12 shows the experimental results showing the effect of the nitrogen and atmospheric bonding atmosphere on the bonding results.
第 1 3 図は、 接合表面の汚れ状態を示すォージェ分析結果。  Fig. 13 shows Auger analysis results showing the contamination on the joint surface.
第 1 4図は、 大気雰囲気のガス組成。  Fig. 14 shows the gas composition in the atmosphere.
第 1 5図は、 各種接合雰囲気が接合結果に与える影響を示す実験結果 第 1 6 図は、 接合雰囲気の水分含有量が接合結果に与える影響を示す 実験結果。  Fig. 15 shows the experimental results showing the effect of various bonding atmospheres on the bonding results. Fig. 16 shows the experimental results showing the effect of the moisture content of the bonding atmosphere on the bonding results.
第 1 7 図は、 本発明による半導体パッケージの温度サイ クル試験結果 第 1 8 図は、 本発明による半導体パッケージの半田リ フ ロー繰返し試 験結果。  FIG. 17 is a result of a temperature cycle test of the semiconductor package according to the present invention. FIG. 18 is a result of a repeated solder reflow test of the semiconductor package according to the present invention.
第 1 9図は、 半導体パッケージのモデル。  Figure 19 shows a model of a semiconductor package.
第 2 0図は、 バンプ高さ と歪みの関係。  Figure 20 shows the relationship between bump height and distortion.
第 2 1 図は、 圧壊率と接合強度の関係。 発明を実施するための最良の形態  Fig. 21 shows the relationship between the crushing rate and the joint strength. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施例を図面を用いて詳細に説明する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第 1 図は、 本発明による半導体パッケージの断面構造を示す。 図にお いて、 半導体チップ 1 (以下チップ 1 と記す) の A 1 ま たは A u電極パ ッ ド 2 に A uバンプ 7 がポールボンディ ングによ って形成されている。 有機キャ リ ア基板は、 有機絶縁板 3 と、 有機絶縁板 3 の一方の表面に設 けられる内部接続端子 4 と、 一方の表面の裏面に設けられる外部接続端 子 5 と、 外部接続端子 5 の周囲の絶縁板表面を覆うめっ き レジス ト 6 か ら構成されている。 内部接続端子 4および外部接続端子 5 は C uめっ き あるいは C u箔を貼付けてェッチングする方法によつて形成され、 各接 続端子間は有機絶縁板 3 に設けたスルホールと配線によって電気的に結 線されている。 各接続端子には、 下地に N i や P dめっ きを施してから 最表面に A uめっ きが施されている。 ノ ッケージの組立ては、 キャ リ ア 基板の内部接続端子 4 に A uバンプ 8 をポールボンディ ングによって形 成し、 チップ 1 の A uバンプ 6 と位置合わせして A uバンプ同士が接す るよ う に搭載し、 その雰囲気を 1 P a以下に真空排気して 1 5 O 〜250 °Cに加熱し加圧接合を行っている。 荷重は 3 0 〜 8 0 g Zバンプであ り 、 バンプが潰れ過ぎないよ う に変位量制御を行って接合している。 FIG. 1 shows a sectional structure of a semiconductor package according to the present invention. In the figure, Au bumps 7 are formed on A 1 or Au electrode pads 2 of semiconductor chip 1 (hereinafter referred to as chip 1) by pole bonding. The organic carrier substrate includes an organic insulating plate 3, an internal connection terminal 4 provided on one surface of the organic insulating plate 3, an external connection terminal 5 provided on the back surface of one surface, and an external connection terminal 5 The plating resist covering the insulating plate surface around the It is composed of The internal connection terminals 4 and the external connection terminals 5 are formed by Cu plating or a method of attaching and etching Cu foil, and the connection terminals are electrically connected by through holes provided in the organic insulating plate 3 and wiring. It is connected to. Each connection terminal is provided with Ni or Pd plating on the base and then Au plating on the outermost surface. To assemble the knocker, the Au bumps 8 are formed on the internal connection terminals 4 of the carrier board by pole bonding, and are aligned with the Au bumps 6 of the chip 1 so that the Au bumps come into contact with each other. The atmosphere is evacuated to 1 Pa or less and heated to 15 O to 250 ° C to perform pressure bonding. The load is 30 to 80 g Z bump, and the joining is performed by controlling the amount of displacement so that the bump is not crushed too much.
第 2 図にポールボンディ ングによ って形成した初期の A uバンプ形状 を示す。 チップ側のポールバンプ形状 ( A ) は、 圧着径 D c が 1 1 0 土 1 0 m , キヤ ビラ リ ツールの先端面が接触していた肩の高さ H c が 2 5 ± 5 μ πι, バンプ中央の盛り 上がり 部分の直径 D hが 5 0 m, そ の部分の高さ H hが 5 0 土 1 0 mとなる よ う に放電やボンディ ング条 件とキヤ ビラ リ ツール形状を選択している。 接合強度は剪断強度で 8 0 g以上が得られている。 一方、 基板側のポールバンプ形状 ( B ) は、 チ ップ側よ りポールの変形を小さ く して肩の高さ H kが 4 0 ± 1 0 m程 度と高く なる条件で接合している。 この場合のポールボンディ ングでは、 接合性を上げるためボンディ ングの直前に基板の接合端子表面をスパッ タ ク リ ーニングしている。 接合強度は剪断強度で 5 0 g以上を得ている。 この両者のバンプを圧着した後の形状は、 バンプ中央の盛り上がった部 分でバンプ同士が金属的に接合した形状となるよ う にバンプの圧壊量を 変位量制御でコ ン トロールして接合している。 接合されたバンプ柱で最 も く びれた部分はバンプ同士の接合部分に形成され、 強度の点でもその 接合界面がもっとも低く なっている。 圧着後のチップ/基板間の高さ H は 7 0 ± 1 0 m程度が得られ、 圧着後は大気中に取り 出 して基板にダ ム 1 9 を形成し、 流動性の高い樹脂 9 を流し込んで硬化させ、 最後に外 部接続端子に半田バンプ 1 0 を形成してパッケージを完成している。 本実施例によれば、 次のよ う な効果が有る。 1 ) チップの A 1 電極パ ッ ドと有機キャ リ ア基板の内部接続端子間をフ リ ップチップ接合方式で 接続しているため、 多ピンの L S I チップであってもパッ ドをエリ ア状 に配置してパッ ドピッチを緩和して接合でき、 半導体パッケージに実装 することが可能となる。 2 ) チップと有機キャ リ ア基板間を最短距離で 電気的に接続する構造であるため、 伝送速度の早いパッケージを構成で き高速処理の L S I チップの性能を十分引 き出せるパッケージを実現で きる。 3 ) チップと基板間が 5 0 以上離れて接合されているため A uバンプ柱に発生する歪が小さ く なる。 4 ) チップと基板間の熱膨張 差による歪を A uバンプ柱の中央部で吸収する構造であるため最も弱い A 1 パッ ド A uバンプ接合界面に高い応力が加わらない。 5 ) A uが 半田に比べて高強度で疲労寿命が長く 、 パッケージ内接合部の温度サイ クル寿命が長い。 6 ) プリ ン ト配線基板にパッケージを搭載した場合に、 外部接続端子が配線基板と同じ熱膨張率を持つ有機キャ リ ア基板上に形 成されているため両者を接合している半田バンプには大きな熱歪が発生 しない。 7 ) 3 ) ~ 6 ) によ り 、 パッケージの内部及び外部接合部の温 度サイ クル信頼性が著し く 高く なる。 ま た、 新しい接合組立てプロセス の採用によ って接合荷重が小さい条件で高強度の接合が可能となるため、 接合プロセスにおけるチップ損傷の危険性が減少し、 歩留ま リ の高い実 装プロセスを実現できる。 すなわち、 高速で超多ピンの L S I チップを、 性能を損なう ことなく 、 信頼性の高い半導体パッケージに高い歩留ま リ で実装できる。 Fig. 2 shows the initial Au bump shape formed by pole bonding. The tip-side pole bump shape (A) has a crimp diameter D c of 110 soil 10 m, a shoulder height H c at which the tip surface of the kyabila tool is in contact is 25 ± 5 μπι, Select the discharge and bonding conditions and the shape of the drilling tool so that the height Dh of the raised part at the center of the bump is 50 m and the height Hh of that part is 50 m at 10 m. ing. The bonding strength is 80 g or more in shear strength. On the other hand, the shape of the pole bump on the substrate side (B) is such that the deformation of the pole is smaller than on the chip side and the shoulder height Hk is as high as about 40 ± 10 m. I have. In pole bonding in this case, the bonding terminal surface of the board is sputter-cleaned immediately before bonding in order to improve the bondability. The bonding strength is 50 g or more in shear strength. The shape of both bumps after crimping is controlled by controlling the amount of crushing of the bumps by controlling the amount of displacement so that the bumps are metallically joined at the raised portion at the center of the bumps. ing. The most constricted part of the joined bump pillars is formed at the joint between the bumps, and in terms of strength, The bonding interface is the lowest. After the crimping, the height H between the chip and the substrate is about 70 ± 10 m.After the crimping, it is taken out into the atmosphere to form a dam 19 on the substrate, and the resin 9 with high fluidity is removed. It is poured and cured, and finally, solder bumps 10 are formed on the external connection terminals to complete the package. According to the present embodiment, the following effects are obtained. 1) Since the A1 electrode pad of the chip and the internal connection terminal of the organic carrier substrate are connected by the flip-chip bonding method, the pads are arranged in an area even for multi-pin LSI chips. By arranging, the pad pitch can be reduced and bonding can be performed, and it can be mounted on a semiconductor package. 2) Since the chip and the organic carrier substrate are electrically connected at the shortest distance, a package with a high transmission speed can be configured, and a package that can fully exploit the performance of high-speed processing LSI chips can be realized. . 3) Since the chip and the substrate are bonded at a distance of 50 or more, the distortion generated in the Au bump pillars is reduced. 4) Due to the structure that absorbs the strain due to the difference in thermal expansion between the chip and the substrate at the center of the Au bump pillar, high stress is not applied to the weakest A1 pad Au bump bonding interface. 5) Au has higher strength and longer fatigue life than solder, and has a longer temperature cycle life at the junction in the package. 6) When the package is mounted on a printed wiring board, the external connection terminals are formed on an organic carrier substrate that has the same coefficient of thermal expansion as the wiring board. Does not generate large thermal strain. 7) According to 3) to 6), the temperature cycle reliability of the internal and external junctions of the package is significantly improved. In addition, the adoption of a new joining assembly process enables high-strength joining under conditions where the joining load is small, reducing the risk of chip damage during the joining process and increasing the yield rate of the mounting process. Can be realized. In other words, a high-speed, ultra-high-pin-count LSI chip can be produced in a highly reliable semiconductor package without deteriorating its performance. Can be implemented with
さ らに、 本実施例によれば、 フ ェイスダウンで接続がチップ投影エリ ァ内で完了するため、 複数のチップを近接して実装できる。 従って、 マ ルチチップパッケージにおいては、 ノ ッケージサイズを大幅に小型化で きる。 また、 パッケージ内の接合部の耐熱性が従来の A u ワイヤポンデ ィ ング方式のパッケージと同 じであるため、 従来と同じ半田リ フ ロープ 口セスで配線基板への実装が可能である。  Further, according to the present embodiment, since the connection is completed within the chip projection area by the face down, a plurality of chips can be mounted close to each other. Therefore, in a multi-chip package, the knock size can be significantly reduced. Also, since the heat resistance of the joints in the package is the same as that of the conventional Au wire bonding type package, it can be mounted on a wiring board with the same solder reflow opening as before.
第 3 図に、 本発明による他の実施例である半導体パッケージの断面構 造を示す。 図において有機キャ リ ア基板には、 開口部を設けたポリ イ ミ ドテープ 1 3 とパターニングされ同じ C uラン ドの表裏両面をそれぞれ 内部及び外部接続端子とする内部 · 外部兼用接続端子 1 4で構成される テープ基板が用いられている。 接続端子の両面は、 下地に N i めっ きが 施され、 最表面に A uめっ きが施されている。 開口部側の内部接続端子 には A uバンプ 1 6 が形成され、 L S I チップ 1 1 の A 1 ま たは A u電 極 1 2 の上に形成された A uバンプ 1 5 と接合されている。 A uバンプ の接合方法は次のとおり である。 まず基板側の A uバンプ表面を A r ス パッタ によ り清浄化して、 大気に曝さず気密で水蒸気分圧 1 0 0 P a以 下の乾燥した雰囲気の接合室に基板を搬入する。 A uバンプを形成した チップは真空室で加熱して吸着水分を脱離させて接合室に搬入する。 接 合室で両者の A uバンプを位置合わせしてチップを基板上にフ ェイスダ ゥンで搭載し、 チップ側から接合ツールで加熱加圧し、 5 〜 1 0 mの 数回のスクラブまたは超音波振動をかけて接合する。 このと き、 変形量 制御によ り A uバンプの過大な圧壊を防ぎ、 チップ Z基板間の空隙を 5 0 m以上確保している。 チップ Z基板間の間隙には樹脂 1 7 が充填 硬化された後、 基板の外部接続端子には鉛レスで液相温度 1 9 0 °C〜 2 3 0 °Cの半田バンプ 1 8が形成されている。 本パッケージでは、 チッ プとテープ基板の寸法が同 じに設計されている。 FIG. 3 shows a cross-sectional structure of a semiconductor package according to another embodiment of the present invention. In the figure, the organic carrier substrate is patterned with polyimide tape 13 with openings, and the internal and external connection terminals 14 are used as internal and external connection terminals on the front and back surfaces of the same Cu land. A tape substrate is used. On both sides of the connection terminals, Ni plating is applied to the base and Au plating is applied to the outermost surface. Au bumps 16 are formed on the internal connection terminals on the opening side, and are joined to Au bumps 15 formed on A 1 or Au electrodes 12 of the LSI chip 11. . The method of joining Au bumps is as follows. First, the Au bump surface on the substrate side is cleaned by an Ar sputter, and the substrate is carried into a bonding chamber in a dry atmosphere having a water vapor partial pressure of 100 Pa or less without being exposed to the air. The chip on which the Au bumps are formed is heated in a vacuum chamber to remove adsorbed moisture, and then carried into the bonding chamber. The two Au bumps are aligned in the joining chamber, the chip is mounted on the substrate with a face-down, and heated and pressed with a joining tool from the chip side, and several scrubs or ultrasonic waves of 5 to 10 m are performed. Join by applying vibration. At this time, by controlling the amount of deformation, excessive crushing of the Au bump is prevented, and a gap between the chip Z substrate of 50 m or more is secured. The gap between the chip Z substrates is filled with resin 17 and cured.After that, the external connection terminals of the substrates are lead-free and the liquid phase temperature is 190 ° C or more. A solder bump 18 at 230 ° C. is formed. In this package, the dimensions of the chip and the tape substrate are designed to be the same.
本実施例によれば、 第 1 図の実施例と同様の理由によって、 超高速処 理の L S I チップを特性を損なわずに小型のパッケージに実装可能とな る。 同時に配線基板に搭載した場合のパッケージの内外接合部の長期信 頼性を十分高く できるという効果がある。 ま た、 マルチチップパッケ一 ジの場合のパッケージサイズを大幅に小型化できるという効果もある。 さ らに本実施例によれば、 チップとテープ基板の寸法が同じであ り、 接合個所が投影面上で全てチップ面の内部に収納された構造となってい る。 このため、 A uバンプを有する複数の半導体集積回路装置 (例えば L S I ) が 1 枚の S i ゥエーハ上に形成されたものを、 複数のパッケ一 ジ分のパターンが形成されたテープ基板に搭載して実装し、 半田バンプ 形成後の最終工程で切断分離する ことによ り複数のチップサイズパッケ —ジを一括して組み立てる こ とが可能となり 、 生産コス トを大幅に低減 できる。 なお、 詳細な製法は第 1 図の実施例と同様である。  According to this embodiment, for the same reason as in the embodiment of FIG. 1, it is possible to mount an LSI chip for ultra-high-speed processing in a small package without deteriorating the characteristics. At the same time, there is an effect that the long-term reliability of the internal and external junctions of the package when mounted on a wiring board can be sufficiently enhanced. Another advantage is that the package size in the case of a multi-chip package can be significantly reduced. Furthermore, according to the present embodiment, the chip and the tape substrate have the same dimensions, and the joining portion is entirely housed inside the chip surface on the projection surface. For this reason, a plurality of semiconductor integrated circuit devices (for example, LSIs) having Au bumps formed on a single Si wafer are mounted on a tape substrate on which patterns for a plurality of packages are formed. By mounting and mounting in a final step after the formation of the solder bumps, it is possible to assemble a plurality of chip-size packages at once, and the production cost can be greatly reduced. The detailed manufacturing method is the same as that of the embodiment shown in FIG.
ま た、 本実施例は 2 0 0 ピン以下の場合に好適である。  Further, the present embodiment is suitable for the case of 200 pins or less.
第 4図に、 本発明による他の半導体パッケージの断面構造を示す。 ま た第 5図は、 第 4図に用いられている有機キヤ リ ア基板の平面図を示す。 有機キャ リ ア基板は、 ポ リ イ ミ ドテープ 2 3 と、 そのテープに接着され てエッチングされた C u箔パターンで構成されるテープ基板である。 ポ リ イ ミ ドテープには、 外部接続端子部および内部接続端子領域 2 4 と外 部接続端子領域 2 5の境界に開口部が設けられている。 後者の開口部で あるスリ ッ ト 2 9 は、 内部接続領域のテープの歪が外部接続領域に伝わ らない程度の大きさである。 C u箔パタ一ンは内部 · 外部接続端子 2 6 , 2 7 と、 スリ ッ ト 2 9 を通る配線部 2 8 で構成されている。 テープ基板 の A uめっ きされた内部接続端子 2 6 とチップ 2 1 の電極端子 2 2 に形 成された A uバンプ 3 0 は金属的に接合されている。 接合方法は、 まず テープ基板の内部接続端子表面を A r イオンでスパッタ して清浄化し、 水蒸気分圧 1 0 0 P a以下の乾燥した雰囲気中でチップを位置決め して 搭載し、 全体の温度を 2 0 0 °Cに加熱してチップ側から加圧と超音波振 動を加えて圧着している。 外部接続端子領域のチップ搭載側には、 パッ ケージを実装する配線基板と同等の熱膨張率を有する補強板 3 1 を接着 剤 3 2で貼付けている。 チップと基板間には流動性の高い樹脂 3 3 を流 し込んで固めている。 樹脂を注入すると きは、 ス リ ッ ト部 2 9 から樹脂 が洩れださないよ う に下当て材を用い、 ス リ ッ ト部も樹脂で固めている。 従ってスリ ッ 卜を通る配線は樹脂で覆われて保護される。 FIG. 4 shows a cross-sectional structure of another semiconductor package according to the present invention. FIG. 5 is a plan view of the organic carrier substrate used in FIG. The organic carrier substrate is a tape substrate composed of a polyimide tape 23 and a Cu foil pattern adhered to the tape and etched. The polyimide tape has an opening at the boundary between the external connection terminal area and the internal connection terminal area 24 and the external connection terminal area 25. The slit 29, which is the latter opening, is large enough that the distortion of the tape in the internal connection area is not transmitted to the external connection area. The Cu foil pattern is composed of internal and external connection terminals 26 and 27 and a wiring portion 28 passing through a slit 29. Tape board The Au bumps 30 formed on the Au-plated internal connection terminals 26 and the electrode terminals 22 of the chip 21 are metallically joined. The bonding method is as follows. First, the surface of the internal connection terminals of the tape substrate is cleaned by sputtering with Ar ions, the chip is positioned and mounted in a dry atmosphere with a water vapor partial pressure of 100 Pa or less, and the overall temperature is reduced. Heating is performed at 200 ° C, and pressure is applied from the chip side and ultrasonic vibration is applied to perform pressure bonding. On the chip mounting side of the external connection terminal area, a reinforcing plate 31 having the same thermal expansion coefficient as the wiring board on which the package is mounted is adhered with an adhesive 32. Highly fluid resin 33 is poured between the chip and the substrate and solidified. When injecting the resin, an underlining material is used so that the resin does not leak from the slit portion 29, and the slit portion is also solidified with the resin. Therefore, the wiring passing through the slit is covered and protected by the resin.
本実施例によれば、 電極端子数が 1 5 0 ピンを超えるよ う な超多ピン のし S I チップをテープ基板の端子に高融点で疲労寿命が長く 耐環境性 の高い部材で確実にフ リ ップチップ接合できるため、 超多ピン · 超高速 処理の L S I チップを、 コス トが安く しかも配線基板実装状態での信頼 性が高いプラスチックパッケージに組み立てる ことが可能となる。 ま た、 本実施例によるパッケージを配線基板に搭載したと き、 チップとキヤ リ ァ基板間の熱膨張差による熱歪がス リ ッ ト部で遮断されて、 外部接続端 子領域の熱膨張率がほぼ配線基板の熱膨張率と同じになる。 従って、 半 田バンプ接続部に大きな熱応力が発生せず、 半田バンプ接続部の温度サ ィ クル寿命が非常に長く なる。  According to the present embodiment, an ultra-high number of electrode terminals having more than 150 pins are used, and the SI chip is securely connected to the terminals of the tape substrate with a material having a high melting point, a long fatigue life and a high environmental resistance. Because it can be rip-chip bonded, it is possible to assemble an ultra-high-pin-count, ultra-high-speed processing LSI chip into a plastic package with low cost and high reliability when mounted on a wiring board. Further, when the package according to the present embodiment is mounted on a wiring board, thermal distortion due to a difference in thermal expansion between the chip and the carrier board is cut off by the slit portion, and thermal expansion of the external connection terminal area is prevented. The rate is almost the same as the coefficient of thermal expansion of the wiring board. Therefore, no large thermal stress is generated in the solder bump connection part, and the temperature cycle life of the solder bump connection part becomes very long.
第 6 図は、 本発明を複数のチップが 1 mm以下の間隙で近接配置される マルチチップパッケージに適用 した実施例のパッケージ断面構造を示す。 図において、 モジュール基板 4 3 の各面に、 内部接続端子 4 4 と外部接 続端子 4 5 および配線パターンが形成されている。 内部接続端子には下 地に厚い N i めっ き 4 7 を施してその上に A uめっ き 4 8 を形成した A uノ ンプが作られている。 チップ 4 1 の A 1 電極パッ ド 4 2 には A u スタ ッ ドバンプ 4 6 がワイヤボンディ ング法で形成されている。 A uバ ンプ同士の接合は、 基板側の A uバンプ表面をスパッタク リ ーニングに よ リ清浄化し、 大気に晒さずに気密で乾燥した雰囲気ガスを充填した接 合室に搬送し、 チップ側の A uバンプは真空中で加熱処理して吸着水分 や有機物を除去し、 両者を位置合わせして対面させ、 加熱と加圧とスク ラブ振動を加えて接合している。 モジュール基板には複数のチップを接 合しており 、 チップノ基板間には樹脂 4 9 が充填されている。 モジュ一 ル基板の裏面には、 マザ一ボー ドと接続するための、 液相温度 1 9 0 °C 以上の半田バンプ 5 0が形成されている。 外部接続機構と して、 半田バ ンプに替えて リ ー ド端子に し、 リ ー ド端子をマザ一ボー ドに半田付けす る構造でも よい。 FIG. 6 shows a cross-sectional structure of an embodiment in which the present invention is applied to a multi-chip package in which a plurality of chips are closely arranged with a gap of 1 mm or less. In the figure, an internal connection terminal 44, an external connection terminal 45, and a wiring pattern are formed on each surface of the module substrate 43. Internal connection terminals Au bumps are made by applying thick Ni plating 47 on the ground and forming Au plating 48 on it. Au stud bumps 46 are formed on the A1 electrode pads 42 of the chip 41 by a wire bonding method. The bonding of Au bumps is performed by cleaning the surface of the Au bumps on the substrate side by sputter cleaning, transporting it to a bonding chamber filled with an air-tight and dry atmosphere gas without exposing it to the air, Au bumps are heat-treated in vacuum to remove adsorbed moisture and organic matter, are aligned and faced, and are joined by applying heat, pressure and scrub vibration. A plurality of chips are joined to the module substrate, and a resin 49 is filled between the chip substrates. Solder bumps 50 with a liquidus temperature of 190 ° C. or higher are formed on the back surface of the module substrate for connection to the motherboard. As an external connection mechanism, a structure in which a lead terminal is used instead of a solder bump and the lead terminal is soldered to a mother board may be used.
本実施例によれば、 モジュール基板とチッ プの接続が強度が高い A u バンプ同士の金属接合であるため、 内部接続部の温度サイ クル信頼性が 高いこと、 かつ耐熱性のある接合部であるためマザーポ一 ドへの半田付 けにおける加熱温度の制約がないという効果がある。 ま た、 モジュール 基板へのチップの搭載間隔をチップ同士が接する状態まで近接して実装 する ことができ、 モジュールの寸法を最小限まで小さ く する ことができ るという効果もある。  According to the present embodiment, since the connection between the module substrate and the chip is a metal joint between Au bumps having high strength, the temperature cycle reliability of the internal connection portion is high, and the connection portion having heat resistance is used. Therefore, there is an effect that there is no restriction on a heating temperature in soldering to a mother node. In addition, it is possible to mount the chips on the module substrate at close intervals so that the chips are in contact with each other, so that there is an effect that the dimensions of the module can be reduced to a minimum.
第 7 図は、 本発明による接合方法の接合手順を示す。 ポールワイヤポ ンディ ング法で形成した A uバンプは、 バンプ材質の A u純度が高く て 柔らかく 、 フ リ ップチップ接合の直前の工程でバンプ形成できるためバ ンプ表面の清浄度が高いという特徴を持つ。 このため、 両者の表面清浄 化処理を省略する ことができ、 大気圧下でキャ リ ア基板上にチップを位 置合わせして搭載し、 その状態で周囲の雰囲気を 1 0 0 P a以下に真空 に排気して加熱し、 バンプ表面に吸着している水分や有機物を離脱させ て加圧接合する。 このと き、 加圧と共に振幅 : 数〜十数 ^ mのスクラブ を複数回行えば、 あるいは超音波振動を施せば、 接合強度の向上が容易 に図れる。 チップの位置決めは大気中で接合装置に基板とチップをセ ッ 卜 して行い、 位置決め後は加圧治具でチップにバンプ当た り数 g以下程 度の荷重を加えておく 。 こ うすることで、 加圧時のチップと基板間の位 置ずれ発生を防止し、 真空雰囲気に晒す接合面積をできるだけ多く して 吸着物の離脱を促すこ とができるのである。 接合後は、 チップ付きの基 板を大気中に取り 出 し、 液状レジンをチップ 基板間に浸透させ気泡を 脱気後に加熱によってレジンを硬化させる。 その後、 キャ リ ア基板裏面 の A uめっ きされた外部接続端子にフラ ックスを塗布して半田ポールを 搭載し、 加熱によ り半田を リ フ ローして半田バンプを形成する。 複数の パッケージを 1 枚の基板で組み立てる場合は、 最後の工程と して、 パッ ケージを個別に切り離す切断加工を行って、 組立て工程を完了する。 第 8 図は、 第 7 図の接合方法を実現するための接合装置の一構成例を 示す。 図において、 真空排気のための上チャ ンバ一 5 4 と下チャ ンバ一 5 1 は 0 リ ング 6 1 を介して密着する。 上チャ ンバ一 5 4の中央部には、 チップ 6 8 に加圧を加えるための加圧治具兼真空フラ ンジ 5 5 がべロー ズ 5 6 を介して気密に一体化されている。 フランジの上部には、 支持ァ ーム 5 3 に固定されたシリ ンダー 6 2 が配置され、 そのピス トン 7 5 は フラ ンジに取り付けられてフ ラ ンジの上下動を制御している。 上チャ ン バーは、 フラ ンジの動きとは独立して上下動でき、 支持アームに取り付 けた駆動機構 6 3 によって制御している。 上チャ ンバ一とフ ラ ンジの相 対移動距離は 2 0 mm以上に設計しており 、 フラ ンジで半導体チップ 6 8 に低い荷重を加えている状態で上チャ ンバ一を上に引上げ、 位置確認力 メラ をチャ ンバ一内に揷入できる構造となっている。 A uバンプ 6 9 と A uパッ ド 7 1 が接触した状態で半導体チップ 6 8及びキヤ リ ァ基板 ― 7 0 を供給セ ッ トするヒー トステージ 5 7 は、 内部にヒータ 6 0 を備え、 さ らにステージを左右に微小量だけ駆動するためのステージ駆動機構 5 9 を備えている。 そ して、 ヒー トステージは移動と接合荷重を支える 役割を持つペアリ ング 5 8で支えられている。 真空排気する空間の大き さは、 チップと基板を収納できる最小の大きさ に設計しており 、 1 0 to rr以下までの真空排気時間が 2 0秒以下になるよ う に真空排気ポンプ 6 4 を選択している。 チャ ンバ一を大気圧に戻すリ ークガスには N 2 ガ ス 6 6 を用いている。 FIG. 7 shows a joining procedure of the joining method according to the present invention. Au bumps formed by the pole wire bonding method are characterized by high Au purity of the bump material, softness, and high cleanliness of the bump surface because bumps can be formed in the process immediately before flip chip bonding. For this reason, the surface cleaning treatment of both can be omitted, and the chip is placed on the carrier substrate under atmospheric pressure. Then, the surrounding atmosphere is evacuated to a vacuum of 100 Pa or less and heated, and moisture and organic substances adsorbed on the bump surface are separated and pressure-bonded. At this time, the bonding strength can be easily improved by performing scrubbing with an amplitude: several to several tens ^ m a plurality of times together with the pressurization, or by applying ultrasonic vibration. The chip is positioned by setting the substrate and chip in a bonding apparatus in the atmosphere, and after positioning, a load of about several g or less per bump is applied to the chip with a pressing jig. By doing so, displacement between the chip and the substrate during pressurization can be prevented, and the bonded area exposed to the vacuum atmosphere can be increased as much as possible to promote the detachment of the adsorbed material. After bonding, the substrate with the chips is taken out into the atmosphere, liquid resin is allowed to penetrate between the chip substrates, bubbles are removed, and the resin is cured by heating. After that, apply flux to the Au-plated external connection terminals on the back of the carrier board, mount the solder poles, and reflow the solder by heating to form solder bumps. If multiple packages are assembled on a single board, the final step is to cut the packages individually to complete the assembly process. FIG. 8 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG. In the figure, the upper chamber 54 and the lower chamber 51 for evacuation closely contact each other via the 0-ring 61. At the center of the upper chamber 54, a pressing jig / vacuum flange 55 for applying pressure to the chip 68 is hermetically integrated via a bellows 56. A cylinder 62 fixed to a support arm 53 is disposed above the flange, and the piston 75 is attached to the flange to control the vertical movement of the flange. The upper chamber can move up and down independently of the movement of the flange, and is controlled by a drive mechanism 63 attached to the support arm. The relative movement distance between the upper chamber and the flange is designed to be 20 mm or more. The structure is such that the upper chamber can be pulled up while a low load is applied to it, and the position confirmation force camera can be inserted into the chamber. The heat stage 57 for supplying and setting the semiconductor chip 68 and the carrier substrate 70 in a state where the Au bump 69 and the Au pad 71 are in contact with each other has a heater 60 inside. Further, a stage drive mechanism 59 is provided for driving the stage left and right by a small amount. The heat stage is supported by a pairing 58 that has the role of supporting movement and joining load. The size of the space to be evacuated is designed to be the smallest size that can accommodate the chip and the substrate, and the evacuation pump 64 is designed so that the evacuation time to 10 to rr or less is 20 seconds or less. Is selected. N 2 gas 66 is used as the leak gas for returning the chamber to atmospheric pressure.
本実施例によれば、 接合機構を真空チャ ンバ一の外に配置して接合試 料周辺のみを真空排気できる構造と しているため、 大気圧下で位置合わ せしてから接合に必要な真空雰囲気を得るまでの所要時間が大幅に短縮 され、 基板とチップの位置合わせ→真空排気→加圧接合→大気リ ーク と いった 1 回の接合工程を 1 分以内の時間で行う ことができるよう にな り 、 量産品の生産に本発明による接合方法を適用可能となる。 ま た、 加圧接 合過程で基板側から数 μ πι程度のスクラブをかけられるため、 低い荷重 で接合強度を上げる こ とが可能とな り 、 チップ損傷の可能性をさ らに低 減できるという効果もある。  According to the present embodiment, the joining mechanism is arranged outside the vacuum chamber so that only the periphery of the joining sample can be evacuated, so that it is necessary for the joining to be performed under atmospheric pressure before joining. The time required to obtain a vacuum atmosphere is greatly reduced, and a single bonding process such as alignment of substrate and chip → evacuation → pressure bonding → atmospheric leak can be performed in less than one minute. As a result, the joining method according to the present invention can be applied to mass production. In addition, since a scrub of several μπι can be applied from the substrate side during the pressure bonding process, the bonding strength can be increased with a low load, and the possibility of chip damage can be further reduced. There is also an effect.
第 9 図は、 本発明による接合方法の他の接合手順を示す。 めっ きによ リ形成する A uパッ ドあるいは A uバンプは、 数 / i m以上に厚く 形成す るとコス トの点で高価になるため、 1 μ ηι以下の厚さで製造する必要が ある。 一方、 A uめっ きが薄い場合、 パッ ドの A uの変形が非常に小さ く なるため表面の汚染レベルが接合に大き く 影響する ことになる。 この ため図の手順では、 基板側の A uパッ ド表面をスパッタ ク リ ーニングに よ り清浄化し、 チップ側の A uバンプ表面は真空中で加熱して吸着水分 を除去する処理のみ行っている。 両処理を行った後は、 大気に触れない 状態で水蒸気分圧が 1 0 0 P a以下の乾燥した空気、 あるいは、 N 2 ま たは A r を主体とするガス雰囲気でガス圧が 5 X 1 0 3〜 2 X 1 0 5 P a 以上の気密なチャ ンバ一に導入し、 基板はヒー トステージに載せ、 チッ プは加圧治具に真空吸着でチヤ ッキングし、 両者を位置合わせして加圧 し、 超音波振動あるいはスクラブを加えて圧着し接合する。 基板が複数 パッケージ分のパターンで構成されている場合は、 チップを順次供給し て接合を行う 。 接合後は大気に取り 出 し、 チップ Z基板間に樹脂を充填 • 硬化し、 基板側の外部接続端子に半田バンプを形成してから切断加工 を行い、 組立てを完了する。 FIG. 9 shows another joining procedure of the joining method according to the present invention. The Au pad or Au bump formed by plating is expensive in terms of cost if it is formed thicker than several ims, and must be manufactured with a thickness of 1 μηι or less. is there. On the other hand, if the Au plating is thin, the Au deformation of the pad is so small that the surface contamination level has a large effect on the bonding. this Therefore, in the procedure shown in the figure, the Au pad surface on the substrate side is cleaned by sputter cleaning, and the Au bump surface on the chip side is only heated in vacuum to remove adsorbed moisture. After performing both treatments, dry air with a partial pressure of water vapor of 100 Pa or less without contact with the air, or a gas atmosphere mainly composed of N 2 or Ar with a gas pressure of 5 X 1 0 3 was introduced into ~ 2 X 1 0 5 P a more airtight tea Nba one, the substrate is placed on heating preparative stage, chips were Chiya Kkingu by vacuum suction pressurizing jig, aligning and both And pressurize and apply ultrasonic vibration or scrub to bond. When the substrate is configured with a pattern for a plurality of packages, chips are sequentially supplied to perform bonding. After joining, the chip is taken out to the atmosphere, filled with resin between the chip Z board and hardened. Solder bumps are formed on the external connection terminals on the board side, and then cut to complete assembly.
第 1 0 図は、 第 9 図の接合方法を実現するための接合装置の一構成例 を示す。 装置の基本構成は、 基板のパッ ド表面を清浄化処理する前処理 室 8 1 , 半導体チップを真空加熱処理して後述の接合室に供給するチッ プ供給室 8 3 , 基板とチップを位置合わせして加圧 · 加熱してスクラブ あるいは超音波ボンディ ングする接合室 8 2 , 接合室からチップ付き基 板を取り 出す基板搬出室 8 6 , 各々気密な前処理室, 接合室, チップ供 給室及び基板搬出室に乾燥したガスを供給する ドライ ガス供給機構 8 5 , 各室を真空に排気する真空排気系 6 4 と前処理室に基板を供給する基板 供給機構 8 7 から成っている。 各室間はゲー トバルブ 8 8 , 8 9 , 9 0 で連結され、 基板あるいはチップの移送が行われる構造となっている。 乾燥ガスは、 空気, 窒素, アルゴンなど水蒸気分圧が 1 0 0 P a以下で あれば酸化性あるいは非酸化性を問わず、 いずれのガスでもよい。  FIG. 10 shows an example of the configuration of a joining apparatus for realizing the joining method of FIG. The basic configuration of the equipment consists of a pretreatment chamber 81 for cleaning the pad surface of the substrate, a chip supply chamber 83 for supplying a semiconductor chip with vacuum heating and supplying it to the bonding chamber described later, and aligning the substrate and the chip. And heating and bonding and scrubbing or ultrasonic bonding in a bonding room 82, a substrate unloading room 86 to take out a substrate with chips from the bonding room 86, airtight pretreatment room, bonding room, and chip supply room And a dry gas supply mechanism 85 for supplying dry gas to the substrate unloading chamber, a vacuum exhaust system 64 for evacuating each chamber to a vacuum, and a substrate supply mechanism 87 for supplying substrates to the pretreatment chamber. The chambers are connected by gate valves 88, 89, 90 to transfer substrates or chips. The drying gas may be any gas such as air, nitrogen and argon, as long as the partial pressure of water vapor is 100 Pa or less, regardless of oxidizing or non-oxidizing.
第 1 1 図は、 第 1 0 図の前処理室と接合室の装置構成を示す一実施例 である。 図において、 前処理室 1 0 0 には、 キャ リ ア基板 1 2 9 を A r イオンでスパッタ リ ングする機構が設けられている。 カソ一 ド電極 107 は装置と絶縁部材 1 0 8 によって電気的に絶縁されて配置され、 上部に アースと同電位のァノ一ド電極 1 0 6 が配置されている。 基板を力ソー ド電極上にセ ッ ト してチャ ンバ一内を真空に排気した後 A r ガスを導入 し、 各電極間に高周波電源 1 0 9 から直流成分を重畳した高周波電圧を 印加して、 電極間でグロ一放電を発生させる。 このとき A r ガスは電離 されてイオン化し、 直流電圧分によ って基板方向に加速され、 基板表面 を物理的にエッチングし、 清浄化が行われる。 清浄化後は窒素ガスを導 入し、 隣の接合室 1 1 6 と同じガス圧にする。 接合室には、 基板搬送機 構 1 2 7 , カメラ 1 2 5 とその駆動系 1 2 6 と X Y可動ステージ 1 2 4 と制御装置 1 2 3 から成る位置合わせ機構, 加圧機構 1 1 8 と支持ァー ム 1 2 1 と超音波振動機構 1 1 9 と接合ツール 1 2 0 と制御装置 1 2 2 から成る接合機構, 図にはないがチップ 1 3 1 を接合ツールまで搬送す るチップ供給機構が設けられている。 接合室は、 装置稼働時に一度真空 排気して乾燥した窒素ガスを大気圧近傍まで導入 し、 常圧の乾燥した雰 囲気が維持されている。 基板 1 3 0 は、 加熱機構が内蔵されたヒー トス テ一ジ 1 2 8上に搭載される。 チップ 1 3 1 は、 真空吸着によって接合 ツールにチヤ ッキングされる。 カメラはチップと基板の間に挿入され、 チップの A uバンプと基板の A uパッ ドの位置を確認しながら X Y可動 ステージで位置合わせし、 カメラ を移動した後に加圧機構でチップを下 に移動し、 加圧と超音波を加えて接合を行う。 FIG. 11 is an embodiment showing an apparatus configuration of the pretreatment chamber and the bonding chamber in FIG. 10. It is. In the figure, the pretreatment chamber 100 is provided with a mechanism for sputtering the carrier substrate 129 with Ar ions. The cathode electrode 107 is electrically insulated from the device by an insulating member 108, and a cathode electrode 106 having the same potential as the ground is arranged on the upper portion. The substrate is set on a force source electrode, the chamber is evacuated to a vacuum, then Ar gas is introduced, and a high frequency voltage superimposed with a DC component is applied between the electrodes from a high frequency power source 109. To generate a glow discharge between the electrodes. At this time, the Ar gas is ionized and ionized, accelerated in the direction of the substrate by the DC voltage component, physically etches the substrate surface, and is cleaned. After cleaning, nitrogen gas is introduced, and the gas pressure is set to the same value as the adjoining chamber 1 16. The bonding chamber contains a substrate transfer mechanism 127, a camera 125, its drive system 126, an XY movable stage 124, a positioning mechanism consisting of a controller 123, and a pressurizing mechanism 118. A joining mechanism consisting of a support arm 121, an ultrasonic vibration mechanism 1 19, a joining tool 120, and a controller 122, a chip supply (not shown) that transports the chip 13 1 to the joining tool A mechanism is provided. During the operation of the equipment, the bonding chamber is evacuated once, and dried nitrogen gas is introduced to near atmospheric pressure to maintain a dry atmosphere at normal pressure. The substrate 130 is mounted on a heat stage 128 having a built-in heating mechanism. The tip 13 1 is chucked to the joining tool by vacuum suction. The camera is inserted between the chip and the substrate, and the position of the Au bump on the chip and the Au pad on the substrate are checked while aligning with the XY movable stage.After moving the camera, the chip is lowered by the pressure mechanism. It moves and joins by applying pressure and ultrasonic waves.
本実施例によれば、 基板側の内部接合端子である A uパッ ドが有機汚 染あるいは下地からの拡散による酸化性金属で汚染されていても、 表面 を A r イオンで物理的にエッチングして清浄化しているため、 チップ側 の A uバンプとの接合性が大幅に改善され、 信頼性の高い高強度の接合 部が得られるのである。 ま た、 接合室の雰囲気を水分含有量の少ない乾 燥した常圧の窒素ガス雰囲気と しているため、 接合性を損なわず、 かつ チップを真空吸着方式でチヤ ッキングでき、 駆動系の可動部が凝着を起 こすこと無く 長寿命で使用できるため、 量産性のあるプロセスと装置を 実現でき、 信頼性の高いチップとキヤ リ ア基板の接合を達成することが できるのである。 このことによって、 チップ上の電極パッ ドがエリ ア状 に配置された超多ピンで超高速の L S I チップであっても、 A uバンプ を介して直接にかつ高強度にチップと有機キャ リ ア基板を接合する こと ができ、 チップの性能を損なわず高信頼で低コス トの半導体パッケージ を実現できるのである。 According to the present embodiment, even if the Au pad, which is the internal bonding terminal on the substrate side, is contaminated with oxidizing metal due to organic contamination or diffusion from the base, the surface is physically etched with Ar ions. Chip side This greatly improves the bondability with the Au bump, and provides a highly reliable, high-strength joint. Also, since the atmosphere in the joining chamber is a dry, normal-pressure nitrogen gas atmosphere with a low water content, the joining performance is not impaired, and the chips can be chucked by the vacuum suction method. Since they can be used for a long life without causing adhesion, mass-produced processes and equipment can be realized, and highly reliable bonding between the chip and the carrier substrate can be achieved. As a result, even if an ultra-high-pin-count, ultra-high-speed LSI chip in which the electrode pads on the chip are arranged in an area, the chip and the organic carrier can be directly and highly intense via Au bumps. Substrates can be bonded, and a highly reliable and low-cost semiconductor package can be realized without deteriorating the performance of the chip.
以上詳述したよ う に、 本発明によれば、 超多ピンあるいは高速動作の L S I チップをコ ンパク トに収納して、 そのチップ性能を最大限に引き 出すことができる。 ま た、 低コス トの有機キャ リ ア基板を用いて接続部 信頼性の高い半導体パッケージを提供する ことができる。 さ らに、 その 半導体パッケージを量産性の高いプロセスで生産可能な A uバンプ/ A uパッ ドあるいは A uバンプ A uバンプのフ リ ヅプチップ接合方法 及びその方法を実現するための接合装置を提供する ことができる。  As described in detail above, according to the present invention, an ultra-high pin count or high-speed LSI chip can be housed in a compact, and the chip performance can be maximized. Further, a semiconductor package having a highly reliable connection portion can be provided by using a low-cost organic carrier substrate. In addition, the present invention provides an Au bump / Au pad or an Au bump, a flip-chip bonding method of an Au bump capable of producing the semiconductor package by a process with high productivity, and a bonding apparatus for realizing the method. can do.

Claims

請 求 の 範 囲 The scope of the claims
1 . 電極端子を有する半導体チップと、 1. a semiconductor chip having electrode terminals;
前記電極端子と接続される内部接続端子を有する有機基板と、 一 前記半導体チップと前記有機基板との間に充填される樹脂と、 を備え、  An organic substrate having an internal connection terminal connected to the electrode terminal; anda resin filled between the semiconductor chip and the organic substrate,
前記電極端子と前記内部接続端子とが、 直径 3 0 0 μ m以下で高さ 5 0 μ ιη以上かつ高さ /直径の比が 1 5以上である A uバンプを介し て接合される こと を特徴とする半導体パッケージ。  The electrode terminal and the internal connection terminal are bonded via an Au bump having a diameter of 300 μm or less, a height of 50 μιη or more, and a height / diameter ratio of 15 or more. Characteristic semiconductor package.
2 . 請求項 1 において、 1 バンプ当 り の引張破壊強度が 3 0 g以上の接 合強度を有する こと を特徴とする半導体パッケージ。  2. The semiconductor package according to claim 1, wherein a tensile strength per bump is 30 g or more.
3 . 複数の電極端子を有する半導体チップと、 3. A semiconductor chip having a plurality of electrode terminals;
前記電極端子と寸法的に同一に配列され、 A uバンプを介して前記電 極端子と接続される複数の内部接続端子、 及び液相温度 1 9 0 °C以上の 半田バンプで構成される複数の外部電極端子を有する有機基板と、 前記半導体チップと前記有機基板との間に充填される樹脂と、 を備える こと を特徴とする半導体パッケージ。  A plurality of internal connection terminals that are dimensionally identical to the electrode terminals and are connected to the electrode terminals via Au bumps, and a plurality of solder bumps having a liquidus temperature of 190 ° C or higher. A semiconductor package comprising: an organic substrate having the external electrode terminals described above; and a resin filled between the semiconductor chip and the organic substrate.
4 . 半導体チップと、 4. The semiconductor chip,
複数の外部接続端子と、 ピッチ 4 0 0 以下の A uバンプを介して 前記半導体チップとフ リ ップチップ接合される複数の内部接続端子と、 を有し、 前記外部接続端子の領域と前記内部接続端子の領域がスリ ッ 卜 によって分割され、 前記外部接続端子と前記内部接続端子が前記スリ ッ トを通る配線で結線される有機基板と、  A plurality of external connection terminals, and a plurality of internal connection terminals that are flip-chip bonded to the semiconductor chip via Au bumps having a pitch of 400 or less, and a region of the external connection terminals and the internal connection An organic substrate in which a terminal area is divided by a slit, and the external connection terminal and the internal connection terminal are connected by wiring passing through the slit;
前記半導体チップと前記有機基板との間に充填され、 前記配線を覆う  Filled between the semiconductor chip and the organic substrate to cover the wiring
を備える こと を特徴とする半導体パッケージ。 A semiconductor package comprising:
5 . 半導体チップと、 5. The semiconductor chip,
エリ ア状に配置され、 A uバンプを介して前記半導体チップとフェイ スダウ ンで接合される複数の内部接続端子と、 エリ ア状に配置される複 数の外部接続端子とを有し、 前記内部接続端子の領域と前記外部接続端 子の領域が投影面上で重なる有機基板と、  A plurality of internal connection terminals arranged in an area and joined to the semiconductor chip via a Au bump at a face-down, and a plurality of external connection terminals arranged in an area. An organic substrate in which a region of the internal connection terminal and a region of the external connection terminal overlap on the projection surface;
前記半導体チップと前記有機基板との間に充填される樹脂と、 を備えること を特徴とする半導体パッケージ。  A semiconductor package comprising: a resin filled between the semiconductor chip and the organic substrate.
6 . 請求項 5 において、 1 対の前記内部接続端子と前記外部接続端子が 1 個の C uラ ン ドの裏と表に形成されている こと を特徴とする半導体パ ッケージ。  6. The semiconductor package according to claim 5, wherein the pair of the internal connection terminals and the external connection terminals are formed on the back and front of one Cu land.
7 . 電極端子を有し、 1 mm以下の間隙で配置される複数の半導体チップ と、  7. A plurality of semiconductor chips having electrode terminals and arranged with a gap of 1 mm or less;
前記電極端子と A uバンプを介して接続される複数の内部接続端子、 及び液相温度 1 9 0 °C以上の半田バンプで構成される複数の外部電極端 子を有する有機基板と、  An organic substrate having a plurality of internal connection terminals connected to the electrode terminals via Au bumps, and a plurality of external electrode terminals composed of solder bumps having a liquidus temperature of 190 ° C. or more;
前記半導体チップと前記有機基板との間に充填される樹脂と、 を備える こと を特徴とする半導体パッケージ。  A semiconductor package, comprising: a resin filled between the semiconductor chip and the organic substrate.
8 . 半導体チップの電極端子に A uバンプを形成し、 有機キャ リ ア基板 あるいはテープ基板の内部接続端子の表面に A uめっ き層を形成し、 基 板側接合部とチップ側接合部の A u接合表面を A u濃度が 2 0原子%以 上となるよ う に清浄化処理し、 その表面を大気に曝すこ となく 水蒸気分 圧が 1 0 0 P a以下の乾燥した雰囲気中で加熱 · 加圧して圧着する こと を特徴とする有機基板と半導体チップのフ リ ップチップ接合方法。 8. Au bumps are formed on the electrode terminals of the semiconductor chip, Au plating layers are formed on the surface of the internal connection terminals of the organic carrier substrate or the tape substrate, and the substrate-side joint and the chip-side joint are formed. The Au bonding surface is cleaned so that the Au concentration is 20 atomic% or more, and the surface is not exposed to the atmosphere, but in a dry atmosphere with a water vapor partial pressure of 100 Pa or less. A method of bonding a flip chip between an organic substrate and a semiconductor chip, wherein the chip is heated and pressurized and pressure-bonded.
9 . 請求項 8 において、 基板側接合部の清浄化処理が A r イオンによる スパッタ ク リ ーニングであ リ 、 接合雰囲気が水蒸気分圧 : 1 0 0 P a以 下で、 ガス圧力が 5 X 1 0 3〜 2 X 1 0 6 P aの空気あるいは窒素あるい は A r を主体とするガスであり 、 加熱 · 加圧時にスクラブあるいは超音 波振動を加えて圧着する こ とを特徴とする有機基板と半導体チップのフ リ ップチップ接合方法。 9. The cleaning method according to claim 8, wherein the cleaning process of the substrate-side bonding portion is sputter cleaning using Ar ions, and the bonding atmosphere is water vapor partial pressure: 100 Pa or less. Below, a gas mainly composed of air or nitrogen or Ar having a gas pressure of 5 × 10 3 to 2 × 10 6 Pa, which is heated or pressurized by applying scrubbing or ultrasonic vibration. A flip-chip bonding method for bonding an organic substrate and a semiconductor chip, characterized by performing pressure bonding.
1 0 . 半導体チップの電極端子と有機キャ リ ア基板あるいはテープ基板 の内部接続端子に A uバンプを A uポールボンディ ング法によって形成 し、 大気圧下で基板側接合部とチップ側接合部の A uバンプを位置合わ せし、 その状態で気密空間を形成するかあるいは位置合わせした基板と チップを気密室に移送し、 接合雰囲気が 1 O O P a以下となるまで真空 排気し、 加圧加熱して、 あるいは加圧加熱にスクラブま たは超音波振動 を併用 して圧着すること を特徴とする有機基板と半導体チップのフ リ ツ プチップ接合方法。  10. Au bumps are formed on the electrode terminals of the semiconductor chip and the internal connection terminals of the organic carrier substrate or the tape substrate by Au pole bonding, and the substrate-side joint and the chip-side joint are formed under atmospheric pressure. A u Align bumps and form an airtight space in that state or transfer the aligned substrate and chip to an airtight chamber, evacuate until the bonding atmosphere is 1 OOPa or less, pressurize and heat. A flip chip bonding method for an organic substrate and a semiconductor chip, characterized in that the bonding is performed by using pressure or heating together with scrubbing or ultrasonic vibration.
1 1 . 基板の A uパッ ド表面を清浄化する気密な前処理室と、 ドライな 雰囲気を維持してスクラブあるいは超音波を加えつつ基板の A uパッ ド と半導体チップの A uバンプを加熱圧着する気密な接合室と、 接合室に A uバンプ付の半導体チップを供給する気密なチップ供給室と、 接合さ れた半導体チップ及び基板を大気に取り 出す気密な搬出室と を備え、 前 処理室と接合室及び接合室とチッ プ供給室及び接合室と搬出室がゲー ト バルブで接続されている こ と を特徴とするフ リ ップチップ接合装置。  1 1. Airtight pretreatment chamber for cleaning the Au pad surface of the substrate, and heating the Au pad of the substrate and the Au bump of the semiconductor chip while applying a scrub or ultrasonic while maintaining a dry atmosphere. An airtight bonding chamber for crimping, an airtight chip supply chamber for supplying semiconductor chips with Au bumps to the bonding chamber, and an airtight unloading chamber for taking out the bonded semiconductor chip and substrate to the atmosphere. A flip-chip bonding apparatus, wherein a processing chamber and a bonding chamber, a bonding chamber and a chip supply chamber, and a bonding chamber and an unloading chamber are connected by a gate valve.
1 2 . 加圧と加熱を加える接合機構部と、 接合機構部に基板と半導体チ ップを供給する供給機構部と、 半導体チップ及び基板がセ ッ 卜される気 密な容器と、 真空排気機構部とで構成され、 気密な容器が上容器と下容 器に分割され、 上容器が加圧機構部と連結される部品と、 下容器に 0 リ ングを介して密着される部品とから成り 、 かつ両部品が相対移動可能な ベローズで気密に結合されている ことを特徴とするフ リ ップチップ接合 12. Bonding mechanism for applying pressure and heat, supply mechanism for supplying substrate and semiconductor chip to the bonding mechanism, airtight container in which semiconductor chip and substrate are set, and evacuation The airtight container is divided into an upper container and a lower container, and the upper container is connected to the pressurizing mechanism and the parts that are in close contact with the lower container via a ring. A flip-chip joint, characterized in that both parts are airtightly connected by a bellows which can move relative to each other.
1 3 . A uバンプを有する半導体集積回路装置が複数形成された半導体 ゥエーノヽと、 13. A semiconductor device in which a plurality of semiconductor integrated circuit devices having Au bumps are formed;
A uバンプあるいは A uパッ ドが形成された複数パッケージ分の有機 基板とを、 有機基板の A uバンプあるいは A uパッ ドに表面清浄化処理 を施した後、 スクラブあるいは超音波振動をかけながら加熱圧着して接 合し、  After performing surface cleaning treatment on the Au bumps or Au pads of the organic substrate with the Au substrate on which Au bumps or Au pads are formed, apply scrubbing or ultrasonic vibration. Heat bonding
次に、 樹脂を、 半導体ゥエーハと有機基板の間に流入して硬化し、 その後、 有機基板の外部接続端子に半田バンプを形成し、  Next, the resin flows between the semiconductor wafer and the organic substrate and is cured, and then, a solder bump is formed on an external connection terminal of the organic substrate.
半田バンプ形成後に、 切断加工によ り 、 複数のチップサイズパッケ一 ジを組み立てる こと を特徴とする半導体パッケージの製造方法。  A method for manufacturing a semiconductor package, comprising: assembling a plurality of chip size packages by cutting after forming solder bumps.
PCT/JP1998/004337 1998-09-28 1998-09-28 Semiconductor package and flip-chip bonding method therefor WO2000019514A1 (en)

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