[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2000005748A3 - Blind pin placement on circuit boards - Google Patents

Blind pin placement on circuit boards Download PDF

Info

Publication number
WO2000005748A3
WO2000005748A3 PCT/US1999/016745 US9916745W WO0005748A3 WO 2000005748 A3 WO2000005748 A3 WO 2000005748A3 US 9916745 W US9916745 W US 9916745W WO 0005748 A3 WO0005748 A3 WO 0005748A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit boards
pin placement
blind pin
pin
hole
Prior art date
Application number
PCT/US1999/016745
Other languages
French (fr)
Other versions
WO2000005748A2 (en
Inventor
Timothy C Collins
Bo Pi
James Brunsch
Original Assignee
Digirad Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digirad Corp filed Critical Digirad Corp
Priority to AU51266/99A priority Critical patent/AU5126699A/en
Publication of WO2000005748A2 publication Critical patent/WO2000005748A2/en
Publication of WO2000005748A3 publication Critical patent/WO2000005748A3/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09472Recessed pad for surface mounting; Recessed electrode of component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1031Surface mounted metallic connector elements
    • H05K2201/10318Surface mounted metallic pins
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

A technique for use in manufacturing electronic assemblies involves forming a hole (170) in one side (128) of a circuit board (130) and only partially through the board. A pin (164, 166), such as an electrically conductive lead, is then inserted into the hole, and an adhesive material (176, 178) is used to bond the pin to the circuit board.
PCT/US1999/016745 1998-07-22 1999-07-22 Blind pin placement on circuit boards WO2000005748A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU51266/99A AU5126699A (en) 1998-07-22 1999-07-22 Blind pin placement on circuit boards

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US9383398P 1998-07-22 1998-07-22
US60/093,833 1998-07-22
US35905899A 1999-07-21 1999-07-21
US35905799A 1999-07-21 1999-07-21
US09/359,057 1999-07-21
US09/359,058 1999-07-21

Publications (2)

Publication Number Publication Date
WO2000005748A2 WO2000005748A2 (en) 2000-02-03
WO2000005748A3 true WO2000005748A3 (en) 2000-05-04

Family

ID=27377583

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/016745 WO2000005748A2 (en) 1998-07-22 1999-07-22 Blind pin placement on circuit boards

Country Status (2)

Country Link
AU (1) AU5126699A (en)
WO (1) WO2000005748A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4237966B2 (en) * 2002-03-08 2009-03-11 浜松ホトニクス株式会社 Detector
CN106501706B (en) * 2016-11-03 2019-06-04 昆山万像光电有限公司 A kind of blind hole detection method of printed circuit board

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5483102A (en) * 1994-05-12 1996-01-09 Intel Corporation Employing on die temperature sensors and fan-heatsink failure signals to control power dissipation
US5485037A (en) * 1993-04-12 1996-01-16 Amkor Electronics, Inc. Semiconductor device having a thermal dissipator and electromagnetic shielding
US5615086A (en) * 1994-05-17 1997-03-25 Tandem Computers Incorporated Apparatus for cooling a plurality of electrical components mounted on a printed circuit board
US5625166A (en) * 1994-11-01 1997-04-29 Intel Corporation Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect
US5744863A (en) * 1994-07-11 1998-04-28 International Business Machines Corporation Chip carrier modules with heat sinks attached by flexible-epoxy
US5872026A (en) * 1995-06-07 1999-02-16 Lsi Logic Corporation Process of fabricating an integrated circuit die package having a plurality of pins

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5485037A (en) * 1993-04-12 1996-01-16 Amkor Electronics, Inc. Semiconductor device having a thermal dissipator and electromagnetic shielding
US5483102A (en) * 1994-05-12 1996-01-09 Intel Corporation Employing on die temperature sensors and fan-heatsink failure signals to control power dissipation
US5615086A (en) * 1994-05-17 1997-03-25 Tandem Computers Incorporated Apparatus for cooling a plurality of electrical components mounted on a printed circuit board
US5744863A (en) * 1994-07-11 1998-04-28 International Business Machines Corporation Chip carrier modules with heat sinks attached by flexible-epoxy
US5625166A (en) * 1994-11-01 1997-04-29 Intel Corporation Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect
US5872026A (en) * 1995-06-07 1999-02-16 Lsi Logic Corporation Process of fabricating an integrated circuit die package having a plurality of pins

Also Published As

Publication number Publication date
WO2000005748A2 (en) 2000-02-03
AU5126699A (en) 2000-02-14

Similar Documents

Publication Publication Date Title
MXPA06000842A (en) Circuit board with embedded components and method of manufacture.
WO2000013190A8 (en) Conductive paste, conductive structure using the same, electronic part, module, circuit board, method for electrical connection, method for manufacturing circuit board, and method for manufacturing ceramic electronic part
AU5495998A (en) Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
WO2001033927A8 (en) Inter-circuit encapsulated packaging for power delivery
WO2005076353A3 (en) Apparatus incorporating small-feature-size and large-feature-size components and method for making same
AU6121598A (en) Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board
GB2344463B (en) Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board
EP0774888A3 (en) Printing wiring board and assembly of the same
MY128015A (en) Multilayer printed circuit board and multilayer printed circuit board manufacturing method
EP1220588A4 (en) Method of manufacturing printed-circuit board
EP1250033A3 (en) Printed circuit board and electronic component
EP0939453A3 (en) An electrical connection box
AU2002211084A1 (en) Methods of manufacturing a printed circuit board shielded against interfering radiation
WO2004038798A3 (en) Stacked electronic structures including offset substrates
EP1219693A4 (en) Conductive adhesive, apparatus for mounting electronic component, and method for mounting the same
EP1035759A3 (en) Edge-mountable integrated circuit package and method of attaching the same to a printed wiring board
WO2002100140A3 (en) Circuit board with at least one electronic component
CA2030826A1 (en) Composite circuit board with thick embedded conductor and method of manufacturing the same
EP1069811A3 (en) Multi-layer wiring board and method for manufacturing the same
WO2000047025A3 (en) Method for forming printed circuit board electrical interconnects
CA2080094A1 (en) Multilayer circuit board with repaired i/o pin and process for repairing i/o pin on multilayer circuit board
EP0933834A3 (en) Fastener for an electrical connector
WO2001065344A3 (en) Method and apparatus for providing power to a microprocessor with integrated thermal and EMI management
EP0917191A3 (en) Electronic component unit, electronic assembly using the unit, and method for manufacturing the electronic component unit
EP0755101A3 (en) High density card edge connection system with outrigger and sequentially connected contacts

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW SD SL SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase