WO2000068474A1

WO2000068474A1 - SiC WAFER, SiC SEMICONDUCTOR DEVICE AND SiC WAFER PRODUCTION METHOD

Info

Publication number: WO2000068474A1
Application number: PCT/JP2000/002932
Authority: WO
Inventors: Hiroyuki Matsunami; Tsunenobu Kimoto; Hiromu Shiomi
Original assignee: Sixon Inc.; Sumitomo Electric Industries, Ltd.; Kansai Electric Power C.C., Inc.; Mitsubishi Corporation
Priority date: 1999-05-07
Filing date: 2000-05-08
Publication date: 2000-11-16
Also published as: AU4318600A; JP2000319099A; JP4185215B2

Abstract

An SiC substrate (2) having a plane orientation of almost (11-20) and being of a 4H type polytype or 15R type polytype, and a buffer layer (4) formed on the SiC substrate (2) and made of SiC are provided.

Description

Akitoda:

S i C wafer, S i C semiconductor device, and method for manufacturing S i C wafer

The present invention relates to a SiC wafer suitable for semiconductor electronic components, a SiC semiconductor device provided with the SiC wafer, and a method for manufacturing a SiC wafer. Background art

In recent years, compound semiconductors composed of light elements such as silicon carbide (SiC) or gallium nitride (GaN) have been actively studied. Since such compound semiconductors are composed of light elements, they have a high binding energy, and as a result, are characterized by a large energy forbidden band (band gap), a high breakdown electric field, and a high thermal conductivity. Utilizing the characteristics of this wide bandgap, it has attracted attention as a material for high-efficiency, high-withstand-voltage power devices, high-frequency power devices, high-temperature operating devices, or blue to ultraviolet light-emitting devices. However, due to the strong binding energy, these compounds do not melt even at high temperatures at atmospheric pressure, and grow Nork crystals by recrystallization of the melt used in other semiconductors such as silicon (Si). Is difficult.

For example, in order to use SiC as a semiconductor material, it is necessary to obtain a high-quality single crystal having a certain size. For this reason, small pieces of SiC single crystal have conventionally been obtained by a method using a chemical reaction called the Acheson method or a method using a sublimation recrystallization method called the Rayleigh method. Recently, a silicon carbide single crystal produced by these methods was used as a substrate, and a SiC ingot was grown thereon by an improved Rayleigh method of sublimation and recrystallization, and the SiC ingot was sliced and mirror-polished. Polished SiC substrates are now being manufactured. Then, single-SiC of the target scale is deposited on the substrate by vapor-phase epitaxy or liquid-phase epitaxy. By growing crystals, an active layer with controlled impurity density and film thickness was formed, and this was used to fabricate SiC semiconductor devices such as Pn junction diodes, Schottky diodes, and various transistors. .

However, of the above methods, the Acheson method heats a mixture of silica and coke in an electric furnace and precipitates crystals by spontaneous nucleation, so that there are many impurities, and it is difficult to control the shape and crystal plane of the obtained crystal. It is. In the Rayleigh method, the crystal grows by spontaneous nucleation, and it is difficult to control the shape and plane of the crystal. In the improved Rayleigh method, for example, in the invention described in Japanese Patent Publication No. 59-48772, a large SiC ingot consisting of a single crystal polymorph is obtained. However, such ingots generally contain large defects called micropipes (<0.001> small holes penetrating in the axial direction), usually at a density of about 1 to 50 cm- ² . Furthermore, a screw dislocation with A vector Burgers in the c-axis direction that exists about 1 0 ³ ~1 0 ⁴ cm one ^2.

Usually, the SiC {00001} plane or a substrate with an off angle of 3 to 8 degrees from this plane is used for epitaxy growth. At this time, most of the micropipe defects and screw dislocations existing on the substrate penetrate into the SiC epitaxial growth layer, and the SiC device fabricated using the epitaxial growth layer contains micropipe defects. It is known that device characteristics are significantly deteriorated. Therefore, the mouth opening defect is the biggest barrier to the production of high capacity (high current, high breakdown voltage) SiC semiconductor devices at high yield. In addition, when SiC homoepitaxial growth is performed using a normally used SiC {00001} plane or a SiC substrate having an off angle of several degrees from this plane, the atomic Aggregation of steps (step bunching) Phenomena are likely to occur. If the degree of this step bunching increases, the surface roughness of the SiC epitaxial growth layer increases, and the flatness of the metal monoxide-semiconductor (MOS) interface deteriorates. The channel mobility of the inversion layer of the MOSFET) decreases. Also, pn junction, The flatness of the interface between the barriers is deteriorated and electric field concentration occurs at the junction interface, causing problems such as a decrease in breakdown voltage and an increase in leakage current.

There are many crystalline polymorphs in S i C. Among them, the 4H-polytype (4H-S i C) has high mobility, and the ionization energy of the donor is small. It is considered to be the most suitable SiC polytype for SiC semiconductor device fabrication. However, when MO SFETs are fabricated using the 4H—SiC {0001} plane or an epitaxially grown layer on a substrate with an off angle of 3 to 8 degrees from this plane, the channel mobility becomes 1 to Ten

Very small and cannot realize high-performance transistors.

In order to solve these problems, Japanese Patent Publication No. 2804860 discloses that the SiC (0

By using a seed crystal having a plane other than the (001) plane, for example, a (1-100) plane, and growing by the improved Rayleigh method, a SiC ingot with a small number of micropipes has been obtained. However, when epitaxial growth is performed on the SiC (1-100) plane, stacking faults are likely to occur during the growth, and it is difficult to obtain a high-quality SiC single crystal sufficient for semiconductor device fabrication.

In recent years, researches have been made to fabricate SiC wafers using 6H-type polytype SiC (11-20) substrates in addition to SiC (1-100) substrates. If such a 6H-polytype SiC (1 1-20) substrate is used, micropipes and screw dislocations extending in the <0001> axial direction do not reach the epitaxial layer on the substrate. Micropipe defects in the epitaxial layer can be reduced. Disclosure of the invention

However, the SiC wafer using the 6 6 polytype SiC (11-20) substrate has the following problems. In other words, when a SiC epitaxial layer is grown on a conventional SiC (11-20) substrate, SiC epitaxial growth and Distortion occurs at the interface with the i C substrate due to lattice mismatch. This distortion adversely affects the crystallinity of the epitaxial growth layer, making it difficult to produce a high-quality epitaxial silicon growth layer.

Also, when a device is fabricated using a 6-3 type 1-6 (11-20) substrate of a 6-inch polytype, anisotropy of electron mobility becomes a problem. In detail, the 6H-SiC crystal has a small electron mobility in the <0001> axial direction, <11-100>, and about 20-30% of the mobility in the <11-20> direction. -In the growth layer on the SiC (ll-20) plane, the in-plane electric conduction has 3 to 5 times anisotropy.

The present invention has been made in view of such circumstances, and when used as a semiconductor device, has low anisotropy of electron mobility, and has an SiC substrate and a SiC epitaxial growth layer. It is an object of the present invention to provide a SiC wafer capable of alleviating distortion due to lattice mismatch with a semiconductor device, a semiconductor device having the SiC wafer, and a method for manufacturing a SiC wafer. In order to achieve the above object, the SiC wafer of the present invention has a plane orientation of approximately (11-20), a 4H-type or 15R-type SiC substrate, and a SiC substrate. And a buffer layer made of SiC formed on a C substrate.

According to the SiC wafer according to the present invention, since the SiC substrate whose plane orientation is substantially (111-20) is used, the active layer of the SiC is epitaxially formed on the SiC wafer of the present invention. Even when grown, micropipes and screw dislocations extending in the <0001> axis direction of the SiC substrate do not reach the active layer. In addition, since a 4H-type or 15R-type polysubstrate, which has a smaller anisotropy of electron mobility than a 6H-type SiC substrate, is used, it grows on a SiC wafer. The anisotropy of the electron mobility in the activated layer is reduced. Furthermore, since the buffer layer made of SiC is formed on the SiC substrate, when the SiC active layer is grown on the SiC wafer of the present invention, the SiC substrate and the SiC substrate are formed. It is possible to prevent a situation in which distortion due to lattice mismatch with the C active layer is generated in the SiC active layer. The thickness of the buffer layer is preferably not less than 0.3 zm and not more than 15 μm. According to the inventor's intensive research, when a SiC active layer is grown on the buffer layer of the present invention and the thickness of the buffer layer is set to 0.3 μm or more, distortion based on lattice mismatch is caused. Was found to be able to be effectively reduced, and the crystallinity of the SiC active layer was improved. If the buffer layer is made 15 μm or less, the growth time and cost can be reduced.

Furthermore, the buffer layer, nitrogen, including phosphorus, aluminum, or one even without less of boron as an impurity, the density of impurities in the buffer layer, 2 x 1 0 ¹⁵ cm one ³ or more 3 x 10 ¹⁹ cm- It is preferably ³ or less. To the free Murrell impurity density in this range is the buffer layer, diminished the effect of strain relaxation based on the lattice mismatching when the impurity concentration is less than 2 X 10 ^{1 5} cm one ^{3, 3} X 10 ¹⁹ cm If the value is larger than ^—3 , the high concentration doping degrades the crystallinity of the buffer layer itself.

Further, it is preferable that the density of the impurity in the buffer layer is lower than the density of the impurity in the SiC substrate. By setting the impurity density of the buffer layer in this way, when the SoC active layer is formed on the SoC wafer, the impurity density is gradually increased in the order of the SoC wafer, the buffer layer, and the SoC active layer. Can be reduced.

Further, the SiC wafer of the present invention is characterized in that an active layer made of SiC is further provided on the buffer layer. Further, in this case, it is preferable to decrease the density of impurities in the buffer layer from the interface with the SiC substrate to the interface with the SiC active layer.

A SiC semiconductor device according to the present invention includes the above-described SiC wafer. As described above, the SiC wafer has a small anisotropy of electron mobility and hardly generates distortion due to lattice mismatch between the SiC substrate and the SiC active layer. It will be of high quality.

The SiC semiconductor device of the present invention has a surface formed by a SiC active layer and a metal layer. It may have a barrier, or a pn junction formed by epitaxial growth or ion implantation. In addition, an oxide film formed by thermal oxidation or chemical vapor deposition is used as a gate insulating film, or an oxide film formed by thermal oxidation or chemical vapor deposition is used as a part of the surface protection film. Is also good.

According to the method for manufacturing a SiC wafer of the present invention, the plane orientation is almost (11-20) and the SiC substrate of the 4H-type or 15R-type polytype is formed on the SiC substrate. It is characterized by growing a buffer layer made of iC. Further, an active layer made of SiC may be further grown on the buffer layer. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a SiC wafer of the present invention.

FIG. 2 is a diagram showing micropipes and screw dislocations in a SiC substrate. FIGS. 3A to 3C are diagrams showing the surface states of the SiC active layers grown on different SiC substrates.

Figure 4 is a graph showing the relationship between the thickness of the buffer layer and the FWHM of the X-ray rocking curve.

FIG. 5A to FIG. 5D are views showing SoC wafers provided with buffer layers having different impurity densities.

FIG. 6 is a graph showing the X-ray rocking force of a SiC active layer formed on a 15R-SiC (ll-20) substrate.

FIG. 7 is a diagram showing a SiC Schottky diode of the present invention.

FIG. 8 is a diagram showing current-voltage characteristics of a Schottky diode manufactured using an S i C active layer grown on a 4H—S i C (11-20) substrate.

FIG. 9 is a graph showing the relationship between the electrode area and the breakdown voltage of the 4H—SiC Schottky diode.

FIG. 10 is a diagram showing a MOSFET (SiC semiconductor device) of the present invention. FIG. 11 is a diagram showing current-voltage characteristics of an M〇SFET manufactured using an SiC active layer grown on a 4H—SiC (11-20) substrate.

FIG. 12 is a table showing channel mobility of a MOS FET manufactured using a plurality of SiC substrates. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of a SiC wafer, a SiC semiconductor device, and a method for manufacturing a SiC wafer according to the present invention will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are used for the same elements, and duplicate description will be omitted. Further, in the description of the embodiments and examples, the lattice direction and the lattice plane of the crystal may be used. Here, the symbols of the lattice direction and the lattice plane will be described. The individual direction is [:], the collective direction is <>, the individual plane is (), and the collective plane is {}. For negative indices, "one" (bar) is attached to the number in crystallography, but a negative sign is added before the number for the convenience of preparing the specification. .

FIG. 1 is a side view of the SiC wafer 1 of the present embodiment. The SiC wafer 1 is a 4H polytype (“H” is a hexagonal system, “4” is a crystal structure with four atomic layers and one period), 4H—SiC (11-20) A substrate 2, a buffer layer 4 made of SiC formed on the SiC (11-20) substrate 2, and an active layer 6 made of SiC for device fabrication formed on the buffer layer 4. , have. The plane orientation of the 4H—SiC (ll-20) substrate 2 may be slightly inclined from (11-20). Each of the layers 2 to 6 is all n-type.

Next, a method for manufacturing the SiC wafer 1 of the present embodiment will be described. The 4H—SiC (1 1-20) substrate 2 is fabricated by, for example, slicing an ingot grown on the 4H—SiC (000-1) plane by the modified Rayleigh method in parallel to the growth direction and mirror-polishing. . At this time, it is preferable that the thickness of the 4H_SiC (ll-20) substrate 2 be in a range of about 150 / m to about 400 μm. Also, the effective donor density Is preferably in the range of about 5 x 10 ¹⁷ cm- ³ ~ about 5 x 10 ¹⁹ c m_ ^3. Next, the 4H—SiC (ll—20) substrate 2 is mirror-finished, and thereafter, a chemical vapor deposition (CV D) method is used, which has excellent controllability of film thickness, impurity doping, and surface flatness of the grown layer. The buffer layer 4 and the active layer 6 are epitaxially grown. Specifically, first, the 4H—SiC (11-20) substrate 2 is washed with an organic solvent, aqua regia, hydrofluoric acid, etc., rinsed with deionized water, and coated with a SiC film. Installed on a Graphite susceptor and set in a CVD growth system. For CVD growth, a normal pressure horizontal CVD system using hydrogen (H ₂ ) as a carrier gas is used, and the susceptor is heated by high-frequency induction heating. 4H- S i C (1 1- 20 ) after placing the substrate 2 in the reaction furnace, repeated several times gas replacement and high-vacuum evacuation, into the CVD growth program by introducing of H ₂ Kiyaryagasu.

First, after vapor Edzuchingu by HC 1 / H ₂ gas at about 1300 ° C, 4 HS i C (1 1 -20) was heated substrate 2 to approximately 1500 ° C, the raw material gas (silane: S iH ₄ , propane: C ₃ H ₈ etc.) are introduced to start the growth of the buffer layer 4 and the active layer 6. The CVD growth, after about 0. 3 Zm～ about 15〃M growing an n-type S i C buffer layer 4 of an effective donor density of approximately 10 ¹⁶ cm- ³ ~ about 10 ¹⁹ cm one ^3, the effective donor one density of about 10 An n-type active layer 6 of ¹⁴ cm— ³ to about 10 ¹⁶ cm — ³ is grown for about 5 μm to about 80 m. The n-type conductivity is controlled by adding nitrogen gas during growth.

In addition, the thickness of the buffer layer 4 is preferably not less than 0.3 / m and not more than 15 / m. Further, the impurity contained in the buffer layer 4 is preferably any one of nitrogen, phosphorus, aluminum, and boron. It is preferable that the impurity density in the buffer layer 4 gradually decreases from the interface with the 4H—SiC (11-20) substrate 2 toward the interface with the active layer 6.

Next, the effects of the SiC wafer 1 of the present embodiment will be described with reference to FIG. Usually, micropipes and screw dislocations are present on the SiC substrate. In addition, micropipes extend in the axial direction of the SiC substrate. However, since the SiC wafer 1 of this embodiment uses a SiC substrate having a plane orientation of (11-20), micropipes (shown by dashed lines) 8 and screw dislocations (shown by broken lines) 1 0 hardly reaches the active layer 6. Therefore, the active layer 6 has few defects and excellent flatness.

Further, in the present embodiment, since a 4H polytype substrate having smaller anisotropy of electron mobility than a 6H polytype SiC substrate or the like is used, the substrate is grown on the SiC wafer 1. The anisotropy of the electron mobility in the active layer 6 is reduced. In addition, contamination of different polytypes is completely prevented. Further, since the buffer layer 4 made of SiC is formed on the SiC substrate 2, strain occurs in the active layer 6 due to lattice mismatch between the SiC substrate 2 and the SiC active layer 6. Can be prevented.

In addition, according to the inventor's intensive research, the strain due to lattice mismatch can be effectively reduced by setting the thickness of the buffer layer 4 to 0.3 zm or more, and the crystallinity of the active layer 6 is improved. Was found to work. On the other hand, if the buffer layer 4 is set to 15 zm or less, the growth time and cost can be reduced.

Furthermore, the density of impurities to be contained in Bruno Dzufa layer 4 is preferably in the 2 X 10 ¹⁵ cm one ³ or more 3 X 10 ¹⁹ cm one ³ below. To the impurity density contained in the buffer layer 4 to this range, diminished the effect of strain relaxation based on the lattice mismatching when the impurity concentration is less than 2 10 ^{1 5} cm one ^{3, 3} x 10 ¹⁹ cm- ^If it is larger than ³ , the high concentration doping degrades the crystallinity of the buffer layer 4 itself.

In this embodiment, the 4H-type poly-type SiC substrate is used. In addition, a 15 R-type polytype (“R” is a rhombohedral system, “15” is a 15-layer atomic stack and one period) Even if a 15R—SiC (11-20) substrate is used, the active layer grown on the SiC wafer does not have micropipes or screw dislocations. It is excellent in flatness.

Various SiC semiconductor devices can be manufactured using the SiC wafer 1 of the present embodiment. Can be manufactured. For example, such a SiC semiconductor device can be configured to have a metal / SiC Schottky barrier or pn junction formed by epitaxial growth or ion implantation on the surface. Further, an oxide film formed by thermal oxidation or chemical vapor deposition is used as a gate insulating film, and an oxide film formed by thermal oxidation or chemical vapor deposition is used as a surface protection film. You may comprise so that it may have as a part.

As described above, since the SiC wafer 1 has a small anisotropy of electron mobility and almost no distortion due to lattice mismatch between the SiC substrate 2 and the SiC active layer 6, such a semiconductor The device will be of high quality. More specifically, since the surface flatness of the active layer 6 is particularly excellent, the electric field concentration at the pn junction formed by epitaxial growth and at the Schottky barrier interface formed on the epitaxially grown surface is greatly reduced. This makes it easy to increase the breakdown voltage of the device. Furthermore, S i C (11-20) has fewer atomic bond bonds per unit area than the S i C {000 1} plane, so the interface state of the oxide film / S i C at the MOS interface is reduced. A high-quality MOS interface can be fabricated, and a high-performance MOS transistor can be realized. Ma Bell I

Hereinafter, examples of the above embodiment will be described. However, the present invention is not limited to the examples.

[Example 1]

The first embodiment will be described with reference to FIG. In this embodiment, in order to investigate the penetration of a microphone opening pipe or a screw dislocation from the SiC substrate to the SiC active layer and the flatness of the surface of the active layer 6, n-type 4H—SiC (11 -20) An n-type active layer 6 was grown on the substrate 2 by chemical vapor deposition (CVD). For comparison, the active layer was simultaneously grown on a substrate with 4H-SiC (1-100) and (0001) 8 degrees off (<11-20> direction) as the plane direction. did. 4H—SiC (1 1—20), (1—10 0) The substrate was prepared by slicing an ingot grown on the 4H-SiC (000-1) plane by the modified Rayleigh method parallel to the growth direction and mirror-polishing. The substrates were all n-type, and the effective donor calculated from the capacitance-voltage characteristics of the Schottky barrier—density was 1 × 10 ¹⁸ cm— ³ to 2 10 ¹⁸ cm— ³ , and the thickness was about 380 mm. .

Result of market shares Tsuchingu in the these substrates 500 ° C, 10 minutes in a molten potassium hydroxide (KOH) conditions, both micropipe density 12 cm one ² ~ 28 cm- ^2, the dislocation density N racemate 5 X 10 ³ it did not amount to ^{^{cm- 2 ~2 X 10 4 c m_}} 2 about defects are present. However, for the (11-20) and (1-100) planes, the edge of the substrate is polished at an angle of about 80 degrees to obtain a plane inclined about 10 degrees from the (000 1) plane, and this plane is etched. Observation was made later to estimate the defect density.

Next, the KOH-etched substrate was polished again, mirror-finished, and CVD grown. These substrates were washed with an organic solvent, aqua regia, and hydrofluoric acid, rinsed with deionized water, placed on a graphite susceptor coated with a SiC film, and set in a CVD growth apparatus. Then, after repeating several times the gas replacement and high-vacuum evacuation, entered the CVD growth program with H ₂ introduced Kiyaryagasu.

First, after vapor phase etching by HC 1 / H ₂ gas at 1300 ° C, the temperature was raised to 15 00 ° C, the raw material gas (silane: S i H _4, propane: C _3, etc. H ₈₎ introduced And started growing. The CVD growth, after the n-type S i C buffer layer effective donor density ^{^{3 X 10 17 cm- 3 ~4 x}} 1 0 17 cm- 3 4. to 6 / m growth, the effective donor one density IX 10 ¹⁶ CM_ An n-type active layer of ^{3 to} 2 × 10 ¹⁶ cm- ³ was grown at 12 zm. The main growth conditions at this time are as follows. In general, since the efficiency of taking in impurities is different between the (0001) plane and the (11-20) plane, it is preferable to adjust the doping gas flow rate according to the plane orientation of the substrate.

Buffer layer: SiH4 flow rate 0.30sccm

C3H8 flow rate 0.20sccm N2 flow 6x10—seem

H2 style] 3.0slm

1500 ° C

Growth time 110 minutes Active layer: SiH4 flow rate 0.50sccm

C3H8 flow rate 0.50sccm

N2 flow 2xl0- ² sccm

H2 flow 3.0slm

Substrate temperature 1500 ° C

Growth time 180 minutes

Observation of the surface of the active layer 6 grown by epitaxy with a differential interference optical microscope revealed that a mirror surface was obtained on the 4H (11-20) and (0001) 8 degree off substrates, but 4H (1-100). ) On the substrate, streaky irregularities and grooves running in the direction 1 1-20> were observed. This streak-like defect on the 4H (1-100) plane is also observed in the growth layer on the 6H (1-100) plane, and optimization of the substrate surface treatment method before growth 成長 growth conditions with low oversaturation Performing CVD growth (for example, at low source gas flow rates) slightly reduced the occurrence of streak defects, but could not completely eliminate them. Observing the active layer surface on a 15 mm x 20 mm substrate and estimating the density of surface defects (which do not always match structural defects such as dislocations), the 4H (11-20) substrate ^{^{4 X 10 2 cm_ 2, (}} 1- 100) 8 x 10 3 cm_ 2 denotes a substrate, (000 1) in the 8-degree off substrates is ^{^{2 x 10 3 cm_ 2, 4H}} (1 1 -20) active on the board The active layer was the best.

FIGS. 3A to 3C are graphs showing the results obtained by performing an atomic force microscope (AFM) observation and measuring the surface profile. Figures 3A, 3B, and 3C show 4H (1 1-20) board, 4H (1-100) board, (000 1) 8 degree off It is a graph regarding a board. (1-100) The surface of the active layer formed on the substrate has severe irregularities as shown in Fig. 3B, even if the area without the above-mentioned deep groove (depth about 100-300nm) is selected. . Also, from FIG. 3C, it was found that the surface of the active layer formed on the (000 1) 8 ° off-substrate had step-like irregularities due to the assembling of atomic steps (step bunching). . On the other hand, in the active layer formed on the 4H (11-20) substrate, no grooves, hillocks, steps, etc. were observed at all, as shown in Fig. 3A. Good surface was obtained. In addition, the root mean square (Rms) of the surface roughness when observing the area of 2 pi mx 2 m by AFM is 0.18 nm for the active layer formed on the (11-20) substrate, and the (1-100) substrate The active layer grown on the (11-20) substrate was the best, with 6.4 nm above and 0.24 nm on the (000 1) 8 degree off substrate.

Next, the grown sample was etched with molten KOH, and structural defects in the active layer 6 were examined. (000 1) In the active layer on the 8 ° off-substrate, the micropipe density is 18 c ~ screw dislocation density 8 × 10 ³ cm- ¹² , which is almost the same as the value of the substrate before growth, and was generated by etching. The position of the pit was in good agreement with that before growth. When etching the active layer (1 one 100) substrate, in addition to polygonal pitch Bok was seen many (1 x 10 ⁵ CM_ ^2), is deeper summer streak defects that appeared on the surface of the active layer Was. This streak-like groove always extends in the <111> direction, and is considered to be caused by stacking faults. The number of deep etched grooves by molten KOH is growth before (1 100) in the substrate while was 3 to 8 cm- ^1, after the growth has increased the 30 to 200 DEG cm one ¹ Was. Therefore, when an active layer is grown on a (1-100) substrate, it is considered that stacking faults are newly generated by CVD growth.

In contrast, when the active layer grown on the (11-20) substrate was etched with molten KOH, the density of triangular pits reflecting dislocations was about ² × 10 ³ cm_2, and the stacking fault density was 5 It was as small as ¹ cm or less. In addition, the surface obtained by diagonally polishing this sample was etched. Micropipe density is less than 1 CM_ ² was estimated by quenching, also screw dislocation density of 1

It was found to be less than 00 cm- ² . In other words, by using a 4H—SiC (11-20) substrate, it is possible to greatly suppress the penetration of micropipes and screw dislocations from the substrate, and to produce high-quality SiC epitaxial crystals with extremely few stacking faults. It becomes possible. This is mainly because micropipes and screw dislocations are mainly S

Since it extends in the <0001> direction of the 1C crystal (see Fig. 2), if the (11-20) plane, which is a crystal plane parallel to this direction, is used, micropipes and the like existing in the SiC substrate will be This is because the active layer does not carry over. Note that 15R—S iC (1

1-20) Even when the active layer on the substrate was epitaxially grown, the active layer was extremely excellent in flatness, and there was almost no penetration of micropipes or screw dislocations.

[Example 2]

In this example, in order to investigate the effect of the buffer layer on the active layer, n-type 4H-SiC buffer layers of various thicknesses were formed on an n-type 4H—SiC (11-20) substrate. After that, a high-purity thick epitaxial growth layer to be an active layer was formed and its crystallinity was evaluated. The S i C substrate 2 used was 4H—S i C (11-

20) For an n-type 4H-SiC (11-20) fabricated by slicing a 4HSiC ingot grown on a seed crystal, the effective donor density obtained from the capacitance-voltage characteristics of the Schottky barrier is It was 3 × 10 ¹⁸ cm— ³ to 4 × 10 ¹⁸ cm— ³ and was about 340 μm thick.

The S i C Donna on the substrate 2 one density ^{^{4 X 10 17 cm- 3 ~ 5}} X 10 17 cm- 3 of n-type 4H- after forming the S i C buffer layer, a high-purity n-type 4H-S i. A layer (done density 4 × 10 ¹⁵ cm— ³ ) was grown about 24 μm. The n-type conductivity was controlled by adding nitrogen gas during growth. Then, a SiC wafer with a buffer layer thickness varied from 0.1 lm to 22 m, and a high-purity SiC active layer grown directly on the substrate without a buffer layer for comparison The fabricated SiC wafer was manufactured. CV The same CVD apparatus as in Example 1 was used for D growth. First, after performing gas phase etching with HC1ZH2 gas at 1400 ° C, the temperature was raised to 1650 ° C, growth was started by introducing a source gas, and the growth conditions were as follows. As is,

Fa layer: SiH4 flow 0.30sccm

υ3Ηο flow _ι 0.20scc

Ν2 flow rate 9xl0 sccm

Η2 flow rate 3.0slm

1560 ° C

Growth time 3 minutes to 520 minutes Active layer: SiH4 flow rate 0.50sccm

¾t village 0.66sccm

N2 flow 6x10— ³ sccm

nZ style 3.0slm

Substrate temperature 1560 ° C

Growth time 360 minutes

Figure 4 shows the dependence of the half-width (F HM) of the diffraction peak on the buffer layer thickness obtained from the X-ray diffraction rocking force measurement of the active layer 6 of the SiC wafer with buffer layers of various thicknesses. It is a graph which shows sex. For the X-ray diffraction, five-crystal X-ray diffraction using Ge single crystal (400) diffraction was used. The sex was evaluated. The half width of the diffraction peak obtained by measuring the 4 H—Si C (11—20) substrate before growth was 32 to 38 arcsec (average 35 arcsec).

In the active layer 6 of a SiC wafer in which a high-purity n-type SiC layer (24 m) was grown directly on the substrate without using a buffer layer, the half-width of the X-ray rocking curve was 52 arcsec. However, it was worse than the SiC substrate 2 (indicated by a square in FIG. 4). The problem is n-type This was improved by introducing a buffer layer. In other words, when the thickness of the buffer layer was 0 μm, a half width (43 arcsec) was still obtained, which was slightly worse than that of the substrate. However, when the thickness of the fa layer was 0.3 μm or more, the half width was smaller than the substrate. The value range was obtained, and it was found that crystallinity was improved by epitaxial growth. In particular, when the thickness of the buffer layer was about 1.2 m or more, the half width became almost constant at 2 larcsec. When the dislocation density on the (11-20) plane was evaluated by molten KOH etching, the buffer layer was 6 × 10 ⁴ cm_ ² on the substrate, ² × 10 ⁵ cm— ² on the active layer grown without the buffer layer, and 2 zm or more. the provided was ^{^{3 X 10 3 cm- 2 ~6 x}} 10 3 cm one ² becomes the active layer, the effect of also the buffer layer was clearly seen.

The reason why the buffer layer is effective for producing a high-quality SiC epitaxial growth layer is that the highly doped SiC substrate and the lightly doped high-purity SiC active layer are effective. It is considered that the strain caused by the lattice mismatch existing between them is alleviated by the buffer layer. Generally, the S i C crystals containing 10 ¹⁸ cm one ³ about or more impurities, the lattice constant of the S i C crystal according to the type of impurity increased or decreased, yet the ratio of the lattice constant increase or decrease, (11 one 20) On the plane is larger than on the {0001} plane. Therefore, when epitaxial growth is performed on a 4H—SiC (11-20) substrate, the impurity density has an intermediate value between that of the substrate and the active layer for device fabrication formed thereon. It is effective to provide a SiC buffer layer to reduce lattice distortion caused by lattice mismatch. Normally, when fabricating a vertical power device, a substrate is used which is heavily doped with impurities (donor or acetonitrile) to reduce the resistance of the substrate. It is preferable to provide a SiC buffer layer that is low and is doped higher than the impurity density of the active layer. In the above embodiment, the nitrogen (N) doped n-type SiC was used, but the phosphorus (P) doped n-type SiC, aluminum (A1), and boron (B) doped SiC were used. When an experiment was performed using p-type SiC, a similar effect of the buffer layer was observed. Also, using a 15R-SiC (11-20) substrate However, the same effect was obtained.

[Example 3]

In the present example, the effect was investigated by changing the impurity density in the buffer layer 4 while keeping the thickness of the buffer layer 4 constant (3 μm). The substrate used was an n-type 15R—SiC (ll—20) substrate with a size of 1 Ommx15 mm, an effective donor density of 5 × 10 ¹⁸ cm— ³ , and a thickness of 350 mm. . Then, a buffer layer 4 having a thickness of 3 / m having a nitrogen donor density distribution as shown in FIGS. 5A to 5C is formed on the SiC substrate, and then a donor density of 5 × 10 ¹⁴ cm— ^3. A high-purity 11-type 15R-SiC active layer 6 with a thickness of 32 to 111 was epitaxially grown. For comparison, a SiC wafer without the noise layer 4 (hereinafter referred to as “sample (d)”) was also prepared as shown in FIG. 5D. In the S i C wafer (sample (a)) shown in FIG. 5A, the donor density in the buffer layer is constant at 5 × 10 ¹⁷ cm− ³ , while the S i C wafer (sample (a)) shown in FIG. (B)) from the bottom 2 x 10 ¹⁷ cm_ ⁸ (8〃m thick), 7 x 10 ¹ cm " ³ (8〃m thick), 2 xl 0 ¹⁷ cm— ³ (0.8 thick m), 5 x 10 ¹⁷ cm- ³ (0.6 厚 m thick) in a stepwise manner. For the SiC wafer (sample (c)) shown in Fig. 5C, 3 x 10 ¹⁸ cm ^1-3 to 2 x _c the major growth conditions inclined alter the donor density from the bottom to the top to 10 ¹⁶ cm one ³ is as follows.

Buffer layer: SiH4 flow rate 0.15sccm

C3H8 flow rate O.lOsccm

N2 flow rate 2xl0— ^{3 to} 0.3sccm (depends on sample)

H2 flow 3.0slm

Substrate temperature 1550 ° C

Growth time 150 minutes Active layer SiH4 W 0.50sccm

N2 flow rate 7xl0- ⁴ sccm

H2 flow 3.0slm

Substrate temperature 1550 ° C

Growth time 480 minutes

FIG. 6 shows the results of measuring rocking curves of X-ray diffraction for these samples (a) to (d) in the same manner as in Example 2. In sample (d) without the buffer layer, the degree of mosaic of the active layer increased due to the lattice mismatch between the active layer and the substrate, and the half-width of the opening curve was 86 arcsec, which was larger than that of the substrate (43 arcsec). On the other hand, sample (a), which has a buffer layer with a constant doving density, has a half-width of 35 arcsec, which is better than the substrate. In samples (b) and (c) where the donor density was gradually reduced inside the buffer layer, the half-value width was 28 to 3 larcsec, which was slightly better than sample (a). As described above, it has been found that it is most effective to provide the buffer layer 4 having the impurity density gradually reduced from the SiC substrate 2 to the active layer 6. It should be noted that no significant difference was observed between the case where the impurity density distribution inside the buffer layer 4 was reduced stepwise and the case where it was changed continuously (linearly).

[Example 4]

In this example, a high breakdown voltage diode shown in FIG. 7 was manufactured using a 4H—SiC (11-20) substrate and a SiC wafer using a (0001) 8 ° off substrate. The S iC substrate 2 was fabricated by slicing an ingot grown on a 4H-S i C (000-1) seed crystal by the modified Rayleigh method in parallel to the growth direction and mirror-polishing. Substrate are both n-type, the capacity of the Schottky barrier - the effective donors was determined from the voltage characteristic density 6 X 10 ¹⁸ cm- ^3, the thickness was about 340〃M. Then, a nitrogen-doped n-type 4H-SiC layer was epitaxially grown on the SiC substrate 2 by a CVD method.

As well as the sample (b) of Example 3, 3 x 10 ¹⁸ cm one ³ from 1 x 10 ¹⁶ cm one ³ or After forming a buffer layer 4 of about 11.5〃m in total, about 0.3〃m for each layer while changing the donor density stepwise, a high-purity n-type 4 H-S An i C layer was grown. The active layer has a donor density of 6 × ^{10 15} cm— ³ and a thickness of 16 zm. A sample without a buffer layer was also prepared for comparison. In addition, a buffer layer and an active layer were similarly grown on a 4H-SiC (00001) 8 ° off substrate to produce a SiC wafer. The main growth conditions are as follows.

Buffer layer: SiH4 flow rate 0.30sccm

C3H8 flow rate 0.20sccm

N2 flow rate 2xl0-3 ~ 0.5sccm

HH22 flow flow 3.0slm

1520 ° C

Growth time 60 minutes Active layer: SiH4 flow rate 0.50sccm

C3H8 flow rate 0.50sccm

N2 flow rate 4xl0-3sccm

H2 flow 3.0slm

Substrate temperature 1520 ° C

Growth time 240 minutes

Further, a Schottky electrode 12 and an ohmic electrode 14 were formed on each SiC wafer thus manufactured. The Schottky electrode 12 was formed on the upper surface of the active layer 6, and the ohmic electrode 14 was formed on the lower surface of the SiC substrate 2. The Schottky electrode 12 was made of titanium (Ti: 180 nm), and the back ohmic electrode 14 was made of nickel (Ni: 200 nm) heat-treated at 100 ° C. for 20 minutes. That is, a Schottky barrier is formed on the surface of the active layer 6 by the SiC active layer and the metal layer. In addition, the Schottky electrode 12 is circular, with a diameter of 100 1m to 3 mm. Was changed.

Then, in order to alleviate the electric field concentration at the end of the Schottky electrode 12, boron (B) ions were implanted to form a high-resistance p-type region (guard ring) 16, thereby completing a Schottky diode. Boron ion implantation was performed in four steps of 120 keV, 80 keV, 50 keV, and 30 keV, and the total dose was 3 × 10 ¹³ cm− ² . The width of the P-type region 16 forming the guard ring is 100 μm, and the width of the overlapping portion between the p-type region 16 and the Schottky electrode 12 is 1. The ion implantation was performed at room temperature, and the heat treatment (anneal) for activating the implanted ions was performed in an argon gas atmosphere at 1550 ° C. for 30 minutes. The photolithography technology was used for patterning the mask metal for selective ion implantation.

FIG. 8 is a graph showing typical current density-voltage characteristics of the produced Schottky diode. This is a diode fabricated on a 4H-SiC (11-20) SiC wafer grown with a buffer layer on it, and the electrode diameter is 500 m. To achieve the breakdown voltage 2100 V in reverse characteristics, moreover - leakage current at 1000V applied is small and ^{^{6 X 10- 6 A / cm 2}} . In the forward characteristics, excellent on-voltage (voltage drop at a current density of 10 OA / cm ² ) of 1.2 V and on-resistance of 4 × 10 ³ Ω cm ² were obtained. Similar diode characteristics were obtained on a 4H-SiC (0001) 8 ° off substrate in a small diode with an electrode area of 300 zm or less, but there was a large difference between the two in a diode with a large electrode area. Was seen.

Figure 9 shows a total of three types of 4H—SiC (11-20) substrates (with and without buffer layer) and 4H-SiC (0001) 8 ° off substrate, for a total of three types of SiC substrates. 4 is a graph showing the electrode area dependence of the breakdown voltage (average value) of a Schottky diode manufactured using a SoC wafer having an active layer grown thereon. For each electrode area, at least 12 diodes were measured and the average withstand voltage was determined. The 4H-S i C (0001) 8 ° Shodzutoki one Daiodo prepared by using the growth layer off the substrate, rapidly breakdown voltage when the electrode area is more than ^{^{5 X 10_ 3 cm 2 ~l X}} 10 one ² cm ² descend. 4H— Even in the case of a S i C (11-20) substrate, a diode having an electrode area larger than about 1 × 10 ¹² cm ² has a reduced breakdown voltage unless a buffer layer is provided.

In contrast, 4H-S i C in the case of using the Epitakisharu growth layer produced by providing a buffer layer (1 1 20) on the substrate, 5 10- ^² cm ² about the electrode area even higher breakdown voltage Even at 0.07 cm ² , a withstand voltage of 1500 V or more was obtained with a yield of 40% or more. In addition to the breakdown voltage, when comparing the average value of the leak current density when applying 1 000 V with a diode with an electrode diameter of 500 m, the diode fabricated on a 4H-SiC (000 1) 8 degree off substrate in ^{8 X 1 0_ 5 a / cm} 2, with respect to 6 X 10- ⁵ to a a / cm ² at Daiodo on without buffer layer (1 1 20) surfaces, provided Bruno couch layer (1 1 20) in Daio de on the surface was the smallest and ^{^{1 X 10- 5 a / cm 2}} .

This is because the use of the 4H—SiC (11-20) plane suppresses the penetration of micropipes and screw dislocations from the SiC substrate into the active layer, and the use of a buffer layer provides high quality SiC. This is probably because crystals were obtained. Also, the use of the 4H-SiC (11-20) plane improves the flatness of the growth surface, and also has the effect of reducing the electric field concentration at the Schottky electrode / SiC interface. In this embodiment, an example of manufacturing a Schottky diode has been described. However, even in the case of a pn junction diode サイ thyristor having a Pn junction formed by epitaxial growth or ion implantation, 4H-Si It is effective to use a C (11-20) substrate or a 15R-SiC (111-20) substrate.

[: Example 5]

In this example, an n-channel inversion type MOSFET 20 shown in FIG. 10 was manufactured using a SiC wafer formed by a (111-20) substrate and a (001) off substrate. The S i C substrate 2 used was fabricated by slicing an ingot grown by the modified Rayleigh method and polishing it to a mirror surface. (1) 6 H—S i C (000 1) 3.5-degree off substrate, (2) 6H-S i C (1 1 -20) substrate, (3) 4H-S i C (00 01) 8 ° off board, (4) 4H— S i C (1 1 -20) board, (5) 15R-S i C (000 1) 3. 5 ° off board, and (6) 15 R— S i C (11-20) substrate.

All the SiC substrates 2 are p-type, the effective peak density determined from the Schottky-barrier capacitance-voltage characteristics is 2 × 10 ¹⁸ cm— ³ to 5 × 10 ¹⁸ cm— ³ , and the thickness is 320 μm or more. 340 m. Then, a boron-doped P-type SiC layer was epitaxially grown on each SiC substrate 2 by a CVD method. First, as in the case of the sample (b) of Example 3, the thickness of each layer was about 0.4 μm while the step density was varied stepwise from 8 × 10 ¹⁷ cm- ³ to 1 × 10 ¹⁶ cm- ^3. After forming a buffer layer 4 having a total thickness of about 1.6 μm, a high-purity p-type SiC layer serving as an active layer 6 was grown. The active layer 6 has an average density of 5 × 10 ¹⁵ cm— ³ and a thickness of 5 μm. The main growth conditions are as follows.

Buffer layer: SiH4 flow rate 0.30sccm

C3H8 flow rate 0.20sccm

B2H6 flow rate 8xl0- ⁵ ~7xl0- ³ sccm

H2 flow 3.0slm

Substrate temperature 1500 ° C

Growth time 70 minutes Active layer: SiH4 flow rate 0.48sccm

C3H8 flow rate 0.64sccm

B2H6 flow rate 4xl0 " ⁶ sccm

H2 flow 3.0slm

Substrate temperature 1500 ° C

Growth time 120 minutes

The source and drain regions are further formed on the SiC wafer prepared as in For this purpose, low-resistance n-type regions 22 and 24 were formed by implanting nitrogen (N) ions. ΝIon implantation was performed in four stages of 14 Oke V, 80 keV, 50 keV, and 25 keV, and the total dose was 8 xl 0 ¹⁴ cm- ² . The ion implantation was performed at room temperature, and the heat treatment for activating the implantation ions was performed in an argon gas atmosphere at 1450 ° C. for 30 minutes. Next, an insulating layer 26 was formed on the SiC wafer 1 by dry oxidation. Oxidation conditions are 1 150 ° C for 3 hours when using the SiC (0001) off substrate, and 1 150 ° C for 1 hour for the SiC (1 1-20) sample. Layer 26 has a thickness of 35-46 nm.

Next, a source electrode 28 and a drain electrode 30 were formed on the n-type regions 22 and 24, respectively. Aluminum / titanium (A1:

Using a 250 dish, Ti: 30 nm), a heat treatment was performed at 800 ° C. for 60 minutes. Further, a gate electrode 32 (thickness: 200 nm) made of A1 is formed on the insulating layer 26, and then subjected to a heat treatment at 450 ° C. for 10 minutes in a forming gas (H ₂ ZN ₂ ). Was done. In addition, photolithography technology was used for the selective ion implantation mask and electrode metal patterning.

The channel length of the MOS FET 20 is set to 3 3 3, and the channel width is set to 200 m. Furthermore, when fabricating a MOS FET on the SiC (1 1 -20) plane, the drain current must flow in the <0001> direction or the <100> direction in consideration of the plane orientation. did.

FIG. 11 is a graph showing typical drain characteristics of the fabricated MOS FET. This is a characteristic of a MOS FET using an active layer grown on a 4H—SiC (11-20) substrate, with the channel parallel to the <0001> axis. The linear region and the saturation region are clearly observed, and the device operates well as a normally-off type MOS FET that turns off at zero gate bias. In the case of MO S FET using other samples, FET operation was confirmed, but differences were found in channel mobility and threshold voltage. Figure 12 shows the average of the effective channel mobilities obtained for each MOS FET from the linear region. The channel mobility was measured by evaluating at least 6 or more of the MOSFETs for each sample, and the average was determined. In addition, for MO SFETs fabricated on SiC (11-20) substrates, the channel mobility in the direction parallel to <0001> (〃), especially the 1-100> direction (the direction perpendicular to the <0001> axis) The channel mobility (〃丄) was determined, and the ratio was also shown.

As can be seen from Fig. 12, when comparing 6H-SiC, 4H-SiC, and 15R-SiC with 丄, the M〇 SFET fabricated on the (0001) off-substrate has a higher (11—20) plane. The higher channel mobility is obtained with the MOS FET prepared in Example 1. The reason is that in the active layer 6 on the (11_20) substrate, the surface roughness due to step bunching is reduced, an extremely flat MOS interface is obtained, and scattering due to the surface roughness is reduced. It is conceivable that it has been reduced. Furthermore, when comparing the (0001) substrate and the (11-20) substrate, the number of SiC bond bonds per unit area is smaller on the (11-20) plane, so that the number The lower the interface state density, the lower the (11-20) plane.

Next, comparing the characteristics of each polytype, the S of the MOS FET on the 6H—SiC (11-20) substrate is relatively high at 74 cm ² / Vs, but the 〃丄 is 22 cm ² / Vs And small. This is similar to the electron mobility anisotropy in the 6HSiC bulk, and is thought to be due to the effective mass and the anisotropy of the scattering factor. In any case, a device exhibiting more than three times the anisotropy of electrical conduction in the plane is undesirable. In the case of 4H-SiC, the channel mobility is as small as 8.4 cm ² / Vs in MOSF ET on the (0001) 8 ° off substrate, but 〃丄 = 46 cm on the (11-20) substrate ² / Vs, u // = 55 cm ² / Vs, which are relatively good values and small in anisotropy. On the other hand, for MOSF ET on a 15 R—SiC (11-20) substrate, 〃丄 = 76 cm ² / Vs and 〃〃 = 64 cm ² / V s, indicating higher channel mobility than 4H-SiC. Obtained. From the above results, 4H— S iC (11— 20) or 15R—MOMO SFETs fabricated on SiC (11-20) substrates have high channel mobility and low anisotropy, so high-performance MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), It is effective for making gate thyrists and the like.

Although an insulating layer 26 for the gate electrode by a thermal oxidation, using even 4H-S i C or 15R- S i C (11-20) when depositing the S I_〇 ₂ film by CVD here Is effective. In addition, here we fabricated an inverting MOSFET to investigate the characteristics of the MOS interface, but using 4H-SiC or 15R-SiC (l 1-20) gives good oxide / SiC interface characteristics. Can be obtained, so that it can be applied to other device fabrication. For example, when a surface protection film having an oxide film as a first layer is formed on a SoC semiconductor device by thermal oxidation or chemical vapor deposition, very stable interface characteristics with a low carrier generation rate at the interface can be obtained. Can be Industrial applicability

As described above, according to the SiC wafer according to the present invention, since the SiC substrate having a plane orientation of approximately (11-20) is used, an active SiC layer is formed on the wafer. Even with xy growth, micropipes and screw dislocations extending in the <0001> axis direction of the SiC substrate do not reach the active layer. In addition, since a 4H-type or 15R-type polytype substrate, which has a smaller anisotropy in electron mobility than a 6H-type SiC substrate, is used, it can be grown on a SiC wafer. The anisotropy of electron mobility in the activated layer is reduced. Furthermore, since the buffer layer made of SiC is formed on the SiC substrate, when the SiC active layer is grown on the wafer, the 3; 1 ( It is possible to prevent a situation in which distortion due to lattice mismatch occurs in the SiC active layer.

Claims

The scope of the claims

1. SiC substrate of 4H polytype or 15R polytype, whose plane orientation is almost (11-20),

A buffer layer made of SiC formed on the SiC substrate,

An S i C wafer comprising:

2. The SiC wafer according to claim 1, wherein the buffer layer has a thickness of 0.3 to 15 m.

3. the buffer layer comprises at least one of nitrogen, phosphorus, aluminum, or boron as an impurity;

Density of the impurity in said buffer ^{layer, 2 X 1 0 15 c m_} 3 or 3 X 10 ¹⁹ cm one ³ S i C © perillaヽof claim 1 or claim 2, wherein the less.

4. The SiC wafer according to claim 3, wherein the density of the impurities in the buffer layer is lower than the density of the impurities in the SiC substrate.

5. The SiC wafer according to claim 1, further comprising an active layer made of SiC on the buffer layer.

6. The method according to claim 5, wherein the density of the impurities in the buffer layer decreases from an interface with the SiC substrate to an interface with the SiC active layer. S i. Wafer.

7. An SiC semiconductor device comprising the SiC wafer according to claim 5 or 6.

8. The SiC semiconductor according to claim 1, wherein a metal layer is provided on a surface of the SiC active layer, and a Schottky barrier is formed by the active layer and the metal layer. device.

9. Has pn junction formed by epitaxial growth or ion implantation 8. The SiC semiconductor device according to claim 7, wherein:

10. The SiC semiconductor device according to claim 7, comprising an oxide film formed by thermal oxidation or chemical vapor deposition as a gate insulating film.

11. The SiC semiconductor device according to claim 7, comprising an oxide film formed by thermal oxidation or chemical vapor deposition as a part of the surface protective film.

1 2. A buffer layer composed of SiC is grown on a 4H-type or 15R-type polytype SiC substrate having a plane orientation of approximately (11-20). Manufacturing method of SiC wafer.

13. The method for manufacturing a SiC wafer according to claim 12, wherein an active layer made of SiC is further grown on the buffer layer.