WO1999060480A1

WO1999060480A1 - Shared, reconfigurable cache memory execution subsystem

Info

Publication number: WO1999060480A1
Application number: PCT/US1998/010065
Authority: WO
Inventors: Richard Rubinstein
Original assignee: Richard Rubinstein
Priority date: 1998-05-15
Filing date: 1998-05-15
Publication date: 1999-11-25
Also published as: AU7575398A

Abstract

A shared, reconfigurable cache memory system is accessible to both a host processor or CPU and to one or more execution units. The execution unit is tightly coupled to the memory for concurrent execution under control of a local micro-coded controller. The controller executes micro-code stored in ROM, on board the controller or in the cache itself, and provides address generation. The cache combines SRAM and DRAM technologies to improve density and lower cost, while a 'look-ahead' read strategy maintains SRAM performance. The controller and micro-code provide control and parameters to the execution unit to support computation intensive tasks such as DSP without processor intervention. The described cache memory execution subsystem operates over a standard CPU or memory interface.

Description

SHARED, RECONFIGURABLE CACHE MEMORY EXECUTION SUBSYSTEM

Related application data:

This application is a continuation-in-part of co-pending application Serial no. 08/821326 filed March 21 , 1997. The prior application is incorporated herein by this reference to the extent that portions of it are not included below.

FIELD OF THE INVENTION

The present invention is generally in the field of digital computing and, more specifically, is directed to an execution subsystem that combines shared, reconfigurable memory techniques together with a micro-coded controller in the context of a cache memory system.

BACKGROUND OF THE INVENTION The prior application, entitled "Shared, Reconfigurable Memory Architectures for Digital Signal Processing" described the need to improve digital signal processing performance while containing or reducing cost. That application describes improved computer architectures that utilize available memory resources more efficiently by providing for shared and reconfigurable memory so as to reduce I/O processor requirements for computation intensive tasks such as digital signal processing. The memory systems described in the prior case are shared in the sense that a given block of memory can first be configured for access by the CPU, for example to load data, and then "swapped" so that the same block of physical memory can be directly accessed by an execution unit, for example a DSP execution unit, to carry out various calculations on that data. After the calculations are completed, the same block of memory can be "swapped" once again, so that the CPU has immediate access to the results. The memory is reconfigurable in a variety of ways, as described below, so as to allocate memory resources as between the CPU and the execution unit (or multiple execution units) in the most efficient manner possible. Reconfiguring the memory can include forming memory 5 blocks of various sizes; selecting write (input) sources; selecting read (destination) targets; selecting word size, and so forth. Various particulars and alternative embodiments are set forth below, so as to enable one skilled in the art to implement shared, reconfigurable memory architectures.

The parent case described the invention with reference to digital signal o processing. However, DSP is just one example of computation-intensive calculation. The concepts of the prior case as well as the present invention are applicable to a wide variety of execution tasks, including but not limited to DSP and related tasks such as motion picture encoding, decoding, and encryption, decryption, etc. Moreover, the principles of the parent application can be applied advantageously in the context of a cache memory. 5 Accordingly, the present specification adds additional disclosure directed to application of shared, configurable memory and tightly coupled execution units to the cache memory context.

Another aspect of the prior application is a memory-centric DSP controller ("MDSPC"). The MDSPC was described as providing memory address generation and a o variety of other control functions, including reconfiguring the memory as summarized above to support a particular computation in the execution unit. The name "MDSPC" was appropriate for that controller in the context of the parent case, in which the preferred embodiment was described for digital signal processing. However, the principles of the parent case and the present invention are not so limited. Accordingly, the present 5 application includes description of a "controller" which is functionally similar to the "MDSPC" introduced in the parent case. Drawing Figs. 1-22 and the corresponding description herein were included in the parent application. The present application includes additional drawing Figs. 23-28. SUMMARY OF THE INVENTION

The parent application describes a memory subsystem that is partitioned into two or more blocks of memory space. One block of the memory communicates with an I/O or 5 DMA channel to load data, while the other block of memory simultaneously communicates with one or more execution units that carry out arithmetic operations on data in the second block. Results are written back to the second block of memory. Upon conclusion of that process, the memory blocks are effectively "swapped" so that the second block, now holding processed (output) data, communicates with the I/O channel to output that data, o while the execution unit communicates with the first block, which by then has been filled with new input data. Methods and apparatus are shown for implementing this memory swapping technique in real time so that the execution unit is never idle. The present application extends these concepts to cache memory.

Another aspect of the parent case describes interfacing two or more address 5 generators to the same block of memory, so that memory block swapping can be accomplished without the use of larger multi-ported memory cells. The present application extends these concepts to cache memory as well.

The parent application identified earlier describes the concept of reconfiguring an execution unit in several ways, including selectable depth (number of pipeline stages) and o width (i.e. multiple word sizes concurrently). Preferably the pipelined execution unit(s) includes internal register files with feedback. The execution unit configuration and operation also can be controlled by execution unit configuration control signals. The execution unit configuration control signals can be determined by "configuration bits" stored in the memory, or stored in a separate "configuration table". The configuration table 5 can be downloaded by the host core processor, and/or updated under software control. Preferably, the configuration control signals are generated by the controller mentioned above executing microcode.

This combination of reconfigurable memory, together with reconfigurable execution units, and the associated techniques for efficiently moving data between them, provides an architecture that is highly flexible. Microcoded software can be used to take advantage of this architecture so as to achieve new levels of performance. Because the circuits described herein require only one-port or two-port memory cells, they allow higher density and the associated advantages of lowered power dissipation, reduced capacitance, etc. in the preferred integrated circuit embodiments, whether implemented as a stand-alone coprocessor, or together with a standard processor core, or by way of modification of an existing processor core design. An important feature of the architectures described herein is that they provide a tightly coupled relationship between memory and execution units. This feature provides the advantages of reducing internal interconnect requirements, thereby lowering power consumption. In addition, the invention provides for doing useful work on virtually all clock cycles. This feature minimizes power consumption as well. The present application extends these concepts to cache memory systems.

One object of the present invention therefore is to reduce the effective cost of cache memory by utilizing DRAM technology. Another object of the invention is to provide improved cache memory performance at reduced cost by deploying a combination of SRAM and DRAM technologies in a cache memory.

Another object of the present invention is to improve performance in execution of complex operations by tightly coupling a cache memory to an execution unit. A further object of the invention is to improve effective cache density and reduce costs through new applications of DRAM memory cells, combined with a new local cache memory controller strategy.

Yet another object of the present invention is to apply reconfigurable memory circuits and methodologies to improve performance in connection with cache memory applications. A still further object is to apply shared, reconfigurable DRAM memory circuits and methodologies to cache memory applications in order to build high performance computing engines. A further object is to provide for concurrent execution of a calculation using a tightly coupled execution unit, while allowing concurrent access to a cache memory subsystem by the CPU. One aspect of the present invention is a cache memory subsystem that includes a microprogrammable controller. The subsystem also includes address selection circuitry so as to provide a selected address to the cache memory from any of several address sources. The address sources can include the CPU address bus, the local controller, and 5 potentially another circuit arranged for addressing the memory in connection with downloading execution parameters.

The controller executes microcode which can be stored in any of at least three places. First, the microcode can be stored on board the local controller. Second, the microcode can be stored in a separate read-only memory, e.g., ROM or flash memory. o Third, the microcode can be stored in the data portion of the cache memory.

Another aspect of the invention provides for downloading microcode from the CPU into a portion of the cache data memory for subsequent execution by the local controller. The microcode can include configuration bits, op-codes for the execution unit, contants, parameters, etc. which the controller in turn provides to the execution unit. A further 5 aspect of the invention includes providing an address decoder coupled to the CPU address line, for detecting assertion of a predetermined address that is used to trigger a particular execution. In response to detecting the predetermined address, the controller then configures the execution unit as appropriate, and begins execution of a microcoded sequence to carry out the corresponding calculation in the execution unit. By applying the o principles of shared, reconfigurable memory architecture as described in the parent case, these aspects can be implemented while allowing for concurrent access to the cache memory by the CPU. Upon completion of its task in the execution unit, the controller can notify the CPU, for example by writing control bits to a special memory address monitored by the CPU. 5 The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system level block diagram of an architecture for digital signal processing (DSP) using shared memory according to the present invention. 5 FIG. 2 illustrates circuitry for selectively coupling two or more address generators to a single block of memory.

FIG. 3 is a block diagram illustrating portions of the memory circuitry and address generators of Fig. 1 in a fixed-partition memory configuration.

FIG. 4 shows more detail of address and bit line connections in a two-port memory o system of the type described.

FIGS. 5A-5C illustrate selected address and control signals in a Processor Implementation of a DSP system, i.e. a complete DSP system integrated on a single chip.

FIG. 6A illustrates an alternative embodiment in which a separate DSP program counter is provided for accessing the memory. 5 FIG. 6B illustrates an alternative embodiment in which an MDSPC accesses the memory.

FIGS. 7A-B are block diagrams that illustrate embodiments of the invention in a Harvard architecture.

FIG. 8 is a conceptual diagram that illustrates a shared, reconfigurable memory o architecture according to the present invention.

FIG. 9 illustrates connection of address lines to a shared, reconfigurable memory with selectable (granular) partitioning of the reconfigurable portion of the memory.

FIG. 10 illustrates a system that implements a reconfigurable segment of memory under bit selection table control. 5 FIG. 11A is a block diagram illustrating an example of using single-ported RAM in a DSP computing system according to the present invention.

FIG. 11 B is a table illustrating a pipelined timing sequence for addressing and accessing the one-port memory so as to implement a "virtual two-port" memory.

FIG. 12 illustrates a block of memory having at least one reconfigurable segment with selectable write and read data paths.

FIG. 13A is a schematic diagram showing detail of one example of the write selection circuitry of the reconfigurable memory of Fig. 12.

FIG. 13B illustrates transistor pairs arranged for propagating or isolating bit lines 5 as an alternative to transistors 466 in Fig. 13A or as an alternative to the bit select transistors 462, 464 of Fig. 13A.

FIG. 14 is a block diagram illustrating extension of the shared, reconfigurable memory architecture to multiple segments of memory.

FIG. 15 is a simplified block diagram illustrating multiple reconfigurable memory o segments with multiple sets of sense amps.

FIGS. 16A-16D are simplified block diagrams illustrating various examples of memory segment configurations to form memory blocks of selectable size.

FIG. 17 is a block diagram of a DSP architecture illustrating a multiple memory block to multiple execution unit interface scheme in which configuration is controlled via 5 specialized address generators.

FIGS. 18A-18C are simplified block diagrams illustrating various configurations of segments of a memory block into association with multiple execution units.

FIG. 19 is a simplified block diagram illustrating a shared, reconfigurable memory system utilizing common sense amps. o FIG. 20 is a simplified block diagram illustrating a shared, reconfigurable memory system utilizing multiple sense amps for each memory segment.

FIG. 21 is a timing diagram illustrating memory swapping cycles.

FIG. 22A is a block diagram illustrating memory swapping under bit table control.

FIG. 22B is a block diagram illustrating memory swapping under MDSPC control. 5 FIG. 23 is a simplified block diagram of a known cache memory system.

FIG. 24 is a block diagram of a memory-centric architecture having an execution unit tightly coupled to a cache memory under control of a memory-centric controller.

FIG. 25 is a simplified block diagram of a hybrid SRAM and DRAM cache memory system. FIG. 26 illustrates read data transfer from a cache memory utilizing SRAM and DRAM memory latching techniques.

FIG. 27 is a block diagram illustrating one method of loading microcode data into the memory-centric controller of Fig. 24. FIG. 28 is a block diagram illustrating deployment of a block of cache data memory as micro-code storage for execution in the the memory-centric controller of Fig. 24.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIGURE 1

Fig. 1 is a system-level block diagram of an architecture for memory and computing-intensive applications such as digital signal processing. In Fig. 1 , a microprocessor interface 40 includes a DMA port 42 for moving data into a memory via path 46 and reading data from the memory via path 44. Alternatively, a single, bidirectional port could be used. The microprocessor interface 40 generically represents an interface to any type of controller or microprocessor. The interface partition indicated by the dashed line 45 in Fig. 1 may be a physical partition, where the microprocessor is in a separate integrated circuit, or it can merely indicate a functional partition in an implementation in which all of the memory and circuitry represented in the diagram of Fig. 1 is implemented on board a single integrated circuit. Other types of partitioning, use of hybrid circuits, etc., can be used. The microprocessor interface (DMA 42) also includes control signals indicated at 52. The microprocessor or controller can also provide microcode (not shown) for memory control and address generation, as well as control signals for configuration and operation of the functional execution units, as described later.

Because the present invention may be integrated into an existing processor or controller core design, so that both the core processor and the present invention reside in the same integrated circuit, reference will be made herein to the core processor meaning the processor that the present invention has been attached to or integrated with.

In Fig. 1 , a two-port memory comprises the first memory block 50, labeled "A" and a second memory block 60, labeled "B." The memory is addressed by a source address generator 70 and a destination address generator 80. A functional execution unit 90 also 5 is coupled to the two-port memory, left and right I/O channels, as illustrated at block B. Preferably, these are not conventional two-port memory I/O ports; rather, they have novel structures described later.

In operation, the interface 44, 46 to the two-port memory block A is a DMA interface that is in communication with the host processor or controller 40. Block A o receives data coefficients and optionally other parameters from the controller, and also returns completed data to the controller that results from various DSP, graphics, MPEG encode/decode or other operations carried out in the execution unit 90. This output data can include, for example, FFT results, or convolution data, or graphics rendering data, etc. Thus the single memory can alternately act as both a graphics frame buffer and a 5 graphics computation buffer memory.

Concurrently, the memory block "B" (60) interfaces with the functional execution unit 90. The functional execution unit 90 receives data from the two-port memory block B and executes on it, and then returns results ("writeback") to the same two-port memory structure. The source address generator 70 supplies source or input data to the functional o execution unit while the destination address generator 80 supplies addresses for writing results (or intermediate data) from the execution unit to the memory. Put another way, source address generator 70 provides addressing while the functional execution unit is reading input data from memory block B, and the destination address generator 80 provides addressing to the same memory block B while the functional execution unit 90 is 5 writing results into the memory.

As mentioned above, when the execution unit has completed its work on the data in block B, the memory effectively "swaps" blocks A and B, so that block B is in communication with the DMA channel 42 to read out the results of the execution. Conversely, and simultaneously, the execution unit proceeds to execute on the new input data in block A. This "swapping" of memory blocks includes several aspects, the first of which is switching the memory address generator lines so as to couple them to the appropriate physical block of memory.

In an alternative embodiment, the system can be configured so that the entire 5 memory space (blocks A and B in the illustration) are accessed first by an I/O channel, and then the entire memory swapped to be accessed by the processor or execution unit. In general, any or all of the memory can be reconfigured as described. The memory can be SRAM, DRAM or any other type of random access semiconductor memory or functionally equivalent technology. DRAM refresh is provided by address generators, or may not be l o required where the speed of execution and updating the memory (access frequency) is sufficient to obviate refresh.

FIGURE 2

15 Figure 2 illustrates one way of addressing a memory block with two (or more) address generators. Here, one address generator is labeled "DMA" and the other "ADDR GEN" although they are functionally similar. As shown in Fig. 2, one of the address generators 102 has a series of output lines, corresponding to memory word lines. Each output line is coupled to a corresponding buffer (or word line driver or the like), 130 to 140.

2 o Each driver has an enable input coupled to a common enable line 142. The other address generator 104 similarly has a series of output lines coupled to respective drivers 150 to 160. The number of word lines is at least equal to the number of rows of the memory block 200. The second set of drivers also have enable inputs coupled to the common enable control line 142, but note the inverter "bubbles" on drivers 130 to 140,

25 indicating the active-low enables of drivers 150 to 160. Accordingly, when the control line 142 is low, the DMA address generator 102 is coupled to the memory 200 row address inputs. When the control line 142 is high, the ADDR GEN 104 is coupled to the memory 200 row address inputs. In this way, the address inputs are "swapped" under control of a single bit. Alternative circuitry can be used to achieve the equivalent effect. For example, the devices illustrated can be tri-state output devices, or open collector or open drain structures can be used where appropriate. Other alternatives include transmission gates or simple pass transistors for coupling the selected address generator outputs to the memory address lines. The same strategy can be extended to more than two address sources, as will be apparent to those skilled in the art in view of this disclosure.

FIGURE 3

Figure 3 is a block diagram illustrating a physical design of portions of the memory circuitry and address generators of Fig. 1 in a fixed-partition configuration. By "fixed partition" I mean that the size of memory block A and the size of memory block B cannot change dynamically, in Fig. 3, the memory block A (50) and block B (60) correspond to the same memory blocks of Fig. 1. The memory itself preferably is dynamic RAM, although static RAM or other solid state memory technologies could be used as well. In memory block B, just two bits or memory cells 62 AND 64 are shown by way of illustration. In a typical implementation, the memory block is likely to include thousands or even millions of rows, each row (or word) being perhaps 64 or more bits wide. A typical memory block using today's technology is likely to be one or two megabytes. The memory blocks need not be of equal size. Neither memory depth nor word size is critical to the invention. Two bits are sufficient here to illustrate the concept without unduly complicating the drawing. The source address generator 70 is coupled to both memory blocks A and B. In block B, the top row includes a series of cells including bit cell 62. In fact, the source address generator preferably has output lines coupled to all of the rows of not only block B, but block A as well, although only one row line is illustrated in block A. Note also that corresponding address lines from the AG 70 and the DMA 102 are shown as connected in common, e.g. at line 69. However, in practice, these address lines are selectable as described above with reference to Fig. 2.

A destination address generator 80 similarly is coupled to the row lines of both blocks of memory. Memory cells 62 and 64 are full two-ported cells on the same column in this example. Thus, either source AG 70 or DMA 102 address the left port, while either destination AG 80 or DMA 100 address the right port. A write select multiplexer 106 directs data either from the DMA (42 in Fig. 1) (or another block of memory) or from the execution unit 90, responsive to a control signal 108. The control signal is provided by the controller or microprocessor of Fig, 1 , by a configuration bit, or by an MDSPC. The selected write data is provided to column amplifiers 1 10, 112 which in turn are connected to corresponding memory cell bit lines. 110 and 112 are bit and /bit ("bit bar") drivers. Below cell 64 is a one-bit sense amplifier 116. A bit output from the sense amp 1 16 is directed, for example, to a latch 72. Both the DMA and the execution unit are coupled to receive data from latch 72, depending on appropriate control, enable and clock signals (not shown here). Or, both the DMA and the execution path may have separate latches, the specifics being a matter of design choice. Only one sense amp is shown for illustration, while in practice there will be at least one sense amp for each column. Use of multiple sense amps is described later.

FIGURE 4

Fig. 4 shows more detail of the connection of cells of the memory to source and destination address lines. This drawing shows how the source address lines (when asserted) couple the write bit line and its complement, i.e. input lines 110,112 respectively, to the memory cells. The destination address lines couple the cell outputs to the read bit lines 114, 1 15 and thence to sense amp 116. Although only one column is shown, in practice write and read bit lines are provided for each column across the full width of the memory word. The address lines extend across the full row as is conventional.

FIGURES 21 , 22A AND 22B Timing

Fig. 21 is a conceptual diagram illustrating an example for the timing of operation of the architecture illustrated in Fig. 1. T0A, T1A, etc., are specific instances of two operating time cycles TO and T1. The cycle length can be predetermined, or can be a parameter downloaded to the address generators. TO and T1 are not necessarily the same length and are defined as alternating and mutually exclusive, i.e. a first cycle T1 starts at the end of TO, and a second cycle TO starts at the end of the first period T1 , and so on. Both TO and T1 are generally longer than the basic clock or memory cycle time. Fig. 22A is a block diagram of a single port architecture which will be used to 5 illustrate an example of functional memory swapping in the present invention during repeating TO and T1 cycles. Execution address generator 70 addresses memory block A (50) during TO cycles. This is indicated by the left (TO) portion of AG 70. During T1 cycles, execution address generator 70 addresses memory block B (60), as indicated by the right portion of 70. During T1 , AG 70 also receives setup or configuration data in preparation o for again addressing Mem Block A during the next TO cycle. Similarly, during TO, AG 70 also receives configuration data in preparation for again addressing Mem Block B during the next T1 cycle.

DMA address generator 102 addresses memory block B (60) during TO cycles. This is indicated by the left (TO) portion of DMA AG 102. During T1 cycles, DMA address 5 generator 102 addresses memory block A (50), as indicated by the right portion of 102. During T1 , DMA AG 102 also receives setup or configuration data in preparation for again addressing Mem Block B during the next TO cycle. Similarly, during TO, DMA 102 also receives configuration data in preparation for again addressing Mem Block A during the next T1 cycle. 0 During a TO cycle, the functional execution unit (90 in Fig. 1) is operating continuously on data in memory block A 50 under control of execution address generator 70. Simultaneously, DMA address generator 102 is streaming data into memory block B 60.

At the beginning of a T1 cycle, memory blocks A and B effectively swap such that 5 execution unit 90 will process the data in memory block B 60 under control of execution address generator 70 and data will stream into memory block A 50 under control of DMA address generator 102. Conversely, at the beginning of a TO cycle, memory blocks A and B again effectively swap such that execution unit 90 will process the data in memory block A 50 under control of execution address generator 70 and data will stream into memory block B 60 under control of DMA address generator 102.

In Fig. 22B, the functions of the execution address generator and DMA address generator are performed by the MDPSC 172 under microcode control.

FIGURES 5A-C

Processor implementation

The preferred architecture for implementation in a processor application, as distinguished from a coprocessor application, is illustrated in Figs. 5A-C. In Fig. 5A, a two- port memory again comprises a block A (150) and a block B (160). Memory block B is coupled to a DSP execution unit 130. An address generator 170 is coupled to memory block B 160 via address lines 162. In operation, as before, the address generator unit is executing during a first cycle TO and during time TO is loading parameters for subsequent execution in cycle T1. The lower memory block A is accessed via core processor data address register 142A or core processor instruction address register 142B. Thus, in this illustration, the data memory and the instructional program memory are located in the same physical memory. A microprocessor system of the Harvard architecture has separate physical memory for data and instructions. The present invention can be used to advantage in the Harvard architecture environment as well, as described below with reference to Figs. 7A and 7B.

Bit Configuration Tables

Fig. 5A also includes a bit configuration table 140. The bit configuration table can receive and store information from the memory 150 or from the core processor, via bus 180, or from an instruction fetched via the core processor instruction address register 142B. Information is stored in the bit configuration table during cycle TO for controlling execution during the next subsequent cycle T1. The bit configuration table can be loaded by a series of operations, reading information from the memory block A via bus 180 into the bit configuration tables. This information includes address generation parameters and opcodes. Examples of some of the address parameters are starting address, modulo- address counting, and the length of timing cycles TO and T1. Examples of op codes for controlling the execution unit are the multiply and accumulate operations necessary for to perform an FFT.

Essentially, the bit configuration table is used to generate configuration control 5 signal 152 which determines the position of virtual boundary 136 and, therefore, the configuration of memory blocks A and B. It also provides the configuration information necessary for operation of the address generator 170 and the DSP execution unit 130 during the T1 execution cycle time. Path 174 illustrates the execution unit/memory interface control signals from the bit configuration table 140 to the DSP execution unit 130. o Path 176 illustrates the configuration control signal to the execution unit to reconfigure the execution unit. Path 178 illustrates the op codes sent to execution unit 130 which cause execution unit to perform the operations necessary to process data. Path 188 shows configuration information loaded from the configuration tables into the address generator 170. 5 The architecture illustrated in Fig. 5A preferably would utilize the extended instructions of a given processor architecture to allow the address register from the instruction memory to create the information flow into the bit configuration table. In other words, special instructions or extended instructions in the controller or microprocessor architecture can be used to enable this mechanism to operate as described above. Such 0 an implementation would provide tight coupling to the microprocessor architecture.

Memory-centric DSP Controller

Fig. 5B illustrates an embodiment of the present invention wherein the functions of address generator 170 and bit configuration table 140 of Fig. 5A are performed by 5 memory-centric DSP controller (MDSPC) 172. In the embodiment shown in Fig. 5B, the core processor writes microcode for MDSPC 172 along with address parameters into memory block B 150. Then, under core processor control, the microcode and address parameters are downloaded into local memory within MDSPC 172.

A DSP process initiated in MDPSC 172 then generates the appropriate memory configuration control signals 152 and execution unit configuration control signals 176 based upon the downloaded microcode to control the position of virtual boundary 136 and structure execution unit 130 to optimize performance for the process corresponding to the microcode. As the DSP process executes, MDSPC 172 generates addresses for memory block B 160 and controls the execution unit/memory interface to load operands from memory into the execution unit 130 which are then processed by execution unit 130 responsive to op codes 178 sent from MDSPC 172 to execution unit 130. in addition, virtual boundary 136 may be adjusted responsive to microcode during process execution in order to dynamically optimize the memory and execution unit configurations. In addition, the MDSPC 172 supplies the timing and control for the interfaces between memory and the execution unit. Further, algorithm coefficients to the execution unit may be supplied directly from the MDSPC. The use of microcode in the MDSPC results in execution of the DSP process that is more efficient than the frequent downloading of bit configuration tables and address parameters associated with the architecture of Fig. 5A. The microcoded method represented by the MDSPC results in fewer bits to transfer from the core processor to memory for the DSP process and less frequent updates of this information from the core processor. Thus, the core processor bandwidth is conserved along with the amount of bits required to store the control information. Fig. 5C illustrates an embodiment of the present invention wherein the reconfigurability of memory in the present invention is used to allocate an additional segment of memory, memory block C 190, which permits MDPSC 172 to execute microcode and process address parameters out of memory block C 190 rather than local memory. This saves the time required for the core processor controlled download of microcode and address parameters to local memory in MDSPC 172 that takes place in the embodiment of Fig. 5B. This embodiment requires an additional set of address 192 and data 194 lines to provide the interface between memory block C 190 and MDSPC 172 and address bus control circuitry 144 under control of MDSPC 172 to disable the appropriate address bits from core processor register file 142. This configuration permits simultaneous access of MDSPC 172 to memory block C 190, DSP execution unit 130 to memory block B and the core processor to memory block A.

Similar to the embodiments shown in Figs. 5A and 5B, virtual boundaries 136A and 136B are dynamically reconfigurable to optimize the memory configuration for the DSP process executing in MDSPC 172.

The bit tables and microcode discussed above may alternatively reside in durable store, such as ROM or flash memory. The durable store may be part of memory block A or may reside outside of memory block A wherein the content of durable store is transferred to memory block A or to the address generators or MDSPC during system initialization. Furthermore, the DSP process may be triggered by either decoding a preselected bit pattern corresponding to a DSP function into an address in memory block A containing the bit tables or microcode required for execution of the DSP function. Yet another approach to triggering the DSP process is to place the bit tables or microcode for the DSP function at a particular location in memory block A and the DSP process is triggered by the execution of a jump instruction to that particular location. For instance, at system initialization, the microcode to perform a DSP function, such as a Fast Fourier Transform (FFT) or HR, is loaded beginning at a specific memory location within memory block A. Thereafter, execution of a jump instruction to that specific memory location causes execution to continue at that location thus spawning the DSP process.

FIGURES 6A and 6B

Referring now to Fig. 6A, in an alternative embodiment, a separate program counter 190 is provided for DSP operations. The core controller or processor (not shown) loads information into the program counter 190 for the DSP operation and then that program counter in turn addresses the memory block 150 to start the process for the DSP. Information required by the DSP operations would be stored in memory. Alternatively, any register of the core processor, such as data address register 142A or instruction address register 142B, can be used for addressing memory 150. Bit Configuration Table 140, in addition to generating memory configuration signal 152, produces address enable signal 156 to control address bus control circuitry 144 in order to select the address register which accesses memory block A and also to selectively enable or disable address lines of the registers to match the memory configuration (i.e. depending on the position of virtual boundary 136, address bits are enabled if the bit is needed to access all of memory block A and disabled if block A is smaller than the memory space accessed with the address bit).

Thus, Fig. 6A shows the DSP program counter 190 being loaded by the processor with an address to move into memory block A. In that case, the other address sources in register file 142 are disabled, at least with respect to addressing memory 150. In short, three different alternative mechanisms are illustrated for accessing the memory 150 in order to fetch the bit configurations and other parameters 140. The selection of which addressing mechanism is most advantageous may depend upon the particular processor architecture with which the present invention is implemented.

Fig. 6B shows an embodiment wherein MDSPC 172 is used to generate addresses for memory block A in place of DSP PC 190. Address enable signal 156 selects between the address lines of MDSPC 172 and those of register file 142 in response to the microcode executed by MDSPC 172. As discussed above, if the microcode for MDSPC 172 resides in memory block A or a portion thereof, MDSPC 172 will be executing out of memory block A and therefore requires access to the content of memory block A,

Memory Arrangement

Referring again to Fig. 5, memory blocks A (150) and B (160) are separated by "virtual boundary" 136. In other words, block A and block B are portions of a single, common memory, in a preferred embodiment. The location of the "virtual boundary" is defined by the configuration control signal generated responsive to the bit configuration table parameters. In this regard, the memory is reconfigurable under software control. Although this memory has a variable boundary, the memory preferably is part of the processor memory, it is not contemplated as a separate memory distinct from the processor architecture. In other words, in the processor application illustrated by Figs. 5 and 6, the memory as shown and described is essentially reconfigurable directly into the microprocessor itself. In such a preferred embodiment, the memory block B, 160, duly configured, executes into the DSP execution unit as shown in Fig. 5. 5 In regard to Fig. 5B, virtual boundary 136 is controlled based on the microcode downloaded to MDSPC 172. Similarly, in Fig. 5C, microcode determines the position of both virtual boundary 136A and 136B to create memory block C 190.

FIGURES 7A and 7B ι o Fig. 7A illustrates an alternative embodiment, corresponding to Fig. 5A, of the present invention in a Harvard-type architecture, comprising a data memory block A 206 and block B 204, and a separate core processor instruction memory 200. The instruction memory 200 in addressed by a program counter 202. Instructions fetched from the instruction memory 200 pass via path 220 to a DSP instruction decoder 222. The

15 instruction decoder in turn provides addresses for DSP operations, table configurations, etc., to an address register 230. Address register 230 in turn addresses the data memory block A 206. Data from the memory passes via path 240 to load the bit configuration tables etc. 242 which in turn configure the address generator for addressing the data memory block B during the next execution cycle of the DSP execution unit 250. Fig, 6

2 o thus illustrates an alternative approach to accessing the data memory A to fetch bit configuration data. A special instruction is fetched from the instruction memory that includes an opcode field that indicates a DSP operation, or more specifically, a DSP configuration operation, and includes address information for fetching the appropriate configuration for the subroutine.

25 In the embodiment of Fig. 7B, corresponding to the embodiments in Figs, 5B and

5C, MDPSC 246 replaces AG 244 and Bit Configuration Table 242. Instructions in core processor instruction memory 200 that correspond to functions to be executed by DSP Execution Unit 250 are replaced with a preselected bit pattern which is not recognized as a valid instruction by the core processor. DSP Instruction Decode 222 decodes the preselected bit patterns and generates an address for DSP operations and address parameters stored in data memory A and also generates a DSP control signal which triggers the DSP process in MDSPC 246. DSP Instruction Decode 222 can also be structured to be responsive to output data from data memory A 206 into producing the 5 addresses latched in address register 230.

The DSP Instruction Decode 222 may be reduced or eliminated if the DSP process is initiated by an instruction causing a jump to the bit table or microcode in memory block A pertaining to the execution of the DSP process.

To summarize, the present invention includes an architecture that features shared, o reconfigurable memory for efficient operation of one or more processors together with one or more functional execution units such as DSP execution units. Fig. 6A shows an implementation of a sequence of operations, much like a subroutine, in which a core controller or processor loads address information into a DSP program counter, in order to fetch parameter information from the memory. Fig. 6B shows an implementation wherein 5 the DSP function is executed under the control of an MDSPC under microcode control. In Figs. 5A-C, the invention is illustrated as integrated with a von Neumann microprocessor architecture. Figs. 7A and 7B illustrate applications of the present invention in the context of a Harvard-type architecture. The system of Fig. 1 illustrates an alternative stand-alone or coprocessor implementation. Next is a description of how to implement a shared, o reconfigurable memory system.

Reconfigurable Memory Architecture FIGURE 8

Fig. 8 is a conceptual diagram illustrating a reconfigurable memory architecture for 5 DSP according to another aspect of the present invention. In Fig. 8, a memory or a block of memory includes rows from 0 through Z. A first portion of the memory 266, addresses 0 to X, is associated, for example, with an execution unit (not shown). A second (hatched) portion of the memory 280 extends from addresses from X+1 to Y. Finally, a third portion of the memory 262, extending from addresses Y+1 to Z, is associated, for example, with a DMA or I/O channel. By the term "associated" here we mean a given memory segment can be accessed directly by the designated DMA or execution unit as further explained herein. The second segment 280 is reconfigurable in that it can be switched so as to form a part of the execution segment 266 or become part of the DMA segment 262 as required.

The large vertical arrows in Fig. 8 indicate that the execution portion and the DMA portion of the memory space can be "swapped" as explained previously. The reconfigurable segment 280 swaps together with whichever segment it is coupled to at the time. In this block of memory, each memory word or row includes data and/or coefficients, as indicated on the right side of the figure.

Additional "configuration control bits" are shown to the left of dashed line 267, This extended portion of the memory can be used for storing a bit configuration table that provides configuration control bits as described previously with reference to the bit configuration table 140 of Figs. 5A and 6A. These selection bits can include write enable, read enable, and other control information. So, for example, when the execution segment 266 is swapped to provide access by the DMA channel, configuration control bits in 266 can be used to couple the DMA channel to the I/O port of segment 266 for data transfer. In this way, a memory access or software trap can be used to reconfigure the system without delay. The configuration control bits shown in Fig. 8 are one method of effecting memory reconfiguration that relates to the use of a separate address generator and bit configuration table as shown in Figs. 5A and 7A. This approach effectively drives an address configuration state machine and requires considerable overhead processing to maintain the configuration control bits in a consistent and current state. When the MDSPC of Figs. 5B, 5C and 7B is used, the configuration control bits are unnecessary because the MDSPC modifies the configuration of memory algorithmically based upon the microcode executed by the MDSPC. Therefore, the MDSPC maintains the configuration of the memory internally rather than as part of the reconfigured memory words themselves. FIGURE 9

Fig. 9 illustrates connection of address and data lines to a memory of the type described in Fig. 8. Referring to Fig. 9, a DMA or I/O channel address port 102 provides sufficient address lines for accessing both the rows of the DMA block of memory 262, indicated as bus 270, as well as the reconfigurable portion of the memory 280, via additional address lines indicated as bus 272. When the block 280 is configured as a part of the DMA portion of the memory, the DMA memory effectively occupies the memory space indicated by the brace 290 and the address lines 272 are controlled by the DMA channel 102. Fig. 9 also shows an address generator 104 that addresses the execution block of memory 266 via bus 284. Address generator 104 also provides additional address lines for controlling the reconfigurable block 280 via bus 272, Thus, when the entire reconfigurable segment 280 is joined with the execution block 266, the execution block of memory has a total size indicated by brace 294, while the DMA portion is reduced to the size of block 262.

The address lines that control the reconfigurable portion of the memory are switched between the DMA address source 102 and address generator 104 via switching means 296. Illustrative switching means for addressing a single block of memory from multiple address generators was described above, for example with reference to Fig. 2. The particular arrangement depends in part on whether the memory is single-ported (see Fig. 2) or multi-ported (see Figs. 3-4). Finally, Fig. 9 indicates data access ports 110 and 120. The upper data port 110 is associated with the DMA block of memory, which, as described, is of selectable size. Similarly, port 120 accesses the execution portion of the memory. Circuitry for selection of input (write) data sources and output (read) data destinations for a block of memory was described earlier. Alternative structures and implementation of multiple reconfigurable memory segments are described below. It should be noted that the entire block need not be switched in toto to one memory block or the other. Rather, the reconfigurable block preferably is partitionable so that a selected portion (or all) of the block can be switched to join the upper or lower block. The granularity of this selection (indicated by the dashed lines in 280) is a matter of design choice, at a cost of additional hardware, e.g. sense amps, as the granularity increases, as further explained later.

FIGURE 10

Fig. 10 illustrates a system that implements a reconfigurable segment of memory 280 under bit selection table control. In Fig. 10, a reconfigurable memory segment 280 receives a source address from either the AG or DMA source address generator 274 and it receives a destination address from either the AG or DMA destination address generator 281. Write control logic 270, for example a word wide multiplexer, selects write input data from either the DMA channel or the execution unit according to a control signal 272. The source address generator 274 includes bit table control circuitry 276. The configuration control circuitry 276, either driven by a bit table or under microcode control, generates the write select signal 272. The configuration control circuitry also determines which source and destination addresses lines are coupled to the memory - either "AG" (address generator) when the block 280 is configured as part of the an "AG" memory block for access by the execution unit, or the "DMA" address lines when the block 280 is configured as part of the DMA or I/O channel memory block. Finally, the configuration control logic provides enable and/or clock controls to the execution unit 282 and to the DMA channel 284 for controlling which destination receives read data from the memory output data output port 290.

FIGURE 11

Fig. 11 is a partial block/partial schematic diagram illustrating the use of a single ported RAM in a DSP computing system according to the present invention. In Fig. 11 , a single-ported RAM 300 includes a column of memory cells 302, 304, etc. Only a few cells of the array are shown for clarity. A source address generator 310 and destination address generator 312 are arranged for addressing the memory 300. More specifically, the address generators are arranged to assert a selected one address line at a time to a logic high state. The term "address generator" in this context is not limited to a conventional DSP address generator. It could be implemented in various ways, including a microprocessor core, microcontroller, programmable sequencer, etc. Address generation can be provided by a micro-coded machine. Other implementations that 5 provide DSP type of addressing are deemed equivalents, However, known address generators do not provide control and configuration functions such as those illustrated in Fig. 10 - configuration bits 330. For each row of the memory 300, the corresponding address lines from the source and destination blocks 310, 312, are logically "ORed" together, as illustrated by OR gate 316, with reference to the top row of the memory o comprising memory cell 302. Only one row address line is asserted at a given time. For writing to the memory, a multiplexer 320 selects data either from the DMA or from the execution unit, according to a control signal 322 responsive to the configuration bits in the source address generator 310. The selected data is applied through drivers 326 to the corresponding column of the memory array 300 (only one column, i.e. one pair of bit lines, 5 is shown in the drawing). For each column, the bit lines also are coupled to a sense amplifier 324, which in turn provides output or write data to the execution unit 326 and to the DMA 328 via path 325. The execution unit 326 is enabled by an execution enable control signal responsive to the configuration bits 330 in the destination address block 312. Configuration bits 330 also provide a DMA control enable signal at 332. o The key here is to eliminate the need for a two-ported RAM cell by using a logical

OR of the last addresses from the destination and source registers (located in the corresponding destination or source address generators). Source and destination operations are not simultaneous, but operation is still fast. A source write cycle followed by a destination read cycle would take only a total time of two memory cycles. 5

FIGURE 12

Fig. 12. The techniques and circuits described above for reconfigurable memory can be extended to multiple blocks of memory so as to form a highly flexible architecture for digital signal processing. Fig. 12 illustrates a first segment of memory 400 and a second memory segment 460. In the first segment 400, only a few rows and a few cells are shown for purposes of illustration. One row of the memory begins at cell 402, a second row of the memory begins at cell 404, etc. Only a single bit line pair, 410, is shown 5 for illustration. At the top of the figure, a first write select circuit such as a multiplexer 406 is provided for selecting a source of write input data. For example, one input to the select circuit 406 may be coupled to a DMA channel or memory block M1. A second input to the MUX 406 may be coupled to an execution unit or another memory block M2. In this discussion, we use the designations M1 , M2, etc., to refer generically, not only to other o blocks of memory, but to execution units or other functional parts of a DSP system in general. The multiplexer 406 couples a selected input source to the bit lines in the memory segment 400. The select circuit couples all, say 64 or 128 bit lines, for example, into the memory. Preferably, the select circuit provides the same number of bits as the word size. 5 The bit lines, for example bit line pair 410, extend through the memory array segment to a second write select circuit 420. This circuit selects the input source to the second memory segment 460. If the select circuit 420 selects the bit lines from memory segment 400, the result is that memory segment 400 and the second memory segment 460 are effectively coupled together to form a single block of memory. Alternatively, the o second select circuit 420 can select write data via path 422 from an alternative input source. A source select circuit 426, for example a similar multiplexer circuit, can be used to select this input from various other sources, indicated as M2 and M1. When the alternative input source is coupled to the second memory segment 460 via path 422, memory segment 460 is effectively isolated from the first memory segment 400. In this 5 case, the bit lines of memory segment 400 are directed via path 430 to sense amps 440 for reading data out of the memory segment 400. When the bitlines of memory segment 400 are coupled to the second segment 460, sense amps 440 can be sent to a disable or low power standby state, since they need not be used. FIGURE 13

Fig. 13 shows detail of the input selection logic for interfacing multiple memory segments. In Fig. 13, the first memory segment bit line pair 410 is coupled to the next memory segment 460, or conversely isolated from it, under control of pass devices 466. 5 When devices 466 are turned off, read data from the first memory segment 406 is nonetheless available via lines 430 to the sense amps 440. The input select logic 426 includes a first pair of pass transistors 426 for connecting bit lines from source M1 to bit line drivers 470. A second pair of pass transistors 464 controllabiy couples an alternative input source M2 bit lines to drivers 470. The pass devices 462, 464, and 466, are all l o controllable by control bits originating, for example, in the address generator circuitry described above with reference to Fig. 9. Pass transistors, transmission gates or the like can be considered equivalents for selecting input (write data) sources.

15 FIGURE 14

Fig. 14 is a high-level block diagram illustrating extension of the architectures of Figs. 12 and 13 to a plurality of memory segments. Details of the selection logic and sense amps is omitted from this drawing for clarity. In general, this drawing illustrates how any available input source can be directed to any segment of the memory under control of

20 the configuration bits.

Fig. 15 is another block diagram illustrating a plurality of configurable memory segments with selectable input sources, as in Fig. 14. In this arrangement, multiple sense amps 482, 484, 486, are coupled to a common data output latch 480. When multiple memory segments are configured together so as to form a single block, fewer than all of

25 the sense amps will be used. For example, if memory segment 0 and memory segment 1 are configured as a single block, sense amp 484 provides read bits from that combined block, and sense amp 482 can be idle.

Figs. 16A through 16D are block diagrams illustrating various configurations of multiple, reconfigurable blocks of memory. As before, the designations M1 , M2, M3, etc., refer generically to other blocks of memory, execution units, I/O channels, etc. In Fig. 16A, four segments of memory are coupled together to form a single, large block associated with input source M1. In this case, a single sense amp 500 can be used to read data from this common block of memory (to a destination associated with M1). In Fig. 16B, the first 5 block of memory is associated with resource M1 , and its output is provided through sense amp 502. The other three blocks of memory, designated M2, are configured together to form a single block of memory - three segments long - associated with resource M2. In this configuration, sense amp 508 provides output from the common block (3xM2), while sense amps 504 and 506 can be idle. Figs. 16C and 16D provide additional examples that o are self explanatory in view of the foregoing description. This illustration is not intended to imply that all memory segments are of equal size. To the contrary, they can have various sizes as explained elsewhere herein.

Fig. 17 is a high-level block diagram illustrating a DSP system according to the present invention in which multiple memory blocks are interfaced to multiple execution 5 units so as to optimize performance of the system by reconfiguring it as necessary to execute a given task. In Fig. 17, a first block of memory M1 provides read data via path 530 to a first execution unit ("EXEC A") and via path 532 to a second execution unit (EXEC B"). Execution unit A outputs results via path 534 which in turn is provided both to a first multiplexer or select circuit MUX-1 and to a second select circuit MUX-2. MUX-1 o provides select write data into memory M 1.

Similarly, a second segment of memory M2 provides read data via path 542 to execution unit A and via path 540 to execution unit B. Output data or results from execution unit B are provided via path 544 to both MUX-1 and to MUX-2. MUX-2 provides selected write data into the memory block M2. In this way, data can be read from either 5 memory block into either execution unit, and results can be written from either execution unit into either memory block.

A first source address generator S1 provides source addressing to memory block M1. Source address generator S1 also includes a selection table for determining read/write configurations. Thus, S1 provides control bit "Select A" to MUX-1 in order to select execution unit A as the input source for a write operation to memory M1. S1 also provides a "Select A" control bit to MUX-2 in order to select execution unit A as the data source for writing into memory M2.

A destination address generator D1 provides destination addressing to memory block M1. D1 also includes selection tables which provide a "Read 1 " control signal to execution A and a second "Read 1 " control signal to execution unit B. By asserting a selected one of these control signals, the selection bits in D1 directs a selected one of the execution units to read data from memory M1.

A second source address generator S2 provides source addressing to memory segment M2. Address generator S2 also provides a control bit "select B" to MUX-1 via path 550 and to MUX-2 via path 552. These signals cause the corresponding multiplexer to select execution unit B as the input source for write back data into the corresponding memory block. A second destination address generator D2 provides destination addressing to memory block M2 via path 560. Address generator D2 also provides control bits for configuring this system. D2 provides a read to signal to execution unit A via path 562 and a read to signal to execution unit B via path 564 for selectively causing the corresponding execution unit to read data from memory block M2.

Fig. 18A illustrates at a high level the parallelism of memory and execution units that becomes available utilizing the reconfigurable architecture described herein. In Fig. 18A, a memory block, comprising for example 1 ,000 rows, may have, say, 256 bits and therefore 256 outputs from respective sense amplifiers, although the word size is not critical. 64 bits may be input to each of four parallel execution units E1 - E4. The memory block thus is configured into four segments, each segment associated with a respective one of the execution units, as illustrated in Fig. 18B. As suggested in the figure, these memory segments need not be of equal size. Fig. 18C shows a further segmentation, and reconfiguration, so that a portion of segment M2 is joined with segment M1 so as to form a block of memory associated with execution unit E1. A portion of memory segment M3, designated "M3/2" is joined together with the remainder of segment M2, designated "M2/2", to form a memory block associated with execution unit E2, and so on. Note, however, that the choice of one half block increments for the illustration above is arbitrary, Segmentation of the memory may be designed to permit reconfigurability down to the granularity of words or bits if necessary.

FIG. 19.

The use of multiple sense amps for memory segment configuration was described previously with reference to Figs. 15 and 16. Fig. 19 illustrates an alternative embodiment in which the read bit lines from multiple memory segments, for example read bit lines 604, are directed to a multiplexer circuit 606, or its equivalent, which in turn has an output coupled to shared or common set of sense amps 610. Sense amps 610 in turn provide output to a data output latch 612, I/O bus or the like. The multiplexer or selection circuitry 604 is responsive to control signals (not shown) which select which memory segment output is "tapped" to the sense amps. This architecture reduces the number of sense amps in exchange for the addition of selection circuitry 606. Fig. 20. is a block diagram illustrating a memory system of multiple configurable memory segments having multiple sense amps for each segment. This alternative can be used to improve speed of "swapping" read data paths and reduce interconnect overhead in some applications.

CACHE MEMORY APPLICATIONS

Cache memories are well-known for reducing performance degradation due to relatively slow memory in a digital computer system. Cache memories are high-speed buffers for holding recently-accessed data and neighboring data in a memory. By adding a cache memory between the fast device and the slower memory system, a designer can provide an apparently fast memory system. Some caches are invisible to the architecture: the hardware regulates them without software control. Other caches, notably those within RISC systems, are an integral part of the architecture: the instruction set includes instructions for invalidating specific cache entries, for loading and clearing cache contents, and for preventing the cache from mapping specific ranges of addresses. Various types of cache memory systems, including associative cache, direct-mapped cache, set-associative cache, and sector-mapped cache, are described generally in Barron and Higbie, COMPUTER ARCHITECTURE (Addison-Wesley, 1992) at pp. 196-204. The present invention can be applied to all of these types of cache memories. 5 Fig. 23 is a simplified block diagram of a known cache memory system. As illustrated in Fig. 23, the CPU issues an address comprising a tag, an index and a block offset field. The cache memory consists of a series of cache entries or lines, each cache entry consisting of two parts: a tag (or address tag) and data, In this illustration, the tag portion of the cache also includes validity bits. The data portion of the cache memory is o usually high-speed SRAM, and the data it holds are either copies of selected current main- memory data, or newly stored data that are not yet in main memory. The tag indicates the physical addresses of the data in main memory and, as noted, some validity information. Operation of the known cache system is summarized as follows. Whenever the CPU initiates a memory access, the storage system sends the physical address to the cache. 5 The cache compares the physical address with all of its address tags to see if it holds a copy of the datum. If the operation is a read access and the cache holds the given data, the cache reads the requested datum from its own high-speed RAM and delivers it to the CPU. This is a "cache hit" and it is usually much faster than reading those same value directly from main memory. In Fig. 23, the block offset information is used to select a o portion of the cache line corresponding to the segment or words requested by the CPU.

If the cache does not hold the datum, however, a cache miss occurs, and the cache passes the address to the main memory system to read the datum. When the datum arrives from main memory, both the CPU and the cache receive a copy. The cache then stores its copy with the appropriate address tag. While the CPU executes the 5 instruction or processes the data, the cache may concurrently read additional data from nearby main memory cells and store them with their address tags in its high-speed memory.

Referring to Fig. 24, a cache memory having the usual support logic as in Fig. 23 (not shown in Fig. 24) is arranged in two or more blocks or memory arrays 10 and 20. Each row in the arrays includes valid, tag and data fields as shown. The data memory will be used for several purposes other than actual data, according to the present invention - namely special address information, and "instructions" for the controller and execution unit, explained below. First we explain the hardware arrangement in a presently preferred 5 embodiment, and then its operation.

In Fig. 24, the data memory output port (see path 24) provides read information to three destinations: First, it provides address information via path 26 to a parameter/control circuit 22 as futher explained later. Second, the data 24 is coupled via path 28 to the controller 30. This path is used to provide op-code information to the controller which in o turn will control operation and configuration of the execution unit 32. The execution unit 32 can be of conventional design or reconfigurable as mentioned previously. Third, the data field 24 is coupled to the execution unit via path 34 to provide actual data or parameters during execution.

An address selection circuit 40, similar to a multiplexer, selects an address for 5 accessing the cache from any of three sources — the CPU address bus, the controller 30 (which preferably includes an address generator) or the parameter /control circuit 22. The address selection can be controlled by the parameter /control circuit 22 via control signals not shown, or by the controller 30. The controller 30 is not merely a conventional address generator although it includes the conventional addressing capabilities that support DSP o and other complex executions. But it also includes the capabilities for configuring and controlling the execution unit, as described above in connection with the shared DRAM execution unit for DSP.

OPERATION 5 The system of Fig. 24 operates generally as follows. First, the address selection

40 selects the CPU address bus as the address source. This allows the CPU to access the memory in the usual fashion. The cache operates as conventional cache memory, interfacing with the processor and main memory. When the CPU "hits" any of one or more predetermined "DSP memory locations" e.g. location 12 in array 20, several "macro- events" are triggered: First, the parameter /control circuit 22 conditions the address selection 40 to select the parameter /control circuit 22 itself as the address source. Second, using its own local memory lookup table, the control circuit 22 looks up an address in the cache memory array where the necessary execution parameters are stored. 5 These are the parameters needed for execution of a specific operation corresponding to the particular address hit by the CPU. In other words, the particular address accessed by the CPU triggers a corresponding execution.

This parameter address is provided via path 42 to the address selection 40, and used to access those parameters in the memory. Then, the parameters looked up in l o memory are loaded from the data memory via path 28 to the controller 30. The controller uses these parameters to configure itself for the upcoming execution. It selects the correct addressing mode, start address, length, etc. The controller also configures the execution unit and sends op-code information via path 44. Finally, the address selection switches to the controller 30 to provide addressing, and execution by the execution unit 32 begins,

15 under control of the address generator. The execution unit is executing directly out of the cache, with the cache being updated as needed in the conventional manner. Memory array 20 is configured for access by the execution unit as described earlier, for example with reference to Figs. 1 ,3,5,8,9 and others. In an alternative embodiment, the functions of the parameter /control circuit 22 are implemented directly in the controller 30.

20

FIGURE 25

Fig. 25 illustrates the use of smaller DRAM cells in implementation of a cache memory. Fig. 25 again shows a portion of cache tag memory and cache data memory 50 and associated circuitry, Here, the processor 52 issues an address 54 comprising tag field

25 56 and index field 58 and block offset bits 60. The cache index 58 addresses the tag memory to determine if the desired block is currently in the cache. The size of the index, i.e., the number of bits, depends upon the cache size, set associativity characteristics, and block size. In the case of direct mapping, for example, set associativity is established to be 1 , and each cache access requires checking only a single cache entry identified by the index. Set associative caches directly index into the tag memory with part of the address to get a set of tags. They then compare the remaining high order address bits to all of the tag entries in the set.

In this case, the tag selected by the index is compared to the tag bits 56 provided 5 by the processor in comparison circuitry 62. This comparison can be carried out in various ways, the details of which a known in the prior art, and therefore need not be repeated here. The comparison circuit 62 provides the "hit" signal in the case of a tag match, which in turn initiates loading data from the data portion of the cache into the CPU.

In the arrangement of Fig. 25, the data portion of the cache memory comprises a o series of segments - illustrated as segments 66, 68 and 70, although the number of segments preferably is on the order of 10 or 20 segments; the exact number is not critical and may depend on the particular application. Each segment comprises e.g., 32, 64, 128 or more bits. Thus, the total size of the data portion of each row is the number of segments times the number of bits per segment. 5 According to the present invention, when the index addresses a given data row, illustrated in the figure as the shaded portion 72, the data in that row is immediately read into a data latch 74. This occurs while the compare operation (62) for the corresponding tag, and validity bit checking occurs. Thus, by the time the tag comparison and validity checking is completed, the row of data is already available in latch 74, If there is a hit, the o data from latch 74 is passed through select logic 76 to the processor 52. The select logic

76 selects the particular bytes of data from the latch 74 according to the block offset bits 60. A series of bytes in the data latch 74 can be clocked out to the processor without an additional memory access operation.

Additional improvements in performance can be obtained by implementing high 5 speed SRAM memory cells in at least a portion of the data memory, Preferably, the first bytes of each block of data would be stored in SRAM memory. These first bytes of data would be the information first sent back to the CPU through the selection circuitry 76. The SRAM bytes are indicated at 80, 82 and 84 in the drawing. This arrangement provides for the first bytes to be read as quickly as possible back to the CPU, with subsequent bytes read from the DRAM portion in due course. The portion of the row implemented in SRAM is flexible, depending upon speed requirements. Part or all of the word can be implemented in DRAM with some performance penalty. Fig. 26 illustrates this arrangement of segments of the data row in which the first bytes 1 through n of each segment are implemented in SRAM, and the remaining bytes n + 1 to m are implemented in DRAM.

The controller 30 previously described with reference to Fig, 24, can be implemented in several ways. Essentially the controller 30 is a type of microprogrammable controller or sequencer - it includes circuitry similar to that that can be found in programmable sequencers known in prior art. In addition, the controller 30 includes address generation circuitry having features and functions similar to those that can be found in address generators known in DSP prior art. Typically, the controller 30 will include multiple address generation circuits, for independently addressing multiple blocks of memory, as described previously with reference to the MDSPC. In one embodiment, the controller 30 includes on board memory for storing microcode.

Next we describe illustrative circuits and methods of providing micro-code to the controller. Referring to Fig. 27, an address decoder 102 is coupled to the CPU address bus 100, and arranged to detect a particular predetermined address. When the predetermined address is asserted by the CPU, the decoder 102 so indicates to the controller 30 via control signal line 104. The controller 30 also is coupled to the CPU data bus 110. In response to the control signal 104, the controller 30 downloads data from the CPU data bus 110 into the microcode storage 106. To implement this methodology, the CPU is programmed to provide the appropriate microcode on the data bus following assertion of the predetermined address mentioned above. This arrangement has the advantage in that it enables programming the controller 30 under control of the CPU without modifying the standard CPU hardware interface. In other words, this methodology can be implemented using standard memory interface, or other standard bus architectures such as the PCI local bus, the VME e bus, Sun s bus, PCMCIA, multi-bus, etc. Moreover, it is anticipated that emerging new standards for high-speed serial interface to peripheral devices, such as the universal serial bus (USB) could be used in connection with implementing the present invention in a peripheral device.

An alternative arrangement is illustrated in Fig. 28. Here, a controller 31 is arranged so that it can provide address, data or microcode information to the data portion of the cache memory 120. Read data output from the memory 120 is developed in sense amp 124, whereas, in practice, multiple sense amps 124 would be provided, one for each column, over the full width of a row of the memory. The output of the sense amps 124 is coupled to the controller 31 via bus 130. In this arrangement, microcode for execution by the controller is stored in the data portion of the cache memory. Using memory reconfiguration methods and circuits described above, a block of memory can be formed in the cache specifically for storing microcode for the controller. In a case in which the microcode is not required or does not fill the entire space reserved for that purpose, the cache memory can utilize this space for standard storage.

The microcode stored in this fashion for execution by the controller is not limited to "instructions" per se - rather, the microcode itself can include imbedded constants and parameters for use by the execution unit. Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications and variation coming within the spirit and scope of the following claims.

Claims

I Claim:

1. A cache memory subsystem for use in connection with a processor, the processor being coupled to an address bus and a data bus and the cache memory subsystem comprising: a cache tag memory and a cache data memory, the tag memory including tag address information indicating the corresponding main memory locations of data currently stored in the cache data memory; an address selection circuit coupled to the cache tag memory to provide a tag address, the address selection circuit having a first address input coupled to the address bus to receive the first address and a second address input for receiving a second address, and a selection control input, and means for providing a selected one at a time of the first and second addresses, or a portion of either address, to the cache tag memory as a tag address responsive to a selection control signal applied to the selection control input; a controller having a first output coupled to the address selection circuit to provide the selection control signal; the controller further including a second output and means for generating an address at the second output, the second output being coupled to the second input of the address selection circuit to provide the second address.

2. A cache memory subsystem according to claim 1 and further comprising means interconnecting the controller and the cache data memory so as to allow the controller to access the cache data memory at memory locations corresponding to the second address so that the controller can execute microcode stored in the cache data memory.

3. A cache memory subsystem according to claim 1 and further comprising: an address decoder connected to the CPU address bus to receive the first address; means in the address decoder for detecting assertion of a predetermined address on the CPU address bus and providing an indication to the controller of the assertion of the predetermined address; and means in the controller for starting execution of a predetermined micro-program responsive to said indication from the address decoder, thereby triggering execution of the micro-program in response to said assertion of the predetermined address on the CPU bus.

4. A cache memory subsystem according to claim 3 wherein the address decoder is programmable and further comprising means in the controller for loading a selected address-i╧Çto the address decoder so as to replace the predetermined address.

5. A cache memory subsystem according to claim 3 further comprising a microcode memory for storing a micro-program executable by the controller.

6. A cache memory subsystem according to claim 5 wherein the microcode memory comprises read-only memory (ROM).

7. A cache memory subsystem according to claim 5 wherein the microcode memory comprises FLASH memory.

8. A cache memory subsystem according to claim 5 wherein the microcode memory comprises programmable read-only memory.

9. A cache memory subsystem according to claim 3 further comprising means in the controller for downloading micro-code from the CPU responsive to said indication from the address decoder, thereby providing a mechanism for programming the controller through a standard bus interface,

10. A cache memory subsystem according to claim 9 wherein the means in the controller for downloading the micro-code from the CPU includes means for storing the micro-code in the cache data memory.

11. A cache memory subsystem according to claim 9 wherein the cache data memory is reconfigurable into two or more blocks of memory and the means for storing the micro-code in the cache data memory includes means for reconfiguring the cache data memory so as to form a memory block for storage of micro-code.

12. A cache memory subsystem according to claim 9 wherein the means in the controller for downloading the micro-code from the CPU includes means for storing the micro-code in the controller.

13. A cache memory subsystem according to claim 9 wherein the controller is configured to execute predetermined micro-code stored in a read-only memory.

14. A cache memory execution subsystem for use in connection with a processor, the processor being coupled to an address bus and a data bus and the cache memory subsystem comprising: a cache tag memory and a cache data memory, the cache tag memory including tag address information indicating the corresponding main memory locations of data currently stored in the cache data memory; at least a portion of the cache data memory comprising rows of memory cells reconfigurable so as to form two or more blocks of memory; and an execution unit coupled directly to the cache data memory so as to allow the execution unit to access to at least a selected one of said blocks of memory concurrently with the CPU having access to at least a selected one other one of said blocks of memory.

15. A cache memory execution subsystem according to claim 14 and further comprising: an address selection circuit coupled to the cache tag memory to provide a tag address, the address selection circuit having a first address input coupled to the address bus to receive the first address and a second address input for receiving a second address, and a selection control input, and means for providing a selected one at a time of the first and second addresses, or a portion of either address, to the cache tag memory as a tag address responsive to a selection control signal applied to the selection control input; a controller having a first output coupled to the address selection circuit to provide the selection control signal; the controller further including a second output and means for generating an address at the second output, the second output being coupled to the second input of the address selection circuit to provide the second address so that the controller itself can address the cache memory; and means in the controller for providing an op-code to the execution unit.

16. A cache memory execution subsystem according to claim 15 wherein the controller is micro-programmable and the means for providing the op-code to the execution unit includes obtaining the op-code from a predetermined micro-program.

17. A cache memory execution subsystem according to claim 16 wherein the controller includes means for downloading the micro-program from the CPU.

18. A cache memory execution subsystem according to claim 17 wherein the means for downloading a micro-program includes means for storing the micro-program in the cache data memory.

19. A cache memory execution subsystem according to claim 16 further comprising: an address decoder coupled to the CPU address bus to receive the first address; means in the address decoder for detecting assertion of a predetermined execute address on the CPU address bus and providing an indication to the controller of the assertion of the execute address; and means in the controller for starting execution of a predetermined micro-program responsive to said indication from the address decoder.

20. A cache memory execution subsystem according to claim 16 further comprising means in the controller for reconfiguring the cache data memory responsive to micro-code instructions.

21. A cache memory execution subsystem according to claim 16 further comprising: a parameter circuit for providing execution parameters to the execution unit without requiring intevention of the processor nor a separate memory access operation; and wherein the address selection circuit includes a third address input coupled to the parameter circuit so as to allow the parameter circuit itself to address the cache memory to access predetermined constants and or parameters stored in the cache data memory.

22. A cache memory execution subsystem according to claim 21 wherein the parameter circuit includes control logic to enable it to address the cache data memory via the address selection circuit and to download data from the cache data memory into the execution unit.

23. A cache memory execution subsystem according to claim 14 wherein the rows of memory comprise DRAM memory cells.

24. A cache memory execution subsystem according to claim 14 wherein the rows of memory cells in the cache data memory include at least one block of rows in which a first portion of each row comprises SRAM memory cells and a second portion of each row comprises DRAM memory cells.

25. A method of performing a calculation out of a cache memory concurrently with and without interrupting CPU access to the cache memory, the method comprising the steps of: partitioning a cache memory so as to form at least two blocks of memory; configuring a first one of said blocks of memory for access by the CPU via the address bus; coupling an execution unit to a second one of said blocks of memory so as to allow the execution unit access to the second block of memory concurrently with access by the CPU to the first block of memory; downloading parameter information from the second block of memory to setup execution of a selected calculation in the execution unit; and then executing the said calculation in the execution unit without invervention of the CPU, said executing step including accessing the second block of memory to read input data and to write-back results data; and after completion of the calculation, swapping the first and second blocks of cache memory so as to provide CPU access to the results data without delay.

26. A method according to claim 25 further comprising: detecting assertion of a predetermined address on the CPU address bus; and wherein said downloading of parameter information is triggered in response to said assertion of the predetermined address, thereby providing setup and execution of a selected calculation without modifying the standard cache memory system interface to the CPU.