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WO1999050903A1 - Circuit integre a semi-conducteur et procede de fabrication correspondant - Google Patents

Circuit integre a semi-conducteur et procede de fabrication correspondant Download PDF

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Publication number
WO1999050903A1
WO1999050903A1 PCT/JP1998/001434 JP9801434W WO9950903A1 WO 1999050903 A1 WO1999050903 A1 WO 1999050903A1 JP 9801434 W JP9801434 W JP 9801434W WO 9950903 A1 WO9950903 A1 WO 9950903A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
insulating film
integrated circuit
circuit device
semiconductor integrated
Prior art date
Application number
PCT/JP1998/001434
Other languages
English (en)
Japanese (ja)
Inventor
Shinichi Fukada
Haruo Akahoshi
Kenichi Takeda
Takuya Fukuda
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001434 priority Critical patent/WO1999050903A1/fr
Publication of WO1999050903A1 publication Critical patent/WO1999050903A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to a semiconductor integrated circuit device capable of operating at high speed and a method of manufacturing the same.
  • Copper-based interconnects have lower specific resistance, higher electromigration resistance and higher allowable current density in fine patterns than aluminum-based interconnects.
  • Japanese Patent Application Laid-Open No. 8-78410 discloses a problem that the Cu wiring is inferior in oxidation resistance, and oxidizes the surface of the Cu wiring so that the Cu wiring is not exposed. , Alsi, Au, Ag or alloys mainly composed of Ag) are disclosed.
  • Japanese Patent Application Laid-Open No. 9-55429 discloses a method for manufacturing a multilayer wiring structure in which the interlayer insulating film has a low dielectric constant to reduce the capacitance between wirings in a small number of steps.
  • a wiring groove is formed in the interlayer insulating film using a low dielectric constant material such as polyimide, and embedded in the groove.
  • a technology in which only wiring is formed is formed. According to this publication, the underlying wiring is buried in a groove of a silicon oxide film on a semiconductor substrate.
  • an A1 wiring is formed, and a first buried wiring and a second buried Cu wiring are formed in an interlayer insulating film (photosensitive polyimide film) groove on the A1 wiring.
  • JP-A-5-206065 discloses that Cu is selectively deposited only on a desired region by using an electroless deposition process in forming a Cu wiring. More specifically, it discloses that a Cu wiring is formed by electroless Cu plating only on a specific surface using palladium silicide as a catalyst.
  • Japanese Patent Application Laid-Open No. 6-29246 discloses a Cu wiring technique in which metal is electrolessly plated in a relatively deep and narrow trench in a dielectric substrate.
  • the inventors of the present invention it is effective to use the A1 wiring for the first layer wiring and the Cu wiring above the second layer from the viewpoint of reliability, cost, etc. in the multilayer wiring using Cu wiring.
  • a plating method that is more advantageous in terms of embedding and cost than the sputtering method and the CVD method will be used as the method for forming the Cu wiring. The details are described below.
  • the Cu wiring process is more expensive than the A1 wiring process, and it is considered necessary to use the A1 wiring layer and the Cu wiring layer separately for multi-layer wiring depending on the application. Especially multiple semiconductor devices
  • the first layer wiring (so-called local wiring), which is closest to the (elements) and connects the elements, has a short wiring length and low resistance, and prevents Cu contamination of semiconductor elements.
  • A1 It is considered effective to use Cu wiring for the wiring on the second layer or higher (so-called global wiring).
  • Known techniques for selectively using the A1 wiring and the Cu wiring include the techniques disclosed in the aforementioned Japanese Patent Application Laid-Open Nos. 8-78410 and 9-55429.
  • Japanese Patent Application Laid-Open No. 8-78410 discloses a technique of providing a wiring such as A1 on a Cu wiring, and there is no idea to apply A1 to a first-layer wiring closest to a semiconductor element. That is, in the invention disclosed in this publication, in order to improve the bonding property with the wire in the pad region, the upper part of the Cu wiring is made of Al, Alsi, Au, Ag or an alloy mainly composed of Ag in addition to AlSiCu. In this way, oxidation of the Cu wiring is suppressed during bonding. That is, the invention disclosed in this publication addresses the problem of the upper surface of the Cu wiring, and there is no idea to apply a wiring material different from Cu as the lower wiring of the Cu wiring.
  • JP-A-9-55429 discloses a technique in which a Cu wiring is provided on an A1 wiring.
  • local wiring is formed by forming a vertical connection hole (through hole) and a wiring groove in a silicon oxide film, forming a film of A1 by a high-temperature sputtering method, and This is achieved by forming vertical connection wiring and embedded A1 wiring by removing the A1 film on the silicon oxide film by chemical mechanical polishing.
  • the global wiring on the local wiring is formed by forming wiring grooves and vertical connection holes in an interlayer insulating film made of a low dielectric constant resin (specifically, benzocyclobutene). Vertical connection by polishing Cu on low dielectric constant resin film by chemical mechanical polishing method This is achieved by forming wiring and embedded Cii wiring.
  • the technique disclosed in this publication merely provides a method for forming both the lower layer A1 wiring and the upper Cu wiring including the via wiring by the trench filling wiring technique.
  • the sputter method it is difficult to embed in a wiring formation groove having a depth of 400 nm (0.4 ⁇ m) or 400 nm or more and a via hole diameter of 0.5 ⁇ m or less or a width of 0.35 ⁇ m or less. there were. This is because a cavity is formed in the trench due to the overhang of the Cu film. Therefore, there is a limit to miniaturization of wiring.
  • the CVD method uses an expensive organic compound gas, so it is difficult to reduce the process cost. For the above reasons, it is effective to use the plating method for fine Cu wiring, especially for multilayer wiring.
  • the method of forming the Cu wiring itself using the plating technique is based on the electroless Cu plating only on a specific surface using a palladium silicide as a catalyst described in JP-A-5-206065.
  • There is a method of forming a wiring a method of forming a Cu wiring in a deep and narrow wrench by electroless plating, as described in JP-A-6-29246.
  • the inventors have clarified that there is a problem that has not been assumed in the past when forming a Cu film by the plating method.
  • the lower wiring is made of Al (or A1 alloy) and a via wiring is to be formed on the lower wiring by the Cu plating method, the A1 wiring will be corroded.
  • a strong aqueous solution is used for forming a Cu film by electroless Cu plating.
  • A1 is a material that easily corrodes in both acidic and alkaline conditions. Therefore, in the case of Cu plating, A1 corrosion prevention measures are indispensable. However, in practice, it is impossible to completely cover the A 1 surface with a chemically stable conductive film and eliminate the possibility of corrosion at all with fine wiring that allows “missing” . In particular, in order to improve the adhesion between the lower wiring and the Cu plating film, a step of simultaneously performing Cu plating while etching the underlying conductive film is required.
  • FIG. 37 it is attempted to form a Cu electroless plating film in the via hole (127) provided in the insulating film (126).
  • FIG. 37 It is sectional drawing which shows wiring connection.
  • the figure shows a state in which a reaction prevention barrier TiN layer (129) for Cu electroless plating has been formed in the via hole (127) prior to the formation of the Cu electroless plating film.
  • a TiN film (122), a 0.5% Cu film (123), and a TiN film (124) are stacked via an oxide film (not shown).
  • the layered A1 wiring (125) is formed by dry etching.
  • an insulating film (126) is formed on the A1 wiring (125).
  • holes (128 ) are easily generated in the wiring side walls due to overetching when forming via holes, and the side walls are exposed.
  • no barrier film formation technology has been established to cover these sidewalls with good coverage, leaving a major problem as in the next MECIE.
  • An object of the present invention is to provide a semiconductor integrated circuit device having a fine wiring pattern capable of operating at high speed and having improved reliability.
  • Another object of the present invention Tonime ⁇ > 0 to provide a method of manufacturing a high-speed operable has a fine wiring pattern, and a semiconductor integrated circuit device having improved reliability
  • Another object of the present invention is to realize a semiconductor integrated circuit device having a fine wiring pattern capable of operating at high speed at low cost.
  • Another object of the present invention is to provide a semiconductor integrated circuit device having a multilayer wiring structure including a wiring mainly composed of aluminum (A1) and a wiring mainly composed of copper (Cu).
  • a typical configuration of the present invention has a first wiring on a main surface of a semiconductor substrate, a first interlayer insulating film so as to cover the first wiring, and a first interlayer insulating film formed on the first interlayer insulating film.
  • a first via wiring connected to a part of the first wiring via the provided via hole, a wiring provided in the second interlayer insulating film on the first interlayer insulating film;
  • a second wiring made of a material different from that of the via wiring and the first wiring, the second wiring being embedded in the groove for use and connected to the first via wiring.
  • a semiconductor element is provided in a semiconductor substrate, and a first wiring mainly composed of aluminum is provided on the main surface of the semiconductor substrate as a local wiring near the main surface of the substrate.
  • a second wiring made of copper as the main material is provided as a global wiring on the first wiring, and the via wiring connected to the first wiring is made of a conductor material different from Cu It is characterized by the following.
  • the via wiring and the third wiring formed on the second wiring are made of a conductive material mainly composed of Cu having a lower specific resistance than A1.
  • the present invention it is possible to prevent contamination of the semiconductor element with Cu, and the CU wiring (second wiring) in the upper layer is excellent in migration resistance and has a low resistance, so that it can be operated at a high speed because of its small size.
  • a semiconductor integrated circuit device having a wiring pattern and having improved reliability can be obtained.
  • FIG. 1 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 11 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.
  • FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 22 shows a semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.
  • FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG. 23.
  • FIG. 25 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 24.
  • FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 25.
  • FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 28 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 27.
  • FIG. 29 is a cross-sectional view showing a manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
  • FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 29.
  • FIG. 31 is a cross-sectional view showing a manufacturing step of the device following FIG. 30.
  • FIG. 32 is a cross-sectional view showing a manufacturing step of the device following FIG. 31.
  • FIG. 33 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 32.
  • FIG. 34 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 33.
  • FIG. 35 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.
  • FIG. 36 is a sectional view showing a semiconductor integrated circuit device according to the fifth embodiment.
  • FIG. 37 is a sectional view showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention.
  • FIG. 38 shows a partial cross-sectional view of a multilayer wiring structure which has been a problem of the present inventors.
  • FIGS. 1-10 A method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS.
  • the wiring (103) is formed.
  • the first wiring (103) is, in order from the bottom, Ti 30nra to improve adhesion to the Si02 film, TiN 70 nm as the barrier layer, Al-0.5 0Cu 300 nm with A1 as the main wiring material, anti-reflection It is composed of laminated wiring in which TiN 50 nm as a layer is sequentially formed by a sputtering method.
  • the first wiring (103) is patterned by a known photolithography technique.
  • a wiring pattern is formed on the laminated conductor layer deposited on the Si02 film (102) by the sputtering method using a resist (photoresis t lm), transferred to the laminated conductor layer by a dry etching technique, and then transferred to the laminated conductor layer. Then, the first wiring (103) is obtained.
  • This second The first wiring (103) has a shorter wiring length than an upper wiring described later and is a wiring (local wiring) for connecting adjacent elements, for example, about 50 to 60 m.
  • a pair of a P-channel MISFET (PM ⁇ S) and an N-channel MISFET (NM 0 S) is provided in the main surface of the semiconductor substrate (101) as semiconductor elements constituting a circuit.
  • Multiple CMOS transistors composed of transistors are formed.
  • a plug such as polycrystalline silicon or tungsten is connected to the source / drain region of these CM0S transistors through contact through holes provided in the Si02 film (102). I have.
  • the first wiring (103) is connected to this plug.
  • the semiconductor substrate (101) is a semiconductor substrate in the claims.
  • the semiconductor substrate includes, in addition to the semiconductor substrate (101), a semiconductor substrate having a surface on which an epitaxial layer (for example, a thickness of 1 ⁇ m to 4 ⁇ m) is formed, that is, a so-called epitaxy wafer.
  • an epitaxial layer for example, a thickness of 1 ⁇ m to 4 ⁇ m
  • a U02 nm Si02 film (104) is formed on the first wiring (103) by a plasma CVD method.
  • a step is formed on the surface of the Si02 film (104) deposited on the Si02 film (102) where the first wiring is not formed.
  • the surface of the above-mentioned Si02 film (104) is polished and flattened by chemical mechanical polishing (hereinafter, abbreviated as CMP), and an interconnect having a thickness of 800 on the first wiring (103) is formed.
  • An insulating film that is, an interlayer insulating film (105) is formed.
  • a via hole (106) is formed in the interlayer insulating film (105) by the FI technology.
  • a via hole pattern is formed by a resist (not shown) on the interlayer insulating film (105) by a photolithography technique.
  • the via hole pattern is transferred to the interlayer insulating film (105) by a dry etching technique to form a via hole (106), and then the above-mentioned resist is removed.
  • a first via wiring (107) is formed in the via hole (106).
  • the connection of the first wiring made of A1 (or A1 alloy) to the via wiring using Cu (or Cu alloy) is avoided from the recognition of the above-described problem.
  • Cu should be avoided as a material for via wiring (107) that electrically connects the first wiring (oral wiring) made of A1 and the second wiring (global wiring) made of Cu.
  • a high melting point metal such as W is applied.
  • Ti 30 nm was formed as an adhesive layer for improving the adhesion to the first wiring and reducing the contact resistance
  • TiN 50 nm was formed as a barrier layer for preventing the reaction between the first wiring and the via wiring.
  • a W film is formed to a thickness of 500 nm on the entire surface by CVD.
  • the ff film, the TiN film and the Ti film in the flat portion of the interlayer insulating film (105) are polished and removed by a CMP method to form a via wiring (107).
  • a 100 nm SiN film (108) is formed on the entire surface of the interlayer insulating film (105) on which the via wiring (107) is formed by a plasma CVD method, and a Si02 film is formed on the SiN film (108). (109) is deposited to a thickness of 300 nm to form an interlayer insulating film.
  • This inter-wiring insulating film is formed by photolithography technology.
  • a wiring pattern is formed on (108, 109) by a resist (not shown).
  • the Si02 film (109) is etched by dry etching using the resist as a mask. At this time, the lower SiN film (108) acts as an etching stopper.
  • an etching gas for etching the Si02 film (109) is used.
  • the SiN film (108) is not etched by the etching gas for the Si02 film (109). Therefore, the etching of the Si02 film (109) stops at the surface of the SiN film (108). Since the SiN film (108) becomes an etch stop, the lower interlayer insulating film (105) is not etched. Subsequently, by switching the etching gas and etching the SiN film (108), the wiring pattern is transferred to the interlayer insulating film to form a wiring forming groove (wiring groove), and then the above-mentioned resist is removed. .
  • a second wiring (110) is formed in a wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109).
  • Ti 30 nm and TiN 70 are sequentially formed as an adhesive layer on the main surface of the semiconductor substrate on which the wiring groove is formed, and a Cu film is formed on the TiN by 50 mn by an electroless plating method. Subsequently, a Cu film is further formed to a thickness of 250 nm on the Cu film by an electrolytic plating method. The Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second wiring (110).
  • Cu electroless plating is used as a plating solution, 5 mol / l copper sulfate (CuS04) as a copper source, 0.03 ⁇ 1 / 1 / formaldehyde (HCH0) as a reducing agent, and 0.1 mol / l as a chelating agent.
  • CuS04 copper sulfate
  • HCH0 formaldehyde
  • 0.1 mol / l as a chelating agent.
  • EDTA ethylenediaminetetraacetic acid
  • I 1 of 2,2'-bipyridyl adjust the viscosity by adding poly (ethylene glycol), pH 13, and liquid temperature 80 ° C. so This is performed by immersing the substrate in this Mek's solution.
  • the Cu electroplating is performed using a 0.3 mol I 1 copper sulfate (CuS04) solution as a plating solution.
  • the thickness of the formed Cu film is controlled by the plating time.
  • a second via wiring (114) is formed in the via hole (113).
  • Ti 30 nm and TiN 70 mn are formed as adhesive layers on the entire surface of the interlayer insulating film (111, 112) in which the via hole (113) is formed, and a 50 nm Cu film is formed on the TiN by electroless plating.
  • a Cu film is further formed to a thickness of 250 nm by the electrolytic plating method, and the Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second via wiring (114).
  • the same plating solution as used in the formation of the second wiring (110) is used as the plating solution used for forming the Cu film.
  • Step (i) As shown in Fig. 9, a 100 nm SiN film (115) and a 300 nm Si02 film (116) are deposited on the entire surface of the interlayer insulating film (111, 112) with via wiring (114) formed by plasma CVD. An insulating film is formed. A wiring pattern is formed on this interlayer insulating film (115, 116) by photolithography using a resist. Next, using the resist as a mask, the Si02 film (116) is etched by dry etching technology. At this time, the lower SiN film (115) acts as an etching stopper. Subsequently, by switching the etching gas and etching the SiN film (115), the wiring pattern is transferred to the interlayer insulating film to form a wiring groove, and then the resist is removed.
  • a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116).
  • a Ti film of 30 nm and a TiN of 70 ⁇ are formed on the entire surface of the interlayer insulating film (115, 116) as an adhesive layer, and a Cu film of 50 nm is formed on the TiN by an electroless plating method.
  • a Cu film is further formed by electrolytic plating, and the flat Cu film and the adhesive layer are polished and removed by a CMP method to form a third wiring (11).
  • the plating solution used for forming the Cu film a plating solution similar to the plating solution for forming the second wiring (110) is used.
  • the second wiring which has a longer wiring length than the first wiring (local wiring: 103), mainly uses copper (Cu). It has a buried wiring structure made of a material, and it is fine and the wiring resistance can be reduced by about 40% compared to A1 wiring, and the CR wiring delay of the second layer or more can be improved. Therefore, c high-speed operation possible semiconductor integrated circuit device can be obtained
  • the first wiring (oral wiring) closest to the semiconductor element is mainly made of aluminum (A1), and can prevent Cu contamination of the semiconductor element. Therefore, the reliability of the semiconductor integrated circuit device can be improved. Even if A1 is used, this local wiring has a short wiring length, so it has little effect on high-speed operation.
  • the second wiring which has a longer wiring length than the first wiring (oral wiring), is mainly made of copper (Cu). Is a material that has better migration resistance than A1, so that the wiring reliability can be improved.
  • a high melting point metal which is a different material from the first wiring, is applied to the via wiring connecting the first wiring and the second wiring. Therefore, the problem such as the case of forming the via wiring by the Cu plating process shown in FIG. 38 is solved. That is, corrosion of the first wiring can be avoided, and the reliability of the wiring can be improved. Therefore, "missing" of the first wiring and the via hole provided on the first wiring is allowed, so that the first wiring and the via hole can be miniaturized.
  • the second wiring made of Cu as the main material, the via wiring on the second wiring, and the third wiring have a buried wiring structure, and they are formed by the plating method.
  • the process cost can be reduced.
  • the plating method does not require a vacuum device as used in normal semiconductor processes, and is concerned about safety such as high voltage, high temperature, and toxic gas.
  • the chemicals used are also less expensive than conventional semiconductor process gases. Therefore, even if Cu wiring can be formed by sputtering or CVD, the plating method is overwhelmingly advantageous in terms of cost.
  • a buried wiring forming technique using CMP is applied to the formation of the first wiring made of A1.
  • a film (104) is formed.
  • This interlayer insulating film (104) has a thickness of 300 nm, and is made of a silicon oxide film Si02 formed by a plasma CVD method using ortho-ethyl silicate Si (OC 2 H 5 ) 4 as a source gas.
  • a wiring pattern is formed by a resist (not shown) on the inter-layer insulating film (104) by a photolithography technique.
  • the Si02 film (104) is etched by a dry etching technique using the resist as a mask.
  • the wiring pattern (wiring forming groove) is transferred to the interlayer insulating film.
  • the above-mentioned resist is removed.
  • the semiconductor substrate is also used in the second embodiment.
  • a semiconductor element (elements) constituting a circuit a CM0S transistor composed of a pair of transistors of a P-channel MISFET (PMOS) and an N-channel MISFET (NMOS) is used. A plurality is formed.
  • plugs such as polycrystalline silicon or tungsten are connected to the source / drain regions of these CMOS transistors through contact through holes provided in the Si02 film (102). I have.
  • a conductor layer (103a) is deposited on the interlayer insulating film (104) on which the wiring pattern (wiring forming groove) is formed. This conductor layer
  • (103a) is a stack of 30 nm of Ti to improve the adhesion to the Si02 film, 70 nm of TiN as a barrier layer, and 300 nm of Al-0.5Cu with Al as the main wiring material, in order from the bottom. Consists of a membrane. Then, the conductor layer is reflowed by annealing at 500 ° C. and buried in the wiring forming groove.
  • the unnecessary conductor layer on the interlayer insulating film (104) is polished by the CMP method so that the first wiring (103) is formed in the wiring forming groove of the interlayer insulating film (104). Is buried.
  • a via hole (106) is formed in the interlayer insulating film (105) by photolithography.
  • an interlayer insulating film (105) having a thickness of 800 nm is formed on the first wiring (103). Similar to the interlayer insulation Enmaku (105) the interlayer insulating film (104), the orthosilicate Echiruesute Le Si (0C 2 H 5) 4 as a source gas, is formed by a plasma CVD method Made of silicon oxide film Si02. Subsequently, as in the step (c) of the first embodiment, via holes (106) are formed in the interlayer insulating film (105) by photolithography.
  • via wiring (107) is formed in the via hole (106).
  • the via wiring (107) is formed for the same reason and in the same method as in the step (d) of the first embodiment. That is, the material as the via wiring (10 ends) for electrically connecting the first wiring (oral wiring) made of Cu and the second wiring (global wiring) made of Cu can be avoided.
  • a high melting point metal such as
  • a 100 nm SiN film (108) is formed on the entire surface of the interlayer insulating film (105) on which the via wiring (107) is formed by plasma CVD, and a Si02 film is formed on the SiN film (108).
  • a film (109) is deposited to a thickness of 300 nm to form an interlayer insulating film.
  • a wiring pattern is formed by a resist (not shown) on the interlayer insulating film (108, 109) by a photolithography technique. Next, using the above resist as a mask, dry etching
  • the etching gas is controlled so that the selection ratio between the two is sufficiently large so that the Si02 film is etched and the SiN film is not etched. For this reason, the lower SiN film (108) acts as an etching stopper. That is, the etching of the Si02 film (109) stops at the surface of the SiN film (108). Since the SiN film (108) becomes an etching stopper, the lower interlayer insulating film (105) is not etched. Subsequently, the etching gas is switched and the wiring is formed by etching the SiN film (108). The pattern is transferred to an interlayer insulating film to form a wiring forming groove (wiring groove), and then the above-mentioned resist is removed.
  • a second wiring (109) is formed in a wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109).
  • nm of Ti and 70 nm of TiN are sequentially formed as an adhesive layer on the main surface of the semiconductor substrate on which the wiring grooves are formed by the Spack method.
  • a Cu film is formed to a thickness of 50 nm on the TiN as a seed film by a sputtering method.
  • a 250 nm thick Cu film is formed on the Cu film by an electrolytic plating method.
  • the Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second wiring (110).
  • the Cu electroplating is performed using a 0.3 mol I1 copper sulfate (CuS04) solution as a plating solution, similarly to the step (f) of the first embodiment.
  • the thickness of the formed Cu film is controlled by the masking time.
  • an interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded, and the interlayer insulating film (111, 112) is formed.
  • a via hole (113) is formed by ordinary photolithography technology. This step is achieved by a method similar to step (e) of the first embodiment.
  • via wiring (114) is formed in the via hole (113).
  • Ti 30 nm and TiN 70 nm are formed as an adhesive layer by a sputtering method on the entire surface of the interlayer insulating film (111, 112) in which the via hole (113) is formed.
  • a Cu film was formed on TiN as a seed film by sputtering. 50 nm is formed.
  • a 250 nm Cu film is further formed on the Cu film by an electrolytic plating method.
  • the thickness of the conductor film (Ti film / TiN film / sputter Cu film / Cu plating film) for forming via wiring is thinner (400M) than the depth (900nm) of the via hole (113).
  • an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) in which the second wiring (114) is embedded, and the interlayer insulating film (115, 116) is formed.
  • a wiring groove is formed by a normal photolithography technique, and then the resist is removed. This step is achieved by a method similar to step (i) of the first embodiment.
  • a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116). This step is achieved by a method similar to step (g) of the second embodiment.
  • the first wiring is formed by the embedded wiring forming technique
  • the first embodiment (the first wiring is usually The formation of a TiN film as an anti-reflection layer, which is required by photolithography, is not required.
  • the contact resistance between the via wiring and the second wiring connected to the via wiring is reduced.
  • the method of manufacturing a semiconductor integrated circuit device includes the following steps (f) to (1) following the steps (a) to (e) of the second embodiment. Is executed.
  • the Si02 film (105) is polished by the CMP method, and the via wiring (107) is formed. 107) is projected.
  • the protrusion of the via wiring (107) is formed at a height of, for example, 50 nm.
  • an interlayer insulating film (108, 109) is formed on the interlayer insulating film (105) according to the step (f) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (108, 109).
  • the layer A second wiring (109) is formed in a wiring forming groove (wiring groove) formed in the inter-insulating film (108, 109).
  • the second wiring (109) is formed by a CMP method. Therefore, the surface of the second wiring (109) is flattened, and the protrusion of the via wiring (107) does not appear on the surface of the second wiring (109).
  • the interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded. ) Is formed, and a via hole (113) is formed in the interlayer insulating film (111, 112) by ordinary photolithography.
  • a via wiring (114) made of Cu is formed in the via hole (113) according to the step (i) of the second embodiment.
  • the interlayer insulating film (111, 112) is polished by a CMP method to project the via wiring (114).
  • the protrusion of the via wiring (114) is formed at a height of, for example, 10.
  • the Cu that composes the via wiring (114) is softer than W, so it is removed during polishing of the interlayer insulating film (111, 112).
  • the surface of the via wiring (114) has a convex shape of about 10 nm. If so, the purpose of reducing contact resistance will be achieved.
  • an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) according to the step (j) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (115, 116).
  • a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116) according to the step (k) of the second embodiment.
  • the first wiring is formed by the buried wiring forming technique as in the second embodiment, the first wiring is formed by the ordinary photolithography technique. It is not necessary to form a required TiN film as an antireflection layer.
  • step (f) after the via wiring (107) is formed by the CMP method, the Si02 film (105) is polished by the CMP method, and the first via wiring (107) is projected. I have. That is, the side surface of the first via wiring (107) is exposed to increase the surface area of the wiring. Therefore, the contact area between the first via wiring (107) and the second wiring (110) is increased as compared with the case of the second embodiment, and the contact resistance can be reduced.
  • the second via wiring (114) is projected for the same purpose. Therefore, the contact area between the first via wiring (114) and the third wiring (117) is increased as compared with the case of the second embodiment, and the contact resistance can be reduced.
  • the third embodiment has at least two layers on the semiconductor substrate.
  • a semiconductor integrated circuit device having a multilayer wiring having upper Cu wiring and via wiring connecting between respective wiring layers, wherein at least one Cu wiring (second wiring 110) and lower wiring (first wiring) are provided. 103), the upper surface of the via wiring (107) is above the bottom surface (the contact surface with the inter-layer insulating film 105) of the Cu wiring excluding the connection region with the via wiring.
  • FIGS. 29 to 35 A method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to FIGS. 29 to 35.
  • the fourth embodiment reduces the wiring (plug) resistance by reducing the height of the first via wiring (plug) made of W in particular.
  • the following steps (f) to (1) are performed.
  • the via wiring (107) made of W shown in FIG. 15 is excessively polished by the CMP method. Therefore, the main surface of the polished via wiring (107) is lower than the surface of the interlayer insulating film (105) as shown in FIG.
  • the step of the via wiring (107) has, for example, 10 nm.
  • an interlayer insulating film (108, 109) is formed on the interlayer insulating film (105) according to the step (f) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (108, 109). P
  • the second wiring (wiring groove) is formed in the wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109). 109).
  • the second wiring (109) is formed by a CMP method. Therefore, the surface of the second wiring (109) is flattened, and the recess of the via wiring (107) does not appear on the surface of the second wiring (109).
  • the interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded. ) Is formed, and a via hole (113) is formed in the interlayer insulating film (111, 112) by ordinary photolithography.
  • a via wiring (114) made of Cu is formed in the via hole (113) according to the step (i) of the second embodiment.
  • the via wiring (114) is CMP-processed so that no step is formed between the surface of the interlayer insulating film (111, 112) and the surface of the via wiring (114).
  • an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) according to the step (j) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (115, 116).
  • a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116) according to the step (k) of the second embodiment. Also in the fourth embodiment, when an upper layer Cu wiring is further stacked on the third wiring (117), the steps (h) to (k) of this embodiment are repeatedly performed.
  • the first wiring is formed by a buried wiring forming technique. Therefore, the first wiring is formed (the first wiring is formed by a normal photolithography technique). Thus, the formation of a TiN film as an anti-reflection layer, which is required in the above, becomes unnecessary.
  • step (f) the via wiring (107) is excessively polished by the CMP method. Therefore, the main surface of the first via wiring (107) made of polished W is lower than the surface of the interlayer insulating film (105) as shown in FIG. Therefore, by reducing the height of the first via wiring (plug) made of W, the resistance of the wiring (plug) can be reduced.
  • the fourth embodiment is a semiconductor integrated circuit device having at least two or more Cu wiring layers and a via wiring connecting each wiring layer on a semiconductor substrate, and at least one Cu wiring (The upper surface of the via wiring (107) connecting the second wiring 110) and the lower wiring (first wiring 103) is formed on the bottom surface of the Cu wiring excluding the connection region with the via wiring (interlayer insulating film 105 and Below the contact surface).
  • a method of manufacturing a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described with reference to FIG.
  • the fifth embodiment reduces the connection resistance between the first wiring and the via wiring connected to the first wiring. I have.
  • a step (d ′) described below is added following the steps (a) to (d) of the second embodiment. .
  • the first wiring (103) of the A1-0.5% Cu layer exposed in the via hole (106) is dry-etched.
  • a groove is provided.
  • the groove (103) is self-aligned with the via hole (106).
  • the depth of the groove is arbitrary, for example, about 50 mn.
  • the first wiring is formed by a buried wiring forming technique, so that the first wiring (the first wiring is a conventional photolithography technique) It is not necessary to form a TiN film as an anti-reflection layer, which is required in the step.
  • the first wiring (103) is provided with a groove by dry etching. Therefore, the first via wiring (107) and the second wiring (110) are in contact with the groove bottom surface and the groove side wall surface, and the contact area between them increases as compared with the case of the second embodiment. Therefore, the contact resistance can be reduced.
  • a metal other than Cu is used as a main component.
  • FIG. 37 is a cross-sectional view of the semiconductor integrated circuit device showing a state where the semiconductor element (M0S) is formed on the semiconductor base.
  • an element isolation region GI is selectively formed on the main surface of the semiconductor substrate (101).
  • the element isolation region GI is formed by forming a groove on the substrate surface and burying an insulating film in the groove.
  • This element isolation region GI is also referred to as trench isolation.
  • the MOS transistor (M0S) is composed of a gate electrode having a laminated structure of polycrystalline silicon and a metal formed thereon as a gate electrode, and a side wall spacer is provided on the side wall. Have been. Then, a plug (for example, W) is provided in the interlayer insulating film (102). This plug is connected to a source drain region (not shown) provided in the semiconductor substrate (101).
  • the wiring and the interlayer insulating film on the interlayer insulating film (102) are formed, for example, according to the first embodiment.
  • the present invention is an effective technique when applied to a semiconductor integrated circuit device having a high-speed logic circuit requiring fine wiring and high speed operation. More specifically, the present invention relates to an LSI in which a memory (DRAM, SRAM, or EEPROM, or a combination thereof) and a high-speed logic circuit are mounted on a single semiconductor substrate. This is effective for realizing an LSI in which high-speed logic circuits are mounted on a single semiconductor substrate.
  • a memory DRAM, SRAM, or EEPROM, or a combination thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention se rapporte à un circuit intégré à semi-conducteur susceptible de fonctionner à vitesse élevée, qui possède un motif de câblage fin et est doté d'une fiabilité accrue. Dans ledit circuit, un élément semi-conducteur est disposé sur un substrat semi-conducteur (101). Un premier câblage (103) constitué principalement d'aluminium est disposé sur la surface principale du substrat (101) et constitue le câblage local coté-surface principale, et un second câblage (110) constitué principalement de cuivre est disposé sur le premier câblage (103) en tant que câblage global. Le câblage des traversées (107) qui est amené en contact avec le premier câblage (103) est constitué d'une matière conductrice différente du cuivre.
PCT/JP1998/001434 1998-03-30 1998-03-30 Circuit integre a semi-conducteur et procede de fabrication correspondant WO1999050903A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001434 WO1999050903A1 (fr) 1998-03-30 1998-03-30 Circuit integre a semi-conducteur et procede de fabrication correspondant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001434 WO1999050903A1 (fr) 1998-03-30 1998-03-30 Circuit integre a semi-conducteur et procede de fabrication correspondant

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Publication Number Publication Date
WO1999050903A1 true WO1999050903A1 (fr) 1999-10-07

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PCT/JP1998/001434 WO1999050903A1 (fr) 1998-03-30 1998-03-30 Circuit integre a semi-conducteur et procede de fabrication correspondant

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WO (1) WO1999050903A1 (fr)

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JP2009505385A (ja) * 2005-08-08 2009-02-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 相互接続コンタクトのドライ・エッチバック
JP2010123998A (ja) * 2002-05-17 2010-06-03 Semiconductor Energy Lab Co Ltd 半導体装置
WO2011158319A1 (fr) * 2010-06-14 2011-12-22 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur et son procédé de fabrication
CN104952790A (zh) * 2010-06-14 2015-09-30 瑞萨电子株式会社 半导体器件的制造方法
JP2021036594A (ja) * 2015-03-19 2021-03-04 株式会社半導体エネルギー研究所 半導体装置

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JPH0799198A (ja) * 1993-06-24 1995-04-11 Nec Corp 半導体装置の製造方法
JPH0955429A (ja) * 1995-08-10 1997-02-25 Nec Corp 半導体装置およびその製造方法

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JPH04116953A (ja) * 1990-09-07 1992-04-17 Seiko Epson Corp メッキ配線層を備えた半導体装置の製造方法
JPH0799198A (ja) * 1993-06-24 1995-04-11 Nec Corp 半導体装置の製造方法
JPH0955429A (ja) * 1995-08-10 1997-02-25 Nec Corp 半導体装置およびその製造方法

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016197750A (ja) * 2002-05-17 2016-11-24 株式会社半導体エネルギー研究所 半導体装置
JP2010123998A (ja) * 2002-05-17 2010-06-03 Semiconductor Energy Lab Co Ltd 半導体装置
US9847355B2 (en) 2002-05-17 2017-12-19 Semiconductor Energy Laboratory Co., Ltd. Silicon nitride film, and semiconductor device
US8866144B2 (en) 2002-05-17 2014-10-21 Semiconductor Energy Laboratory Co., Ltd. Thin film semiconductor device having silicon nitride film
JP4742147B2 (ja) * 2005-08-08 2011-08-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 相互接続コンタクトのドライ・エッチバック
JP2009505385A (ja) * 2005-08-08 2009-02-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 相互接続コンタクトのドライ・エッチバック
CN102939649A (zh) * 2010-06-14 2013-02-20 瑞萨电子株式会社 半导体器件及其制造方法
US9030014B2 (en) 2010-06-14 2015-05-12 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN104952790A (zh) * 2010-06-14 2015-09-30 瑞萨电子株式会社 半导体器件的制造方法
TWI512898B (zh) * 2010-06-14 2015-12-11 Renesas Electronics Corp Semiconductor device and manufacturing method thereof
US9337016B2 (en) 2010-06-14 2016-05-10 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP5684254B2 (ja) * 2010-06-14 2015-03-11 ルネサスエレクトロニクス株式会社 半導体装置
WO2011158319A1 (fr) * 2010-06-14 2011-12-22 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur et son procédé de fabrication
US10049984B2 (en) 2010-06-14 2018-08-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN104952790B (zh) * 2010-06-14 2019-01-01 瑞萨电子株式会社 半导体器件的制造方法
US10418328B2 (en) 2010-06-14 2019-09-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US11515257B2 (en) 2010-06-14 2022-11-29 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2021036594A (ja) * 2015-03-19 2021-03-04 株式会社半導体エネルギー研究所 半導体装置

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