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WO1997011492A1 - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture Download PDF

Info

Publication number
WO1997011492A1
WO1997011492A1 PCT/JP1995/001875 JP9501875W WO9711492A1 WO 1997011492 A1 WO1997011492 A1 WO 1997011492A1 JP 9501875 W JP9501875 W JP 9501875W WO 9711492 A1 WO9711492 A1 WO 9711492A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
semiconductor device
bonding
metal thin
semiconductor
Prior art date
Application number
PCT/JP1995/001875
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuhiko Sasaki
Akiomi Kohno
Masaya Horino
Mitsuo Usami
Masahide Tokuda
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001875 priority Critical patent/WO1997011492A1/en
Priority to JP51256397A priority patent/JP3400459B2/en
Publication of WO1997011492A1 publication Critical patent/WO1997011492A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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    • H01L2225/1035—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which various semiconductor elements are joined to achieve high density and multifunctionality, and a method of manufacturing the same.
  • Hei 5-109593 discloses that a semiconductor device is stacked via a solder plate and then heated. A method for manufacturing a semiconductor device for bonding a semiconductor element is disclosed.
  • No. 17 1643 discloses that solid-state bonding is performed by irradiating an atom or ion energy beam to the electrodes of a substrate of a semiconductor device and a CCB bump as a bonding material. A bonding method for performing liquid phase bonding by reflowing bumps is disclosed.
  • the method of bonding the silicon substrate by bringing the silicon substrate into close contact and heating according to the prior art 1 is a bonding method with high dimensional accuracy after bonding, but the bonding temperature is low. Since it is as high as 10 oot or more, if this bonding method is used to join the silicon substrate (conductor element) on which the element is formed, the semiconductor element will be destroyed due to melting of the wiring inside the semiconductor element, diffusion of the semiconductor element, etc. It has been done.
  • the bonding operation can be easily performed because the adhesive is used. There is a possibility that the bonded semiconductor element may be detached, and the reliability as a semiconductor device is not sufficient. In addition, since the heat resistance of the bonding portion is large, it is difficult to dissipate the heat of the semiconductor element bonded by the adhesive, and the heat may hinder the semiconductor device. Furthermore, since the adhesive is liquid and it is difficult to control the film thickness, it is difficult to secure the dimensional accuracy of the joint.
  • the method of manufacturing a semiconductor device in which the semiconductor elements of the prior art 3 are stacked via a solder plate and then heated to join the semiconductor elements can easily perform the joining work as in the above-described prior art 2.
  • the flux contained in the solder is caught in the connection portion and evaporates, voids are generated and it is difficult to secure the bonding strength. Also, the residual flux may cause corrosion at the joint.
  • the bonding temperature is higher than the melting point of the solder, the semiconductor elements that can be bonded are limited to those whose heat-resistant temperature is lower than the melting point of the solder.
  • the melting temperature of the joint is the melting point of the solder, it is not possible to use the same solder when joining a plurality of semiconductor devices in sequence according to the manufacturing process.
  • An object of the present invention is to provide a highly reliable semiconductor device in which various semiconductor elements are joined and a method for manufacturing the same.
  • the above object can be achieved by solid-state bonding of at least two or more semiconductor elements to a junction between the semiconductor elements via a metal thin film.
  • the joint In order to manufacture a highly reliable semiconductor device by joining semiconductor elements, the joint must have sufficient strength, the joint must have high heat dissipation, and the dimensional accuracy after joining must be high. It is necessary that the heating temperature at the time is low.
  • FIG. 8 (a) is a graph showing the relationship between bonding strength and bonding pressure at a bonding temperature of 10 Ot: where the vertical axis indicates bonding strength and the horizontal axis indicates bonding pressure.
  • Fig. 8 (b) is a graph showing the relationship between the joining strength and the joining temperature at a joining pressure of 5 MPa, where the vertical axis represents the joining strength and the horizontal axis represents the joining temperature.
  • a bonding temperature of 100 or more and a bonding pressure of 5 OMPa are required.
  • the pressure may be set to MPa or more.
  • the junction temperature range is 100 to 400 and the junction pressure range is 5 to 50 MPa. This temperature Since the pressure range and the pressure range are sufficiently low for the semiconductor device, this bonding method is adopted for the bonding of the semiconductor device, and the high-density, multifunctional and highly reliable semiconductor The device can be provided.
  • the semiconductor element is solid-phase bonded in a thickness direction of the semiconductor device.
  • the semiconductor element is arranged on a substrate in a length direction or a width direction of the semiconductor device and solid-phase bonded.
  • An optical semiconductor element and an optical waveguide are solid-phase bonded on a substrate via a metal thin film.
  • the metal film is composed of two or more thin film layers made of different materials.
  • the metal film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
  • the metal film may be a titanium (Ti) thin film of 0,5 to 1 OOO nm and a gold (Au) of 2 to 1 OOOO nm It is composed of a thin film.
  • a plurality of films are formed electrically independently on the bonding surface of the semiconductor element, and a part or all of the plurality of formed metal thin films is used as an electrode.
  • Desirable aspects of the method for manufacturing a semiconductor device of the present invention are as follows.
  • the solid-state bonding is performed in such a manner that at least one of the bonding surfaces of the semiconductor elements to be bonded to each other is a bonding surface on which a metal thin film is formed in advance, and the solid-state bonding is performed in a vacuum.
  • the metal thin film is formed in a bonding atmosphere in which the bonding surface does not re-contaminate.
  • the joining surfaces are brought into close contact with each other at a temperature equal to or lower than the solidus temperature and pressurized to join in the solid state.
  • the metal thin film is composed of two or more thin film layers made of different materials.
  • the metal thin film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
  • the metal thin film comprises a titanium (Ti) thin film of 0.5 to 1000 nm and a gold (Au) thin film of 2 to 1000 nm.
  • a semiconductor element has an independent function
  • a component of a semiconductor device Refers to a component of a semiconductor device.
  • an optical waveguide in an optical semiconductor device is also called a semiconductor element.
  • solid-phase bonding means bonding at a temperature lower than the solidus of the bonding material, and includes bonding at a temperature higher than the solidus of the bonding material.
  • the solid-state bonding of the semiconductor element via the metal thin film can lower the bonding temperature and the bonding pressure, so that the reliability of the semiconductor device can be secured. In addition, sufficient bonding strength can be ensured, and there is no concern that the semiconductor element will be detached because the bonded portion does not deteriorate with time. In addition, since the melting temperature of the bonding portion is sufficiently higher than the bonding temperature, the semiconductor device that has been bonded once can be bonded many times under the same bonding conditions. The semiconductor element can be bonded to the substrate. Further, since the bonding portion is a metal bonding, heat of the semiconductor element can be efficiently radiated.
  • the integration density with respect to the installation area of the semiconductor device can be increased.
  • semiconductor devices with different functions selected according to the required specifications are arranged in the length direction or width direction of the semiconductor device and solid-phase bonded on the substrate, so that they can be individually designed. Compatible semiconductor devices can be manufactured in a short time.
  • solid-state bonding of an optical element and an optical waveguide to a substrate via a metal thin film allows a high-performance optical semiconductor device to be manufactured in a short time.
  • a gallium arsenide semiconductor device is interposed on a silicon semiconductor device via a metal thin film.
  • a highly accurate optical transmission semiconductor device can be manufactured.
  • the peel strength of the metal thin film from the semiconductor element can be increased.
  • a plurality of metal thin films are formed electrically independently on the bonding surface of the semiconductor element and part or all of the formed metal thin films are used as electrodes, wiring between the semiconductor elements is unnecessary. Therefore, labor saving of wiring work can be achieved. Further, since the wiring length is shortest, the operation speed of the semiconductor device can be increased.
  • FIG. 1 is an external view of a stacked semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a method of manufacturing a stacked semiconductor device according to a first embodiment of the present invention.
  • FIG. 3 is a metal cross-sectional view of a bonding interface according to the first embodiment of the present invention.
  • FIG. 4 is an external view of a planar junction type semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a diagram illustrating a method of manufacturing an optical transmission semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 is a diagram showing a method for manufacturing an optical semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a diagram showing a defect repair method for a large-scale semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 8 is a diagram showing a relationship between bonding conditions and bonding strength of the present invention.
  • Fig. 1 shows the appearance of the stacked semiconductor device.
  • 4 11 1 is the gate of the transistor
  • 4 12 is the gate oxide film of the transistor
  • 4 4 is the wiring
  • 4 7 1 is the upper electrode
  • 7 2 is the lower electrode
  • 4 7 3 is the substrate electrode
  • Reference numerals 481 and 82 denote metal thin films
  • 46 denotes a conductive film
  • 404 denotes a substrate
  • 410, 402, and 403 denote semiconductor elements for stacking and bonding.
  • FIG. 2 shows a method of manufacturing a stacked semiconductor device.
  • 49 is an argon (Ar) atomic beam.
  • FIG. 3 shows a metal cross section at the bonding interface.
  • 21 is a gold thin film
  • 22 is twin deformation
  • 23 is a bonding interface
  • 24 is a void.
  • Fig. 4 shows the appearance of a planar junction type semiconductor device.
  • Reference numeral 61 denotes a substrate
  • reference numerals 61 to 606 denote semiconductor elements for planar bonding
  • reference numerals 631 and 632 denote metal thin films.
  • the stacked semiconductor device is a semiconductor device in which a plurality of stacked junction semiconductor elements shown in FIG. 1 (a) are stacked as shown in FIG. 1 (b), and which achieves high density and multifunctionality.
  • the transistor is manufactured by forming a gate 411 gate oxide film 412 and the like using a normal semiconductor process.
  • the transistors are isolated from each other by a front insulating layer 421, a rear insulating layer 42, and an inter-element insulating film 43, and both ends of the single-crystal silicon film 43 of each transistor.
  • Wirings 44 are respectively connected to the source and drain 432 formed at the bottom.
  • the wiring 44 is connected to the upper electrode 471 via a conductive film 46 filled in a surface through hole 451 formed on the surface insulating layer 421.
  • the wiring 44 is connected to the lower electrode 472 via a conductive film 46 filling the rear through hole 452 formed in the rear insulating layer 42.
  • the upper electrode 471 and the lower electrode 472 have a thickness of 0. ⁇
  • Ti titanium
  • Au gold
  • the thickness range of the titanium (Ti) thin film is set to 0.5 to 100 nm is that, in this range, the titanium (Ti) forms a thin film and the titanium (Ti) thin film is formed. This is because there is no decrease in peel strength due to internal stress and sufficient bonding strength is exhibited.
  • the reason why the thickness range of the gold (Au) thin film is set to 2 to 1000 ⁇ is that within this range, the surface roughness of the silicon where the gold (Au) thin film is the bonding surface can be covered.
  • the workability of providing a gold (Au) thin film is good and the strength is sufficient.
  • the gold (Au) thin film was inserted on the titanium (Ti) thin film in order to increase the peel strength of the gold (Au) thin film, and instead of titanium, the peel strength of a thin gold film such as chromium (Cr) was used. May be inserted.
  • the wiring can be omitted by using the bonding surface as an electrode, so that it is possible to save the labor of the semiconductor manufacturing process and improve the operation speed of the semiconductor device.
  • a titanium (Ti) thin film having a thickness of 0.5 to 100 nm as a metal thin film 481, and then a gold (Au) thin film as a metal thin film 481 are provided on the surface of the surface insulating layer 421 for fixing the device.
  • a thickness of 2 to 1000 nm is formed, and a similar metal thin film 482 is formed also on the surface of the backside insulating layer 422, each having a gold (Au) surface as a bonding surface. I have.
  • the joining step will be described.
  • Figure 4 urchin by showing (a), the Arugo emissions (Ar) atomic bi chromatography beam 4 9 pressure under that can by irradiation morphism (eg if 1 X 1 0 one 4 ⁇ 1 X 1 0- 3 Torr).
  • the first stacked junction semiconductor element 401 is placed below and the second stacked junction semiconductor element 402 is placed above, and the front side of the first stacked junction semiconductor element 401 is placed in a vacuum.
  • the bonding surface and the bonding surface on the back side of the second stacked bonding semiconductor element 402 are irradiated with an argon (Ar) atomic beam 49.
  • Ar argon
  • the bonding surfaces are opposed to each other in a vacuum of 5 ⁇ 10 to 16 Torr or less, and then bonded together in a solid state.
  • the bonding time of the pressure not be a vacuum below 5 X 1 0- 6 Torr, argon (Ar) atoms beam 4
  • Any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate.
  • the third stack of FIG. 4 (c) to I shown urchin, argon (Ar) atoms beam 4 under a pressure 9 can be irradiated (e.g., 1 x 1 0- 4 ⁇ 1 x 1 0- 3 Torr of vacuum)
  • the argon (Ar) atomic beam 49 is irradiated to the front-side bonding surface of the semiconductor device 401 for use and the rear-side bonding surface of the third stacked bonding semiconductor device 400 3.
  • any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate.
  • the temperature of the joining surface that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
  • the oxide film (Si02) of the surface insulating layer 421 is used as a eutectic film between silicon (Si) as a base material and gold (Au) of a metal thin film.
  • the melting temperature of the joint can be set to 600 T or more. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if the joining is performed several times.
  • the eutectic protection In this embodiment, the oxide film of the soI wafer itself is used as the stop film, but the same effect can be obtained by using a thermal oxide film or an oxide film formed by CVD. Also, under the conditions of the bonding temperature and the bonding pressure, as shown in FIG.
  • twin deformation 22 occurs in the gold (Au) thin film 21 which is a metal thin film, so that the bonding surfaces are bonded to each other.
  • bonding with few voids 24 at the bonding interface 23 can be performed.
  • the strength of the joint is equal to or more than l OM pa, which is sufficient for the soldering of the semiconductor device manufacturing process.
  • FIG. 4 shows that semiconductor elements 600 1 to 600 are arranged in a plane on a substrate 610 and joined according to the present invention.
  • semiconductor elements 600 1 to 600 are arranged in a plane on a substrate 610 and joined according to the present invention.
  • a semiconductor device that has been conventionally designed according to individual specifications can be manufactured in a short time. Can be manufactured.
  • FIG. 5 shows a junction in an optical transmission semiconductor device.
  • 51 is a silicon substrate
  • 52 is an optical waveguide
  • 53 is an optical semiconductor element
  • 54 is an optical fiber
  • 515 to 554 are metal thin films.
  • the optical transmission semiconductor device has an optical waveguide 52, an optical semiconductor element 53 fixed on a silicon (Si) substrate 51, and an optical fiber 54 attached. It has a structure.
  • the optical waveguide 52, the optical semiconductor element 53, and the optical fiber 54 cannot exhibit their performance unless their mounting accuracy is high.
  • a titanium (Ti) thin film was formed to a thickness of 0.5 to 100 nm by vacuum evaporation as metal thin films 551, 552, and then Money (Au)
  • the optical element 53 formed with 54 is placed under a pressure (for example, a vacuum of 1 xl O— 4 to 1 xl O— 3 Torr) under which the argon (Ar) atom beam 56 can irradiate, and Irradiate an argon (Ar) atomic beam 56.
  • the bonding surfaces of the silicon substrate 51 and the optical element 53 are brought into close contact with each other and bonded in a solid state.
  • the temperature of the bonding surface that is, the bonding temperature is 100 to 400C
  • the bonding pressure is 5 to 50 MPa.
  • the optical semiconductor element 53 and the optical waveguide 52 are joined according to the present invention, the only member that may cause a dimensional error due to the joining is the metal thin film. If it is correct, the position after joining can be set correctly.
  • FIG. 6 shows the manufacturing process of the optical semiconductor device.
  • 31 is a silicon semiconductor device
  • 32 is a gallium arsenide semiconductor device
  • 34 is argon (Ar) Atomic beam
  • 331 and 332 are metal thin films.
  • Optical semiconductor devices consist of silicon (Si) semiconductor devices and gallium arsenide.
  • GaAs GaAs It can be manufactured by joining different materials of semiconductor elements.
  • a titanium (Ti) thin film is formed to a thickness of 0.5 to 100 nm by vacuum evaporation and then a gold (Au) thin film as a metal thin film 331.
  • the joint surface irradiated with 4 does not recontaminate the surface.
  • the temperature of the joining surface that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
  • the height of the silicon semiconductor device 31 and the height of the gallium arsenide semiconductor device 32 can be made the same. Since the wiring between them can be made of thin-film metal wiring, the wiring density is increased, and high integration of semiconductor devices becomes possible. In addition, by using a part of the joint surface as a contact point, it is possible to save labor in wiring work.
  • FIG. 7 shows a method for repairing a defect in a large-scale semiconductor device.
  • 11 is a large-scale semiconductor device
  • 13 is a junction groove
  • 15 is a thin-film large-scale semiconductor device
  • 16 is an argon (Ar) atomic beam
  • 121, 122 are macro
  • 123 are defects
  • the relief macro, 141 and 142 are metal thin films.
  • defects are remedied to improve yield. This is to remove the defective macro from the circuit blocks that have individual functions called macros that make up a large-scale semiconductor device, and join macros without defects to them. The task is to rescue large-scale semiconductor devices that have become defective.
  • FIG. 7 (a) shows a large-scale semiconductor device requiring defect relief.
  • Large-scale semiconductor devices 11 made from SOI wafers are composed of circuit blocks with individual functions called macros 121 and 122. For example, it is assumed that there is no defect in the circuit of the macro mouth 1221, and that the circuit of the macro 122 has a defect.
  • the defect removing step will be described.
  • the macro 122 having this defect is removed by etching to form a junction groove 13 as shown in FIG. 1 (b).
  • a titanium (Ti) thin film having a thickness of 0.5 to 1000 nm is formed in the joining groove 13 as a metal thin film 141 by vacuum evaporation, and then a gold thin film is formed.
  • Ti titanium
  • Au gold
  • a thin film is formed with a thickness of 2 to 1000 ⁇ , and the gold surface is used as a bonding surface.
  • the reason why the titanium thin film is inserted between the bonding groove 13 and the gold thin film is to increase the peel strength of the gold thin film.
  • a thin film such as chromium (Cr) that increases the peel strength of the gold thin film is used. May be inserted.
  • the thin-film large-scale semiconductor element 15 shown in Fig. 1 is a thin-film version of a large-scale semiconductor element having a circuit configuration similar to that of the large-scale semiconductor element 11, and is the same as the macro-122. No defect has occurred in the defect repair macro 123.
  • Fig. 1 ( e ) As shown in (5), the thin-film large-scale semiconductor device 15 is divided into macro units, and the defect relief macros 123 are extracted. Then, as shown in FIG. 1 (f), a metal thin film 142 is formed in the same manner as the bonding groove 13 and the gold (Au) surface is used as the bonding surface.
  • the joining step will be described with reference to FIG.
  • a large semiconductor element 1 1 and remedies macros 1 2 3 argon (Ar) atoms beam 1 6 under pressure that can be irradiated (1 x 1 0 one 3 Torr of vacuum example 1 x 1 0- 4 ⁇ )
  • the joint surface is irradiated with an argon (Ar) atomic beam 16.
  • contaminants such as an oxide film, moisture, oils and fats adhering to the joint surface are removed, and the joint surface is activated.
  • the surface irradiated with the argon (Ar) atomic beam 16 is a metal surface, the irradiated surface does not charge up and does not damage the semiconductor device electrically. Thereafter, Remind as in FIG.
  • the adhesion is allowed after being opposed joint surfaces each other at 5 X 1 0- 6 To rr in the following vacuum bonding state of the solid phase.
  • the bonding time of the pressure not be a vacuum below 5 x 1 0- 6 Torr, the bonding surface was irradiated with argon (Ar) atoms beam 1 6 may be any atmosphere that does not re-contamination.
  • the temperature of the bonding surface that is, the bonding temperature is 100 to 400, and the bonding pressure is 5 to 50 MPa. Since bonding can be performed at a low temperature and a low pressure in this manner, bonding can be performed while ensuring the reliability of the integrated circuit.
  • the dimensional accuracy is high, and the height of the relief macro 123 and the height of the defect-free macro 122 can be the same.
  • the wiring between the macros is thin-film like the non-defective large-scale semiconductor device. Since the wiring can be formed using metal wiring, the wiring density can be increased, and high integration of semiconductor devices can be achieved. Also, since the joint is a metal joint, the relief macros 123 can sufficiently dissipate heat.
  • the oxide film (Si02) in the joint groove 13 and the relief macro 123 Is used as an anti-eutectic film between silicon (Si), which is the base material of the large-scale semiconductor element 11 and the defect relief macro 123, and gold (Au) as a metal thin film.
  • the melting temperature of the joint can be raised to 600 ° C. or higher. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if this joining is performed several times.
  • the oxide film of the SOI wafer itself is used as the eutectic prevention film. However, the same effect is obtained with a thermal oxide film or an oxide film formed by CVD.

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Abstract

A semiconductor device whose packing density is high and which has a lot of functions. This device is manufactured by joining semiconductor elements to each other by solid phase welding through metallic thin films. Since the semiconductor elements, which have conventionally been joined to each other with an adhesive or solder, are joined by the method of the invention, the strength, heat radiating property, and dimensional accuracy of the joint are improved and the length of wiring is shortened or the wiring itself can be omitted. Semiconductor elements are stacked by using this joining method, and hence a high-density semiconductor device which performs arithmetic operation at a high speed and has a high reliability is manufactured.

Description

明 細 書  Specification
半導体デバイスおよび製造方法  Semiconductor device and manufacturing method
技術分野 Technical field
本発明は半導体デバイ スおよびその製造方法に係わり、 特に、 高密度 化および多機能化を図るために各種の半導体素子を接合した半導体デバ イスおよびその製造方法に関する。  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which various semiconductor elements are joined to achieve high density and multifunctionality, and a method of manufacturing the same.
背景技術 Background art
半導体デバイスの高密度化や多機能化に伴い、 半導体素子の積層化や 接合が要求されている。  2. Description of the Related Art As semiconductor devices become more dense and multifunctional, semiconductor devices are required to be stacked and bonded.
半導体素子を接合した半導体デバイスまたはその接合方法に関する従 来技術と しては、 例えば、 「応用物理 第 6 0卷 第 8号 （ 1 9 9 1 ) P 7 9 0〜P 7 9 3 j (以下、 従来技術 1 という） 【こ、 シ リ コン基板同 志を洗浄活性化し接合面に O H基を形成した後、 シ リ コン基板同志を密 着させて加熱するこ とによ り シリ コン基板を接合する方法が開示されて いる。 また、 特開平 4一 5 6 2 6 2号公報 （以下、 従来技術 2 という） に、 半導体素子と樹脂を交互に接着剤を介して積層した多層構造の半導 体デバイ スが開示されている。 また、 特開平 5— 1 0 9 5 9 3 号公報 (以下、 従来技術 3 という） に、 半導体素子をはんだ板を介して積層し たのちに加熱して半導体素子を接合する半導体デバイ スの製造方法が開 示されている。 また、 特開平 3— 1 7 1 6 4 3号公報 （以下、 従来技術 4 という） に、 半導体デバイスの基板の電極と接合材である C C Bバン プとに原子またはイオンエネルギービームを照射して固相接合した後、 C C Bバンプをリ フローして液相接合する接合方法が開示されている。 発明の開示  As a conventional technology related to a semiconductor device in which semiconductor elements are bonded or a bonding method thereof, for example, “Applied Physics Vol. 60, No. 8, (1991) P790-P793j (hereinafter, referred to as“ Applied Physics ”) [This is referred to as Conventional Technology 1] [After silicon wafers are cleaned and activated to form OH groups on the bonding surface, the silicon substrates are adhered to each other and heated to heat the silicon substrates. Also, Japanese Patent Application Laid-Open No. HEI 5-56262 (hereinafter referred to as “prior art 2”) discloses a half-layer structure of a multilayer structure in which semiconductor elements and resins are alternately laminated via an adhesive. Japanese Patent Application Laid-Open No. Hei 5-109593 (hereinafter referred to as “prior art 3”) discloses that a semiconductor device is stacked via a solder plate and then heated. A method for manufacturing a semiconductor device for bonding a semiconductor element is disclosed. No. 17 1643 (Prior Art 4) discloses that solid-state bonding is performed by irradiating an atom or ion energy beam to the electrodes of a substrate of a semiconductor device and a CCB bump as a bonding material. A bonding method for performing liquid phase bonding by reflowing bumps is disclosed.
上記従来技術を半導体素子の接合に用いると次のよ うな問題が発生す る。 すなわち、 従来技術 1 のシリ コ ン基板を密着させて加熱するこ とによ り シ リ コ ン基板を接合する方法は、 接合後の寸法精度が高い接合方法で あるが、 接合時の温度が 1 0 o o t以上と高いため、 素子を形成したシ リ コン基板 （ 導体素子） の接合に本接合方法を用いると、 半導体素子 内配線の溶融、 半導体素子の拡散等によ り 、 半導体素子が破壊されてし ま う。 When the above-described conventional technology is used for joining semiconductor elements, the following problems occur. In other words, the method of bonding the silicon substrate by bringing the silicon substrate into close contact and heating according to the prior art 1 is a bonding method with high dimensional accuracy after bonding, but the bonding temperature is low. Since it is as high as 10 oot or more, if this bonding method is used to join the silicon substrate (conductor element) on which the element is formed, the semiconductor element will be destroyed due to melting of the wiring inside the semiconductor element, diffusion of the semiconductor element, etc. It has been done.
従来技術 2の半導体素子と樹脂を交互に接着剤を介して積層 した多層 構造の半導体デバイスは、 接着剤を使用するため接合作業を容易に行う こ とができるが、 接着剤の経時変化によ り接合した半導体素子が離脱す る可能性があり 半導体デバイ スと しての信頼性が十分ではない。 また、 接着部の熱抵抗が大きいため接着剤にて接合された半導体素子の放熱が 困難であり、 熱によ り 半導体デバイスが支障をきたす可能がある。 さ ら に、 接着剤は液状であり膜厚管理が困難であるため接合部の寸法精度を 確保するのが困難である。  In the case of a multi-layered semiconductor device in which the semiconductor element and resin of the prior art 2 are alternately laminated via an adhesive, the bonding operation can be easily performed because the adhesive is used. There is a possibility that the bonded semiconductor element may be detached, and the reliability as a semiconductor device is not sufficient. In addition, since the heat resistance of the bonding portion is large, it is difficult to dissipate the heat of the semiconductor element bonded by the adhesive, and the heat may hinder the semiconductor device. Furthermore, since the adhesive is liquid and it is difficult to control the film thickness, it is difficult to secure the dimensional accuracy of the joint.
従来技術 3の半導体素子をはんだ板を介して積層したのちに加熱して 半導体素子を接合する半導体デバイ スの製造方法は、 上記の従来技術 2 と同様、 接合作業を容易に行う こ とができるが、 はんだに含まれている フラ ックスが接続部内に巻き込まれて蒸発するこ とによ り ボイ ドが発生 しゃすく 、 接合強度を確保するのが困難である。 また、 フラ ックスの残 留によ り接合部に腐食が発生する可能性がある。 また、 接合温度ははん だの融点以上となるため、 接合可能な半導体素子は、 耐熱温度がはんだ の融点以下の半導体素子に限られてしま う。 また、 接合部の溶融温度は はんだの融点となるため複数の半導体デバイスを製造プロセスに従って 順番に接合する場合に同一のはんだを使用するこ とはできない。 また、 接合時ははんだが液状となっているため、 接合部の寸法精度を確保する のが困難である。 従来技術 4の C C Bバンプに原子またはイオンエネルギービームを照 射して固相接合した後、 C C Bバンプをリ フローして液相接合する接合 方法は、 接合と同時に素子と基板の配線が行われるため、 配線作業の省 力化を図るこ とができるが、 C C Bバンプがはんだによ り できているた め、 接合においては、 上記従来技術 3 と同様の問題がある。 The method of manufacturing a semiconductor device in which the semiconductor elements of the prior art 3 are stacked via a solder plate and then heated to join the semiconductor elements can easily perform the joining work as in the above-described prior art 2. However, when the flux contained in the solder is caught in the connection portion and evaporates, voids are generated and it is difficult to secure the bonding strength. Also, the residual flux may cause corrosion at the joint. Also, since the bonding temperature is higher than the melting point of the solder, the semiconductor elements that can be bonded are limited to those whose heat-resistant temperature is lower than the melting point of the solder. Also, since the melting temperature of the joint is the melting point of the solder, it is not possible to use the same solder when joining a plurality of semiconductor devices in sequence according to the manufacturing process. In addition, since the solder is in a liquid state at the time of joining, it is difficult to ensure the dimensional accuracy of the joined portion. The bonding method of prior art 4, in which the CCB bump is irradiated with an atom or ion energy beam and solid-phase bonded, then the liquid phase bonding is performed by reflowing the CCB bump because the wiring between the element and the substrate is performed simultaneously with the bonding. However, the wiring work can be saved, but since the CCB bumps are made of solder, there is the same problem as in the above-described conventional technology 3 in joining.
本発明の目的は、 各種の半導体素子を接合した信頼性の高い半導体デ バイスおよびその製造方法を提供することにある。  An object of the present invention is to provide a highly reliable semiconductor device in which various semiconductor elements are joined and a method for manufacturing the same.
上記目的は、 少なく と も 2個以上の半導体素子を接合して成る半導体 デバイスにおいて、 半導体素子間の接合部に金属薄膜を介して固相接合 したこ とにより達成される。  The above object can be achieved by solid-state bonding of at least two or more semiconductor elements to a junction between the semiconductor elements via a metal thin film.
半導体素子を接合して信頼性の高い半導体デバイスを製造するために は、 接合部の強度が十分であるこ と、 接合部の放熱性が高いこ と、 接合 後の寸法精度が高いこ と、 接合時の加熱温度が低いこ となどが必要であ る。  In order to manufacture a highly reliable semiconductor device by joining semiconductor elements, the joint must have sufficient strength, the joint must have high heat dissipation, and the dimensional accuracy after joining must be high. It is necessary that the heating temperature at the time is low.
そこで、 半導体素子間の接合部に金属薄膜を設け、 その金属薄膜に原 子またはイ オンのエネルギービームを照射した後、 接合面同志を密着さ せて加熱および加圧する方法を実験によ り確立した。  Therefore, a method was established through experiments in which a metal thin film was provided at the junction between semiconductor elements, and the metal thin film was irradiated with an energy beam of an atom or ion, and then the bonding surfaces were brought into close contact and heated and pressed. did.
第 8図 （ a ) は接合温度 1 0 O t:における接合強度と接合圧力の関係 を表したグラフであり 、 縦軸が接合強度、 横軸が接合圧力である。 第 8 図 （ b ) は接合圧力 5 M P a における接合強度と接合温度の関係を表し たグラフであり、 縦軸が接合強度、 横軸が接合温度である。 これらのグ ラフから判るよ う に、 本願発明の接合方法によれば、 半導体デバイスと して必要な接合部強度 1 O M P a を確保するには、 接合温度を 1 0 0 以上、 接合圧力を 5 M P a以上とすればよい。 また、 接合温度および接 合圧力の上限値を半導体素子が破壊しない限界値とすれば、 接合温度範 囲は 1 0 0〜 4 0 0で、 接合圧力範囲は 5〜 5 0 M P a となる。 この温 度範囲および圧力範囲は半導体素子に対して十分低い値となっているた め、 この接合方法を半導体デバイ スの接合に採用するこ と によ り 、 高密 度で多機能な信頼性の高い半導体デバイスの提供を可能にした。 FIG. 8 (a) is a graph showing the relationship between bonding strength and bonding pressure at a bonding temperature of 10 Ot: where the vertical axis indicates bonding strength and the horizontal axis indicates bonding pressure. Fig. 8 (b) is a graph showing the relationship between the joining strength and the joining temperature at a joining pressure of 5 MPa, where the vertical axis represents the joining strength and the horizontal axis represents the joining temperature. As can be seen from these graphs, according to the bonding method of the present invention, in order to secure a bonding strength of 1 OMPa required for a semiconductor device, a bonding temperature of 100 or more and a bonding pressure of 5 OMPa are required. The pressure may be set to MPa or more. Assuming that the upper limit of the junction temperature and the junction pressure is a limit value at which the semiconductor element is not broken, the junction temperature range is 100 to 400 and the junction pressure range is 5 to 50 MPa. This temperature Since the pressure range and the pressure range are sufficiently low for the semiconductor device, this bonding method is adopted for the bonding of the semiconductor device, and the high-density, multifunctional and highly reliable semiconductor The device can be provided.
すなわち本発明の半導体デバイスの望ま しい態様は以下のとおりであ る。  That is, desirable aspects of the semiconductor device of the present invention are as follows.
( 1 ) 少なく と も 2個以上の半導体素子を接合して成る半導体デバイス において、 前記半導体素子間の接合部に金属薄膜を介して固相接合する。  (1) In a semiconductor device formed by joining at least two or more semiconductor elements, solid-state joining is performed at a junction between the semiconductor elements via a metal thin film.
( 2 ) 上記 （ 1 ) において、 前記半導体素子を前記半導体デバイスの厚 さ方向に固相接合する。  (2) In the above (1), the semiconductor element is solid-phase bonded in a thickness direction of the semiconductor device.
( 3 ) 上記 （ 1 ) において、 基板上に前記半導体素子を前記半導体デバ イ スの長さ方向または幅方向に配置して固相接合する。  (3) In the above (1), the semiconductor element is arranged on a substrate in a length direction or a width direction of the semiconductor device and solid-phase bonded.
( ) 基板上に光半導体素子および光導波路を金属薄膜を介して固相接 合する。  (2) An optical semiconductor element and an optical waveguide are solid-phase bonded on a substrate via a metal thin film.
( 5 ) シ リ コ ン半導体素子とガリ ゥム砒素半導体素子とを金属薄膜を介 して固相接合する。  (5) Solid-state bonding between the silicon semiconductor element and the gallium arsenide semiconductor element via a metal thin film.
( 6 ) 上記 （ 1 ) 、 （ 4 ) 、 （ 5 ) のいずれかにおいて、 前記金属膜を、 材質の異なる 2つ以上の薄膜層によ り構成する。  (6) In any one of the above (1), (4) and (5), the metal film is composed of two or more thin film layers made of different materials.
( 7 ) 上記 （ 1 ) 、 （ 4 ) 、 （ 5 ) のいずれかにおいて、 半導体素子と 前記金属膜の間に、 前記半導体素子および前記金属薄膜と共晶しない材 料を挿入する。  (7) In any one of the above (1), (4) and (5), a material which does not eutectic with the semiconductor element and the metal thin film is inserted between the semiconductor element and the metal film.
( 8 ) 上記 （ 1 ) 、 （ 4 ) 、 （ 5 ) のいずれかにおいて、 前記金属膜を チタン（Ti)薄膜と金（Au)薄膜によ り構成する。  (8) In any one of the above (1), (4) and (5), the metal film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
( 9 ) 上記 （ 1 ) 、 （ 4 ) 、 （ 5 ) のいずれかにおいて、 前記金属膜を 0 , 5 〜 1 O O O n mのチ タ ン （Ti)薄膜と 2 〜 1 O O O O n mの金 (Au)薄膜により構成する。  (9) In any one of the above (1), (4) and (5), the metal film may be a titanium (Ti) thin film of 0,5 to 1 OOO nm and a gold (Au) of 2 to 1 OOOO nm It is composed of a thin film.
( 1 0 ) 上記 （ 1 ) 、 （ 4 ) 、 ( 5 ) のいずれかにおいて、 前記金属薄 膜を半導体素子の接合面に電気的に独立して複数形成し、 この複数形成 した金属薄膜の一部または全部を電極とする。 (10) In any one of (1), (4) and (5) above, A plurality of films are formed electrically independently on the bonding surface of the semiconductor element, and a part or all of the plurality of formed metal thin films is used as an electrode.
また、 本発明の半導体デバイスの製造方法の望ま しい態様は以下のと おりである。  Desirable aspects of the method for manufacturing a semiconductor device of the present invention are as follows.
( A) 少なく と も 2個以上の半導体素子を接合して成る半導体デバイス の製造方法において、 前記半導体素子間の接合部に金属薄膜を介して固 相接合する。  (A) In a method of manufacturing a semiconductor device in which at least two or more semiconductor elements are joined, solid-state joining is performed at a junction between the semiconductor elements via a metal thin film.
( B ) 上記 （A) において、 前記固相接合は、 互いに接合すべき前記半 導体素子の接合面のう ち少なく と も一方は予め金属薄膜を形成した接合 面と し、 真空中にて前記接合面に原子またはイ オンのエネルギービーム を照射して前記接合面の上 p汚染物を除去して前記接合面を活性化した 後、 前記接合面が再汚染しない接合雰囲気中にて金属薄膜の固相線温度 以下の温度で接合面同志を密着させて加圧し、 固相の状態で接合する。  (B) In the above (A), the solid-state bonding is performed in such a manner that at least one of the bonding surfaces of the semiconductor elements to be bonded to each other is a bonding surface on which a metal thin film is formed in advance, and the solid-state bonding is performed in a vacuum. After irradiating the bonding surface with an energy beam of atoms or ions to remove p contaminants on the bonding surface and activate the bonding surface, the metal thin film is formed in a bonding atmosphere in which the bonding surface does not re-contaminate. The joining surfaces are brought into close contact with each other at a temperature equal to or lower than the solidus temperature and pressurized to join in the solid state.
( C ) 上記 （A) において、 前記金属薄膜を材質の異なる 2つ以上の薄 膜層によ り構成する。  (C) In the above (A), the metal thin film is composed of two or more thin film layers made of different materials.
(D) 上記 （A) において、 前記半導体素子と前記金属薄膜の間に前記 半導体素子および前記金属薄膜と共晶反応しない材料を挿入する。  (D) In the above (A), a material that does not undergo eutectic reaction with the semiconductor element and the metal thin film is inserted between the semiconductor element and the metal thin film.
( E ) 上記 （ C) において、 前記金属薄膜をチタン（Ti)薄膜と金（Au) 薄膜によ り構成する。  (E) In the above (C), the metal thin film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
( F ) 上記 （ E) において、 前記金属薄膜は 0. 5〜 1 0 0 0 n mのチ タン（Ti)薄膜と 2〜 1 0 0 0 0 n mの金（Au)薄膜によ り成る。  (F) In the above (E), the metal thin film comprises a titanium (Ti) thin film of 0.5 to 1000 nm and a gold (Au) thin film of 2 to 1000 nm.
(G ) 上記 （ B ) において、 前記固相接合は前記金属薄膜中に双晶¾形 が生じる温度および庄カにて接合する。  (G) In the above (B), the solid phase bonding is performed at a temperature and a temperature at which a twin crystal form occurs in the metal thin film.
(H ) 上記 （G) において、 前記温度を 1 0 0〜 4 0 0£1( 、 前記圧力を 5〜 5 0M P a とする。 (H) In the above (G), the temperature is 100 to 400 £ 1 (, and the pressure is 5 to 50 MPa.
ところで、 本明細書において、 半導体素子とは、 独立した機能をもち、 半導体デバイスの構成要素となるものを指す。 例えば、 光半導体デバイ スにおける光導波路も半導体素子という。 By the way, in this specification, a semiconductor element has an independent function, Refers to a component of a semiconductor device. For example, an optical waveguide in an optical semiconductor device is also called a semiconductor element.
また、 本明細書において、 固相接合とは、 接合材料の固相線以下の温 度で接合することを意味しており 、 接合材料の固相線以上の温度で接合 を行う ものは含んでいない。  In this specification, solid-phase bonding means bonding at a temperature lower than the solidus of the bonding material, and includes bonding at a temperature higher than the solidus of the bonding material. Not in.
次に本発明の作用について説明する。  Next, the operation of the present invention will be described.
半導体素子を金属薄膜を介して固相接合するこ とによ り 、 接合温度お よび接合圧力を低くするこ とができるため、 半導体デバイ スの信頼性を 確保することができる。 また、 十分な接合強度が確保でき、 しかも、 接 合部が経時劣化するこ と もないため半導体素子が離脱する心配がない。 また、 接合部の溶融温度が接合温度よ り十分高い温度となるため、 1 度 接合を行った半導体素子に対して同じ接合条件で何度も接合するこ とが できるため、 半導体製造プロセスに従って順番に半導体素子を接合する ことができる。 また、 接合部が金属接合となるため、 半導体素子の熱を 効率よ く放熱するこ とができる。  The solid-state bonding of the semiconductor element via the metal thin film can lower the bonding temperature and the bonding pressure, so that the reliability of the semiconductor device can be secured. In addition, sufficient bonding strength can be ensured, and there is no concern that the semiconductor element will be detached because the bonded portion does not deteriorate with time. In addition, since the melting temperature of the bonding portion is sufficiently higher than the bonding temperature, the semiconductor device that has been bonded once can be bonded many times under the same bonding conditions. The semiconductor element can be bonded to the substrate. Further, since the bonding portion is a metal bonding, heat of the semiconductor element can be efficiently radiated.
また、 半導体素子を前記半導体素子の厚さ方向に固相接合するこ とに よ り 、 半導体デバイスの設置面積に対する集積密度を高めるこ とができ る。  Further, by solid-phase bonding the semiconductor element in the thickness direction of the semiconductor element, the integration density with respect to the installation area of the semiconductor device can be increased.
また、 基板上に、 要求された仕様に合わせて選択した各々機能の異 なった半導体素子を半導体素子の長さ方向または幅方向に配置して固相 接合することによ り 、 従来個別に設計対応していた半導体デバイスが短 期間で製作することができる。  Conventionally, semiconductor devices with different functions selected according to the required specifications are arranged in the length direction or width direction of the semiconductor device and solid-phase bonded on the substrate, so that they can be individually designed. Compatible semiconductor devices can be manufactured in a short time.
また、 基板上に光素子および光導波路を金属薄膜を介して固相接合す るこ とによ り、 性能の良い光半導体デバイスを短時間で製作するこ とが できる。  In addition, solid-state bonding of an optical element and an optical waveguide to a substrate via a metal thin film allows a high-performance optical semiconductor device to be manufactured in a short time.
また、 シリ コン半導体素子にガリ ゥム砒素半導体素子を金属薄膜を介 して固相接合することによ り 、 精度の高い光伝送半導体デバイスを製造 するこ とができる。 In addition, a gallium arsenide semiconductor device is interposed on a silicon semiconductor device via a metal thin film. By performing the solid-state bonding, a highly accurate optical transmission semiconductor device can be manufactured.
また、 金属薄膜を、 チタン（T i )薄膜と金（A u )薄膜で構成するこ とに よ り半導体素子に対する金属薄膜の剥離強度を高めるこ とができる。 また、 金属薄膜を、 半導体素子の接合面に電気的に独立して複数形成 し、 この複数形成された金属薄膜の一部または全部を電極とするこによ り、 半導体素子間の配線が不要となるため、 配線作業の省力化が図れる。 また、 配線長さが最短となるため、 半導体デバイ スの演算速度を高める こ とができる。  Further, by forming the metal thin film from a titanium (Ti) thin film and a gold (Au) thin film, the peel strength of the metal thin film from the semiconductor element can be increased. In addition, since a plurality of metal thin films are formed electrically independently on the bonding surface of the semiconductor element and part or all of the formed metal thin films are used as electrodes, wiring between the semiconductor elements is unnecessary. Therefore, labor saving of wiring work can be achieved. Further, since the wiring length is shortest, the operation speed of the semiconductor device can be increased.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
第 1 図は、 本発明の第 1 の実施例による積層形半導体デバイ スの外観 図である。  FIG. 1 is an external view of a stacked semiconductor device according to a first embodiment of the present invention.
第 2図は、 本発明の第 1 の実施例による積層形半導体デバイ スの製造 方法を示す図である。  FIG. 2 is a diagram illustrating a method of manufacturing a stacked semiconductor device according to a first embodiment of the present invention.
第 3図は、 本発明の第 1 の実施例による接合界面の金属断面図である。 第 4図は、 本発明の第 1 の実施例による平面接合形半導体デバイスの 外観図である。  FIG. 3 is a metal cross-sectional view of a bonding interface according to the first embodiment of the present invention. FIG. 4 is an external view of a planar junction type semiconductor device according to a first embodiment of the present invention.
第 5図は、 本発明の第 2の実施例による光伝送半導体デバイスの製造 方法を示す図である。  FIG. 5 is a diagram illustrating a method of manufacturing an optical transmission semiconductor device according to a second embodiment of the present invention.
第 6図は、 本発明の第 3の実施例による光半導体デバイ スの製造方法 を示す図である。  FIG. 6 is a diagram showing a method for manufacturing an optical semiconductor device according to a third embodiment of the present invention.
第 7図は、 本発明の第 4の実施例による大規模半導体デバイスの欠陥 救済方法を示す図である。  FIG. 7 is a diagram showing a defect repair method for a large-scale semiconductor device according to a fourth embodiment of the present invention.
第 8図は、 本発明の接合条件と接合強度の関係を示す図である。  FIG. 8 is a diagram showing a relationship between bonding conditions and bonding strength of the present invention.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[実施例 1 ] 以下、 本発明の第 1 の実施例を図面に従い詳細に説明する。 [Example 1] Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.
第 1 図は、 積層形半導体デバイスの外観を示す。 4 1 1 は 卜ランジス タのゲ一 卜、 4 1 2は ト ランジス タのゲー ト酸化膜、 4 4 は配線、 4 7 1 は上部電極、 7 2は下部電極、 4 7 3 は基板電極、 4 8 1 、 8 2 は金属薄膜、 4 6は導電性膜、 4 0 4は基板、 4 0 1 、 4 0 2 、 4 0 3 は積層接合用半導体素子である。  Fig. 1 shows the appearance of the stacked semiconductor device. 4 11 1 is the gate of the transistor, 4 12 is the gate oxide film of the transistor, 4 4 is the wiring, 4 7 1 is the upper electrode, 7 2 is the lower electrode, 4 7 3 is the substrate electrode, Reference numerals 481 and 82 denote metal thin films, 46 denotes a conductive film, 404 denotes a substrate, and 410, 402, and 403 denote semiconductor elements for stacking and bonding.
第 2図は、 積層形半導体デバイ スの製造方法を示す。 4 9はアルゴン ( A r ) 原子ビームである。  FIG. 2 shows a method of manufacturing a stacked semiconductor device. 49 is an argon (Ar) atomic beam.
第 3図は、 接合界面の金属断面を示す。 2 1 は金薄膜、 2 2は双晶変 形、 2 3は接合界面、 2 4はボイ ドである。  FIG. 3 shows a metal cross section at the bonding interface. 21 is a gold thin film, 22 is twin deformation, 23 is a bonding interface, and 24 is a void.
第 4図は、 平面接合形半導体デバイ スの外観を示す。 6 1 0は基板、 6 0 1 〜 6 0 6は平面接合用半導体素子、 6 3 1 、 6 3 2 は金属薄膜で ある。  Fig. 4 shows the appearance of a planar junction type semiconductor device. Reference numeral 61 denotes a substrate, reference numerals 61 to 606 denote semiconductor elements for planar bonding, and reference numerals 631 and 632 denote metal thin films.
積層形半導体デバイスは、 第 1 図 （ a ) に示す積層接合用半導体素子 を第 1 図 （ b ) よ うに複数積層したものであり 、 高密度化、 多機能化を 図った半導体デバイスである。  The stacked semiconductor device is a semiconductor device in which a plurality of stacked junction semiconductor elements shown in FIG. 1 (a) are stacked as shown in FIG. 1 (b), and which achieves high density and multifunctionality.
トランジスタは、 通常の半導体プロセスを用いてゲー ト 4 1 1ゃゲ一 卜酸化膜 4 1 2などを形成して製造する。 各 ト ラ ンジスタは表面絶縁層 4 2 1 、 裏面絶縁層 4 2 2および素子間絶縁膜 4 2 3によって互いに絶 縁分離されており、 各 ト ランジスタの単結晶シリ コ ン膜 4 3 1 の両端に 形成されたソースおよび ドレイン 4 3 2には、 配線 4 4がそれぞれ接続 されている。 配線 4 4 は表面絶縁層 4 2 1 に形成された表面スルーホー ル 4 5 1 內に充填された導電性膜 4 6 を介して上部電極 4 7 1 に接続さ れている。 さ らに、 配線 4 4 は、 裏面絶縁層 4 2 2 に形成された裏面ス ルーホール 4 5 2を充填する導電性膜 4 6 を介して下部電極 4 7 2 に接 続されている。 こ こで、 上部電極 4 7 1および下部電極 4 7 2は厚さ 0 . θ The transistor is manufactured by forming a gate 411 gate oxide film 412 and the like using a normal semiconductor process. The transistors are isolated from each other by a front insulating layer 421, a rear insulating layer 42, and an inter-element insulating film 43, and both ends of the single-crystal silicon film 43 of each transistor. Wirings 44 are respectively connected to the source and drain 432 formed at the bottom. The wiring 44 is connected to the upper electrode 471 via a conductive film 46 filled in a surface through hole 451 formed on the surface insulating layer 421. Further, the wiring 44 is connected to the lower electrode 472 via a conductive film 46 filling the rear through hole 452 formed in the rear insulating layer 42. Here, the upper electrode 471 and the lower electrode 472 have a thickness of 0. θ
5〜 1 O O O nmのチタン （Ti ) 薄膜、 次いで、 厚さ 2〜 1 O O O O nm の金 （Au) 薄膜によ り形成され、 金 （Au) 面を接合面と している。 It is formed of a titanium (Ti) thin film with a thickness of 5 to 1 OO O nm and then a gold (Au) thin film with a thickness of 2 to 1 OO O nm, and the gold (Au) surface is used as a bonding surface.
こ こで、 チタン （Ti ) 薄膜の厚さ範囲を 0 . 5〜 1 0 0 0 nmと した のは、 この範囲であればチタン （Ti ) が薄膜を形成し、 しかもチタン (Ti) 薄膜が内部応力による剥離強度の低下がなく 十分な接合強度を示 すからである。 また、 金 （Au) 薄膜の厚さ範囲を 2〜 1 0 0 0 0 ηπιと したのは、 この範囲であれば金 （Au) 薄膜が接合面であるシリ コンの表 面荒さをカバ一でき、 しかも金 （Au) 薄膜を設ける作業性がよ く 十分な 強度を示すからである。  Here, the reason that the thickness range of the titanium (Ti) thin film is set to 0.5 to 100 nm is that, in this range, the titanium (Ti) forms a thin film and the titanium (Ti) thin film is formed. This is because there is no decrease in peel strength due to internal stress and sufficient bonding strength is exhibited. The reason why the thickness range of the gold (Au) thin film is set to 2 to 1000 ηπι is that within this range, the surface roughness of the silicon where the gold (Au) thin film is the bonding surface can be covered. In addition, the workability of providing a gold (Au) thin film is good and the strength is sufficient.
また、 チタン（Ti)薄膜の上に金（Au)薄膜を挿入したのは金（Au)薄膜 の剥離強度を高めるためであり、 チタンの代わり にク ロム （Cr) 等金薄 膜の剥離強度を高める薄膜を挿入してもよい。  The gold (Au) thin film was inserted on the titanium (Ti) thin film in order to increase the peel strength of the gold (Au) thin film, and instead of titanium, the peel strength of a thin gold film such as chromium (Cr) was used. May be inserted.
このよ うに、 接合面を電極とするこ とによ り配線を省略するこ とがで き、 半導体製造工程の省力化および半導体デバイスの演算速度の向上を 図るこ とができる。  In this manner, the wiring can be omitted by using the bonding surface as an electrode, so that it is possible to save the labor of the semiconductor manufacturing process and improve the operation speed of the semiconductor device.
また、 装置固定用と して表面絶縁層 4 2 1 の表面に金属薄膜 4 8 1 と し てチタン （Ti) 薄膜を厚さ 0 . 5〜 1 0 0 0 nm、 次いで金 （Au) 薄膜 を厚さ 2〜 1 0 0 0 0 nm形成し、 さ らに、 裏面絶縁層 4 2 2の表面にも 同様な金属薄膜 4 8 2を形成し、 各々金 （Au) 面を接合面と している。 次に、 接合工程について説明する。 第 4図（a)に示すよ うに、 ァルゴ ン （ Ar ) 原 子 ビ ー ム 4 9 が 照 射 で き る 圧 力 下 （ 例 え ば 1 X 1 0一4〜 1 X 1 0— 3 Torrの真空） に第 1 の積層接合用半導体素子 4 0 1 を下方、 第 2の積層接合半導体素子 4 0 2 を上方と して設置し、 第 1 の積層接合用半導体素子 4 0 1 の表面側接合面および第 2 の積層接 合半導体素子 4 0 2の裏面側接合面にアルゴン （Ar) 原子ビーム 4 9を 照射する。 これによ り接合面に付着している酸化膜、 水分、 油脂分等の 汚染物を除去し、 接合面を活性化する。 なお、 アルゴン （Ar) 原子ビ一 ム 4 9を照射する面が金属面であるため照射面がチャージアップせず、 半導体デバイスに電気的なダメージを与えるこ とはない。 その後、 第 4 図（b)に示すよ う に、 5 x 1 0一6 Torr以下の真空中で接合面同志を対 向させた後、 密着させて固相の状態で接合する。 なお、 接合時圧力は 5 X 1 0—6 Torr以下の真空でなく ても、 アルゴン （Ar) 原子ビーム 4 Further, a titanium (Ti) thin film having a thickness of 0.5 to 100 nm as a metal thin film 481, and then a gold (Au) thin film as a metal thin film 481 are provided on the surface of the surface insulating layer 421 for fixing the device. A thickness of 2 to 1000 nm is formed, and a similar metal thin film 482 is formed also on the surface of the backside insulating layer 422, each having a gold (Au) surface as a bonding surface. I have. Next, the joining step will be described. Figure 4 urchin by showing (a), the Arugo emissions (Ar) atomic bi chromatography beam 4 9 pressure under that can by irradiation morphism (eg if 1 X 1 0 one 4 ~ 1 X 1 0- 3 Torr The first stacked junction semiconductor element 401 is placed below and the second stacked junction semiconductor element 402 is placed above, and the front side of the first stacked junction semiconductor element 401 is placed in a vacuum. The bonding surface and the bonding surface on the back side of the second stacked bonding semiconductor element 402 are irradiated with an argon (Ar) atomic beam 49. As a result, the oxide film, moisture, Removes contaminants and activates bonding surfaces. Since the surface irradiated with the argon (Ar) atomic beam 49 is a metal surface, the irradiated surface does not charge up and does not cause electrical damage to the semiconductor device. Thereafter, as shown in FIG. 4 (b), the bonding surfaces are opposed to each other in a vacuum of 5 × 10 to 16 Torr or less, and then bonded together in a solid state. The bonding time of the pressure not be a vacuum below 5 X 1 0- 6 Torr, argon (Ar) atoms beam 4
9を照射した接合面が再汚染しない雰囲気であれば良い。 Any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate.
次いで、 第 4図（c)に示すよ うに、 アルゴン （Ar) 原子ビーム 4 9が 照射できる圧力下 （例えば 1 x 1 0— 4〜 1 x 1 0—3 Torrの真空） に第 3 の積層接合用半導体素子 4 0 3 を上方、 第 1の積層接合用半導体素子 4 0 1 と第 2 の積層接合半導体素子 4 0 2を接合した半導体素子を下方 と して設置し、 第 2の積層接合用半導体素子 4 0 1 の表面側接合面およ び第 3 の積層接合半導体素子 4 0 3 の裏面側接合面にアルゴン （Ar) 原 子ビーム 49を照射する。 これによ り接合面に付着している酸化膜、 水分、 油脂分等の汚染物を除去し、 接合面を活性化する。 その後、 第 4図（d) に示すよ う に、 5 X 10— 6 Torr以下の真空中で接合面同志を対向させた 後 、 密着 さ せて 固 相 の状態 で接合す る 。 な お 、 接合時圧力 は 5 X 1 0—6 Torr以下の真空でなく ても、 アルゴン （Ar) 原子ビーム 4 Then, the third stack of FIG. 4 (c) to I shown urchin, argon (Ar) atoms beam 4 under a pressure 9 can be irradiated (e.g., 1 x 1 0- 4 ~ 1 x 1 0- 3 Torr of vacuum) The semiconductor element in which the first semiconductor element 401 for bonding and the second semiconductor element 402 for bonding in the second layer are connected in the lower position, and the semiconductor element for bonding 400 3 is positioned in the upper part. The argon (Ar) atomic beam 49 is irradiated to the front-side bonding surface of the semiconductor device 401 for use and the rear-side bonding surface of the third stacked bonding semiconductor device 400 3. This removes contaminants such as oxide film, moisture, oils and fats adhering to the joint surface and activates the joint surface. Thereafter, as shown in FIG. 4 (d), the bonding surfaces are opposed to each other in a vacuum of 5 × 10−6 Torr or less, and then bonded together in a solid phase. Contact name joining at pressure not be a vacuum below 5 X 1 0- 6 Torr, argon (Ar) atoms beam 4
9を照射した接合面が再汚染しない雰囲気であれば良い。 こ の とき、 接 合面の温度、 すなわち接合温度は 1 0 0〜 4 0 0で、 接合圧力は 5〜 5 0 M P aである。 Any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate. At this time, the temperature of the joining surface, that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
また、 表面絶縁層 4 2 1 の酸化膜 （Si0 2 ) を母材であるシ リ コ ン (Si) と金属薄膜の金 （Au) との共晶防止膜と して利用するこ と によ り 、 接合部の溶融温度を 6 0 0T以上にするこ とができる。 この温度は、 接合温度 1 0 0〜 4 0 0 Όに比べ、 十分高い温度となっているため、 こ の接合を何度おこなっても接合部が溶融するこ とはない。 なお、 共晶防 止膜と して本実施例では so I ウェハ自体の酸化膜を利用 しているが、 熱酸化膜または C V Dによる酸化膜であってもその効果は同じである。 また、 この接合温度および接合圧力の条件下では、 第 3図に示すよ う に金属薄膜である金 （Au) 薄膜 2 1 中に双晶変形 2 2が生じるため接合 面同志の密着が図られ、 接合界面 2 3でのボイ ド 2 4 の少ない接合がで きる。 接合部の強度は l O M p a 以上であり 、 半導体デバイス製造プロ セスのハン ドリ ングに対しては十分な強度となっている。 Also, the oxide film (Si02) of the surface insulating layer 421 is used as a eutectic film between silicon (Si) as a base material and gold (Au) of a metal thin film. Thus, the melting temperature of the joint can be set to 600 T or more. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if the joining is performed several times. The eutectic protection In this embodiment, the oxide film of the soI wafer itself is used as the stop film, but the same effect can be obtained by using a thermal oxide film or an oxide film formed by CVD. Also, under the conditions of the bonding temperature and the bonding pressure, as shown in FIG. 3, twin deformation 22 occurs in the gold (Au) thin film 21 which is a metal thin film, so that the bonding surfaces are bonded to each other. Thus, bonding with few voids 24 at the bonding interface 23 can be performed. The strength of the joint is equal to or more than l OM pa, which is sufficient for the soldering of the semiconductor device manufacturing process.
第 4図は、 基板 6 1 0上に半導体素子 6 0 1 〜 6 0 6 を平面状に配置 して本発明によ り接合したものである。 このよ う に各々機能の異なった 半導体素子を要求された仕様に合わせて選択し、 本発明によ り平面上に 接合すれば、 従来個別仕様に合わせて設計していた半導体デバイスを短 期間で製作するこ とができる。  FIG. 4 shows that semiconductor elements 600 1 to 600 are arranged in a plane on a substrate 610 and joined according to the present invention. As described above, by selecting semiconductor elements having different functions according to required specifications and bonding them on a plane according to the present invention, a semiconductor device that has been conventionally designed according to individual specifications can be manufactured in a short time. Can be manufactured.
[実施例 2 ]  [Example 2]
以下、 本発明の第 2の実施例を図面に従い詳細に説明する。  Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.
第 5図は、 光伝送半導体デバイスにおける接合を示したものである。  FIG. 5 shows a junction in an optical transmission semiconductor device.
5 1 はシリ コ ン基板、 5 2は光導波路、 5 3は光半導体素子、 5 4は光 ファイバ、 5 5 1 〜 5 5 4は金属薄膜である。 51 is a silicon substrate, 52 is an optical waveguide, 53 is an optical semiconductor element, 54 is an optical fiber, and 515 to 554 are metal thin films.
第 5図（a)に示すよ う に、 光伝送半導体デバイスはシリ コ ン （Si) 基 板 5 1上に光導波路 5 2、 光半導体素子 5 3 を固定し、 光ファイバ 5 4 を取り付けた構造となっている。 光導波路 5 2、 光半導体素子 5 3 、 光 ファイバ 5 4は、 その取付精度が高く ないと、 性能を発揮するこ とがで きない。  As shown in Fig. 5 (a), the optical transmission semiconductor device has an optical waveguide 52, an optical semiconductor element 53 fixed on a silicon (Si) substrate 51, and an optical fiber 54 attached. It has a structure. The optical waveguide 52, the optical semiconductor element 53, and the optical fiber 54 cannot exhibit their performance unless their mounting accuracy is high.
こ こで、 光導波路 5 2および光半導体素子 5 3 をシ リ コ ン基板に接合 する工程について説明する。  Here, a process of joining the optical waveguide 52 and the optical semiconductor element 53 to a silicon substrate will be described.
第 5図（b)に示すよ うに、 まず、 金属薄膜 5 5 1 、 5 5 2 と して真空 蒸着によ り チタ ン （Ti ) 薄膜を厚さ 0 · 5 〜 1 0 0 0 nm、 次いで金 (Au) 薄膜を厚さ 2〜 l O O O O nm形成し、 金面を接合面とするシ リ コン基板 5 1 と、 同様な金属薄膜 5 5 3 を形成した光導波路 5 2および 同様な金属薄膜 5 5 4 を形成した光素子 5 3 をアルゴン （Ar) 原子ビー ム 5 6が照射できる圧力下 （例えば 1 x l O— 4〜 1 x l O— 3Torrの真 空） に設置し、 各接合面にアルゴン （Ar) 原子ビーム 5 6 を照射する。 これによ り接合面に付着している酸化膜、 水分、 油脂分等の汚染物を除 去し、 接合面を活性化する。 その後、 まず、 第 5図（c)に示すよ う に、 5 X 1 0— 6 Torr以下の真空中でシリ コン基板 5 1 および光導波路 5 2 の接合面同志を密着して固相の状態で接合する。 なお、 接合時圧力は 5 X 1 0— 6 Torr以下の真空でなく ても、 アルゴン （Ar) 原子ビーム 5As shown in Fig. 5 (b), first, a titanium (Ti) thin film was formed to a thickness of 0.5 to 100 nm by vacuum evaporation as metal thin films 551, 552, and then Money (Au) A silicon substrate 51 with a thickness of 2 to l OOOO nm and a gold surface as a bonding surface, an optical waveguide 52 with a similar metal thin film 55 3 and a similar metal thin film 5 The optical element 53 formed with 54 is placed under a pressure (for example, a vacuum of 1 xl O— 4 to 1 xl O— 3 Torr) under which the argon (Ar) atom beam 56 can irradiate, and Irradiate an argon (Ar) atomic beam 56. This removes contaminants such as oxide film, moisture, oils and fats adhering to the joint surface and activates the joint surface. Then, first, fifth Remind as in Figure (c), 5 X 1 0- 6 Torr or less in the state of the silicon substrate 5 1 and the optical waveguide 5 2 of closely bonding surfaces each other with the solid phase in vacuo Join with. The bonding time of the pressure not be a vacuum below 5 X 1 0- 6 Torr, argon (Ar) atoms beam 5
6 を照射した接合面が再汚染しない雰囲気であれば良い。 次いで、 第 5 図（d)に示すよ う に、 シ リ コ ン基板 5 1 および光素子 5 3 の接合面同士 を密着して固相の状態で接合する。 このと き、 接合面の温度、 すなわち 接合温度は 1 0 0〜 4 0 01C , 接合圧力は 5〜 5 0 M P a である。 It is sufficient that the atmosphere irradiated with 6 does not recontaminate the joint surface. Next, as shown in FIG. 5 (d), the bonding surfaces of the silicon substrate 51 and the optical element 53 are brought into close contact with each other and bonded in a solid state. At this time, the temperature of the bonding surface, that is, the bonding temperature is 100 to 400C, and the bonding pressure is 5 to 50 MPa.
光伝送用半導体デバイスにおいては、 光半導体素子 5 3 から発せられ る光を効率良く 光導波路 5 2 を経由させ光ファイバ 5 4に導く必要があ る。 従来は、 接着剤にて光素子、 光導波路を接合しているため、 その位 置決めが困難であり、 熟練者の作業となっていた。  In a semiconductor device for optical transmission, it is necessary to efficiently guide the light emitted from the optical semiconductor element 53 through the optical waveguide 52 to the optical fiber 54. In the past, since the optical element and the optical waveguide were bonded with an adhesive, it was difficult to determine the position, and this was an operation of a skilled person.
しかし、 本発明によ り光半導体素子 5 3 、 光導波路 5 2を接合すれば、 接合によ り寸法誤差を発生する可能性のある部材は、 金属薄膜だけであ るため、 接合の位置決めを正しくすれば、 接合後の位置も正しく設定す るこ とができる。  However, if the optical semiconductor element 53 and the optical waveguide 52 are joined according to the present invention, the only member that may cause a dimensional error due to the joining is the metal thin film. If it is correct, the position after joining can be set correctly.
[実施例 3 ]  [Example 3]
以下、 本発明の第 3の実施例を図面に従い詳細に説明する。  Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings.
第 6図は、 光半導体デバイスの製造過程を示したものである。 3 1 は シ リ コ ン半導体素子、 3 2はガリ ウム砒素半導体素子、 3 4はアルゴン (Ar) 原子ビーム、 3 3 1 、 3 3 2は金属薄膜である。 FIG. 6 shows the manufacturing process of the optical semiconductor device. 31 is a silicon semiconductor device, 32 is a gallium arsenide semiconductor device, and 34 is argon (Ar) Atomic beam, 331 and 332 are metal thin films.
光半導体デバ イ ス は、 シ リ コ ン （ Si ) 半導体素子 と ガ リ ウ ム砒素Optical semiconductor devices consist of silicon (Si) semiconductor devices and gallium arsenide.
(GaAs) 半導体素子の異種材を接合するこ と によ り製造する こ とがで さる。 (GaAs) It can be manufactured by joining different materials of semiconductor elements.
第 3図（a)に示すよ う に、 金属薄膜 3 3 1 と して真空蒸着によ り チタ ン （Ti ) 薄膜を厚さ 0 . 5〜 1 0 0 0 nm、 次いで金 （Au) 薄膜を厚さ 2〜 1 O O O O nm形成し、 金面を接合面とするシ リ コ ン半導体素子 3 1 と、 同様な金属薄膜 3 3 2を形成したガリ ゥム砒素半導体素子 3 2 をァ ノレ ゴ ン （ A r ) 原 子 ビ ー ム 3 4 が 照射 で き る 圧 力 下 （ 例 え ば 1 X 1 0— 4〜： I X 1 0— 3 Torrの真空） に設置 し、 接合面にア ル ゴ ン As shown in Fig. 3 (a), a titanium (Ti) thin film is formed to a thickness of 0.5 to 100 nm by vacuum evaporation and then a gold (Au) thin film as a metal thin film 331. A silicon semiconductor element 31 with a thickness of 2 to 1 OOOO nm and a gold surface as a bonding surface, and a gallium arsenide semiconductor element 32 with a similar metal thin film 33 2 emissions (a r) nuclear bi over beam 3 4 pressure under that can irradiation (eg if 1 X 1 0- 4 ~: IX 1 0- 3 Torr of vacuum) was placed in, a Le on the bonding surface Gon
(Ar) 原子ビーム 3 4 を照射する。 これによ り接合面に付着している酸 化膜、 水分、 油脂分等の汚染物を除去し、 接合面を活性化する。 その後、 第 3 図（b)に示すよ う に、 5 x 1 0一6 Torr以下の真空中で接合面同志 を対向させた後密着させて固相の状態で接合する。 なお、 接合時圧力は 5 x 1 0一6 Torr以下の真空でなく ても、 アルゴン （Ar) 原子ビーム 3 (Ar) Irradiation of atomic beam 3 4. This removes contaminants such as an oxide film, moisture, oils and fats adhering to the joint surface and activates the joint surface. Thereafter, as shown in FIG. 3 (b), the bonding surfaces are brought into contact with each other in a vacuum of 5 × 10 to 16 Torr or less, and then brought into close contact with each other to bond in a solid state. Note that even if the bonding pressure is not a vacuum of 5 × 10 to 16 Torr or less, the argon (Ar) atomic beam 3
4 を照射した接合面が再汚染しない雰囲気であれば良い。 この とき、 接 合面の温度、 すなわち接合温度は 1 0 0〜 4 0 0 、 接合圧力は 5〜 5 0 M P a である。 It is sufficient that the joint surface irradiated with 4 does not recontaminate the surface. At this time, the temperature of the joining surface, that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
シリ コ ン半導体素子とガリ ゥム半導体素子との接合を本発明で行えば、 シリ コ ン半導体デバイス 31とガリ ゥム砒素半導体デバイス 32の高さを 同じにするこ とができるため、 半導体素子間の配線は薄膜状の金属配線 で行う こ とができるため配線密度が高ま り半導体デバイスの高集積化が 可能となる。 また、 接合面の一部を接点とするこ とによ り 、 配線作業の 省力化を図るこ とができる。  If the silicon semiconductor element and the gallium semiconductor element are joined by the present invention, the height of the silicon semiconductor device 31 and the height of the gallium arsenide semiconductor device 32 can be made the same. Since the wiring between them can be made of thin-film metal wiring, the wiring density is increased, and high integration of semiconductor devices becomes possible. In addition, by using a part of the joint surface as a contact point, it is possible to save labor in wiring work.
[実施例 4 ]  [Example 4]
以下、 本発明の第 4の実施例を図面に従い詳細に説明する。 第 7図は大規模半導体デバイスの欠陥救済方法を示す。 1 1 は大規模 半導体素子、 1 3は接合溝、 1 5は薄膜大規模半導体素子、 1 6はアル ゴン （Ar) 原子ビーム、 1 2 1 、 1 2 2はマク ロ、 1 2 3は欠陥救済マ ク ロ、 1 4 1 、 1 4 2は金属薄膜である。 Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 7 shows a method for repairing a defect in a large-scale semiconductor device. 11 is a large-scale semiconductor device, 13 is a junction groove, 15 is a thin-film large-scale semiconductor device, 16 is an argon (Ar) atomic beam, 121, 122 are macro, and 123 are defects The relief macro, 141 and 142 are metal thin films.
大規模半導体素子は歩留ま り向上のため欠陥救済という作業を実施す る。 これは、 大規模半導体素子を構成する複数のマク ロ と呼ばれる個別 の機能を持つ回路ブロ ックのう ち不良となったマク ロ を取り除き、 そこ に、 欠陥のないマク ロを接合するこ とによ り不良となった大規模半導体 素子を救済する という作業である。  For large-scale semiconductor devices, defects are remedied to improve yield. This is to remove the defective macro from the circuit blocks that have individual functions called macros that make up a large-scale semiconductor device, and join macros without defects to them. The task is to rescue large-scale semiconductor devices that have become defective.
第 7図（a)は欠陥救済を必要とする大規模半導体素子を示す。 S O I ウェハから作られた大規模半導体素子 1 1 はマク ロ 1 2 1 、 1 2 2 と呼 ばれる個別の機能を持つ回路ブロ ックによ り構成される。 例えば、 マク 口 1 2 1 の回路には欠陥がなく 、 マク ロ 1 2 2の回路には欠陥が生じて いるものとする。  FIG. 7 (a) shows a large-scale semiconductor device requiring defect relief. Large-scale semiconductor devices 11 made from SOI wafers are composed of circuit blocks with individual functions called macros 121 and 122. For example, it is assumed that there is no defect in the circuit of the macro mouth 1221, and that the circuit of the macro 122 has a defect.
まず、 欠陥除去工程について説明する。 この欠陥が生じているマク ロ 1 2 2をエッチングによ り除去し、 第 1 図（b)に示すよ う に接合溝 1 3 を形成する。 次に第 1 図（c)に示すよ うに接合溝 1 3 に金属薄膜 1 4 1 と して真空蒸着によ り チタン （Ti ) 薄膜を厚さ 0 . 5 〜 1 0 0 0 nm、 次いで金 （Au) 薄膜を厚さ 2 ~ 1 0 0 0 0 ηπι形成し、 金面を接合面と する。 こ こで、 接合溝 1 3 と金薄膜の間にチタン薄膜を挿入したのは金 薄膜の剥離強度を高めるためであり 、 チタンの代わり にク ロム （Cr) 等 金薄膜の剥離強度を高める薄膜を挿入してもよい。  First, the defect removing step will be described. The macro 122 having this defect is removed by etching to form a junction groove 13 as shown in FIG. 1 (b). Next, as shown in FIG. 1 (c), a titanium (Ti) thin film having a thickness of 0.5 to 1000 nm is formed in the joining groove 13 as a metal thin film 141 by vacuum evaporation, and then a gold thin film is formed. (Au) A thin film is formed with a thickness of 2 to 1000 ηπι, and the gold surface is used as a bonding surface. Here, the reason why the titanium thin film is inserted between the bonding groove 13 and the gold thin film is to increase the peel strength of the gold thin film. Instead of titanium, a thin film such as chromium (Cr) that increases the peel strength of the gold thin film is used. May be inserted.
次に救済マク ロ作成工程について説明する。 第 1 図（ の薄膜大規模 半導体素子 1 5は大規模半導体素子 1 1 と同様な回路構成をしている大 規模半導体素子を薄膜化したものであり 、 かつ、 マク ロ 1 2 2 と同一機 能の欠陥救済マク ロ 1 2 3 には欠陥が生じていない。 次に、 第 1 図（e) に示すよ う に、 薄膜大規模半導体素子 1 5 をマク ロ単位に分割し、 欠陥 救済マク ロ 1 2 3 を取り 出す。 そして第 1 図（f)に示すよ う に、 接合溝 1 3 と同様に金属薄膜 1 4 2を形成し、 金 （Au) 面を接合面とする。 接合工程について第 1 図（g)を用いて説明する。 大規模半導体素子 1 1 および救済マク ロ 1 2 3 をアルゴン （Ar) 原子ビーム 1 6が照射でき る圧力下 （例えば 1 x 1 0— 4〜： 1 x 1 0一3 Torrの真空） に設置し、 接 合面にアルゴン （Ar) 原子ビーム 1 6を照射する。 これによ り接合面に 付着している酸化膜、 水分、 油脂分等の汚染物を除去し、 接合面を活性 化する。 こ の時、 アルゴン （Ar) 原子ビーム 1 6 を照射する面が金属面 であるため照射面がチャージアップせず、 半導体デバイスに電気的なダ メ 一 ジを与え る こ と はない。 その後、 第 1 図 （h) に示すよ う に、 5 X 1 0— 6 To rr以下の真空中で接合面同志を対向させた後密着させて 固相の状態で接合する。 なお、 接合時圧力は 5 x 1 0— 6 Torr以下の真 空でなく ても、 アルゴン （Ar) 原子ビーム 1 6 を照射した接合面が再汚 染しない雰囲気であれば良い。 また、 この とき、 接合面の温度、 すなわ ち接合温度は 1 0 0〜 4 0 0で、 接合圧力は 5〜 5 0 M P a である。 このよ う に、 低温度、 低圧力で接合できるため、 集積回路の信頼性を 確保して接合するこ とができる。 また、 固相の状態で接合されているた め、 寸法精度も高く 、 救済マク ロ 1 2 3 と欠陥のないマク ロ 1 2 1 の高 さを同じにするこ とができる。 Next, the relief macro creation process will be described. The thin-film large-scale semiconductor element 15 shown in Fig. 1 is a thin-film version of a large-scale semiconductor element having a circuit configuration similar to that of the large-scale semiconductor element 11, and is the same as the macro-122. No defect has occurred in the defect repair macro 123. Next, Fig. 1 ( e ) As shown in (5), the thin-film large-scale semiconductor device 15 is divided into macro units, and the defect relief macros 123 are extracted. Then, as shown in FIG. 1 (f), a metal thin film 142 is formed in the same manner as the bonding groove 13 and the gold (Au) surface is used as the bonding surface. The joining step will be described with reference to FIG. Installed in: a large semiconductor element 1 1 and remedies macros 1 2 3 argon (Ar) atoms beam 1 6 under pressure that can be irradiated (1 x 1 0 one 3 Torr of vacuum example 1 x 1 0- 4 ~) Then, the joint surface is irradiated with an argon (Ar) atomic beam 16. As a result, contaminants such as an oxide film, moisture, oils and fats adhering to the joint surface are removed, and the joint surface is activated. At this time, since the surface irradiated with the argon (Ar) atomic beam 16 is a metal surface, the irradiated surface does not charge up and does not damage the semiconductor device electrically. Thereafter, Remind as in FIG. 1 (h), the adhesion is allowed after being opposed joint surfaces each other at 5 X 1 0- 6 To rr in the following vacuum bonding state of the solid phase. The bonding time of the pressure not be a vacuum below 5 x 1 0- 6 Torr, the bonding surface was irradiated with argon (Ar) atoms beam 1 6 may be any atmosphere that does not re-contamination. At this time, the temperature of the bonding surface, that is, the bonding temperature is 100 to 400, and the bonding pressure is 5 to 50 MPa. Since bonding can be performed at a low temperature and a low pressure in this manner, bonding can be performed while ensuring the reliability of the integrated circuit. In addition, since they are joined in a solid phase, the dimensional accuracy is high, and the height of the relief macro 123 and the height of the defect-free macro 122 can be the same.
救済マク ロ 1 2 3 と欠陥のないマク ロ 1 2 1 の高さを同じするこ とが できるため、 マク ロ間の配線は、 欠陥救済をしない良品の大規模半導体 素子と同様、 薄膜状の金属配線で行う ことができるため、 配線密度が高 ま り、 半導体デバイ スの高集積化を図るこ とができる。 また、 接合部は、 金属接合であるので、 救済マクロ 1 2 3の放熱は十分行われる。  Since the height of the relief macro 123 and the defect-free macro 122 can be the same, the wiring between the macros is thin-film like the non-defective large-scale semiconductor device. Since the wiring can be formed using metal wiring, the wiring density can be increased, and high integration of semiconductor devices can be achieved. Also, since the joint is a metal joint, the relief macros 123 can sufficiently dissipate heat.
また、 接合溝 1 3および救済マク ロ 1 2 3 における酸化膜 （Si02 ) を大規模半導体素子 1 1 および欠陥救済マク ロ 1 2 3 の母材であるシ リ コン （Si) と金属薄膜の金 （Au) との共晶防止膜と して利用する こ と によ り 、 接合部の溶融温度を 6 0 0 ¾以上にするこ とができる。 この温 度は、 接合温度 1 0 0〜 4 0 0 ¾に比べ、 十分高い温度となっているた め、 この接合を何度おこなっても接合部が溶融するこ とはない。 なお、 共晶防止膜と して本実施例では S O I ウェハ自体の酸化膜を利用してい るが、 熱酸化膜または C V Dによる酸化膜であってもその効果は同じで ある。 Also, the oxide film (Si02) in the joint groove 13 and the relief macro 123 Is used as an anti-eutectic film between silicon (Si), which is the base material of the large-scale semiconductor element 11 and the defect relief macro 123, and gold (Au) as a metal thin film. However, the melting temperature of the joint can be raised to 600 ° C. or higher. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if this joining is performed several times. In this embodiment, the oxide film of the SOI wafer itself is used as the eutectic prevention film. However, the same effect is obtained with a thermal oxide film or an oxide film formed by CVD.

Claims

1 . 少なく と も 2個以上の半導体素子を接合して成る半導体デバイスに おいて、 前記半導体素子間の接合部に金属薄膜を介して固相接合したこ とを特徴とする半導体デバイス。 1. A semiconductor device in which at least two or more semiconductor elements are joined, wherein solid-state joining is performed at a junction between the semiconductor elements via a metal thin film.
2. 請求項 1 において、 前記半導体素子を前記半導体デバイ スの厚さ方 向に固相接合したこ とを特徴とする半導体デバイ ス。 2. The semiconductor device according to claim 1, wherein the semiconductor element is solid-phase bonded in a thickness direction of the semiconductor device.
3. 請求項 1 において、 前記半導体素子を前記半導体デバイ スの長さ方 向または幅方向に固相接合したことを特徴とする半導体デバイス。  3. The semiconductor device according to claim 1, wherein the semiconductor element is solid-phase bonded in a length direction or a width direction of the semiconductor device.
4 . 基板上に光素子および光導波路を金属薄膜を介して固相接合したこ とを特徴とする半導体デバイ ス。  4. A semiconductor device in which an optical element and an optical waveguide are solid-phase bonded on a substrate via a metal thin film.
5. シリ コン半導体素子とガリ ウム砒素半導体素子を金属薄膜を介して 固相接合したこ とを特徴とする半導体デバイス。  5. A semiconductor device characterized by solid-state bonding of a silicon semiconductor element and a gallium arsenide semiconductor element via a metal thin film.
6. 請求項 1 、 4、 5のいずれかにおいて、 前記金属薄膜は、 材質の異 なる 2つ以上の薄膜層から構成されているこ とを特徴とする半導体デバ イス。  6. The semiconductor device according to claim 1, wherein the metal thin film is composed of two or more thin film layers made of different materials.
7. 請求項 1 、 4 、 5のいずれかにおいて、 半導体素子と前記金属薄膜 の間に、 前記半導体素子および前記金属薄膜と共晶反応しない材料を挿 入するこ とを特徴とする半導体デバイス。  7. The semiconductor device according to claim 1, wherein a material that does not undergo eutectic reaction with the semiconductor element and the metal thin film is inserted between the semiconductor element and the metal thin film.
8 . 請求項 1 、 4 、 5のいずれかにおいて、 前記金属薄膜は、 チタ ン (Ti)薄膜と金（An)薄膜によ り構成されているこ とを特徴とする半導体 デバイス。  8. The semiconductor device according to any one of claims 1, 4, and 5, wherein the metal thin film is composed of a titanium (Ti) thin film and a gold (An) thin film.
9. 請求項 1 、 4、 5のいずれかにおいて、 前記金属薄膜は、 厚さ 0. 5 〜 1 0 0 O n mのチタ ン（Ti)薄膜と厚さ 2〜 1 0 0 0 O n mの金 (Au)薄膜によ り構成されていることを特徴とする半導体デバイス。  9. The metal thin film according to any one of claims 1, 4, and 5, wherein the metal thin film is a titanium (Ti) thin film having a thickness of 0.5 to 100 nm and a gold thin film having a thickness of 2 to 100 nm. (Au) A semiconductor device comprising a thin film.
1 0. 請求項 1 、 4、 5のいずれかにおいて、 前記金属薄膜は、 半導体 素子の接合面に電気的に独立して複数形成されており 、 こ の複数形成さ れた金属薄膜の一部または全部が電極であるこ と を特徴とする半導体デ バイス。 10. The method according to any one of claims 1, 4, and 5, wherein a plurality of the metal thin films are formed electrically independently on a bonding surface of the semiconductor element. A semiconductor device characterized in that part or all of the thin metal film is an electrode.
1 1 . 少なく とも 2個以上の半導体素子を接合して成る半導体デバイス の製造方法において、 前記半導体素子間の接合部に金属薄膜を介して固 相接合したこ とを特徴とする半導体デバイスの製造方法。  11. A method for manufacturing a semiconductor device, comprising joining at least two or more semiconductor elements, the method comprising: manufacturing a semiconductor device, wherein a solid-phase joining is performed at a junction between the semiconductor elements via a metal thin film. Method.
1 2. 請求項 1 1 において、 前記固相接合は、 互いに接合すべき前記半 導体素子の接合面のうち少なく と も一方は予め金属薄膜を形成した接合 面と し、 真空中にて前記接合面に原子またはイオンのエネルギービーム を照射して前記接合面の上の汚染物を除去して前記接合面を活性化した 後、 前記接合面が再汚染しない接合雰囲気中にて金属薄膜の固相線温度 以下の温度で接合面同志を密着させて加圧し、 固相の状態で接合するこ とを特徴とする半導体デバイ スの製造方法。  12. The solid-state bonding method according to claim 11, wherein at least one of bonding surfaces of the semiconductor elements to be bonded to each other is a bonding surface on which a metal thin film is formed in advance, and the bonding is performed in a vacuum. After irradiating the surface with an energy beam of atoms or ions to remove contaminants on the bonding surface and activate the bonding surface, the solid phase of the metal thin film is placed in a bonding atmosphere in which the bonding surface is not recontaminated. A method for manufacturing a semiconductor device, comprising: bonding surfaces in contact with each other at a temperature equal to or lower than a linear temperature;
1 3 . 請求項 1 1 において、 前記金属薄膜は材質の異なる 2つ以上の薄 膜層から構成されているこ とを特徴とする半導体デバイスの製造方法。  13. The method for manufacturing a semiconductor device according to claim 11, wherein the metal thin film includes two or more thin film layers made of different materials.
1 . 請求項 1 1 において、 前記半導体素子と前記金属薄膜の間に前記 半導体素子および前記金属薄膜と共晶反応しない材料を挿入するこ と を 特徴とする半導体デバイスの製造方法。  11. The method of manufacturing a semiconductor device according to claim 11, wherein a material that does not undergo eutectic reaction with the semiconductor element and the metal thin film is inserted between the semiconductor element and the metal thin film.
1 5. 請求項 1 1 において、 前記金属薄膜はチタン（Ti)薄膜と金（Au) 薄膜から構成されているこ とを特徴とする半導体デバイスの製造方法。  15. The method according to claim 11, wherein the metal thin film includes a titanium (Ti) thin film and a gold (Au) thin film.
1 6. 請求項 1 1 において、 前記金属薄膜は厚さ 0. 5〜 1 O O O n m のチタン （Ti)薄膜と厚さ 2〜 1 0 0 0 0 n mの金（Au)薄膜から構成さ れているこ とを特徴とする半導体デバイスの製造方法。  1 6. The method according to claim 11, wherein the metal thin film is composed of a titanium (Ti) thin film having a thickness of 0.5 to 1 OOO nm and a gold (Au) thin film having a thickness of 2 to 1000 nm. A method for manufacturing a semiconductor device.
1 7. 請求項 1 ュ において、 前記固相接合は前記金属薄膜中に双晶変形 が生じる温度および圧力にて接合するこ とを特徴とする半導体デバイス の製造方法。  17. The method for manufacturing a semiconductor device according to claim 1, wherein the solid-phase bonding is performed at a temperature and a pressure at which twin deformation occurs in the metal thin film.
1 8. 請求項 1 7 において、 前記温度が 1 0 0〜 4 0 0 であり、 前記 圧力が 5〜 5 O M P Aであるこ とを特徴とする半導体デバイスの製造方 法。 1 8. The method according to claim 17, wherein the temperature is 100 to 400, A method for manufacturing a semiconductor device, wherein the pressure is 5 to 5 OMPA.
PCT/JP1995/001875 1995-09-20 1995-09-20 Semiconductor device and its manufacture WO1997011492A1 (en)

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