WO1997003460A1

WO1997003460A1 - Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip

Info

Publication number: WO1997003460A1
Application number: PCT/JP1996/001905
Authority: WO
Inventors: Takeshi Kagatsume
Original assignee: Hoya Corporation
Priority date: 1995-07-12
Filing date: 1996-07-09
Publication date: 1997-01-30

Abstract

A bare chip mounted board on which electronic parts can be mounted at a high density. A bare chip (2) is mounted on a glass substrate (1) and various kinds of thin film electronic elements are formed on the substrate (1). The thin film electronic elements shown in the figure are TFT (3), a diode (4), a capacitor (5), and a resistor (6), all being covered with a protective film (7). The electronic elements are formed by lithography. A wiring layer is also formed by lithography. The bare chip (2) does not have any pad for electrode and electrode terminals are led out from the wiring layer on the lower surface of the chip (2) and directly connected to the connecting terminals of the substrate (1) through A1 wiring (8). When the glass substrate (1) is used as a printed wiring board in such a way, thin film electronic elements can be formed at a high density by lithography.

Description

Description Bare chip mounting board, method for manufacturing bare chip mounting board, and method for forming bare chip electrode

The present invention relates to a bare chip mounting board in which various semiconductor components are provided on a substrate, a method of manufacturing the bare chip mounting board, and a method of forming electrodes of a bare chip directly mounted on a printed wiring board. Miniaturized bare chip mounting board, method of manufacturing bare chip mounting board that enables miniaturization, and method of forming bare chip electrode for mounting miniaturized chip on printed wiring board . Background technology

With the miniaturization and high performance of devices such as computers, miniaturization of various boards equipped with semiconductor chips is desired. To reduce the size of the board, it is effective to reduce the size of various semiconductor chips. Generally, a semiconductor chip such as a CPU chip is incorporated in a package, and this package is mounted on a printed circuit board. The semiconductor chip itself is very small compared to the package size. Therefore, if the semiconductor chip is directly mounted on the board, the board can be reduced by the amount of the package omitted. Note that a semiconductor chip not incorporated in such a package is called a bare chip.

Recently, a bare chip (KGD: Known Good) with a guaranteed quality Die) has been shipped from semiconductor manufacturers, and it is becoming possible to obtain bare chips from various board manufacturers. Therefore, the technology for mounting the bare chip directly on the printed circuit board is important.

Technologies for mounting a bare chip on a printed circuit board include a wire bonding method and a flip chip method. The wire bonding method is a method in which an electrode pad is arranged around a chip and a thin metal wire is connected from the electrode pad to a wiring pattern. On the other hand, in the flip chip method, solder balls called bumps are provided on the electrodes of the chip, and the bumps are directed downward to contact the wiring pattern. Then, electrical connection is made by melting the bumps.

MCMs (multi 'chip' modules) and the like have been commercialized using such technologies.

However, in order to perform wire bonding or provide a pump, an electrode pad that is much larger than the internal wiring must be provided. In other words, in the wire bonding method, since the wire is hit mechanically, the allowable range of the position error at that time must be large, and the head cannot be reduced. On the other hand, with the flip-chip method, the risk of short-circuiting between solders increases when the spacing between the pads is reduced. As described above, it is difficult to reduce the size of the pad in the conventional method, and there is a limit to downsizing the tape. For this reason, there was a limit to the miniaturization of boards equipped with bare chips.

There is lithography as a technology for forming electronic components on a module substrate. It is also possible to increase the density of line patterns. If the wiring pattern can be made denser, the board can be made smaller. However, conventional printed substrates made of glass epoxy, ceramics, or the like do not have sufficient surface smoothness, and the density of electronic components cannot be increased by using lithography.

In addition, if the bare chip is directly mounted on the printed circuit board, the following problems occur with respect to the reliability of the manufactured board.

The first reliability issue is that when glass epoxy is used for the board, the alkali ions on the board migrate to the bare chip mounted. Such transfer of the ion force causes malfunction and lowers the reliability.

The second issue related to reliability is that the thermal expansion coefficient of the substrate using ceramics or glass epoxy differs greatly from the thermal expansion coefficient of various mounted semiconductor components (for example, silicon). The change is likely to cause poor contact between the substrate and the semiconductor component. Disclosure of the invention

The present invention has been made in view of such a point, and an object of the present invention is to provide a bare chip mounting board on which electronic components can be formed with high density and high reliability.

Another object of the present invention is to provide a method of manufacturing a bare chip mounting board that can connect a bare chip and a printed wiring board with extremely small electrodes.

Still another object of the present invention is to provide a bare chip electrode forming method capable of forming an extremely small electrode on a bare chip. It is to be.

In the present invention, in order to solve the above-mentioned problems, in a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on a glass substrate; And a bare chip mounted on a printed wiring board and having electrodes directly connected to the wiring layer.

Further, in a bare chip mounting board in which various semiconductor components are provided on a substrate, a printed wiring board in which a thin film electronic element and a wiring layer are formed on an alkali-free glass substrate; A bare chip mounted board characterized by having a bare chip mounted on a board and a board is provided.

In addition, in a bare chip mounting board on which various semiconductor components are provided on a substrate, printed wiring in which a thin-film electronic element and a wiring layer are formed on a glass substrate having a thermal expansion coefficient similar to that of silicon A bare chip mounting board comprising: a substrate; and a tape mounted on the printed wiring board.

In addition, in the method of manufacturing a base mounting board on which various semiconductor components are mounted, an appropriate portion of the wiring layer connected to the internal semiconductor element is exposed using lithography. An electrode is formed on the surface of the bare chip by lithography, and a wiring layer for connecting to the electrode is formed on the surface of the printed wiring board using a glass substrate by lithography. The bare chip is mounted on the printed wiring board by connecting the electrodes to the wiring layer, and a method for manufacturing a bare chip mounting board is provided. Furthermore, in the method for forming bare chip electrodes directly mounted on a printed wiring board, the surface of the bare chip in which the wiring layer of the internal circuit is formed is covered with a protective film, and the position before the electrode is to be taken out A method for forming an electrode for a bare chip, comprising: removing a protective film by lithography 1; and forming a metal for an electrode by lithography 1 at a position where the protective film is removed. You.

According to the above-described bare chip mounting board, thin-film electronic elements are formed at high density on the surface of the glass substrate having high smoothness. Then, by directly connecting and mounting the semiconductor elements in a bare chip state, the entire circuit of the printed wiring board has a high density, and various electronic circuits are formed in a very narrow area.

In addition, by using a printed wiring board in which a thin film electronic element and a wiring layer are formed on a non-alkali glass substrate, a mounted base chip, TFT (Thin Film Transistor), diode, resistor, capacitor, etc. Alkali ions do not migrate between the thin-film electronic element and the substrate, and a highly reliable bare chip mounting board can be obtained.

Also, since the printed wiring board has a thin-film electronic element and a wiring layer formed on a glass substrate having a thermal expansion coefficient similar to that of silicon, a bare chip and a board can be mounted. As a result, it is possible to prevent the occurrence of contact failure due to aging, and to obtain a highly reliable bay chip mounting board.

Further, according to the method of manufacturing a bare chip mounting board described above, a suitable portion of the wiring layer connected to the internal semiconductor element is exposed to the surface of the bare chip by using a lithography method. The electrodes are formed by lithography and connected to the electrodes. The wiring layer is formed by lithography on the surface of a printed wiring board using a glass substrate, and an electrode about the same as the width of the internal wiring of the bare chip is connected to that electrode. Wiring layer is provided. Since the bare chip is mounted on the printed wiring board by connecting the electrodes of the bare chip to the wiring layer of the printed wiring board, the bare chip can be mounted in a very narrow area.

Further, according to the bare chip electrode forming method described above, the surface of the bare chip in which the wiring layer of the internal circuit is formed is covered with the protective film, and the protective film at the position where the electrode is to be taken out is lithographically integrated. By removing the protective film and forming the electrode metal by lithography at the position where the protective film has been removed, even if the bare chip does not have an electrode pad, the electrode terminal directly connected to the internal wiring layer is provided. . FIG. 1 is a cross-sectional view of a bare chip mounting board of the present invention.

Figure 2 is a table showing the composition of Al-free glass that satisfies the coefficient of thermal expansion.

FIG. 3 is a diagram showing a process of providing electrode terminals on a bare chip, FIG. 4 is a diagram showing a process of wiring electrodes on a printed wiring board (PCB),

Figure 5 is a diagram showing the process of mounting a bare chip on a printed wiring board.

FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a bare chip mounting board of the present invention. On the glass substrate 1, various thin-film electronic elements are formed, and a bare chip 2 is mounted.

The thin film electronic devices shown are TFT 3, diode 4, capacitor 5, and resistor 6. The thin-film electronic element is covered with a protective film 7. These are formed by lithography used in the manufacture of LCD (Liquid Crystal Display) substrates.

The bare chip 2 is not provided with an electrode pad, and the electrode terminals are provided directly on the wiring inside the chip. This electrode terminal is A1 wiring provided by lithography on the internal wiring of the chip.

The wiring layer provided on the glass substrate 1 by lithography and the A 1 wiring for the electrode of the bare chip 2 are directly connected by the aluminum (A) wiring 8.

As described above, by using the glass substrate 1 as a print wiring substrate, it is possible to form a high-density thin-film electronic element by lithography. Moreover, since the bare chip 2 has no pad, it is small in size.

In particular, when non-alkali glass is used for the glass substrate 1, alkali ions do not transfer from the substrate to the thin-film electronic elements or semiconductor components. Therefore, malfunction does not occur due to the influence of alkali ions, and the reliability of the operation of the board mounted with bare chips is maintained. Here, alkali-free glass refers to alkali metal contained in glass components. It is a generic term for glass not included.

Further, if the coefficient of thermal expansion of the glass substrate 1 is close to that of the semiconductor component, a contact failure between the substrate and the semiconductor component does not occur due to aging. Therefore, if glass having a coefficient of thermal expansion similar to that of a semiconductor component is used as the material of the glass substrate, the reliability of the operation of the bare chip mounting board can be improved. The average linear thermal expansion coefficient of the sheet re con which is used as a material of the semiconductor component 3 4 x 1 0 -. And a this is a ⁷ Z ° about C, and because not to cause contact failure due to aging change, the substrate The average coefficient of linear thermal expansion must be within the range of 30 to 48 x 10-7 ° C (when measured in the temperature range of 100 to 300 ° C).

Figure 2 shows the composition of an alkali-free glass that satisfies the requirements for the coefficient of thermal expansion.

Figure 2 shows three types of glass. The average linear thermal expansion coefficient of the first example is 37 x 10 -7 / ° C, and the average linear thermal expansion coefficient of the second example is 43 x 10 -7 / ° C. The average linear thermal expansion coefficient of the example is 46 x 10 -7 / ° C. Therefore, all three sufficiently satisfy the above conditions. That is, the coefficient of thermal expansion is similar to the coefficient of thermal expansion of silicon.

By the way, the glass shown in FIG. 2 has an average coefficient of linear thermal expansion of 30-48 X10-fuda even if each composition is slightly changed. Can be kept within the range of C.

When the composition of the glass shown in the first example is changed, “S i 0 2, B

A total of 95 mol% or more of 203, A12〇3, MgO, CaO, SrO, and BaO is contained, and the content of each component by mol%, S i 0 2 is 62% or more and 68% or less, B203 is 8% or less Less than 12%, A1203 is 9% or more and 13% or less, MgO is 1% or more and 5% or less, Ca0 is 3% or more and 7% or less, SrO is If the glass is 1% or more and less than 3% and B a0 is 1% or more and less than 3%, the average linear thermal expansion coefficient falls within the range of 30 to 48 X 10 -7Z ° C. .

In addition, when the composition of the glass shown in the second example is changed, the content of each component by mol% is 55 to 65% for S i 〇2, and 7 to 11% for A1203. , Pb0 is 1 to 11%, Mg0 is 3 to 13%, Ca0 is 7 to 20%, Zn0 is 3 to 13%, Zr〇2 force is 0 to 3% , F2 force is 0-3%, As203 force is 0-5%, Sb203 force is '0-5% glass', the average linear thermal expansion coefficient is 30- 4 8 X 1 0 - ⁷ fall within the scope of Bruno ° C.

Next, a method of manufacturing the bare chip mounting board shown in FIG. 1 will be described. The manufacturing process is roughly divided into the steps of providing electrode terminals on bare chips without pads (padless bare chips), wiring the electrodes on the printed wiring board, and placing the padless bare chips on the printed wiring board. It can be divided into mounting processes.

FIG. 3 is a diagram illustrating a process of providing an electrode terminal on a bare chip. The figure shows a cross-sectional view of a bare chip for each step.

In step 1 (S1), a bare chip 10 without a pad is prepared. In the bare chip 10, a thin-film electronic element is formed between protective films 12 formed on a silicon (Si) substrate 11. This thin-film electronic device is composed of internal circuit wirings 14a to 14c and A1 wirings 13a to 13c.

A] No special measures are required for connecting the wiring 13a to 13c to the outside. In other words, provided on a conventional bare chip The junction may be very small compared to the electrode pad that has been used. Normally, the electrode pad is about 100 ^ m, but the size of the A1 wirings 13a to 13c can be reduced to 2m or less. In step 2 (S 2), a protective layer 15 of a protective film is formed on the surface of the bare chip 10. The combined thickness of the protective film 12 and the protective layer 15 has an opening of about 5 zm to about 10 m in consideration of the unevenness of the electrode junction on the printed wiring board side.

In step 3 (S 3), lithography is performed using a contact mask for wiring layer extraction with a hole at the position where the electrode is to be extracted, and the protective layer 1 on the A 1 wiring 13 a to l 3 c 5 is provided with holes 16a to 16c. The position from which the electrode is to be taken out is arbitrary, and there is no special restriction such as that it must be around the chip.

In step 4 (S4), a metal such as aluminum or copper is vapor-deposited, sputtered, or plated on the surface, and the lithography is performed using a wiring layer forming mask having a hole at a position where the electrode is to be taken out. Then, A 1 wiring 1 Ί a to l 7 c for connection is formed. Then, the protective layer 15 provided in Step 2 is removed. The remaining A1 wiring 17a to 17c is used as an electrode to connect to the printed wiring board.

FIG. 4 is a view showing a process of wiring electrodes on a printed wiring board (PCB). This step is performed in parallel with the step of providing electrode terminals on the bare chip. The figure shows a cross-sectional view of the printed wiring board 20 in each step.

In step 5 (S5), the printed wiring board 20 is formed by attaching the thin film electronic element and the A] wirings 27a to 27f to the glass substrate 21. It is formed by lithography. Lithography has been used in the manufacture of LCD substrates. Thus, a TFT 23, a diode 24, a capacitor 25, and a resistor 26 are formed on the glass substrate 21. These thin-film electronic elements and A〗 wirings 27 a to 27 f are covered with a protective film 22.

In step 6 (S6), the protective film 22 covering the wirings 27 to 27 is connected to the holes 28a to 2 for connection with the bare chip 10 (shown in FIG. 3). 8 Open c. The positions of the holes 28a to 28c are positions that match the positions of the A1 wiring 17a to I7c of the bare chip 10.

In step 7 (S7), A1 wires 29a to 29c for connection are provided on the A1 wires 27c to 27e exposed from the holes. The A1 wirings 29a to 29c are terminals for connecting the bare chip 10 (shown in Fig. 3).

FIG. 5 is a diagram showing a process of mounting a bare chip on a printed wiring board.

In step 8 (S8), the bare chip 10 created in step 4 (shown in FIG. 3) is overlaid on the printed wiring board 20 created in step 7 (shown in FIG. 4). At this time, the surfaces of the A1 wirings 29a to 29c of the printed wiring board 20 and the A1 wirings 17a to 17c of the bare chip 10 are activated. Then, positioning is performed so that the positions of the A1 wirings 29 a to 29 c of the printed wiring board 20 and the A1 wirings 17 a to l 7 c of the bare chip 10 coincide with each other, and the electric power is supplied. Contact. As a result, the AI wiring 29 a to 29 c of the printed wiring board 20 and the A 1 Wires 17a to 17c are bonded by surface activated cold bonding o

Surface-activated cold bonding is a direct bonding at the atomic level without a reaction layer at the bonding interface, and can be separated reversibly. Such a connection is called a reversible interconnection.

In step 9 (S 9), the periphery of the fused A 1 wirings 31 to 33 is hardened with insulating resin 34.

FIG. 6 is an enlarged view of the joint between the printed wiring board and the bare chip. The cross section near the electrode of the bare chip 10 is composed of a plurality of layers. The layers shown are the wiring 14 of the chip internal circuit and the protective film 12 from above. An A1 wiring 13 is connected to the wiring 14, and an A1 wiring 17 whose surface is activated is connected to the AI wiring 13. The thickness of wiring 14 inside the chip is 0.8 / m, and the thickness of A] wiring 17 is 5 rr! ~ 1 O ^ m. The printed wiring board 20 has an A1 wiring with a width of 1.0 to 1.2 m.

27 are provided. A portion of the A 1 wiring 27 to be connected to the bare chip is provided with a hole in the protective layer, and an A 1 wiring 29 whose surface is activated is provided. By bringing the A1 wiring 17 of the bay chip 10 into close contact with the position of the A1 wiring 29, reversible connection is performed. In addition, if metal bumps such as gold are previously formed on the A 1 wiring 29 for bare chip bonding, the bonding reliability is further improved.

The printed wiring board 20 is provided with an interface 20a, and can be connected to a computer bus via the interface 20a.

In the above example, the case where aluminum was used for the wiring metal was used. As the wiring metal, copper or other various alloys may be used in addition to aluminum.

As described above, a printed wiring board using a glass substrate was not used. A dressless chip can be mounted. Here, since the glass substrate has a very high surface smoothness, high-density wiring can be performed using a technique of lithography. Therefore, about 7 or 8 layers of wiring on a glass epoxy substrate can be covered by about 2 layers. Moreover, by using this lithography, a highly integrated thin-film electronic device can be formed on a glass substrate.

Further, since no pad is required for the bare chip, the size of the bare chip can be reduced. For example, the space for a pad of a general bare chip with a pad around it is 100 to 150 m on one side of a square pad, and the space around the pad is 40 m. Here, assuming that the width of the pad space is 200 im, the ratio of the space for the nod to the size of the bare chip is as follows.

22% if the chip size is 3.5 mm2.

If the chip size is 4.0 mm, 19%.

17% for chip sizes of 4.5 mm.

15% if the chip size is 5.0 mm2.

Thus, the smaller the chip size, the greater the effect of the pad. The small chip size means that the bare chip mounting board can be made smaller, and at the same time, more chips can be cut out from a single substrate in the bare chip manufacturing process. As described above, in the present invention, various thin film electrodes are formed on a glass substrate. Since the bare chip is directly mounted on the printed wiring board on which the child elements are formed, the size of the bare chip mounting board can be reduced.

In addition, high reliability of bare chip mounting boards can be obtained by using non-alkali glass or a printed wiring board using a glass substrate whose coefficient of thermal expansion is similar to that of silicon. Can be done. In addition to those described in the above description, such print wirings include 56 to 64% by weight of SiO 2, 18 to 24% by A1203, and N by weight%. It has a composition of a 20 force 2-3%, Mg O force 2-6%, Zn force 2-11%, and a thermal expansion coefficient of 3 in the same temperature range of 100-300 °. Glass having a temperature of 1 to 36 X 10 -7 ° C can also be used.

In addition, since the electrodes are directly extracted from the internal wiring of the bare chip by lithography, a pad for the electrode is not required, and the bare chip can be further reduced in size.

Claims

Scope of request 1. On a bare chip mounting board on which various semiconductor components are provided on a substrate,

A printed wiring board in which a thin film electronic element and a wiring layer are formed on a glass substrate,

A bare chip mounted on the printed wiring board and having electrodes directly connected to the wiring layer;

A board equipped with bare chips, characterized by having:

2. The bare chip mounting board according to claim 1, wherein the bare chip has an electrode of substantially the same size as the internal wiring taken out at an arbitrary position of the internal wiring. .

3. The bare chip mounting board according to claim 1, wherein the printed wiring board uses non-alkali glass as the glass substrate.

4. The bare chip mounting board according to claim 1, wherein the printed wiring board is made of glass having a thermal expansion coefficient similar to that of silicon as the glass substrate.

δ. The printed circuit board has an average linear thermal expansion coefficient in a temperature range of 100 to 300 ° C. of 30 to 48 × 10−7 / ° C. as the glass substrate. 5. The bare chip mounting board according to claim 4, wherein said glass is used.

6. On a bare chip mounting board on which various semiconductor components are provided on a substrate,

A printed wiring board in which a thin-film electronic element and a wiring layer are formed on a glass substrate; A bare chip mounting board comprising: a bare chip mounted on the printed wiring board.

7. The bare chip mounting board according to claim 6, wherein the printed wiring board is made of glass having a thermal expansion coefficient similar to that of silicon as the glass substrate.

8. The purine DOO wiring board, and with the glass substrate, 1 0 0~ 3 0 0 ° C average linear thermal expansion coefficient of 3 0 ~ 4 8 X 1 0 in the temperature range of - ⁷ of Z ° C 8. The bare chip mounting board according to claim 7, wherein glass within the range is used.

9. On a bare chip mounting board with various semiconductor components provided on a board,

A printed wiring board in which a thin-film electronic element and a wiring layer are formed on a glass substrate having a thermal expansion coefficient similar to that of silicon;

A bare chip mounting board comprising: a base chip mounted on the printed wiring board.

1 0. The purine DOO wiring board, prior to, and the d glass substrate, 1 0 0-3 0 0 average linear thermal expansion coefficient in a temperature range of ° C is 3 0~ 4 8 X 1 0 - 7 / 10. The bare chip mounting board according to claim 9, wherein glass within a temperature range of ° C is used.

1 1. In the manufacturing method of the bare chip mounting board for mounting various semiconductor parts,

An electrode is formed by lithography or plating on the surface of the bare chip in which an appropriate portion of the wiring layer connected to the internal semiconductor element is exposed using lithography, and an electrode is formed on the bare chip. A wiring layer for connection is formed by lithography on the surface of a printed wiring board using a glass substrate. Mounting the bare chip on the printed wiring board by connecting the electrodes to the wiring layer;

A method for manufacturing a board mounted with bare chips, characterized by the above.

12. When mounting the bare chip on the printed wiring board, the electrodes of the bare chip are connected to the wiring layer of the printed wiring board by bonding the metals whose surfaces are activated. 12. The method for producing a bare chip mounting board according to claim 11, wherein the connection is performed.

1 3. In the method of forming bare chip electrodes directly mounted on the printed circuit board,

Cover the surface of the bare chip with the wiring layer of the internal circuit formed with a protective film,

The protective film at the position where the electrode is to be removed is removed by lithography,

Forming an electrode metal by lithography or plating at a position where the protective film has been removed;

A method for forming bare chip electrodes, comprising: