WO1997049131A1

WO1997049131A1 - Semiconductor device with buried conductive silicide layer

Info

Publication number: WO1997049131A1
Application number: PCT/GB1997/001669
Authority: WO
Inventors: Peter Ashburn
Original assignee: Btg International Limited
Priority date: 1996-06-20
Filing date: 1997-06-20
Publication date: 1997-12-24
Also published as: GB9612941D0

Abstract

In order to inhibit latch-up of parasitic bipolar transistors in a CMOS integrated circuit, a conductive silicide layer (10) is interposed between a handling wafer (20) and a component-bearing active wafer (30) which are bonded together.

Description

SEMICONDUCTOR DEVICE WITH BURIED CONDUCTIVE SILICIDE LAYER

This invention relates to semiconductor devices and methods of manufacturing thereof. It is particularly concerned with manufacturing techniques used in the fabrication of CMOS (Complementary Metal Oxide Semiconductor) devices and SOI (Silicon-on- Insulator) devices, although it may be of use for other semiconductor devices.

There are many types of semiconductor device. These are almost without exception fabricated in the form of multi-layered, planar, sandwich-like structures. These sandwich¬ like structures comprise layers of materials in which electronic components are formed, usually by doping different regions with either /?- or w-type impurities so as to form a component layer. One such component layer is isolated from another component layer by an insulating layer or a junction placed between the two component layers.

Having regard to the fact that these semiconductor devices can be extremely small

(often the dimensions of components may be less than 1 micron square 1 x 10"^{, 2}m²); and that during the manufacturing process of a multi-layered, semiconductor device, hostile chemical and temperature environments are encountered, manufacturing these devices can be very difficult.

An example of a semiconductor manufacturing technique, intended to improve yield and reliability, is described in European Patent Application EP-A1-191 981. Despite such techniques, yield of finished devices is sometimes low. If the yield is low, the cost of devices usually rises. Similarly, problems are encountered in the use and operation of multi-layered, semiconductor devices.

US Patent No. US 5,387,555 (Harris Corporation) describes a technique in which a buried suicide layer is interposed between an oxide (insulator) layer on a handle wafer and an oxide layer on a component bearing silicon layer. The purpose of this suicide layer is to provide resistor components within isolated 'islands'. It is well-known that resistors can occupy relatively large amount of area and Harris attempts to improve this situation by burying the resistors below the active components.

A paper entitled "Contacts to monocrystalline «-type andp-type silicon by wafer bonding using cobalt disilicide", by G. Thungstrom et al. published in Physica Scripta vol. 54, pp 77-80 (1994), describes how ohmic cobalt disilicide contacts can be made by wafer bonding.

Another paper entitled "Grounded body SOI n-MOSFET by wafer bonding", by W- G. Kang et al. published in IEEE Electron Device Letters, vol 16, pi (1995) uses a /?^' polysilicon to remove floating body effects. Polysilicon however has a high series resistance.

The present invention arose in an attempt to solve the aforementioned problems and provides an improved method of manufacturing a semiconductor device.

According to a first aspect of the invention there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a silicon component layer on a semiconductor wafer and forming a silicide layer which is in contact with at least a portion of said silicon component layer.

The silicide may be a silicide of any metal, including the refractory metal suicides and the near noble and noble metal suicides.

The silicide layer may be used in the manufacture of bulk CMOS devices or silicon on insulator CMOS devices preferably so as to provide low resistance body contacts to n- channel and p-channel field effect transistors (FET's).

According to another aspect of the present invention, there is provided a method of wafer bonding semiconductor wafers comprising the steps of : forming a first multi- layered structure comprising an insulator and a first semiconductor layer forming a second multi-layered structure comprising an active semiconductor layer and a silicide layer, forming an insulator on said silicide layer and bonding the two insulating layers such that the silicide layer is positioned between the first semiconductor layer and the active semiconductor layer.

The silicide layer is thus envisaged as providing a "buried" low resistance path "beneath" an active semiconductor layer. The term "beneath" is used without limitation as to exact orientation of the semiconductor wafers.

The invention will now be particularly described, by way of example only, and with reference to the accompanying drawings, in which:

Figure 1 is a diagrammatic cross-section showing some of parasitic bipolar transistors in a CMOS process;

Figure 2a and b are equivalent circuits for the device shown in Figure 1 which

-9. illustrates how "latch-up" can occur ; Figure 3 is a diagrammatic cross-section illustrating how "buried" p¹ and M⁴ layers may be used to reduce parasitic resistances; Figure 4 to 5d are cross-sections through a multi-layered, semiconductor device, in accordance with an embodiment of the invention; and

Figure 6a to 9c show diagrammatically the stages of fabrication of a multi-layered semiconductor device in accordance with a preferred embodiment of the present invention.

Referring now to the drawings, Figure 1 is a diagrammatic illustration showing two complementary transistors in a CMOS integrated circuit which exhibits the problem of latch-up. An ^-channel device has n⁺ source and drain electrodes 1, 3 formed in ap-type substrate well 5 having ap' body contact 7. A gate electrode 9 overlies a channel region

1 1 and is insulated therefrom by an oxide layer 13. Adjacent thereto is a complementary

/^-channel device with corresponding electrodes la, 3a, etc. Associated with this structure are parasitic bipolar transistors 15, 15a. Under certain circuit operating conditions, these parasitic bipolar transistors can turn on. This is shown diagrammatically in Figure 2. This so called "latch-up" can cause the shorting of V_DD and GND (or χ_s ) lines and usually results in chip self-destruction or at least system failure.

One way of controlling latch-up is to ensure that there are many connections to the bodies of n-channel and p-channel MOS transistors. The effect is that series resistances R„ and R^ are reduced. Better control of latch-up can be achieved if a buried «^h silicon layer

17 is included below the n-well, or a buried p^* layer 17a is included below the p-well or both are included, for example as shown in Figure 3. These buried layers reduce series resistances R_n and R_p and the gains of the parasitic bipolar transistors. Both these factors prevent the bipolar transistor from turning on and hence prevent latch-up. However, extra processing steps are needed to fabricate the buried layers. These steps include the fabrication of an «⁺ layer, a p layer and an epitaxial layer. The result is that there is a longer throughput during manufacturing, the expense is increased and the yield is poorer.

Silicon on Insulator (SOI) technology offers a solution to latch-up, since Metal- Oxide-Semiconductor (MOS) transistors are fabricated on an insulating substrate and hence the collector of the parasitic bipolar transistor is eliminated. Another advantage of SOI devices is that they are very fast and in general faster than bulk CMOS because the insulating substrate reduces the capacitance. However, SOI devices do suffer from so- called 'floating body' effects, and in particular analogue circuits in SOI devices can suffer from this problem. Floating body effects can be reduced by using a thin silicon layer, the thickness of which is less than the depletion width. However, even with this fully depleted body, associated parasitic bipolar transistor can still cause problems. Floating body effects can be completely eliminated if a body contact to the MOS transistors is provided.

Preferably when used in the manufacture of bulk CMOS devices, (in particular as described below with reference to Figure 4,) a silicide layer is placed between a substrate layer and a component-bearing active layer, the devices being located in the active layer. The substrate layer may be a semiconductor or an insulator or a combination of the two. The buried silicide has a lower sheet resistance than ri' and p buried layers, unlike the arrangement in Figure 3, and provides a better way of reducing the parasitic resistances R„ and R_/;. Ultimately latch-up is reduced. The low sheet resistance allows the use of a single body contact to serve many transistors (as is shown in Figure 4) and fewer body contacts are needed than in standard bulk CMOS. There is thus a general easier layout of components which enables cheaper and more reliable manufacture, therefore improving yield. The method of manufacture avoids the use of epitaxy which is in general an expensive step. It also avoids the use of separate «^* and p^* buried layers, thereby further simplifying and speeding up manufacture.

Referring to Figures 4 and 5a to 5d. when used in the manufacture of SOI devices a silicide layer 10 is placed between an insulator layer 20, for example silicon dioxide, and active layer 30, in which the devices are located. The buried silicide layer 10 (Figures 5a-d) provides body contacts to many n-channel transistors 50 and hence eliminates floating body effects. The same arrangement provides body contacts to a plurality of p-channel transistors and eliminates floating body effects. The silicide layer 10 also provides a thermal dissipating layer for heat removal from the device islands.

Figure 5a shows a scheme which uses a buried silicide layer 10 in conjunction with a thick active silicon film 70 and mesa etching to isolate transistors 72. Figure 5b shows a device which has a buried silicide layer in conjunction with a thick active silicon film and trench isolation to isolate the transistors 72 and give a planar surface. Figure 5c shows a scheme which uses a buried silicide layer 10 in conjunction with a thin active silicon film and mesa etching to isolate transistors 72. Figure 5d shows a scheme which uses a buried silicide in conjunction with a thin active silicon film and trench isolation 19 to isolate the transistors and give a planar surface. The buried silicide layer 10 used in the devices shown in Figures 4, 5a and 5b is produced using wafer bonding, as shown diagrammatically in Figure 6. Firstly separate active 100 and handling wafers 110 are produced. On a surface of the active wafer 100, a silicide layer 10 is formed using any conventional method known to a skilled person. By way of example, the silicide layer 10 may be produced by depositing a metal on to the silicon active layer 100, annealing the resultant wafer 100 to form a silicide layer 105 and then removing any unreacted metal to give the structure shown in Figure 6a. On the handling wafer 1 10, an insulating layer 106 is formed. This insulating layer 106 could be formed from any insulator, but silicon dioxide is preferred. Silicon dioxide insulating layer 106 is produced by oxidising the handling wafer 1 10, by chemical vapour deposition or by other methods, to give the structure shown in Figure 6b. The handling wafer 1 10 and the active wafer are then bonded together using a wafer bonding technique so as to provide the structure shown in Figure 6c. The thickness of active layer 100 is then reduced by chemical and/or mechanical polishing, by etching or by other method to give the required thickness of silicon for active devices (not shown). Reduction of the active layer 100 thus provides the device as shown in Figure 6d.

Referring to Figures 7a to d, additional processes can be used to produce a buried silicide layer 105. Starting with separate active 100 and handling wafers 1 10, a silicide layer 10 is formed on the active wafer 100 by any known method. An insulator layer 120 is then formed on the silicide layer 105. This could be any insulator, but silicon dioxide is used here by way of example. The silicon dioxide insulator layer 120 is produced on the silicide layer 105 by oxidation, chemical vapour deposition or by other methods to give the structure in Figure 7a. An insulator layer 125 is then formed on the handling layer 1 10. The insulator layer 125 is preferably silicon dioxide. The silicon dioxide insulating layer 125 is produced by oxidising the handling layer 1 10, by chemical vapour deposition or by other methods to give the structure shown in Figure 7b. The handling layer (Figure 7b) and the active wafer (Figure 7a) are then bonded together using any wafer bonding technique to give the structure in Figure 7c. The thickness of the active layer 100 is reduced by chemical and/or mechanical polishing, by etching or by other method to give the required thickness of silicon for the active devices, thus giving the structure in Figure 7d.

Alternative processes may be used to produce a buried silicide layer. For example, by starting with separate active and handling wafers, a silicide layer may be formed on the active wafer by any known method. An insulator layer is then formed on the silicide layer. Silicon dioxide is preferred. The silicon dioxide layer is produced on top of the silicide by oxidation, chemical vapour deposition or by other methods, thus yielding, for example, the structure in Figure 8a in which like substances have the same reference numerals as in Figures 7a to d.

A handling wafer, as shown in Figure 8b, has the active layer 100 bonded to it using any wafer bonding technique, so as to give the structure in Figure 8c. The thickness of the active layer 100 is then reduced by chemical and/or mechanical polishing, by etching or by other methods to give the required thickness of silicon for the active devices. This yields the device in Figure 8d.

The buried silicide layer 10, used in the devices shown in Figures 5c and 5d, is produced using wafer bonding, as shown for example in Figure 9. Starting with separate active 100 and handling wafers 110, the active wafer has a recessed silicon dioxide layer 130 formed in it using local oxidation, trench etching and etch back or any other technique. Using local oxidation, a stress relief oxide is formed on the silicon surface, followed by a silicon nitride layer. After patterning, oxidation is carried out to create the recessed silicon dioxide layer 130. The silicon nitride layer and the stress relief oxide are then removed to give the structure in Figure 9a. On the active wafer, an amorphous silicon (or polycrystalline silicon) layer is formed over the patterned, recessed silicon dioxide layer 130. The amorphous or polycrystalline silicon may be undoped, doped p-type or doped n-type. All of the amorphous or polycrystalline silicon is then converted to a silicide layer 135 by any method. By way of example this can be done by depositing a metal onto the amorphous or polycrystalline silicon, annealing the metal to produce a silicide layer and then removing the unreacted metal. On the active wafer 1 10, an insulator 140 is deposited. This may be any insulator, but is preferably silicon dioxide. The insulator is then thinned and planarised using chemical mechanical polishing or a similar technique to give the structure in Figure 9b. A handling wafer 1 10, either with an insulator on the surface as in Figure 7b or without an insulator as in Figure 8b, is then bonded to the active wafer 100 using any wafer bonding technique to yield the finished structure as shown in Figure 9c. The thickness of the active wafer is reduced by chemical and/or mechanical polishing, by etching or by other methods to give the required thickness of silicon for the active devices.

Claims

1. A semiconductor device comprising a substrate layer 20 and a component-bearing active layer 30 characterised in that a conductive silicide layer 10 interposed between said substrate layer 20 and said component-bearing active layer 30 is in electrical contact with said component-bearing active layer.

2. A semiconductor device comprising a substrate layer and a component-bearing active layer according to claim 1 characterised in that an insulating layer 21 is interposed between said substrate layer 20 and said conductive silicide layer 10.

3. A semiconductor device comprising a substrate layer and a component-bearing active layer according to claim 1 or 2 characterised in that said component bearing layer consists substantially of silicon.

4. A semiconductor device comprising a substrate layer and a component-bearing active layer according to claim 1 or 2 characterised in that said substrate layer consists substantially of silicon.

5. A method of making a semiconductor device comprising the steps of forming a conductive silicide layer on a surface of a wafer having a component-bearing active layer and bonding said surface to a substrate wafer.

6. A method of making a semiconductor device according to claim 5 comprising the further step of forming an insulating layer on said substrate wafer prior to bonding said surface to said surface to said substrate wafer.

7. A method of making a semiconductor device according to claim 6 characterised in that said insulating layer includes silicon dioxide.

8. A method of making a semiconductor device according to claim 6 or 7 characterised in that said insulating layer includes silicon nitride.

9. A method of making a semiconductor device according to any one of the preceding claims 5 to 8 characterised in that said silicide layer is formed by depositing a metal on to amorphous or polycrystalline silicon and heat treating it to produce a silicide of said metal.

10. A method of making a semiconductor device according to claim 9 characterised in that surplus metal is removed from a surface of said component-bearing active wafer after formation of said silicide layer.