WO1996041272A1

WO1996041272A1 - Computer system having an improved bus arbiter adapted for real time applications

Info

Publication number: WO1996041272A1
Application number: PCT/US1996/009757
Authority: WO
Inventors: Dale Gulick; Andy Lambrecht; Mike Webb; Larry Hewitt; Brian Barnes
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1995-06-07
Filing date: 1996-06-07
Publication date: 1996-12-19

Abstract

A computer system is provided which includes a bus bridge coupled between a CPU local bus and a PCI bus. The bridge further includes a memory controller for controlling data transfers between a main memory and masters residing on either the CPU local bus or the PCI bus. A variety of peripheral devices are coupled to the PCI bus, including both real time resources and non-real time resources. For example, in one configuration, an SCSI controller, a network interface card, a video adapter, a video capture card, an audio adapter, and a telephony adapter are coupled to the PCI bus. A bus arbiter is advantageously provided for controlling and prioritizing ownership of the PCI bus based in part upon a real time indicator signal asserted by a bus agent that requires a real time data transfer. Each real time device is associated with a unique real time indicator signal. A relatively high level of arbitration priority is given to a master when it asserts its associated real time indicator signal at the time of a bus request. Bus agents which do not assert an associated real time indicator signal at the time of a bus request will lose the arbitration until all real time requests have been serviced. As a result, the system may support numerous real time processing resources while maintaining proper overall operation.

Description

COMPUTER SYSTEM HAVING AN IMPROVED BUS ARBITER ADAPTED FOR REAL TIME APPLICATIONS

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to bus arbitration within computer systems and, more particularly, to a computer system having an improved bus arbiter for arbitrating bus accesses of a CPU, real time DSP hardware, and other system resources.

2. Description of the Relevant Art

Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to a main memory. The bridge logic also typically couples to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus. Modem local bus standards such as the PCI bus and the VL bus are not constrained by a requirement to be backwards compatible with prior expansion bus adapters and thus provide much higher throughput than older expansion buses. Examples of devices which can be coupled to local expansion buses include SCSI adapters, network interface cards, video accelerators, audio cards, telephony cards, etc. An older-style expansion bus may also be coupled to the local expansion bus to provide compatibility with earlier- version expansion bus adapters. Examples of such expansion buses include the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, and the microchannel architecture (MCA) bus. Various devices may be coupled to this second expansion bus, including a fax/modem, sound card, etc.

A CPU local bus arbiter as well as a PCI bus arbiter are typically included as part of the bridge logic in many computer systems. The CPU local bus arbiter determines and prioritizes ownership of the CPU local bus, while the PCI bus arbiter determines and prioritizes ownership of the PCI bus. Mastership of either bus is typically based on a fixed arbitration fairness scheme, such as a round-robin algorithm. In some situations, a master must acquire ownership of both the PCI bus and the CPU local bus before it can proceed with a particular transfer cycle.

Computer systems were originally developed for business applications including word processing and spreadsheets, among others. Recently, computer systems have evolved toward more real time applications, including multimedia applications such as video and audio, video capture and playback, telephony, and speech recognition. Computer systems originally designed for business applications, however, are not well suited for the real time requirements of modern multimedia applications for a variety of reasons. For example, current operating systems for personal computers are not real time operating systems. In addition, the bus architecture of modern personal computer systems still presumes that the majority of applications executing on the computer system are non-real time, business applications such as word processing and/or spreadsheets which are executed solely by the main CPU. A significant problem associated with modern computer systems is that the bus arbiter which arbitrates between real time resources, non-real time resources and the CPU is typically designed to provide the CPU with maximum availability to the system memory, or is otherwise not cognizant of the real time accesses of other bus mastering devices. Real time devices can accordingly be "starved" for memory access, particularly when a relatively large number of real time devices are included within the system. This can correspondingly result in degraded performance, unsynchronized audio and video, and the dropping of frames during video or animation sequences. Therefore, a new bus arbiter system and method are desirable which provide greater access to the bus subsystems and main memory for real time devices to thus better facilitate real time applications.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by a computer system employing a bus arbiter and method for bus arbitration in accordance with the present invention. In one embodiment, a computer system is provided which includes a bus bridge coupled between a CPU local bus and a PCI bus. The bus bridge further includes memory controller logic for controlling data transfers between a main memory and masters residing on either the CPU local bus or the PCI bus. A variety of peripheral devices are coupled to the PCI bus, including both real time resources and non-real time resources. For example, in one configuration a SCSI controller, a network interface card, a video adapter, a video capture card, an audio adapter, and a telephony adapter are coupled to the PCI bus. A bus arbiter is advantageously provided for controlling and prioritizing ownership of the PCI bus based in-part upon a real time indicator signal asserted by a bus agent that requires a real time data transfer. Each real time device is associated with a unique real time indicator signal. A relatively high level of arbitration priority is given to a master when it asserts its associated real time indicator signal at the time of a bus request. Bus agents which do not assert an associated real time indicator signal at the time of a bus request will lose the arbitration until all real time requests have been serviced. As a result, the system may support numerous real time processing resources while maintaining proper overall operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Figure 1 is a block diagram of a computer system including a variety of real time resources and a bus arbiter in accordance with the present invention.

Figure 2 is a block diagram which depicts internal portions of the bus arbiter of Figure 1.

Figure 3 is a mapping diagram which illustrates a possible programmed mapping of request signals to real time indicator signals within the bus arbiter of Figure 2.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to Figure 1, a block diagram of a computer system incorporating a plurality of real time bus devices and bus arbitration logic in accordance with the present invention is shown. As illustrated in the figure, the computer system includes a central processing unit (CPU) 102 which is coupled through a CPU local bus 104 to a host/PCI/cache bridge 106. The bridge 106 includes memory control logic and is coupled through a memory bus 108 to a main memory 110. A cache memory subsystem (not shown) may further be coupled to bus bridge 106. Bus bridge 106 also interfaces to a peripheral component interconnect (PCI) bus 120. Further details regarding PCI bus 120 may be found within the publication "PCI Local Bus Specification"; Revision 2.0; April 30, 1993; PCI Special Interest Group; Hillsboro, Oregon. This publication is incorporated herein by reference in its entirety. It is noted that other local buses could be alternatively employed, such as the VESA (Video Electronics Standards Association) VL bus.

CPU 102 is illustrative of, for example, an x86 microprocessor such as an 80486 microprocessor or a Pentium-compatible microprocessor. It is understood, however, that a system according to the present invention may employ other types of microprocessors. It is further understood that the present invention may be employed within a mutiprocessing environment. Various types of devices may be connected to the PCI bus 120. For the embodiment illustrated in Figure 1, a video adapter 170 for controlling video functions is coupled to PCI bus 120. Other real time DSP devices are also preferably coupled to the PCI bus, including an audio adapter 172, a telephony adapter 174, and a video capture board 176, among others. A SCSI (small computer systems interface) disk controller 122 and a network interface card 140 are additionally shown coupled to the PCI bus 120. SCSI controller 122 is configured to provide an interface to SCSI devices such as a CD-ROM device, a tape drive device, and/or a composite disk array. The network interface card 140 interfaces to a local area network (LAN) 142.

An expansion bus bridge 150 is also preferably coupled to the PCI bus 120. The expansion bus bridge 150 interfaces to an expansion bus 152. The expansion bus 152 may be any of a variety of types, including the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, or the microchannel architecture (MCA) bus. Various devices may be coupled to the expansion bus 152, including expansion bus memory 154 and a modem 156.

A bus arbiter 180 configured to control ownership of PCI bus 120 is illustrated as a portion of bus bridge 106 . As will be explained in further detail below, the arbitration scheme employed by the computer system of Figure 1 provides a unique request signal REQ# and grant signal GNT# for each PCI master. When a particular master requires ownership of PCI bus 120, it asserts its associated request signal REQ#. In accordance with the invention, the requesting master may further assert an associated real time signal RT# to indicate that the requested access relates to a real time data transfer. When bus arbiter 180 detects assertion of a particular request signal REQ#, it further determines whether a real time signal corresponding to the requesting master has also been asserted. If the real time signal is asserted, the bus arbiter 180 assigns the requesting master a relatively high priority in its arbitration algorithm. Further details regarding the bus arbitration scheme employed by the computer system of Figure 1 will be provided further below.

As stated above, each bus master of Figure 1 asserts a unique request signal R£Q# when bus access is desired. These request signals (shown collectively as REQ[7:0]) are routed to bus arbiter 180. For example, request signal REQ2 is generated by video adapter 170, and request signal REQ5 is generated by telephony adapter 174. Corresponding grant signals GNT[7:0] are similarly routed back to the masters from bus arbiter 180 to indicate the current owner of PCI bus 120. It is noted that request signal REQ4 may be asserted by expansion bus bridge 150 if access of PCI bus 120 is required by an agent of expansion bus 152, such as modem 156.

One or more of the PCI masters are further configured to assert a corresponding real time indicator signal RT# which is provided to bus arbiter 180 when bus access is requested. Assertion of a particular real time indicator signal indicates that the requesting master is ready to initiate a real time data transfer.

Figure 2 is a diagram that depicts internal portions of bus arbiter 180. As shown, bus arbiter 180 includes an arbitration state machine 202 coupled to a request detection unit 204, a real time detection unit 206, a grant generator 208 and a configuration mapping unit 210. A decoder 212 is additionally shown coupled to configuration mapping unit 210.

Configuration mapping unit 210 is provided to map each real time indicator signal RT[4:0] to a designated request signal REQ#. Decoder 212 is provided to allow software programming of the configuration mapping unit 210. By utilizing this programmable mechanism, it is noted that the number of real time indicator signals RT# may be less than the total number of PCI masters, thus minimizing pin-count while advantageously allowing programmable flexibility in assigning each of the real time signals RT[4:0] to any of the request signals REQ[7:0]. Figure 3 illustrates a mapping of the real time indicator signals RT[4:0] programmed within configuration mapping unit 210 for the exemplary configuration of Figure 1. As shown, real time indicator signal RT0 is mapped to request signal REQ1, real time indicator signal RT1 is mapped to request signal REQ2, real time indicator signal RT2 is mapped to request signal REQ4, and so on. Different mappings may be programmed as desired depending upon the system configuration. It is noted that in one implementation, configuration mapping unit 210 includes a plurality of registers addressable in either the memory or I/O space of the system. It is further noted that in typical operation, the mapping of real time indicator signals RT[4:0] is performed during initialization of the computer system. It is specifically contemplated that in an alternative configuration, a dedicated real time signal RT# may be associated with each request signal, and that in such a configuration, configuration mapping unit 210 and decoder 212 may be omitted.

Arbitration state machine 202 is configured to transition between several bus arbitration states depending upon assertions of the bus request signals REQ[7:0] detected by request detection unit 204 . Transitions between the various arbitration states of arbitration state machine 202 are further dependent upon the real time indicator signals RT[4:0] received by real time detection unit 206. In one implementation, arbitration state machine 202 is configured to prioritize incoming bus requests based upon a round-robin prioritization scheme, assuming that none of the requests are associated with an asserted real time signal RT#. For example, consider a situation where all request signals REQ[7:0] are asserted, thus indicating that all PCI bus masters are currently requesting access to PCI bus 120. These assertions are detected by request detection unit 204. Assuming that none of the real time indicator signals RT# are also asserted, arbitration state machine 202 initially grants ownership of the bus to, for example, the master asserting request signal REQO. Upon the next bus grant cycle, arbitration state machine 202 grants ownership to the master asserting request signal REQ1, and so on in a round-robin fashion. For each bus grant cycle, arbitration state machine 202 causes grant generator 208 to assert a corresponding grant signal GNT# to indicate the winner of the current arbitration cycle. If a particular requesting master asserts its request signal REQ# and simultaneously asserts a corresponding real time signal RT#, arbitration state machine 202 assigns a higher priority to the requesting master in comparison to a priority it would have been assigned if the real time indicator signal was not asserted. That is, the priority for a particular requesting master is "bumped" to a higher priority level with respect to the implemented arbitration scheme if a corresponding real time indicator signal is asserted. For one implementation, whenever a requesting master asserts its real time indicator signal RT# and contends with other requesting masters (i.e, which are not asserting associated real time indicator signals), the master asserting its real time indicator signal takes precedence and wins the arbitration. If several requesting masters each having asserted real time indicator signals contend for the bus, the arbitration state machine 202 arbitrates those requests in a round-robin fashion, without regard to any remaining requesting masters (which are not associated with asserted real time signals). This operation thus ensures that real time requests are serviced expeditiously. Accordingly, a relatively large number of real time devices may be employed within the computer system while maintaining proper overall operation.

It is noted that the system of Figure 1 may be configured to allow PCI masters to selectively assert an associated real time indicator signal RT# depending upon whether a real time access is currently being requested. For this purpose, a particular PCI master may include a register, such as register 195 shown within video adapter 170, which can be set under software control to cause the master to assert its associated real time signal whenever it requests the bus. If the master is not going to perform a real time operation, the register may be cleared by the system programmer prior to the bus access to thus prevent the associated real time signal from being asserted. This thereby allows the system programmer to selectively control assertions of the real time indicator signals. Real time bus devices may alternatively be configured to independently control assertions of corresponding real time indicator signals depending upon the type of transfers to be effectuated.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

WHAT IS CLAIMED IS:

1. A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor through a CPU local bus; an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus; a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions and to generate a real time indicator signal indicative of a real time bus access request; a non-real time master coupled to said expansion bus, wherein said non-real time master i<T configured to perform non-real time processing functions; and a bus arbiter coupled to said expansion bus, wherein said bus arbiter is configured to detect said real time indicator signal from said real time master and to responsively grant mastership of said extension bus to said real time master in favor of a contending request by said non-real time master.

2. The computer system as recited in claim 1, wherein said non-real time master is configured to assert a first request signal to request ownership of said expansion bus and wherein said real time master is configured to assert a second request signal to request ownership of said expansion bus.

3. The computer system as recited in claim 2 wherein said real time master is configured to assert said second request signal simultaneously with an assertion of said real time indicator signal.

4. The computer system as recited in claim 1 wherein said expansion bus is a PCI bus.

5. The computer system as recited in claim 1 wherein said real time master is an audio adapter.

6. The computer system as recited in claim 5 further comprising a video adapter coupled to said PCI bus, wherein said video adapter is configured to assert a third request signal and a second real time indicator signal when requesting ownership of said expansion bus.

7. The computer system as recited in claim 6 wherein said bus arbiter is further configured to assign a higher level of arbitration priority to said audio adapter and said video adapter in comparison to an arbitration priority of said non-real time master in response to assertions of said first and second real time indicator signals.