WO1995012896A1

WO1995012896A1 - Semiconductor device

Info

Publication number: WO1995012896A1
Application number: PCT/JP1994/001853
Authority: WO
Inventors: Tadahiro Ohmi; Mizuho Morita
Original assignee: Tadahiro Ohmi; Mizuho Morita
Priority date: 1993-11-02
Filing date: 1994-11-02
Publication date: 1995-05-11
Also published as: JPH07131007A

Abstract

A semiconductor device which includes a substrate (13) having a first conductivity type; first and second regions (21, 22) having a second conductivity type opposite to that of the substrate, the two regions being separate from each other in or on the substrate to define a channel inside the substrate between them; an electrode (16) positioned on an insulating layer (15) above the channel between the first and second regions in such a manner that it does not come into direct electric contact with either the first or second region; and third regions (19, 20) having the same first conductivity type as that of the channel inside the substrate and a higher impurity concentration than that of the channel, and positioned on the bottom side of the first and/or second regions, wherein the third regions serve to limit the extension of a depletion layer from the first or second region into the channel due to the voltage applied between the first and second regions, and punch-through is thereby reduced.

Description

Technical field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that can operate at a very high speed. Background art

The conventional technology will be described using an example of a MOS FET as a semiconductor device, particularly a MOS FET with a short channel length.

Conventionally, in semiconductor integrated circuits, high speed has been achieved by miniaturization of elements. For example, by shortening the channel length of a MOS FET element in a semiconductor integrated circuit, the current drive capability of the element has been improved and the load capacitance (gate capacitance of the next-stage element) has been reduced, so that the speed of the semiconductor integrated circuit has been increased. Have been.

However, when the channel length of a MOS FET device is shortened, punch-through becomes remarkable, and the device can no longer operate normally. Conventionally, a MOS FET with a short channel length has been known in which the impurity concentration in the channel portion is increased in order to suppress punch-through. In this MOSFET, when a voltage is applied to the drain electrode, the extension of the depletion layer from the drain is reduced in this high impurity concentration channel portion, and punch-through is reduced. However, this MOS FET has a drawback that, because of the high impurity concentration of the channel, the M 0 SFET has low carrier channel mobility and cannot operate at high speed. In addition, this MOSFET has the disadvantage that the MOSFET has a high depletion layer capacitance due to the high impurity concentration in the channel portion and a large sub-threshold swing, so that it does not operate at high performance. If the sub-threshold swing of the device is large, the threshold voltage of the device cannot be lowered and the power supply voltage cannot be lowered, so that it is difficult to realize a semiconductor integrated circuit with low power consumption. Furthermore, in this MOSFET, the threshold voltage of the MOSFET is high due to the high impurity concentration of the channel. There is a drawback in that a device having a high pressure, a low pressure, and a threshold voltage cannot be realized.

In this case, in order to operate the element with high speed and high performance, it is required to have high mobility and small sub-threshold swing. Therefore, in order to increase the mobility and reduce the sub-threshold swing, it is necessary to lower the impurity concentration in the channel portion.

Conventionally, MOS FETs with a short channel length have the same conductivity type as the channel and the impurity concentration of the channel on the channel and drain substrates or on the channel side and on the channel side of the channel in order to suppress punch-through. It is known that a semiconductor layer region having a higher impurity concentration is provided. In this MOSFET, when a voltage is applied to the drain electrode, the extension of the depletion layer from the drain is reduced by this high-concentration impurity layer, and punch-through is reduced.

However, since the depletion layer extends from the drain to the channel side in this MOSFET, punch-through occurs in MOS FETs with a short channel length, and the MOSFET does not operate normally. In addition, this MOSFET has a disadvantage that the high-concentration impurity layer is provided on the bulk side of the substrate of the channel, so that the depletion layer capacity of the MOS FET is large and the subthreshold swing is large, so that the MOSFET does not operate at high performance. I got it.

In this case, a small sub-threshold swing is required to operate the device with high performance. Therefore, in order to reduce the depletion layer capacitance, it is necessary to lower the impurity concentration on the substrate bulk side of the channel.

Conventionally, MOS FETs with a short channel length have been known in which the drain is surrounded by a semiconductor layer region having the same conductivity type as the channel and an impurity concentration higher than the impurity concentration of the channel in order to suppress punch-through. Have been. In this MOS FET, when a voltage is applied to the drain electrode, the extension of the depletion layer from the drain to the substrate bulk side and the channel side is reduced by this high-concentration impurity layer, and punch-through is reduced.

The MOSFET has a high impurity concentration semiconductor layer between the drain and the channel, and between the source and the channel. There is a disadvantage that it does not work Was. In this MOS SFET, the impurity concentration existing between the drain and the channel and between the source and the channel is high. Due to the semiconductor layer, the depletion layer capacitance is large in the MO SFET with a short channel length, The drawback is that the hold swing is large!

In this case, high mobility is required to operate the device at high speed. Therefore, it is necessary to lower the impurity concentration of the channel between the source and the drain.

As described above, a semiconductor device that suppresses punch-through and has a low impurity concentration in a channel is indispensable for realizing a high-speed and high-performance semiconductor device.

The present invention has been made to solve the above-mentioned problems of the related art, and provides a semiconductor device having high performance and realizing high-speed operation. Disclosure of the invention

A semiconductor device according to the present invention has a first-type electrically conductive substrate and a second-type electrical conductivity opposite to the electrical conductivity of the substrate, and is mutually interconnected in or on the substrate. A first and second region spaced apart and defining a channel in the substrate between each other and forming an electrical connection with the substrate; and between the first and second regions. An electrode placed on the channel via an insulating layer so as not to make direct electrical contact with the first and second regions, or with any of the regions, and an electric current of a channel in the substrate. The conductivity is the same as that of the first type and has an impurity concentration higher than the impurity concentration of the channel of the substrate, and is disposed on at least one of the first and second regions on the substrate bulk side. And a third region, wherein the third region First and reduces the extension of the depletion layer to the channel from the first or the second region by application of a voltage between the second region, thereby characterized in that to reduce the punch-through. Action

According to the semiconductor device of the present invention, even in a semiconductor device having a short channel length, punch-through is suppressed, the channel mobility is high, and the sub-threshold swing is low. In addition, since the semiconductor device has a high t, a high current drive capability, and a high performance that cannot be realized by a conventional semiconductor device, the circuit can be operated at high speed and power can be saved. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional structural view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional structural view of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional structural view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional structural view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional structural view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a graph showing the relationship between the drain current and the drain voltage of the semiconductor device according to the first example of the present invention.

FIG. 11 is a graph showing the relationship between the drain current and the gate voltage of the semiconductor device according to the first example of the present invention.

FIG. 12 is a graph showing the relationship between the threshold voltage and the gate length of the semiconductor device according to the first example of the present invention.

FIG. 13 is a graph showing the relationship between the subthreshold swing and the gate length of the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a graph showing the relationship between the drain current and the gate length of the semiconductor device according to the first example of the present invention.

(Explanation of code)

1 1 Electrode on the back of the board

1 2 p + area,

1 3 High resistivity p-substrate (substrate),

1 4 Isolation area,

1 5 Gate insulating film, 16 Gate electrode,

17 Insulation separation membrane,

18 Insulation separation membrane,

19, 20 punch-through control,

21 η or η + source,

22 η or η + drain,

23 η + source,

24 η + drain,

25 source electrodes,

26 drain electrode,

27 Passive membrane,

28 Metal oxide film. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Example 1)

FIG. 1 is a sectional view of a semiconductor device showing the first embodiment.

Here, only the η-channel MOS included in the semiconductor device is shown. In FIG. 1, 11 is an electrode on the back of the substrate, 12 is a ρ + region, 13 is a high resistivity ρ-substrate (base), 14 is an isolation region, 15 is a silicon oxide film, a silicon nitride film or Ta _20. _{_{5, T i 0 2, Z}} r0 2 or a 1 ₂ 0 ₃ or the like high dielectric constant insulating film (gate insulating film), 1 6 a l, Mo, W, T a, T i, Moshiku is N i Etc. Metal, Mo Si. , WS i ₂ , Ta Si. , T i S i ₂ or N i S i ₂ a metal such as silicon side, or polysilicon (gate electrode), divorced oxide film or a silicon nitride film for isolation 17, 18 for isolation 19, 20 are p or p + regions (punch through control), 21 is n or n + regions (source), 22 is n or n + regions (drain), and 23 is n + Region (source), .24 is the n + region (drain), 25 is the metal electrode (source electrode), 26 is the metal electrode (drain electrode), and 27 is the Silicon oxide film for passivation, PSG film or silicon nitride film. In FIG. 1, the punch-through control 20 having an impurity concentration higher than the impurity concentration of the channel portion of the p-region 13 is formed on the substrate bulk side of the drain 22, and the non-through control 20 and the drain 22 are formed. As a result, a pn junction is formed, and the thickness of the punch-through control 20 is formed larger than the thickness of the depletion layer in the punch-through control 20 when a predetermined voltage is applied to the drain electrode 26. In this structure, since the impurity concentration in the channel region of the P region 13 is lower than the impurity concentration of the punch-through control 20, the termination is performed by the electric force lines from the drain 22 and the ionized impurity of the punch-through control 20. When the voltage is applied to the drain electrode 26, the depletion layer from the drain 22 to the channel region of p-region 13 In order to suppress elongation, and because the thickness of the punch-through control 20 is formed larger than the thickness of the depletion layer in the punch-through control 20 when a predetermined voltage is applied to the drain electrode 26. In order to suppress the extension of the depletion layer from the drain 22 to the p-region 13 on the substrate bulk side of the region 20, punch-through hardly occurs. In FIG. 1, when the impurity concentration of the punch-through control 20 is selected to be a predetermined concentration, it is desirable to lower the impurity concentration of the channel portion of the p − region 13.

In FIG. 1, the material of the gate electrode 16 desirably has a high diffusion potential with respect to the 1+ regions 23 and 24. In CMOS, the gate electrode material is composed of the n + region and the p + region. It is desirable to have a high diffusion potential for both regions. For example, W gives a high diffusion potential. W has a diffusion potential of about 0.5 V for the n + region and about 0.6 V for the P + region. Of course, the gate electrode only needs to have a high potential barrier for both the n + region and the p + region of the work function, and may be Al, a refractory metal or a metal silicide. Therefore, the resistance of the gate electrode is small. Further, in this structure, n by + diffusion potential of the gate electrode 1 6 against the source region 2 3 causes a potential barrier in the channel region, realm 1 3 impurity concentration 1 0 ^l4 ~ 1 0 of channel portion ^Normally- off characteristics during the ^{MOS transit} are realized at approximately ¹ cm- ³ . That is, the region 13 is a high resistivity region, and the impurity concentration is kept low. Therefore, the channel through which electrons flow The width is kept wide, and short channels can be realized without reducing the mobility of the carrier running in the channel. In other words, it is an M〇S transistor with a large conversion conductance.

In FIG. 1, the impurity concentration in the region 13 on the substrate bulk side from the gate insulating film is about 10 ¹⁴ to 1 O ^lD cm− ³ , and the depletion layer capacitance is small. Therefore, the MOS transistor has a small subthreshold noise swing. That is, transistor operation is realized with a low power supply voltage.

In FIG. 1, the junction surface between the regions 21 and 19 and the junction surface between the regions 22 and 20 are flat, and the area of the junction surface is small. The capacitance between the region and the substrate and between the drain region and the substrate is small.

In FIG. 1, the materials of the electrodes 25 and 26 are, for example, A1 and W, and the resistance of the source electrode and the drain electrode is small. Of course, the source and drain electrodes, M o, T a, T i, metals such as N i or _{M, o S i 2, WS} i 2, T a S i. May be a _{T i S i 2, N i} S i 2 etc. of the metal silicide. Since the source resistance, drain resistance, and gate resistance are small, the source and drain capacitances are small, and the conversion conductance is large, the transistor has excellent high-speed performance.

In FIG. 1, the impurity concentration of the drain region ^{22 is} about 10 ^{lo to} 10 O ^ cm ^、, and the electric field strength in the region ²² near the ^gate insulating film 15 and the insulating isolation film ^{18 is} small. It is kept low, has low hot carrier generation efficiency, and has high reliability and high reliability. In order to reduce the electric field strength in the region 22, it is desirable to lower the impurity concentration in the region 22. On the other hand, in order to reduce the resistance of the region 22 and reduce the drain resistance, it is desirable to increase the impurity concentration. Therefore, it is desirable to select the impurity concentration of the drain region 22 such that the resistance of the region 22 is small in the range of the impurity concentration where the electric field intensity in the region 22 is equal to or lower than the dielectric breakdown electric field intensity. In FIG. 1, when no voltage is applied to the drain electrode 26 or when a predetermined voltage is applied to the drain electrode 26, the extension surface of the interface between the gate insulating film 15 and the region 13 in the region 22 The potential of the region corresponding to the extension of the channel along is higher than the potential of the channel portion of the p-region 13, that is, the electron energy of the extension region of the channel in the region 22 is P—region 13.Electron energy in channel 3 The impurity concentration of the cross-through control 20 and the impurity concentration of the region 22 are selected so as to be lower. In FIG. 1, when the impurity concentration of the region 22 and the impurity concentration of the region 20 are selected to be predetermined, in order to suppress punch-through, the interface between the gate insulating film 15 and the region 13 and the region 22 and the region 20 It is desirable to shorten the distance to the interface between the two. In addition, when the impurity concentration of the region 22 is selected to be a predetermined concentration, the distance between the interface between the gate insulating film 15 and the region 13 and the interface between the region 22 and the region 20 are long in order to suppress punch-through. It is desirable to increase the impurity concentration of the punch-through control 20. In this structure, since the potential is gradually increased from the channel portion to the drain, that is, the electron energy is gradually decreased, electrons as carriers easily flow, and punch-through control 20 suppresses the punch-through. .

(Example 2)

FIG. 2 is a sectional view of a semiconductor device showing the second embodiment.

In FIG. 2, 17a is a silicon oxide film or a silicon nitride film for insulating and isolating, 19a 19b 20a 20b is a p or p + region (punch through control), and 21a 21b is n or n + The region (source) and 22a and 22b are n or n + regions (drain).

In FIG. 2, since the impurity concentration of the drain region 22b is lower than the impurity concentration of the region 22a, the electric field intensity in the region 22b is kept low, and the hot carrier generation efficiency is low and the reliability is low. High !, transistor.

(Example 3)

FIG. 3 is a sectional view of a semiconductor device showing the third embodiment.

In Figure 3, 19 c 19 d 20 c 20 d is the p or p + region (punch through control), 21 c 21 d is the n or n + region (source), 22 c. It is an n + region (drain).

In FIG. 3, since the impurity concentration of the punch-through control region 20c is lower than the impurity concentration of the region 20d, the capacitance between the region 22c and the region 20c is small, that is, the capacitance between the drain region and the substrate is small. , It will be a good evening with excellent high speed performance.

(Example 4) 13

9

FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment.

In FIG. 4, 19 e and 20 e are p—, p or p + regions.

In FIG. 4, the impurity concentration of the region 20 e is higher than the impurity concentration of the region 13 and lower than the impurity concentration of the region 20. In this structure, when the distance between the interface between the gate insulating film 15 and the region 13 and the interface between the region 22 and the region 20 is set to a predetermined length and the impurity concentration of the region 22 is set to a predetermined concentration. If the impurity concentration of the region 20 is lowered, a depletion layer extends from the drain 22 to the channel portion of the region 13 to cause punch-through. Suppress the extension of the depletion layer to the channel part. When the impurity concentration in the region 20 e is increased, the mobility of the carrier electrons decreases, and the sub-threshold swing increases, so that the impurity concentration in the region 20 e may be low. desirable. Therefore, the impurity concentration of the region 20 e is made lower than the impurity concentration of the region 20, so that the mobility of carriers as carriers is kept high, and the region 20 and the region 20 e are formed so that carrier punch-through does not occur. It is desirable to select the impurity concentration of e. In this structure, since the region 20 and the region 20 e suppress the extension of the depletion layer from the drain to the channel portion, punch-through force is unlikely to occur.

(Example 5)

FIG. 5 is a sectional view of a semiconductor device showing the fifth embodiment.

In FIG. 5, 23 a is a non-doped, n−, n or n + region, and 24 a is a non-doped, n−, n or n + region.

In Figure 5, the impurity concentration in the region 2 4 a is a throat one flops de ~ 1 0 ¹⁸ c m_ ³ mm, electrons in order to bleed the region 2 4 a is a number carrier of the n + regions 2 2, gate (1) The electric field intensity in the region 22 near the insulating film 15 and the vicinity of the insulating separation film 18 is kept low, so that a hot carrier generation efficiency is low and a highly reliable transistor is obtained.

(Example 6)

FIG. 6 is a sectional view of a semiconductor device showing the sixth embodiment.

In FIG. 6, 15a is a silicon oxide film or a silicon nitride film (gate insulating film), 16a is a metal such as A1, Mo, W, Ta, Ti, or Ni; S i ₂ , _{WS i 2, T a S i} 2, T i S i 2 or N i S i ₂ such metal silicide, if Ku polycrystalline silicon (gate Bok electrode), 1 8 a silicon oxide for isolation Film or silicon nitride film, 19 f and 20 f are p or p + regions (punch through control), 21 e is n or n + regions (source), and 22 e is n or n + regions ( The drain) and 28 are a silicon oxide film, a silicon nitride film, a metal oxide film or a metal fluoride film for insulating and separating.

In FIG. 6, the interface between the region 22 e and the region 20 f is closer to the region 24 than the interface between the gate insulating film 15 a and the region 15 a in the region 13 on the substrate bulk side. That is, it is formed on the opposite side of the substrate bulk. In this structure, when no voltage is applied to the drain electrode 26, or when a predetermined voltage is applied to the drain electrode 26, the potential of the region corresponding to the extension of the channel in the region 22e becomes P-region The punch-through control is performed so that the potential of the channel portion 13 is higher than the potential of the channel portion, that is, the electron energy of the extension region of the channel in the region 22 e is lower than the electron energy of the channel portion of the p-region 13. An impurity concentration of 20 f and an impurity concentration of region 22 e are selected. In FIG. 6, when the impurity concentration of the region 22 e and the impurity concentration of the region 20 f are selected to be the predetermined concentrations, the gate insulating film 15 a and the region 20 f are required to suppress punch-through. It is desirable to shorten the distance between the two. Further, when the impurity concentration of the region 22 e is set to a predetermined concentration, the punch-through control should be performed as the distance between the gate insulating film 15 a and the region 20 f becomes longer, in order to suppress punch-through. It is desirable to increase the impurity concentration at 0 f. In this structure, since the potential is gradually increased from the channel portion to the drain, that is, the electron energy is gradually decreased, electrons as carriers easily flow, and punch-through is performed by the punch-through control 20f. Restrained.

In FIG. 6, the interface between the gate insulating film 15a and the region on the substrate bulk side of the region 15a in the region 13 is closer to the region 13 than the interface between the region 22e and the region 20f. It is formed on the substrate bulk side. With this structure, the electric field strength between the source and drain in the channel section is reduced, so that punch-through of the carrier is suppressed, and the hot carrier generation efficiency in the channel section is kept low. Is high! Region 21 in Figure 1, region 21a, 21b in Figure 2, region 21c, 21d in Figure 3, region 21 in Figure 4, region 21 in Figure 5, 23a and the impurity concentration of the region 21e in FIG. 6 are desirably increased to reduce the resistance of each region. By increasing the impurity concentration in each region, a transistor having low source resistance and excellent high-speed performance can be obtained.

As described above, the semiconductor device having the punch-through control at least on the substrate bulk side from the drain according to the present invention realizes a semiconductor integrated circuit using a transistor having excellent ultra-high speed and high reliability. it can.

In FIG. 1 to FIG. 6, the p-substrate 13 having the p + region 12 on the back surface has been described as the substrate. However, the operation of the semiconductor device described above is also realized using an SOI substrate. Alternatively, a double gate transistor structure having a gate insulating film, a gate electrode or a gate electrode on the back surface, and punch-through control on at least the substrate bulk side of the back surface drain can be realized.

Next, an example of a manufacturing process for manufacturing the semiconductor device of FIG. 1 is shown in FIG. The case where a p-substrate is used as the substrate 13 will be described. Of course, the region 13 may have a pail structure. The isolation region 14 is formed by using, for example, the LOCOS method. That is, after the surface of the substrate 13 is thermally oxidized, a silicon nitride film is deposited by the CVD method. The silicon nitride film or the silicon nitride film and the thermal oxide film corresponding to the region 14 are removed by reactive ion etching. Subsequently, after forming a thermal oxide film in the region 14 by thermal oxidation, the silicon nitride film and the thermal oxide film on the surface of the region 13 are removed by reactive ion etching.

The region 14 is thus formed, but may be formed by any other method without being limited to the above method.

Next, a thermal oxide film having a thickness of 3 to 1 O nm is formed by thermally oxidizing the surface of the region 13. Of course, a high dielectric constant insulating film may be deposited by a CVD method. Subsequently, a metal, metal silicide or polycrystalline silicon layer is deposited by the CVD method, and a silicon oxide film or a silicon nitride film is further deposited by the CVD method, and a predetermined region is reactive as shown in FIG. 7 (a). Etch by ion etching. Of course, region 17 thermally oxidizes the surface of region 16 May form a silicon oxide. Here, the thickness of the insulating layer in the region 17 is formed larger than the thickness of the thermal oxide film or the high dielectric constant insulating film in the region 15.

The regions 19 and 20 having a predetermined impurity concentration shown in FIG. 7B are formed by ion implantation of B and annealing. In order to suppress the diffusion of B into the region 13, the activation annealing temperature is preferably low, preferably 700 ° C. or lower, more preferably 500 ° C. or lower. Of course, rapid thermal annealing may be used as the activation annealing method in order to suppress the diffusion of B into the region 13. Subsequently, regions 21 and 22 having a predetermined impurity concentration are formed by ion implantation of As or P and activation annealing. In order to suppress the diffusion of As or P into the region 13 or the regions 19 and 20, the activation annealing temperature is preferably low, preferably 700 ° C or lower, and 500 ° C or lower. More desirable. Of course, rapid thermal annealing may be used as the activation annealing method in order to suppress the diffusion of As or P into the region 13 or the regions 19 and 20.

The regions 19 and 20 or the regions 21 and 22 shown in FIG. 7B may be formed by reactive ion etching and epitaxy. After the structure shown in FIG. 7A is formed, the region 13 is selectively etched to a predetermined depth by reactive ion etching using the regions 17 and 14 as a mask. Subsequently, regions 19 and 20 are formed by selectively epitaxially growing B-doped single-crystal silicon having a predetermined impurity concentration on the surface of the region 13. Next, regions 21 and 22 are formed by selectively epitaxially growing P-doped single-crystal silicon having a predetermined impurity concentration on the surfaces of the regions 19 and 20.

Next, after depositing a silicon oxide film or a silicon nitride film by the CVD method, etching is performed by reactive ion etching until the silicon oxide film or the silicon nitride film in a region other than the region 18 is removed.

Next, regions 23 and 24 are formed by selectively epitaxially growing P-doped single-crystal silicon on the surfaces of the regions 21 and 22. Of course, after selectively growing non-doped single-crystal silicon, P or As is ion-implanted, followed by activation annealing to form regions 23 and 24 having a predetermined impurity concentration. You may. The regions 23 and 24 may of course be polycrystalline silicon. Of course the area 23 and 24 may be metal or metal silicide. Next, as shown in FIG. 7 (d), a W or A1 layer is selectively formed by a CVD method or a sputtering method.

Further, the structure of the semiconductor device shown in FIG. 1 can be manufactured by forming the passivation layer 27 and then forming the back surface p + layer region 12 and the electrode 11.

Next, an example of a manufacturing process for manufacturing the semiconductor device of FIG. 2 is shown in FIG. After the formation of the insulating isolation region 14, the surface of the region 13 is thermally oxidized to form a thermal oxide film having a thickness of 3 to 1 Onm. Of course, a high dielectric constant insulating film may be deposited by a CVD method. Subsequently, a metal, metal silicide or polycrystalline silicon layer is deposited by a CVD method, and a predetermined region is etched by reactive etching as shown in FIG. 8A.

The surface of the region 16 is thermally oxidized to form a metal oxide or a silicon oxide. Of course, an insulating layer may be formed by depositing a silicon oxide film by a CVD method. Here, the thickness of the insulating layer in the region 17a is formed larger than the thickness of the thermal oxide film or the high dielectric constant insulating film in the region 15. Next, as shown in FIG. 8 (b), etching is performed until a predetermined area of the area 15 is removed by reactive ion etching.

The regions 19a and 20a having a predetermined impurity concentration shown in FIG. 8C are formed by B ion implantation. Subsequently, regions 21a and 22a having a predetermined impurity concentration are formed by As or P ion implantation. Next, heat treatment is performed at a temperature of 500 ° C or more or 700 ° C or more for a predetermined time, and As or P is diffused using the regions 21a and 22a as As or P diffusion sources, as shown in FIG. ) Are formed, and at the same time, regions 19b and 20b are formed by diffusion of B using the regions 19a and 20a as diffusion sources of B. Of course, the regions 19b, 2 Ob and 21b, 22b may be formed by oblique ion implantation of B and As or P and activation annealing after forming the structure shown in FIG. 8 (b). Also, after forming the structure shown in FIG.

Regions 19b and 20b or regions 21b and 22b shown in Fig. 8 (d) After forming reactive regions 19a and 20a and regions 21a and 22a by reactive ion etching and epitaxy, temperature of 500 ° C or more or 700 ° C or more The region 21a and 22a are formed by diffusion of P using the regions 21a and 22a as a diffusion source of P, and the regions 19a and 20a are formed at the same time. Regions 19b and 2Ob may be formed by diffusion of B as a diffusion source of B.

After the structure shown in FIG. 7 (c) is formed in the semiconductor device of FIG. 3, the regions 21, 22 and 22 are formed by reactive ion etching using regions 17, 18 and 14 as a mask. 19, 20 are selectively etched. Subsequently, B-doped single-crystal silicon having a predetermined impurity concentration is selectively grown on the surface of the region 13 by epitaxy to form regions 19c and 20c. Next, on the surfaces of the regions 19c and 20c, P-doped single-crystal silicon having a predetermined impurity concentration is epitaxially grown to form regions 21c and 22c. Here, the impurity concentration of the region 20c is formed lower than the impurity concentration of the region 20d.

In the semiconductor device of FIG. 4, after the structure shown in FIG. 7A is formed, regions 19 and 20 having a predetermined impurity concentration are formed by ion implantation of B. Subsequently, a heat treatment is performed for a predetermined time at a temperature of 500 ° C. or more or 700 ° C. or more, and at the same time, the regions 19 and 20 are diffused by using e, forming 20 e. Of course, the regions 19 e and 20 e may be formed by oblique ion implantation of B and activation annealing after forming the structure shown in FIG. Alternatively, after the structure shown in FIG. 8B is formed, it may be formed by oblique ion implantation of B and activation annealing.

Next, regions 21 and 22 having a predetermined impurity concentration are formed by As or P ion implantation and activation annealing. In order to suppress the diffusion of As or P into the region 13 or the regions 19, 19 e, 20 and 20 e, the activation annealing temperature is preferably low, and preferably 700 ° C. or less. , 500 ° C or less is more desirable. Of course, in order to suppress the diffusion of As or P into the region 13 or the regions 19, 19 e, 20 and 20 e, the rapid annealing method was used as the activation annealing method. Is also good. Of course, the regions 19 and 20 are selectively etched to a predetermined depth using the region 17 and the region 14 as masks by reactive ion etching. After that, regions 21 and 22 may be formed by selectively epitaxially growing P-doped single-crystal silicon having a predetermined impurity concentration on the surfaces of regions 19 and 20. After forming the structure shown in FIG. 7 (c), the semiconductor device of FIG. 5 has a non-doped, n-type, n-type or n + type with a lower impurity concentration than the regions 21 and 22 on the surfaces of the regions 21 and 22. Regions 23a and 24a are formed by selectively epitaxially growing type single crystal silicon, and regions 23 and 24 are formed by epitaxially growing n + type single crystal silicon having a higher impurity concentration.

Next, an example of a manufacturing process for manufacturing the semiconductor device of FIG. 6 is shown in FIG. After forming the isolation region 14, n or n + region layers 21e and 22e are formed on the surface of the region 13 by As or P ion implantation. Of course, n or n + type single crystal silicon may be epitaxially grown. Subsequently, a silicon oxide film is deposited by a CVD method, and a predetermined region is etched by reactive ion etching as shown in FIG. Next, as shown in FIG. 9 (a), regions 19f and 20f are formed by B ion implantation and activation annealing. Here, the impurity concentration of the regions 19 f and 20 f is formed lower than the impurity concentration of the n or n + region layers 21 e and 22 e on the surface of the region 13.

Next, as shown in FIG. 9B, etching is performed by isotropic etching until a predetermined region of the region 29 is removed. Subsequently, after selectively epitaxially growing P-doped single-crystal silicon 23, 24 on the surface of the regions 21 e, 22 e, W, Ta, T A metal film 25, 26 of i, Zr or Nb is formed. Next, a metal oxide film 28 is formed by thermal oxidation or anodic oxidation.

Next, the region 29 is removed by etching. Subsequently, after depositing a silicon oxide film or a silicon nitride film by the CVD method, the silicon oxide film or the silicon nitride film in a region other than the region 18a shown in FIG. 9C is removed by reactive ion etching. Etching until done.

Next, the regions 21a, 22e and 13 are selectively etched to a predetermined depth by reactive ion etching using the regions 18a, 28 and 14 as a mask. Region 15a is formed by thermal oxidation as shown in () I do. Furthermore, the gate electrode 1 6 a is by CVD, metal such as W, to deposit a metal Shirisai de or polycrystalline silicon, such as WS i _2, are formed.

Region 21 in Figure 1, 21a and 21b in Figure 2, 21c and 21d in Figure 3, 21 in Figure 4 and 21 and 23 in Figure 5. a, In order to reduce the resistance of each of the regions 21 e in Fig. 6, the structure in which the impurity concentration in each region is high is made by selectively epitaxially growing high-doped P-doped single-crystal silicon. Thus, each region is formed. Of course, after each region is formed, it may be selectively formed by ion implantation of P or As and activation annealing.

FIG. 10 is a graph showing the relationship between the drain current and the drain voltage of the semiconductor device according to the first embodiment. The horizontal axis of FIG. 10 represents the drain voltage, and the vertical axis represents the drain current. Numerical values in the figure represent gate voltages. The impurity concentration of the B-doped p-type substrate is 1 × 10 ¹⁴ cm. The gate oxide thickness is 3 nm. Tungsten silicide (WS i ₂ ) is used as the gate electrode. The gate length is 0.05〃m. The channel length is 0.05〃m and the channel width is 1. 13 Concentration of Roh inch through control 1 9, 20 is 2 10 ¹⁸ cm- ^3. The depth of the source region 21 and the drain region 22 is 0.01 μm, the impurity concentration of P in the source region 21 and the drain region 22 is 2 × 10 ¹⁹ cm— ³ , The impurity concentration of P in the drain region 24 is 2 ^{× 102} ⁽⁾ cm cm. Tungsten (W) is used for the source and drain electrodes.

It can be seen that the semiconductor device according to Example 1 exhibited normal drain current-drain voltage characteristics even when the gate length was as short as 0.05 μm, and no punch-through occurred. The drain current one drain voltage characteristics of the semiconductor device of the MOS FET structure is the concentration of B in the punch-through control the same 1 X 10 ¹⁴ cnT ³ and the concentration of substrate is not shown the transistor characteristics at all, the characteristics of the resistor Are obtained. In other words, it was found that the semiconductor device according to Example 1 did not cause punch-through even in a short channel, and performed normal transistor operation.

FIG. 11 shows the drain current of the semiconductor device according to the first embodiment described with reference to FIG. 4 is a graph showing a relationship with a gate voltage. In FIG. 11, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Numerical values in the figure represent drain voltages. It can be seen that the semiconductor device according to Example 1 exhibited normal sub-threshold characteristics even when the gate length was as short as 0.05 μm, and no punch-through occurred. When the drain voltage is 0.5V, the threshold voltage is 0.66V, and when the drain voltage is 1.0V, the threshold voltage is 0.58V. The change in threshold voltage due to the increase in drain voltage is 0.08 V, which is kept small. That is, it was found that the semiconductor device according to Example 1 did not generate a punch-through force even in a short channel and operated normally. When the drain voltage is 1.0 V, the sub-threshold swing is 97 mV / decade, which is kept small even for a short channel length. That is, in the semiconductor device according to the first embodiment, the punch-through is suppressed and the impurity concentration of the substrate is kept low. It has been found that the hold swing is small and high-performance transistor operation is performed.

FIG. 12 is a graph showing the relationship between the threshold voltage and the gate length of the semiconductor device according to the first embodiment described in FIG. The horizontal axis in FIG. 12 represents the gate length, and the vertical axis represents the threshold voltage. Numerical values in the figure represent drain voltages.

It can be seen that the semiconductor device according to Example 1 shows normal transistor characteristics even when the gate length is extremely short, 0.05 / zm, and the punch-through is suppressed to a small extent.

FIG. 13 is a graph showing the relationship between the sub-threshold swing and the gate length of the semiconductor device according to the first embodiment described in FIG. The horizontal axis in Fig. 13 represents the gate length, and the vertical axis represents the sub-threshold swing. The numbers in the figure represent the drain voltage.

In the semiconductor device according to the first embodiment, even when the gate length is as short as 0.05 μm, the degree of punch-through is kept low and the impurity concentration of the substrate is kept low. It was found that the sub-threshold swing was small and high-performance transistor operation was performed.

FIG. 14 shows the drain current of the semiconductor device according to the first embodiment described with reference to FIG. It is a graph which shows the relationship with gate length. The horizontal axis in FIG. 14 represents the gate length, and the vertical axis represents the drain current. The difference between the gate voltage and the threshold voltage is 0.3V. It was found that the semiconductor device according to Example 1 had a large drain current of 190 AZ zm at a very short gate length of 0.05 zm, that is, a large current driving capability, and operated a high-speed transistor. . On the other hand, in the case of MOSFET in which the impurity concentration of the channel portion is increased, the concentration of the channel portion where the threshold voltage is 0.08 V when the drain voltage is 0.1 and 1.0 V is 1.16 x 10 ¹⁸ the drain current of the semiconductor device of the MOS FET structure is CM_ ³ is 101 // 1 2 about results showing the performance of a semiconductor device according to AZ / m example 1 is obtained. That is, it was found that the semiconductor device according to the first example operates as a high-speed transistor.

Note that the semiconductor devices according to the second, third, fourth, fifth, and sixth embodiments also have the same connections as those shown in FIGS. 10, 11, 12, 13, and 14. The fruits have been obtained. Industrial applicability

The semiconductor device of the present invention is excellent in performance of suppressing punch-through, so that the channel length can be shortened as necessary, and therefore, an ultra-miniaturized semiconductor device can be realized.

Since it can be manufactured by self-alignment, ultra-fine processing can be performed, and therefore, an ultra-high-density semiconductor device with ultra-fine processing can be obtained.

According to the present invention, it is possible to provide a semiconductor device having high current driving capability and realizing high-speed operation of a circuit.

Claims

The scope of the claims

1. a first type of electrically conductive substrate; and a second type of electrical conductivity opposite to the electrical conductivity of the substrate, and are spaced apart from each other in or on the substrate. Forming a channel in the substrate between each other and forming an electrical connection with the substrate.

Between the first and second regions, and between the first and second regions, but via an insulating layer so as not to be in direct electrical contact with the first and second regions or with the t and shift regions. An electrode placed on the channel, and an electrical conductivity of the channel in the substrate having the same type 1 electrical conductivity and an impurity concentration higher than an impurity concentration of the channel of the substrate; A third region disposed on at least one of the first and second regions on the substrate bulk side, and applying a voltage between the first and second regions by the third region. A semiconductor device characterized by reducing the extension of a depletion layer from the first or second region to the channel due to the above, thereby reducing punch-through.

2. In the third region placed on at least one of the first and second regions on the substrate bulk side and the channel side, the impurity concentration on the substrate bulk side is higher than the impurity concentration on the channel side region. 2. The semiconductor according to claim 1, wherein the semiconductor is high.

3. The thickness of the third region on at least one of the first and second regions on the substrate bulk side is such that the third region is not applied or applied with a voltage between the first and second regions. 3. The semiconductor device according to claim 1, wherein the thickness of the depletion layer is equal to or greater than the thickness of the depletion layer formed in the region.

4. The impurity concentration of at least one of the first and second regions in the third region on the substrate side of the base is determined by the impurity concentration of any one of the first and second regions in direct contact with the third region. 4. The semiconductor device according to claim 1, wherein the concentration is equal to or lower than the concentration.

5. The semiconductor device according to claim 1, wherein an impurity concentration of the channel is equal to or less than 10 ¹⁷ cm ⁻³ .

6.請impurity concentration of the channel is equal to or is 1 0 ^lu cm- ³ or less 6. The semiconductor device according to any one of claims 1 to 5.

7. The semiconductor device according to claim 1, wherein an impurity concentration of the channel is less than or equal to 10 ¹⁵ cm ⁻³ .

8. The semiconductor device according to claim 1, wherein the impurity concentration of the channel is 10 ¹⁴ cm− ³ or less.

9. A region where a depletion layer is formed in the vicinity including an interface between at least one of the first and second regions and the third region and at least a part of a region where the channel is formed are in contact with each other. The semiconductor according to claim 1, wherein an extension surface continuous with a surface of the channel, and an interface between at least one of the first and second regions and the third region. 10. The semiconductor device according to claim 1, wherein the distance is 50 nm or less.

11. A feature characterized in that a distance between an extended surface continuous with the surface of the channel and an interface between at least one of the first and second regions and the interface of the third region is 2 O nm or less. Item 10. The semiconductor device according to any one of Items 1 to 10.

12. The distance characterized by the fact that a distance between an extension surface continuous with the surface of the channel and an interface between at least one of the first and second regions and the interface of the third region is 10 nm or less. Item 2. The semiconductor device according to any one of Items 1 to 11.

13. The distance between an extended surface continuous with the surface of the channel and an interface between at least one of the first and second regions and the interface of the third region is 5 nm or less. 13. The semiconductor device according to any one of items 1 to 12.

14. An extended surface continuous with the surface of the channel, and at least a part of an interface between the third region and at least one of the first and second regions intersects with each other. The semiconductor device according to any one of the preceding claims.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor device performs at least one of a field effect transistor operation and a bipolar transistor operation.

16. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is a MOS field-effect transistor.

17. The semiconductor device according to any one of claims 1 to 16, wherein the semiconductor device is a MES type or a junction field effect transistor.

18. The semiconductor device according to claim 1, wherein the semiconductor device has an SOI structure.

19. The semiconductor device according to any one of claims 1 to 18, wherein the semiconductor device has one or more channels.

20. The semiconductor device according to any one of claims 1 to 19, wherein the semiconductor device has one or more of the electrodes on the channel. The substrate or the channel is made of silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, indium antimony, gallium aluminum arsenide, gallium indium arsenide, or aluminum indium arsenide. 2. The semiconductor device according to item 1. 22. The semiconductor device according to claim 1, wherein the silicon is single-crystal silicon, polycrystalline silicon, or amorphous silicon.