WO1994018661A1

WO1994018661A1 - Method and apparatus for computer video display memory

Info

Publication number: WO1994018661A1
Application number: PCT/US1994/000778
Authority: WO
Inventors: James Cape; Brian Howard; Robert Bailey
Original assignee: Apple Computer, Inc.
Priority date: 1993-02-05
Filing date: 1994-01-24
Publication date: 1994-08-18
Also published as: AU6126494A

Abstract

An apparatus and method for efficiently and economically storing video data in a video random access memory used in a computer video graphics control and display system. Efficient and economical video data storage is achieved by selecting a video random access memory integrated circuit having data storage capacity substantially equal to the storage requirements of the associated computer video graphics control and display system.

Description

METHOD AND APPARATUS FOR COMPUTER VIDEO DISPLAY MEMORY

BACKGROUND OF THE INVENTION Field of the Invention This invention relates generally to computer video display memory systems, and in particular to computer video display memory systems having a resolution of 640 pixels wide by 480 pixels high as used in a Video Graphics Adapter ("VGA").

Description of the Related Technology Computers, especially personal computers have gained substantial popularity among individual users for both business and home use. Personal computers are now being utilized for jobs heretofore performed by mainframe computers and mini-computers. The rapidly growing popularity in the use of personal computers may, in part be attributed to the substantial improvement in its speed of operation, ease of use and sophistication in displaying information to the computer user.

Representing sophisticated information in a computer system requires presenting large amounts of data in an efficient and cost effective manner. Typically, this information is presented visually by means of a type of television screen called a cathode ray tube ("CRT"). The CRT of the computer system may be, for example, monochrome (single color) green or amber, or more recently, multiple colors using standard color television red-green-blue ("RGB") technology.

Color presentation of information gives the most effective and easily understood format for computer users. With the graphical user interface

("GUI") becoming more prevalent today, both display of multiple colors and the resolution or fineness of detail of the color display takes on added importance. Multiple Colors are derived on the face of the CRT by controlling the amount of red, green and blue that is electronically mixed thereon. The fineness of detail of the information is determined by the number of definable picture elements or "pixels". The larger the number of definable pixels available on a CRT screen, the greater the resolution and finer the detail of the picture resulting from the combination of the pixels.

A personal computer industry standard is Video Graphics Adapter ("VGA") which has a pixel matrix 640 pixels wide by 480 pixels high.

Therefore the VGA system has 307,200 discrete pixels that may be individually controlled as to color and intensity. The color of each pixel is determined by the electronic mixture of the red-green-blue signals and the intensity or "z- component" determines the brightness of the resulting RGB color mix.

Color video displays are analog systems using standard broadcasting system standards such as, for example, National Television Systems Committee ("NTSC"), Phase Alternating Line ("PAL") or Sequentiel Couleur avec Memoire ("SECAM"). NTSC is the standard most frequently used in the United States and Japan. All of the above broadcasting standards convey information using analog signals which have continuously variable values. In contrast, a computer system handles information using digital signals having only on and off values. Fortunately, a device called a Digital to Analog Converter ("DAC") may be used to convert binary digital signals to continuously variable analog signals. Thus, the analog values comprising the RGB signals may be defined using binary digital signals from the computer system. An eight bit digital binary value signal may define up to 256 different analog values from the output of an eight bit DAC. The computer system video controller may use three DACs in an RGB color system, each DAC supplying one of the RGB signals. The DACs may be configured for a greater or lesser number of bits, wherein the fewer the number of bits in the DAC, the fewer the available different analog values (colors). The number of bits used to define a pixel or bits per pixel ("bpp") may be, for example, 8, 16, 24 or 32 bits. The greater the bpp, however, the greater the size of digital memory requirements for video image storage in the computer system. Various techniques are used to reduce the required bpp size, such as, for example, color pallette look up tables which have predefined RGB color combinations that drive the RGB DACs.

In an RGB video system, video images must be constantly refreshed on the CRT display. The RGB signals used to refresh the video image are analog. Typically, video is refreshed at 60 times per second to reduce flicker and give a constant image to the computer user. The analog signals used to refresh the video display are from digital information stored in semiconductor random access memory ("RAM") and the digital information is converted by DACs to RGB analog signals.

There are three types of video memory access needed: (1) by the computer system for loading of image data, (2) by the video controller for video manipulation, and (3) by the display refresh circuits for feeding signal information to the video display. Refreshing the video display usually requires the most rapid and frequent number of accesses from the RAM. As an example, a 640 by 480 pixel video display having 8 bpp image and being refreshed at 60 times per second, will require a data rate of 18.432 megabytes per second from the RAM, used to store the video information, for display refresh. The above data rate is extremely hard to achieve from conventional dynamic RAM ("DRAM") even without considering the access needs of the computer system (1) and video controller (2) above. An industry solution to this problem is in making standard DRAM integrated circuits having dual access ports. These dual-ported RAMs have a second output path comprising a serial shift register and are referred hereinafter as a serial port. In addition, the high speed serial port output is completely separate from the usual random access read /write parallel port of a standard DRAM integrated circuit. Thus, the computer system central processing unit ("CPU") may independently access the RAM and not have to wait for the required display refresh actions. In addition, the serial port allows the video display to be continually updated independent of the computer system reading and writing data through the parallel port. This type of RAM shall be referred to hereinafter as Video RAM ("VRAM").

VRAMs are designed in standard sizes of 262,144 x 8 bits and 524,288 x 4 bits (2,097,152 bits total storage capacity). The number of bits required for a VGA 640 x 480 x 8 bpp is 2,457,600 bits. Thus, two standard VRAMS are needed to store the video information required for a total of 4,194,304 bits of storage capacity. Unfortunately, 1,736,704 bits (4,194,304 - 2,457,600) are never used, thus over 40 percent of the VRAM is wasted. In addition to wasting almost half of the VRAM capacity, a corresponding amount of power and integrated circuit chip size is similarly wasted. What is needed is more efficient utilization of VRAM capacity for use with VGA systems.

SUMMARY OF THE INVENTION In contrast to prior VRAM designs, the system and method of the present invention more efficiently and economically stores digital video information for VGA systems. The present invention utilizes a memory storage configuration of 327,680 x 8 bits for a total of 2,621,440 bits of storage. The present invention is configured to store the VGA information with much less wasted space. Thus only 163,840 bits (2,621,440 - 2,457,600) or 6 percent are not utilized in the system and method of the present invention. The present invention may utilize standard VRAM fabrication technology in fabricating a more efficiently sized VRAM for computer systems using VGA systems. RAM is typically made in sections, i.e., for example, quarters. Therefore a RAM chip design may be easily expanded or contracted by adding or subtracting sections, respectively. In addition, the present invention may be fabricated using 327,680 x 16 bit, 327,680 x 24 bit and 327,680 x 32 bit configurations. These configurations may be derived from a plurality of 327,680 x 8 bit VRAM integrated circuit chips or on one high capacity VRAM integrated circuit chip. These expanded capacity VRAM configurations may be utilized to support increased RGB color selection possibilities.

An object of the present invention is lower system cost by utilizing more efficiently configured VRAMs in VGA controller systems.

A further object of the present invention is using a minimum number of VRAMs resulting in smaller VGA controller printed circuit board requirements.

Still a further object of the present invention is lower power requirements allowing longer battery life with increased system reliability and reduced cooling requirements. Yet a further object of the present invention is using fewer address and control signals resulting in less connection requirements and smaller VGA controller packaging.

Another object of the present invention is decreased loading on computer system data, address and control buses. Other and further objects, features and advantages will be apparent from the following description of a presently preferred embodiment of the invention, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram of a prior art eight bit video display memory and controller;

Fig. 2 is a schematic block diagram of the preferred embodiment of the present invention illustrating an eight bit video display memory and controller; Fig. 3 is a schematic block diagram of a prior art sixteen bit video display memory and controller;

Fig. 4 is a schematic block diagram of the preferred embodiment of the present invention illustrating a sixteen bit video display memory and controller; Fig. 5 is a schematic block diagram of a prior art twenty-four bit video display memory and controller; Fig. 6 is a schematic block diagram of the preferred embodiment of the present invention illustrating a twenty-four bit video display memory and controller; and

Figs. 7a, 7b and 7c are schematic memory maps of VRAM storage capacity utilization of Figs. 1-6 above.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A better understanding of the present invention will be obtained when the following detailed description is read with reference to the drawings wherein common elements are designated with like numbers or letters and similar elements are designated with like numbers or letters followed by a lower case letter. The method and apparatus of the present invention teaches a more efficient, cost effective and lower power video memory system for VGA systems.

Referring now to Figs. 1, 3 and 5, illustrated as schematic block diagrams are prior art video controllers referenced generally by the letter C. A video controller generally is comprised of a video RAM controller 20, video random access memory (VRAM) 22, digital to analog converter (DAC) (not illustrated), and signal, address and control buses. These buses are video data to DAC bus 30, processor data bus 32, processor address bus 34, processor control bus 36, and controller 20 control bus 38.

The video RAM controller 20 receives address information on address bus 34 from the computer system central processing unit ("CPU") (not illustrated), and control information on control bus 36. Video data is transferred directly from the CPU to the VRAM 22 parallel port over data bus 32. The address information for reading from or writing to VRAM 22 is obtained from control bus 38. Video data is output to the video DAC over bus 30 and may use, for example, a serial means of data transfer, i.e. serial port.

A VGA system utilizes a pixel matrix comprising 640 pixels wide by 480 pixels high. The gray scale resolution or colors available in this pixel array are determined by the number of binary bits of data that comprise the information sent to the DAC (not illustrated). This resolution is defined as the number of bits per pixel (bpp) and may be 8, 16, 24 or 32 bits. The DAC output drives the electron gun(s) in the video monitor CRT as is well known in the art of video and television monitors. A plurality of DACs may be used to drive the red- green-blue guns of an RGB video monitor for multiple color display.

For an 8 bpp resolution VGA system (640 x 480), the number of bits of VRAM storage required is 2,457,600 bits (640 x 480 x 8). This storage capacity may be implemented by using two 524,288 x 4 bit VRAMs 22 (Fig. 1). Two 4 bit wide VRAMS 22 are necessary because of the requirement of an 8 bit data word to the DAC. Assuming an 8 bit byte as the data word size required by the DAC, 307,200 addresses are required to access all of the 8 bit bytes.

Referring now to Fig. 7a, the required 307,200 VGA addresses 50 are illustrated as 0000 through 4AFFF (Hexadecimal). The addresses of VRAM 22 having 524,288 addresses 52 are illustrated as 0000 through 7FFFF (Hexadecimal). The VRAM 22 storage capacity 56 at addresses from 4AFFF to 7FFFF are wasted when using a VGA system. This not so insignificant waste of VRAM results in increased integrated circuit chip size, power requirements, costs and printed circuit board space.

Referring now to Figs. 2, 4 and 6, illustrated as schematic block diagrams are embodiments of the present invention referenced generally by the letter S. The VGA video controller is comprised of the video RAM controller 20 and VRAM 26 having a parallel port 40 and a serial port 42. The parallel port 40 is adapted for connection to the computer system data bus 32 and the serial port

42 connects to and outputs digital video data to DAC (not illustrated) over bus 30. Serial port 42 can continuously update the DAC independently of the computer system reading and writing video data through the parallel port 40. The VRAM 26 may be a VRAM having 327,680 addressable 8 bit bytes (Fig. 2). VRAM 26 may be paired (Fig. 4) or tripled (Fig. 6) for 16 or 24 bits words respectively.

Referring to Fig. 7a, the 327,680 VRAM 26 addresses 54 are illustrated as 0000 through 4FFFF. As is clearly illustrated, VRAM 26 is more efficiently and effectively utilized by a VGA system for storage of Video information with a minimum of wasted storage space 58. Figs. 7b and 7c illustrate similar address space utilization for 16 and 24 bit DAC data words, respectively.

The VRAM 26 may be fabricated by utilizing standard static RAM ("SRAM") or DRAM technologies as is well known in the art of semiconductor memories. Efficient and economical utilization of VRAM integrated circuits may be obtained by judicious selection of the address configuration of the VRAM during fabrication thereof. Other pixel capacity video systems may also benefit from the method and apparatus of the present invention by selection of economical and efficient address ranges in the manufacture of VRAM integrated circuits. The system and method of the present invention, therefore, is well adapted to carry out the objects and attain the ends and advantages mentioned as well as others inherent therein. While a presently preferred embodiment of the invention has been given for purposes of disclosure, numerous changes in the details of construction, interconnection and arrangement of parts will readily suggest themselves to those skilled in the art and which are encompassed within the spirit of the invention and the scope of the appended claims.

Claims

CLAIMS Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:

1. A computer video graphics control and display system that efficiently stores video data in a video random access memory, comprising:

(a) a video random access memory having data storage capacity substantially equal to the storage requirements of the computer video graphics control and display system;

(b) a video random access memory controller, the controller controlling the memory; and

(c) a video digital to analog converter, the converter adapted to drive a video monitor.

2. The computer video graphics control and display system of Claim 1, wherein the memory is adapted for connection to a computer system data bus.

3. The computer video graphics control and display system of Claim 1, wherein the memory comprises a serial data port for outputing video data to the converter and a parallel port adapted for connection to a computer system data bus, wherein the serial port may continually update the video converter independently of the computer system reading and writing video data through the parallel port.

4. The computer video graphics control and display system of Claim 1, wherein the memory comprises a plurality of video random access memory integrated circuits.

5. The computer video graphics control and display system of Claim

1, wherein the system is adapted for 640 pixels by 480 pixels presentation on a video display monitor.

6. The computer video graphics control and display system of Claim 5, wherein the memory has 327,680 addressable 8 bit bytes of data storage capacity.

7. The computer video graphics control and display system of Claim

5, wherein the memory has 327,680 addressable 16 bit words of data storage capacity.

8. The computer video graphics control and display system of Claim 5, wherein the memory has 327,680 addressable 24 bit words of data storage capacity.

9. The computer video graphics control and display system of Claim 1, wherein the controller is adapted for connection to address and control buses of a computer system.

10. The computer video graphics control and display system of Claim 1, wherein the converter is a plurality of video digital to analog converters for outputting red-green-blue color signals to a color video display.

11. A computer video graphics control and display system that efficiently stores video data in a video random access memory, comprising:

(b) the video memory having a serial data port and a parallel port, the parallel port adapted for connection to a computer system data bus;

(c) a video random access memory controller having address and control buses adapted for connection to computer system address and control buses, respectively, the controller controlling the memory; and

(d) a video digital to analog converter having a digital input and an analog output, the converter input connected to the memory serial port and the converter output adapted to drive a video monitor.

12. A method for efficiently storing video data in a video random access memory used in a computer video graphics control and display system, comprising the steps of: (a) selecting stored video data from a video random access memory having data storage capacity substantially equal to the storage requirements of the computer video graphics control and display system; (b) outputing the stored video data to a digital to analog converter; and (c) outputing the converted to analog video data to a video monitor.

13. The method of claim 12, including the step of accessing the memory through a computer system data bus while the memory outputs the stored video data to the converter.

14. The method of claim 12 wherein 327,680 words of video data are stored in the memory.