WO1994001841A1 - Power conservation method and apparatus for a data communication receiver - Google Patents

Abstract

A data communication receiver (106) comprises a receiver (804) for receiving transmitted coded message signals comprising at least one block of up to N addresses of M bits interleaved to degree N, where M and N are integer numbers. A battery saver circuit (848) supplies power to the receiver (804). A signal recovery circuit (808, 810, 812, 814, 816), coupled to the receiver (804), recovers the received coded message signals to generate up to M N-bit data streams. An address correlator (830), coupled to the signal recovery circuit (808, 810, 812, 814, 816), correlates at least a portion of the M N-bit data streams with a corresponding portion of a predetermined M-bit code word to derive up to N error counts corresponding to the up to N addresses. The battery saving circuit (848) is responsive to the address correlator (830) and suspends the supply of power to the receiver (804) when each of the N error counts exceeds a predetermined error count.

Description

POWER CONSERVATION METHOD AND APPARATUS FOR A DATA COMMUNICATION RECEIVER

This application is a continuation-in-part application of Patent Application Serial No. 07/891,363, filed May 29, 1992 by Schwendeman et al. , entitled "Data Communication Receiver having Variable Length Message Carry-On".

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION:

The present invention relates generally to the field of power conservation in a data communication receiver, and more particularly to a method and apparatus for conserving power in a data communication receiver receiving block interleaved addresses .

DESCRIPTION OF THE PRIOR ART:

Paging receivers have typically employed battery saving techniques to improve battery life when used with limited energy content batteries . Examples of such techniques utilized include code dependent and non-code dependent battery saving techniques . One example of a code dependent battery saving technique utilized was the assignment of paging receivers to specific frames, such as is commonplace in the POCSAG signaling protocol . Since eight assignable frames were provided in the POCSAG signaling format, a battery improvement factor of roughly eight to one was obtained. Another example of a code dependent battery saving technique was to group addresses before the corresponding messages. This allowed a paging receiver which did not detect its address in the address grouping, to battery save during the message portion of the transmission.

One example of a non-code dependent battery saving technique was a signal absence detector which controlled a battery saver circuit which intermittently provided a supply voltage, and which responded to a processed signal which was not of a predetermined character to render the battery saver circuit inoperative. Another non-code dependent battery saving technique employed was to transmit the receiver identification code digits in an order of increasing significance which significantly lessened the receiver power consumption, and thereby prolonged paging receiver battery life. Another non-code dependent battery saving technique employed was to receive a first predetermined number of bits less than the address length and compare the received first predetermined number of bits with the corresponding address bits . When the number of errors detected between the received bits and the address bits exceeded a predetermined error number, address decoding was terminated.

While battery life improvements were provided by the various battery saving techniques, reliable address decoding was not always obtained, especially during signal fading conditions, or when burst errors were present in the address transmission, thus disrupting the battery saving performance provided by such code and non-code dependent battery saving techniques. There is a need to provide improved battery life in a data communication receiver which operates from a limited energy capacity battery, and to also provide improved reliability during address decoding.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the present invention, a data communication receiver comprises a receiver for receiving transmitted coded message signals comprising at least one block of up to N addresses of M bits interleaved to degree N, where M and N are integer numbers . A battery saver circuit supplies power to the receiver. A de-interleaver, coupled to the receiver, de- interleaves the received coded message signals to generate an M by N-bit data stream. An address correlator, coupled to the de-interleaver, correlates sequentially the M by N- bit data stream with a predetermined M-bit code word to derive N error counts corresponding to the N addresses. The battery saving circuit is responsive to the address and suspends the supply of power to the receiver when each of the N error counts exceeds a predetermined error count . In accordance with a second aspect of the present invention, a communication receiver comprises a receiver for receiving transmitted coded message signals comprising a plurality of message streams interleaved to degree K, the message streams comprising at least one block of up to N addresses each of M bits interleaved to degree N, where K, M and N are integer numbers . A battery saver circuit supplies power to the receiver. A data selector, coupled to the receiver, selects one of the K interleaved message streams. A de-interleaver, coupled to the data selector, de-interleaves the received coded message signals to generate an M by N-bit data stream. An address correlator, coupled to the de-interleaver, correlates sequentially the M by N-bit data stream with a predetermined M-bit code word to derive N error counts corresponding to the N addresses. The battery saving circuit is responsive to the address and suspends the supply of power to the receiver when each of the N error counts exceeds a predetermined error count .

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical block diagram of a data transmission system in accordance with the preferred embodiment of the present invention. FIG. 2 is an electrical block diagram of a terminal for processing and transmitting message information in accordance with the preferred embodiment of the present invention.

FIGS. 3-5 are timing diagrams illustrating the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention. FIGS. 6 and 7 are timing diagrams illustrating the synchronization signals utilized in accordance with the preferred embodiment of the present invention.

FIG. 8 is an electrical block diagram of a data communication receiver in accordance with the preferred embodiment of the present invention.

FIG. 9 is an electrical block diagram of a threshold level extraction circuit utilized in the data communication receiver of FIG. 8. FIG. 10 is an electrical block diagram of a 4-level decoder utilized in the data communication receiver of FIG. 8.

FIG. 11 is an electrical block diagram of a symbol synchronizer utilized in the data communication receiver of FIG. 8.

FIG. 12 is an electrical block diagram of a 4-level to binary converter utilized in the data communication receiver of FIG. 8.

FIG. 13 is an electrical block diagram of a synchronization correlator utilized in the data communication receiver of FIG. 8.

FIG. 14 is an electrical block diagram of a phase timing generator utilized in the data communication receiver of FIG. 8. FIG. 15 is a flow chart illustrating the synchronization correlation sequence in accordance with the preferred embodiment of the present invention.

FIG. 16 is a timing diagram illustrating the organization of the transmission frame utilized in accordance with the preferred embodiment of the present invention .

FIG. 17 is a timing diagram illustrating the construction of a control word utilized in accordance with the preferred embodiment of the present invention. FIG. 18 is an electrical block diagram of a frame formatter utilized in the terminal of FIG. 2.

FIGS. 19-21 are electrical block diagrams illustrating the operation of the data concentrator / distributor in accordance with the preferred embodiment of the present invention .

FIGS. 22-24 are timing diagrams illustrating transmission phase and bit interleaving of the message transmissions in accordance with the preferred embodiment of the present invention.

FIGS. 25-27 are timing diagrams illustrating the data communication receiver message bit sampling in accordance with the preferred embodiment of the present invention. FIG. 28 is a timing diagram illustrating the address and data interleaving format in accordance with the preferred embodiment of the present invention.

FIG. 29 is an electrical block diagram of a partial interleaved address correlator in accordance with the preferred embodiment of the present invention.

FIG. 30 is a timing diagram illustrating the battery life improvements obtained with the battery saver circuit operation in accordance with the preferred embodiment of the present invention. FIG. 31 is a flow chart illustrating the battery saver circuit operation in accordance with the preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is an electrical block diagram of a data transmission system 100, such as a paging system, in accordance with the preferred embodiment of the present invention In such a data transmission system 100, messages originating either from a phone, as in a system providing numeric data transmission, or from a message entry device, such as an alphanumeric data terminal, are routed through the public switched telephone network (PSTN) to a paging terminal 102 which processes the numeric or alphanumeric message information for transmission by one or more transmitters 104 provided within the system. When multiple transmitters are utilized, the transmitters 104 preferably simulcast transmit the message information to data communication receivers 106. Processing of the numeric and alphanumeric information by the paging terminal 102, and the protocol utilized for the transmission of the messages is described below.

FIG. 2 is an electrical block diagram of the paging terminal 102 utilized for processing and controlling the transmission of the message information in accordance with the preferred embodiment of the present invention. Short messages, such as tone-only and numeric messages which can be readily entered using a Touch-Tone telephone are coupled to the paging terminal 102 through a telephone interface 202 in a manner well known in the art. Longer messages, such as alphanumeric messages which require the use of a data entry device are coupled to the paging terminal 102 through a modem 206 using any of a number of well known modem transmission protocols. When a call to place a message is received, a controller 204 handles the processing of the message. The controller 204 is preferably a microcomputer, such as an MC68000 or equivalent, which is manufactured by Motorola Inc., and which runs various pre-programmed routines for controlling such terminal operations as voice prompts to direct the caller to enter the message, or the handshaking protocol to enable reception of messages from a data entry device. When a call is received, the controller 204 references information stored in the subscriber database 208 to determine how the message being received is to be processed. The subscriber data base 208 includes, but is not limited to such information as addresses assigned to the data communication receiver, message type associated with the address, and information related to the status of the data communication receiver, such as active or inactive for failure to pay the bill. A data entry terminal 240 is provided which couples to the controller 204, and which is used for such purposes as entry, updating and deleting of information stored in the subscriber data base 208, for monitoring system performance, and for obtaining such information as billing information.

The subscriber database 208 also includes such information as to what transmission frame and to what transmission phase the data communication receiver is assigned, as will be described in further detail below. The received message is stored in an active page file 210 which stores the messages in queues according to the transmission phase assigned to the data communication receiver. In the preferred embodiment of the present invention, four phase queues are provided in the active page file 210. The active page file 210 is preferably a dual port, first in first out random access memory, although it will be appreciated that other random access memory devices, such as hard disk drives, can be utilized as well. Periodically the message information stored in each of the phase queues is recovered from the active page file 210 under control of controller 204 using timing information such as provided by a real time clock 214, or other suitable timing source. The recovered message information from each phase queue is sorted by frame number and is then organized by address, message information, and any other information required for transmission, and then batched into frames based upon message size by frame batching controller 212. The batched frame information for each phase queue is coupled to frame message buffers 216 which temporarily store the batched frame information until a time for further processing and transmission. Frames are batched in numeric sequence, so that while a current frame is being transmitted, the next frame to be transmitted is in the frame message buffer 216, and the next frame thereafter is being retrieved and batched. At the appropriate time, the batched frame information stored in the frame message buffer 216 is transferred to the frame encoder 218, again maintaining the phase queue relationship. The frame encoder 218 encodes the address and message information into address and message code words required for transmission, as will be described below. The encoded address and message code words are ordered into blocks and then coupled to a block interleaver 220 which interleaves preferably eight code words at a time for transmission in a manner well known in the art. The interleaved code words from each block interleaver 220 are then serially transferred to a phase multiplexer 221, which multiplexes the message information on a bit by bit basis into a serial data stream by transmission phase. The controller 204 next enables a frame sync generator 222 which generates the synchronization code which is transmitted at the start of each frame transmission. The synchronization code is multiplexed with address and message information under the control of controller 204 by serial data splicer 224, and generates therefrom a message stream which is properly formatted for transmission. The message stream is next coupled to a transmitter controller 226, which under the control of controller 204 transmits the message stream over a distribution channel 228. The distribution channel 228 may be any of a number of well known distribution channel types, such as wire line, an RF or microwave distribution channel, or a satellite distribution link. The distributed message stream is transferred to one or more transmitter stations 104, depending upon the size of the communication system. The message stream is first transferred into a dual port buffer 230 which temporarily stores the message stream prior to transmission. At an appropriate time determined by timing and control circuit 232, the message stream is recovered from the dual port buffer 230 and coupled to the input of preferably a 4-level FSK modulator 234. The modulated message stream is then coupled to the transmitter 236 for transmission via antenna 238.

FIGS. 3, 4 and 5 are timing diagrams illustrating the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention. As shown in FIG. 3, the signaling protocol enables message transmission to data communication receivers, such as pagers, assigned to one or more of 128 frames which are labeled frame 0 through frame 127. It then will be appreciated that the actual number of frames provided within the signaling protocol can be greater or less than described above. The greater the number of frames utilized, the greater the battery life that may be provided to the data communication receivers operating within the system. The fewer the number of frames utilized, the more often messages can be queued and delivered to the data communication receivers assigned to any particular frame, thereby reducing the latency, or time required to deliver messages .

As shown in FIG. 4, the frames comprise a synchronization code (sync) followed preferably by eleven blocks of message information which are labeled block 0 through block 10. As shown in FIG. 5. each block of message information comprises preferably eight address, control or data code words which are labeled word 0 through word 7 for each phase. Consequently, each phase in a frame allows the transmission of up to eighty-eight address, control and data code words. The address, control and data code words are preferably 31,21 BCH code words with an added thirty-second even parity bit which provides an extra bit of distance to the code word set. It will be appreciated that other code words, such as a 23,12 Golay code word could be utilized as well. Unlike the well known POCSAG signaling protocol which provides address and data code words which utilize the first code word bit to define the code word type, as either address or data, no such distinction is provided for the address and data code words in the signaling protocol utilized with the preferred embodiment of the present invention. Rather, address and data code words are defined by their position within the individual frames.

FIGS. 6 and 7 are timing diagrams illustrating the synchronization code utilized in accordance with the preferred embodiment of the present invention. In particular, as shown in FIG. 6, the synchronization code comprises preferably three parts, a first synchronization code (sync 1) , a frame information code word (frame info) and a second synchronization code (sync 2) . As shown in FIG. 7, the first synchronization code comprises first and third portions, labeled bit sync 1 and BS1, which are alternating 1,0 bit patterns which provides bit synchronization, and second and fourth portions, labeled "A" and its complement "A bar", which provide frame synchronization. The second and fourth portions are preferably single 32,21 BCH code words which are predefined to provide high code word correlation reliability, and which are also used to indicate the data bit rate at which addresses and messages are transmitted. The table below defines the data bit rates which are used in conjunction with the signaling protocol.

Bit Rate "A" Value 1600 bps Al and Al bar

3200 bps A2 and A2 bar

6400 bps A3 and A3 bar

Not defined A4 and A4 bar

As shown in the table above, three data bit rates are predefined for address and message transmission, although it will be appreciated that more or less data bit rates can be predefined as well, depending upon the system requirements. A fourth "A" value is also predefined for future use.

The frame information code word is preferably a single 32,21 BCH code word which includes within the data portion a predetermined number of bits reserved to identify the frame number, such as 7 bits encoded to define frame number 0 to frame number 127.

The structure of the second synchronization code is preferably similar to that of the first synchronization code described above. However, unlike the first synchronization code which is preferably transmitted at a fixed data symbol rate, such as 1600 bps (bits per second) , the second synchronization code is transmitted at the data symbol rate at which the address and messages are to be transmitted in any given frame. Consequently, the second synchronization code allows the data communication receiver to obtain "fine" bit and frame synchronization at the frame transmission data bit rate.

In summary the signaling protocol utilized with the preferred embodiment of the present invention comprises 128 frames which include a predetermined synchronization code followed by eleven data blocks which comprise eight address, control or message code words per phase. The synchronization code enables identification of the data transmission rate, and insures synchronization by the data communication receiver with the data code words transmitted at the various transmission rates .

FIG. 8 is an electrical block diagram of the data communication receiver 106 in accordance with the preferred embodiment of the present invention. The heart of the data communication receiver 106 is a controller 816, which is preferably implemented using an MC68HC05HC11 microcomputer, such as manufactured by Motorola, Inc. The microcomputer controller, hereinafter call the controller 816, receives and processes inputs from a number of peripheral circuits, as shown in FIG. 8, and controls the operation and interaction of the peripheral circuits using software subroutines. The use of a microcomputer controller for processing and control functions is well known to one of ordinary skill in the art . The data communication receiver 106 is capable of receiving address, control and message information, hereafter called "data" which is modulated using preferably 2-level and 4-level frequency modulation techniques. The transmitted data is intercepted by an antenna 802 which couples to the input of a receiver section 804. Receiver section 804 processes the received data in a manner well known in the art, providing at the output an analog -level recovered data signal, hereafter called a recovered data signal. The recovered data signal is coupled to one input of a threshold level extraction circuit 808, and to an input of a 4-level decoder 810. The threshold level extraction circuit 808 is best understood by referring to FIG. 9, and as shown comprises two clocked level detector circuits 902, 904 which have as inputs the recovered data signal. Level detector 902 detects the peak signal amplitude value and provides a high peak threshold signal which is proportional to the detected peak signal amplitude value, while level detector 904 detects the valley signal amplitude value and provides a valley threshold signal which is proportional to the detected valley signal amplitude value of the recovered data signal. The level detector 902, 904 signal outputs are coupled to terminals of resistors 906, 912, respectively. The opposite resistor terminals 906, 912 provide the high threshold output signal (Hi) , and the low threshold output signal (Lo) , respectively. The opposite resistor terminals 906, 912 are also coupled to terminals of resistors 908, 910, respectively. The opposite resistor 908, 910 terminals are coupled together to form a resistive divider which provides an average threshold output signal (Avg) which is proportional to the average value of the recovered data signal. Resistors 906, 912 have resistor values preferably of 1R, while resistors 908, 910 have resistor values preferably of 2R, realizing threshold output signal values of 17%, 50% and 83%, and which are utilized to enable decoding the 4-level data signals as will be described below.

When power is initially applied to the receiver portion, as when the data communication receiver is first turned on, a clock rate selector 914 is preset through a control input (center sample) to select a 128X clock, i.e. a clock having a frequency equivalent to 128 times the slowest data bit rate, which as described above is 1600 bps. The 128X clock is generated by 128X clock generator 844, as shown in FIG. 8, which is preferably a crystal controlled oscillator operating at 204.8 KHz (kilohertz) . The output of the 128X clock generator 844 couples to an input of frequency divider 846 which divides the output frequency by two to generate a 64X clock at 102.4 KHz. Returning to FIG. 9, the 128X clock allows the level detectors 902, 904 to asynchronously detect in a very short period of time the peak and valley signal amplitude values, and to therefore generate the low (Lo) , average (Avg) and high (Hi) threshold output signal values required for modulation decoding. After symbol synchronization is achieved with the synchronization signal, as will be described below, the controller 816 generates a second control signal (Center Sample) to enable selection of a IX symbol clock which is generated by symbol synchronizer 812 as shown in FIG. 8.

Returning to FIG. 8, the 4-level decoder 810 operation is best understood by referring to FIG. 10. As shown, the 4-level decoder 810 comprises three voltage comparators

1010, 1020, 1030 and a symbol decoder 1040. The recovered data signal couples to an input of the three comparators 1010, 1020, 1030. The high threshold output signal (Hi) couples to the second input of comparator 1010, the average threshold output signal (Avg) couples to the second input of comparator 1020, and the low threshold output signal (Lo) couples to the second input of comparator 1030. The outputs of the three comparators 1010, 1020, 1030 couple to inputs of symbol decoder 1040. The symbol decoder 1040 decodes the inputs according to the table provided below.

Threshold Output

Hi Avg Lo MSB LSB

^RCin < ^RCin < ^RCin < 0 0 ^RCin < ^RCin < ^RCin > 0 1

^RCin < ^RCin > ^RCin > 1 1

^RCin ^{> RC}in > ^RCin > 1 0

As shown in the table above, when the recovered data signal (RC*j__n*- is less than all three threshold values, the symbol generated is 00 (MSB = 0, LSB = 0) . Thereafter, as each of the three threshold values is exceeded, a different symbol is generated, as shown in the table above.

The MSB output from the 4-level decoder 810 is coupled to an input of the symbol synchronizer 812 and provides a recovered data input generated by detecting the zero crossings in the 4-level recovered data signal. The positive level of the recovered data input represents the two positive deviation excursions of the analog 4-level recovered data signal above the average threshold output signal, and the negative level represents the two negative deviation excursions of the analog 4-level recovered data signal below the average threshold output signal. The operation of the symbol synchronizer 812 is best understood by referring to FIG. 11. The 64X clock at 102.4 KHz which is generated by frequency divider 846, is coupled to an input of a 32X rate selector 1120. The 32X rate selector 1120 is preferably a divider which provides selective division by 1 or 2 to generate a sample clock which is thirty-two times the symbol transmission rate. A control signal (1600/3200) is coupled to a second input of the 32X rate selector 1120, and is used to select the sample clock rate for symbol transmission rates of 1600 and 3200 symbols per second. The selected sample clock is coupled to an input of 32X data oversampler 1110 which samples the recovered data signal (MSB) at thirty-two samples per symbol. The symbol samples are coupled to an input of a data edge detector 1130 which generates an output pulse when a symbol edge is detected. The sample clock is also coupled to an input of a divide-by-16/32 circuit 1140 which is utilized to generate IX and 2X symbol clocks synchronized to the recovered data signal. The divided-by-16/32 circuit 1140 is preferably an up/down counter. When the data edge detector 1130 detects a symbol edge, a pulse is generated which is gated by AND gate 1150 with the current count of divide-by-16/32 circuit 1140. Concurrently, a pulse is generated by the data edge detector 1130 which is also coupled to an input of the divide-by-16/32 circuit 1140. When the pulse coupled to the input of AND gate 1150 arrives before the generation of a count of thirty-two by the divide-by-16/32 circuit 1140, the output generated by AND gate 1150 causes the count of divide-by-16/32 circuit 1140 to be advanced by one count in response to the pulse which is coupled to the input of divide-by-16/32 circuit 1140 from the data edge detector 1130, and when the pulse coupled to the input of AND gate 1150 arrives after the generation of a count of thirty-two by the divide-by-16/32 circuit 1140, the output generated by AND gate 1150 causes the count of divide-by-16/32 circuit 1140 to be retarded by one count in response to the pulse which is coupled to the input of divide-by-16/32 circuit 1140 from the data edge detector 1130, thereby enabling the synchronization of the IX and 2X symbol clocks with the recovered data signal. The symbol clock rates generated are best understood from the table below.

As shown in the table above, the IX and 2X symbol clocks are generated 1600, 3200 and 6400 bits per second and are synchronized with the recovered data signal.

The 4-level binary converter 814 is best understood by referring to FIG. 12. The IX symbol clock is coupled to a first clock input of a clock rate selector 1210. A 2X symbol clock also couples to a second clock input of the clock rate selector 1210. The symbol output signals (MSB, LSB) are coupled to inputs of an input data selector 1230. A selector signal (2L/4L) is coupled to a selector input of the clock rate selector 1210 and the selector input of the input data selector 1230, and provides control of the conversion of the symbol output signals as either 2-level FSK data, or 4-level FSK data. When the 2-level FSK data conversion (2L) is selected, only the MSB output is selected which is coupled to the input of a parallel to serial converter 1220. The IX clock input is selected by clock rate selector 1210 which results in a single bit binary data stream to be generated at the output of the parallel to serial converter 1220. When the 4-level FSK data conversion (4L) is selected, both the LSB and MSB outputs are selected which are coupled to the inputs of the parallel to serial converter 1220. The 2X clock input is selected by clock rate selector 1210 which results in a serial two bit binary data stream to be generated at 2X the symbol rate, which is provided at the output of the parallel to serial converter 1220. Returning to FIG. 8, the serial binary data stream generated by the 4-level to binary converter 814 is coupled to inputs of a synchronization word correlator 818 and a demultiplexer 820. The synchronization word correlator is best understood with reference to FIG. 13. Predetermined "A" word synchronization patterns are recovered by the controller 816 from a code memory 822 and are coupled to an "A" word correlator 1310. When the synchronization pattern received matches one of the predetermined "A" word synchronization patterns within an acceptable margin of error, an "A" or "A-bar" output is generated and is coupled to controller 816. The particular "A" or "A-bar" word synchronization pattern correlated provides frame synchronization to the start of the frame ID word, and also defines the data bit rate of the message to follow, as was previously described.

The serial binary data stream is also coupled to an input of the frame word decoder 1320 which decodes the frame word and provides an indication of the frame number currently being received by the controller 816. During sync acquisition, such as following initial receiver turn- on, power is supplied to the receiver portion by battery saver circuit 848, shown in FIG. 8, which enabled the reception of the "A" synchronization word, as described above, and which continues to be supplied to enable processing of the remainder of the synchronization code. The controller 816 compares the frame number currently being received with a list of assigned frame numbers stored in code memory 822. Should the currently received frame number differ from an assigned frame numbers, the controller 816 generates a battery saving signal which is coupled to an input of battery saver circuit 848, suspending the supply of power to the receiver portion. The supply of power will be suspended until the next frame assigned to the receiver, at which time a battery saver signal is generated by the controller 816 which is coupled to the battery saving circuit 848 to enable the supply of power to the receiver portion to enable reception of the assigned frame. Returning to the operation of the synchronization correlator shown in FIG. 13, a predetermined "C" word synchronization pattern is recovered by the controller 816 ^■ from a code memory 822 and is coupled to a "C" word correlator 1330. When the synchronization pattern received matches the predetermined "C" word synchronization pattern with an acceptable margin of error, a "C" or "C-bar" output is generated which is coupled to controller 816. The particular "C" or "C-bar" synchronization word correlated provides "fine" frame synchronization to the start of the data portion of the frame.

Returning to FIG. 8, the start of the actual data portion is established by the controller 816 generating a block start signal (Blk Start) which is coupled to inputs of a word de-interleaver 824 and a data recovery timing circuit 826. The data recovery timing circuit 826 is best understood by referring to FIG. 14. A control signal (2L / 4L) is coupled to an input of clock rate selector 1410 which selects either IX or 2X symbol clock inputs. The selected symbol clock is coupled to the input of a phase generator 1430 which is preferably a clocked ring counter which is clocked to generate four phase output signals (01- 04) . A block start signal is also coupled to an input of the phase generator 1430, and is used to hold the ring counter in a predetermined phase until the actual decoding of the message information is to begin. When the block start signal releases the phase generator 1430, the phase generator 1430 begins generating clocked phase signals which are synchronized with the incoming message symbols . Referring back to FIG. 8, the clocked phase signal outputs are coupled to inputs of a phase selector 828. During operation, the controller 816 recovers from the code memory 822, the transmission phase number to which the data communication receiver is assigned. The phase number is transferred to the phase select output (0 Select) of the controller 816 and is coupled to an input of phase selector 828. A phase clock, corresponding to the transmission phase assigned, is provided at the output of the phase selector 828 and is coupled to clock inputs of the demultiplexer 820, block de-interleaver 824, and address and data decoders 830 and 832, respectively. The demultiplexer 820 is used to select the binary bits associated with the assigned transmission phase which are then coupled to the input of block de-interleaver 824, and clocked into the de-interleaver array on each corresponding phase clock. The de-interleaver array is an 8x32 bit array which de-interleaves eight interleaved address, control or message code words, corresponding to one transmission block. The de-interleaved address code words are coupled to the input of address correlator 830. The controller 816 recovers the address patterns assigned to the data communication receiver, and couples the patterns to a second input of the address correlator. When any of the de-interleaved address code words matches any of the address patterns assigned to the data communication receiver within an acceptable margin of error, the message information associated with the address is then decoded by the data decoder 832 and stored in a message memory 850 in a manner well known to one of ordinary skill in the art. Following the storage of the message information, a sensible alert signal is generated by the controller 816. The sensible alert signal is preferably an audible alert signal, although it will be appreciated that other sensible alert signals, such as tactile alert signals, and visual alert signals can be generated as well. The audible alert signal is coupled by the controller 816 to an alert driver 834 which is used to drive an audible alerting device, such as a speaker or a transducer 836. The user can override the alert signal generation through the use of user input controls 838 in a manner well known in the art.

Following the detection of an address associated with the data communication receiver, the message information is coupled to the input of data decoder 832 which decodes the encoded message information into preferably a BCD or ASCII format suitable for storage and subsequent display. The stored message information can be recalled by the user using the user input controls 838 whereupon the controller 816 recovers the message information from memory, and provides the message information to a display driver 840 for presentation on a display 842, such as an LCD display.

FIG. 15 is a flow chart describing the operation of the data communication receiver in accordance with the preferred embodiment of the present invention. At step 1502, when the data communication receiver is turned on, the controller operation is initialized, at step 1504. Power is periodically applied to the receiver portion to enable receiving information present on the assigned RF channel. When data is not detected on the channel in a predetermined time period, battery saver operation is resumed, at step 1508. When data is detected on the channel, at step 1506, the synchronization word correlator begins searching for bit synchronization at step 1510. When bit synchronization is obtained, at step 1510, the "A" word correlation begins at step 1512. When the non- complemented "A" word is detected, at step 1514, the message transmission rate is identified as described above, at step 1516, and because frame synchronization is obtained, the time (Tl) to the start of the frame identification code word is identified, at step 1518. When the non-complemented "A" word is not detected, at step 1514, indicating the non-complemented "A" word may have been corrupted by a burst error during transmission, a determination is made whether the complemented "A" bar" is detected, at step 1520. When the "A bar" word is not detected at step 1512, indicating that the "A-bar" word may also have been corrupted by a burst error during transmission, battery saver operation is again resumed, at step 1508. When the "A*τbar" word is detected, at step 1520, the message transmission rate is identified as described above, at step 1522, and because frame synchronization is obtained, the time (T2) to the start of the frame identification code word is identified, at step 1524. At the appropriate time, decoding of the frame identification word occurs, at step 1526. When the frame ID detected is not one assigned to the data communication receiver, at step 1528, battery saving is resumed, at step 1508, and remains so until the next assigned frame is to be received. When the decoded frame ID corresponds to an assigned frame ID, at step 1528, the message reception rate is set, at step 1530. An attempt to bit synchronize at the message transmission rate is next made at step 1532. When bit synchronization is obtained, at step 1533, the "C" word correlation begins at step 1534. When the non-complemented "C" word is detected, at step 1536, frame synchronization is obtained, and the time (T3) to the start of the message information is identified, at step 1538. When the non-complemented "C" word is not detected, at step 1536, indicating the non-complemented "C" word may have been corrupted by a burst error during transmission, a determination is made whether the complement "C bar" is detected, at step 1540. When the "C bar" word is not detected at step 1540, indicating that the "C-bar" word may also have been corrupted by a burst error during transmission, battery saver operation is again resumed, at step 1508. When the "C-bar" word is detected, at step 1540, frame synchronization is obtained, and the time (T4) to the start of the message information is identified, at step 1542. At the appropriate time, message decoding can begin at step 1544.

In summary, by providing multiple synchronization code words which are spaced in time, the reliability of synchronizing with synchronization information which is subject to burst error corruption is greatly enhanced. The use of a predetermined synchronization code word as the first synchronization code word, and a second predetermined synchronization code word which is the complement of the first predetermined synchronization code word, allows accurate frame synchronization on either the first or the second predetermined synchronization code word. By encoding the synchronization code words, additional information, such as the transmission data rate can be provided, thereby enabling the transmission of message information at several data bit rates . By using a second coded synchronization word pair, "fine" frame synchronization at the actual message transmission rate can be achieved, and again due to spacing in time of the synchronization code words, the reliability of synchronizing at a different data bit rate with synchronization information which is subject to burst error corruption is greatly enhanced, thereby improving the reliability of the data communication receiver to receive and present messages to the receiver user.

FIG. 16 is a timing diagram illustrating the organization of the transmission frame utilized in accordance with the preferred embodiment of the present invention. As previously described for FIG. 4 and shown again in FIG. 16, the transmission frame comprises a synchronization code word 1600 followed by eleven data blocks labeled Block 0 - Block 10. Address, control and message code words are distributed within the eleven data blocks in a predetermined order. The first code word, located in Block 0, is always a block information code word 1602 and includes such information as the beginning locations of an address field 1604 and a vector field 1606, leaving eighty-seven code words available for the transmission of address, vector and data code words. By knowing the beginning location of the address field 1604 and the vector field 1606, the controller is able to calculate how many address code words must be decoded per frame in order to determine when a message is present within the frame. Consequently, the address field 1604 includes one or more address code words corresponding to messages located within a data field 1608. Only address code words specifying numeric and alphanumeric messages have corresponding messages located within the data field 1608. Tone only messages, because no message portion is attached, would not have a corresponding message located within the data field 1608. For those address code words which do have corresponding messages, the vector field 1606 includes control words, or vectors, which define the starting and ending locations of messages located within the data field 1608, and there is a one to one correspondence between the address code words located within the address field 1604 and the vectors located within the vector field 1606. FIG. 17 is a timing diagram illustrating the frame information control word 1702 which is transmitted as a part of the synchronization information previously described in FIG. 7. As shown in FIG. 17, four bits 1704 are used to define a cycle number (numbered 0-14) . When 128 frames are transmitted during a single cycle, the transmission time required for fifteen 128 frame cycles is one hour. Cycle 0 always starts on the hour, thus the current time can be predicted by the cycle frame counts. Seven bits 1706 are used to define the frame number

(numbered 0-127) . Four additional bits 1708 are used to indicate that addresses are located only within the first transmission block (block 0) , and as a result when any bits 1708 are set, additional battery saving performance can be obtained, as will be described in FIG. 29 below.

FIG. 18 is an electrical block diagram of the frame formatter 212 utilized in the controller of FIG. 2. As described above, messages which are received are stored in the active page file 210. The active page file 210 is preferably a dual-port, first-in, first out random access memory which is further delineated by message transmission phase, and which stores the messages in the order in which the messages were received according to the message transmission phase assigned to the data communication receiver. It will be appreciated that other memory types, such as hard disk drives can be utilized as well for implementing the active page file 210.

Periodically, such as once each transmission frame interval, a controller 1902 having outputs 1904 sequentially accesses the messages stored in the message storage areas representing the message transmission phases of the active page file 210. The recovered messages are coupled to inputs of a frame decoder 1906 which identifies those messages which are to be transmitted during the current transmission frame, and those messages which will be transmitted during one or more subsequent transmission frames . The operation of the frame formatter for counting subsequent frames is disclosed in U.S. Patent Application Serial No. 07/891363 filed May 29, 1992 by Schwendeman et al, entitled "Data Communication Receiver Having Variable Length Message Carry-on", which is assigned to the assignee of the present invention, and which is incorporated by reference herein. When a message is detected within any of the message transmission phases and which are to be transmitted during the current transmission frame, the frame decoder 1906 generates a message detection signal which is coupled to the controller 1902. The controller 1902 then analyzes the corresponding message to determine the number of code words which will be required for message transmission. Depending on the transmission frame assigned to the recovered messages, the controller 1902 couples calculated message code word counts to a group of frame counters 1908 which maintain a total count of the message code word requirements for the current frame (N) . The message for the current transmission frame is stored in a current transmission frame buffer 1910. When the code word count maintained by the frame counter 1908 for the current frame (N) exceeds a predetermined transmission frame queue capacity, which as described above equals eight-seven code words, the excess messages which are detected as the active page file 210 is read out are stored in a carry-on buffer 1912. The excess messages stored in carry-on buffer 1912 will be transmitted in one or more of three subsequent transmission frames, as described in Schwendeman et al.

After all messages for the current transmission frame have been recovered, the messages stored in the current frame buffer 1910 are coupled to inputs of a data concentrator 1914 which processes the messages stored in the four message storage areas corresponding to transmission phase depending upon the message transmission speed. The concentrated messages are then coupled to inputs of a data distributor 1916 which then distributes the concentrated messages to the frame message buffer 216, again according to the transmission speed. Thereafter, message processing for transmission is as described for FIG. 2.

FIGS. 19-21 are electrical block diagrams illustrating the operation of the data concentrator/distributor in accordance with the preferred embodiment of the present invention. The data concentrator 1914 is preferably a programmable four line to one, two or four line de¬ multiplexer, the operation of which is controlled by the controller 1902. The data distributor 1916 is preferably a programmable one, two or four line to four line multiplexer, the operation of which is also controlled by the controller 1902. The operations of both the data concentrator 1914 and the data distributor 1916 are readily implemented as software routines using a microcomputer. When the message data is to be transmitted at 1600 bits per second (bps) , the total number of messages stored within the four transmission phase regions of the current frame buffer is typically eighty-seven or less code words without message carry-on, and typically less than 1.5X to 2X times eighty-seven code words with message carry-on. However, a speed change to the next transmission speed is preferable when the current frame transmission queue exceeds two times eighty-seven code words with message carry-on. As shown in FIG. 19, the contents of the four transmission phases are combined to a single serial output using the data concentrator 1914, and then redistributed to two of the four frame message buffer transmission phases (1 and 3) . The second two frame message buffer transmission phases (2 and 4) are coupled to a logic zero by the data distributor 1916 which is then loaded into the frame message buffer. The frame message buffer contents is further processed for transmission as described in FIG. 2 above, and applied to the input of the 4-level FSK modulator at the transmitter, which, because of the logic zero input provided to frame message buffer transmission phases 2 and 4, results in 2-level FSK modulation of the message to be generated at 1600 bps, which also corresponds to a symbol rate of 1600 symbols per second. When the message data is to be transmitted at 3200 bits per second (bps) , the total number of messages stored within the four transmission phase regions of the current frame buffer described above, is typically twice eighty- seven or less code words without message carry-on and typical less than three to four times eighty-seven code words with message carry-on. However, again a speed change to the next transmission speed is preferable when the current frame transmission queue exceeds four times eighty- seven code words with message carry-on. As shown in FIG. 20, the contents of the four transmission phases (1 and 2, and 3 and 4) are combined to two serial outputs (2 and 3) using the data concentrator 1914, and then redistributed to the four frame message buffer transmission phases (1 and 3, and 2 and 4 respectively) by data distributor 1916. The frame message buffer contents is further processed for transmission as described in FIG. 2 above, and applied to the input of the 4-level FSK modulator at the transmitter, which results in 4-level FSK modulation to be generated at 3200 bps, which also corresponds to a symbol rate of 1600 symbols per second.

^■ When the message data is to be transmitted at 6400 bits per second (bps) , the total number of messages stored within the four transmission phase regions of the current frame buffer described above, is typically four times eighty-seven or less code words without message carry-on and typically less than six to eight times eighty-seven code words with message carry-on, although message carry-on to sixteen times eighty-seven code words is possible by forcing a carry-on in all three subsequent transmission frames. As shown in FIG. 21, the contents of the four transmission phases are coupled directly through the data concentrator 1914 and the data distributor 1916 to the frame message buffer. The frame message buffer contents is further processed for transmission as described in FIG. 2 above, and applied to the input of the 4-level FSK modulator at the transmitter, which results in 4-level FSK modulation to be generated at 6400 bps which corresponds to a symbol rate of 3200 symbols per second. In summary, the frame formatter is utilized to sort the messages stored within the active page file, shown in FIG. 2, preparing the messages for transmission. The frame formatter formats the message data to enable transmission at three selected transmission speeds using preferably a 4- level FSK modulator, thereby providing increased message processing capacity as the number of messages being received by the system increases.

FIGS. 22-24 are timing diagrams illustrating transmission phase and bit interleaving of the message transmissions in accordance with the preferred embodiment of the present invention. As described in FIGS. 4 and 8, each transmission block comprises 8 thirty-two bit code words, which are encoded in the signaling protocol of the preferred embodiment of the present invention as either address, control or data code words, and which are then interleaved using methods which are well known to one of ordinary skill in the art using the frame message interleaver. Since the messages are stored in transmission phases, as described above, the messages within each transmission phase are independently encoded and interleaved. Depending upon the message transmission rate, the transmission frame data stored for any given transmission phase can be related to transmission frame data stored in other transmission phases, or can be totally independent of the transmission frame data stored in the other transmission phases, as described in FIGS. 19-21. When the transmission frame data is finally processed for transmission, the transmission frame data for each transmission phase is multiplexed together by a phase multiplexer, further interleaving the interleaved transmission frame data.

Returning to FIG. 22, when the transmission frame data 2502 is transmitted at an effective rate of 1600 bits per second, the message bit information 2504, 2506, 2508 appear on the transmission channel as 2-level FSK modulation having a bit period 2512 equivalent to 1600 bit per second data interleaved in a conventional manner, bit zero of message 1 (B0M1) 2504 followed by bit zero of message 2 (B0M2) 2506, and so on. The transmission frame data is derived from the four transmission phases 2510 and is interpreted by the data communication receiver as being a single data bit transmitted at 1600 bits per second. Returning to FIG. 23, when the transmission frame data 2602, 2604 is transmitted at an effective rate of 3200 bits per second, the message bit information 2606, 2608, 2610, 2612, 2614 and 2616 appear on the transmission channel as 4-level FSK modulation having a bit period 2620 equivalent to 3200 bit per second data interleaved in a non- conventional manner, bit zero of message 1 (B0M1) 2606 directed to a first group of data communication receivers, followed by bit zero of message 1 (B0M1) 2612 directed to a second group of data communication receivers, and so on.

The transmission frame data is still derived from the four transmission phases 2618, but is interpreted by the groups of data communication receivers as being two unrelated data streams, each transmitted at 1600 bits per second. Returning to FIG. 24, when the transmission frame data 2702, 2704, 2706 and 2708 is transmitted at an effective rate of 6400 bits per second, the message bit information 2710, 2712, 2714, 2716, 2718 and 2720 appear on the transmission channel as 4-level FSK modulation having a bit period 2722 equivalent to 6400 bit per second data interleaved in a non-conventional manner, bit zero of message 1 (B0M1) 2710 directed to a first group of data communication receivers, followed by bit zero of message 1 (B0M1) 2716 directed to a second group of data communication receivers, followed by bit zero of message 1 (B0M1) 2718 directed to a third group of data communication receivers, followed by bit zero of message 1 (B0M1) 2720 directed to a fourth group of data communication receivers, and so on. The transmission frame data is still derived from the four transmission phases 2722, but is interpreted by the four groups of data communication receivers as being four unrelated data streams, each transmitted at 1600 bits per second.

In summary, messages are transmitted between the terminal and the transmitter over a distribution channel at a constant effective data bit rate of 6400 bits per second. However, depending on how the messages are formatted within the four transmission phases, and which synchronization code word is transmitted, as described above, the transmitted messages are interpreted by the data communication receivers as messages transmitted to one, two or four groups of data communication receivers at a constant effective transmission rate of 1600 bits per second.

FIGS. 25-27 are timing diagrams illustrating the data communication receiver message bit sampling in accordance with the preferred embodiment of the present invention. As described above, the synchronization code word transmitted indicates the relative transmission rate as 1600 bits per second, 3200 bits per second, or 6400 bits per second. Each of the data communication receivers is assigned to one of four transmission phases initially, 01, 02, 03, and 04. When the synchronization code word received indicates message transmission at 1600 bits per second is to follow, the phase selector 828 of FIG. 8 is addressed to select all four phase outputs, resulting in a phase clock which is provided to the demultiplexer 820, block de-interleaver 822, and address 830 and data 832 correlators which is generated at 1600 bits per second. This results, as shown in FIG. 25 with 1600 bit per second message bits which are sampled by all data communication receivers irregardless of transmission phase to which the data communication receivers are assigned, and sampling is provided within the center of the 1600 bit per second data bit.

When the synchronization code word received indicates message transmission at 3200 bits per second is to follow, the phase selector 828 of FIG. 8 is addressed to select two of four phase outputs, resulting in a phase clock which is provided to the demultiplexer 820, block de-interleaver 822, and address 830 and data 832 correlators which is generated at 1600 bits per second during transmission phases 01 and 02, or transmission phases 03 and 04. This results, as shown in FIG. 26 with 3200 bit per second message bits which are sampled by two groups of data communication receivers (group 1 - 01 and 02, group 2 - 03 and 04) sampling within the center of a 3200 bit per second data bit, thereby effectively doubling the amount of information transmitted on the transmission channel. When the synchronization code word received indicates message transmission at 6400 bits per second is to follow, the phase selector 828 of FIG. 8 is addressed to select one of four phase outputs, resulting in a phase clock which is provided to the demultiplexer 820, block de-interleaver 822, and address 830 and data 832 correlators which is generated at 1600 bits per second during transmission phases 01, 02, 03 and 04. This results, as shown in FIG. 27 with 6400 bit per second message bits which are sampled by four groups of data communication receivers (group 1/01, group 2/02, group 3/03 and group 4/04) sampling within the center of a 6400 bit per second data bit, thereby effectively quadrupling the amount of information transmitted on the transmission channel. The sampling of the received data is controlled by the controller 816, shown in FIG. 8, and generates one sampling pulse at 1600 bit per second bit rates, two sampling pulses at 3200 bit per second bit rates, and four sampling pulses at 6400 bit per second bit rates, the sampling pulses centered within the data bit at each transmission bit rate. Selection of which data bit is recovered at the three transmission bit rates is controlled by the phase clock generated by the phase selector, and is based on which transmission phase each data communication receiver is initially assigned to receive as described above.

Battery saver operation is best understood from FIGs . 28-31. In particular, FIG. 28 is a timing diagram illustrating the address, vector and data interleaving format in accordance with the preferred embodiment of the present invention. As shown in FIG. 28, and as previously described in FIG. 17, the signaling protocol comprises a synchronization code word 2802, followed by eleven transmission blocks 2804-2824. At least one block information code word is transmitted in transmission block 0 (2804) followed by variable length address, vector and data fields, the field lengths being dependent upon the number of addresses being transmitted and the message type, such as tone only, numeric or alphanumeric. All transmission blocks are de-interleaved at the receiver, as described above in FIG. 8, however address information does not have to be completely de-interleaved to provide address decoding, thereby providing additional battery saving performance as will be described below. Returning to FIG. 28, the information transmitted within the transmission blocks 2804-2824 is interleaved as shown in the interleave diagram 2826, with the least significant bits of N code words of length M (where M=32, N=8) within a block being transmitted first, followed by the next least significant bit, and so forth, for each transmission block. The transmission of interleaved code words starting with the least significant bit to the most significant bit also provides additional battery saving performance, as will become apparent from FIG. 29. FIG. 29 is an electrical block diagram of a partial interleaved address correlator in accordance with the preferred embodiment of the present invention. When the address correlator is configured for partial interleaved address correlation, the recovered address information is selected by the demultiplexer 820 shown in FIG. 8 according to the data transmission rate and phase assigned to the receiver, and is applied to the input of the block de- interleaver 824. The address information is also serially coupled to the input of the address correlator 830 which directly processes the interleaved address information, as will be described below. The block de-interleaver is used to recover the block information word transmitted in block 0, and the vector and message information, as was described above . The phase clock which is synchronized to the recovered data and which is generated by the phase timing generator 826 and phase selector 828, as shown in FIG. 8, is coupled to the clock input of the block de-interleaver 824 shown in FIG. 29 to allow the recovered data to be clocked into the de-interleaver, and is also coupled to the clock input of the address correlator 830, more specifically to the clock input of address bit demultiplexer 2902. The address bit demultiplexer 2902 sequentially selects an input of one of eight address correlators 2904-2918 one bit at a time thereby performing the address de-interleaving process. An address pattern, corresponding to the address to which the data communication receiver is assigned is applied to a second input of the address correlators 2904-2918. The address correlators are preferably bit error detectors which include a comparator which compares the recovered address information with the corresponding address assigned to the data communication receiver a bit at a time, thereby performing essentially in parallel eight address correlations. When more than a predetermined number of bit errors, such as two bit errors, are detected by any one of the address correlators, an output is generated which is coupled to an error detection input of the controller 816, which is also shown in FIG. 8. Address correlation continues until either an address is detected, meaning at least one address received was received with less than the predetermined number of bit errors, or until all addresses are found to have more than the predetermined number of bit errors, at which time battery saving is initiated. The battery saving operation described above allows battery saving earlier than would be possible when complete block de-interleaving is used prior to address correlation.

In an alternate embodiment of the operation of the address correlator of the present invention (not shown) , recovered data is clocked into the block de-interleaver a bit at a time as is described above. However, unlike the embodiment described above, address information is recovered from the block de-interleaver, in byte-wise fashion a column at a time, and coupled to the inputs of the address correlators 2904-2918. Bit error detection and monitoring of address correlation is as was described above.

The frame information control word which is transmitted as a portion of the synchronization code, includes four bits which identify whether the address information is confined to block 0, or whether the address information extends into additional blocks. For purposes of illustration, it should be noted that when message transmissions are confined to ten character numeric messages, such as telephone numbers, up to 22 addresses can be transmitted in a single transmission frame. FIG. 30 is a timing diagram which illustrates the battery life improvements which are obtained with the battery saver operation in accordance with the preferred embodiment of the present invention. Waveforms 3002 and 3004 represent a lightly loaded system, such as one where address transmission is limited to transmission block 0 (up to seven addresses) . Waveforms 3006 and 3008 represent a medium loaded system, such as where address transmission is limited to transmission blocks 0 and 1 (up to fifteen addresses) . Waveforms 3010 and 3012 represent a fully loaded system, such as where address transmission is limited to transmission blocks 0, 1 and 2 (up to twenty-two addresses) .

Considering the lightly loaded system, waveform 3002 depicts the battery saving factor which is obtained when the complete block 0 must be received and de-interleaved to enable address decoding. As shown, power would be supplied to the receiver for a total of 450 bits out of 3000 bits in the frame (10 bits for receiver warm-up, 184 synchronization code word bits, and 256 block 0 code word bits), resulting in a battery saving factor of 6.67 to 1. However in the preferred embodiment of the present invention, since interleaved data essentially bypasses the block de-interleaver, as' described above, the decoder can determine that within the time necessary to receive the first nine bits of address information for each of the eight possible addresses which can be transmitted, there is a 47% probability that more than two errors will be detected within each of the eight addresses within the block. As a result address decoding is suspended early and battery saving initiated. When partial interleaved address decoding is performed, power to the receiver need only be supplied for 266 bits out of 3000 bits in a best case, resulting in a battery saving duty cycle of 11.28 to 1, and which degrades to a worst case battery saving duty cycle of 6.67 to 1 when all thirty-two bits of all eight address code words must be received to determine the presence or absence of an address .

Similar battery saving improvements occur in medium and fully loaded systems when using partial interleaved address decoding. In the medium loaded system, a battery saving factor of 4.25 to 1 is obtained, as shown by waveform 3006, when full block de-interleaving is required, as compared to 5.75 to 1, as shown by waveform 3008, when partial interleaved address decoding is performed as the address information is received. In the fully loaded system, a battery saving factor of 3.12 to 1, as shown by waveform 3010, is obtained when full block de-interleaving is required, as compared to 4.97 to 1, as shown by waveform 3006, when partial interleaved address decoding is performed as the address information is received. As shown in waveform 3012, battery saving can also be initiated during a transmission block, such as when no addresses are detected within transmission block 1. When, as shown, additional addresses have been identified as being transmitted in transmission block 2, power is again applied for 10 bits prior to the beginning of transmission block 2, to allow for receiver warm-up, and then as shown for at least 72 additional bits, or until it is determined that there is no address present or an address is detected. FIG. 31 is a flow chart illustrating the operation of an alternate embodiment of the partial interleaved address decoder in accordance with present invention. When a column of address information is loaded into the de- interleaver, as described in the alternate embodiment of the partial interleaved address decoder above, a byte of block interleaved data is transferred to the address correlator, at step 3102. The byte of block interleaved data is compared bit by bit with the assigned address bit corresponding to the column from which the byte of block interleaved data is transferred, at 3104. When the bit (n) being compared does not match the assigned address bit, at step 3106, an error counter (n) corresponding to the bit (n) being compared is incremented, at step 3108. A bit position index (n) is incremented, at step 3110, and when n is not equal to eight, at step 3112, the next bit (n) in the byte is compared as described above, at step 3104. When the bit position index value equals eight, at step 3112, the controller checks to determine whether all error counters have values greater than two, at step 3114. When the values are greater than two for all error counters, the supply of power to the receiver is suspended, at step 3116, and battery saving is performed as described above. When one or more of the error counter values is not greater than two, at step 3114, the controller checks to determine whether the end of the block has been reached, at step 3118. When the end of the block is not reached, at step 3118, a column position index is incremented, at step 3022, after which steps 3102 through 3118 are again performed as described above. When the end of the block is detected, at step 3118, indicating an address may have been detected, the values of the error counters are again evaluated, and when any error counter is found to have a value less than three, at step 3120, address detection is verified, and an alert is generated indicating the reception of an address. In summary, partial interleaved address decoding enables decoding of recovered data, either sequentially, as described in FIG. 29, or in a byte-wise manner, as described in FIG. 31. It will be appreciated that byte- wise decoding allows the use of a microcomputer to perform the decoder functions. Partial decoding of the addresses continues until all addresses within the interleaved block are determined to not match an address assigned to the data communication receiver, at which time battery saving can be initiated. By interleaving addresses as described above, address transmission at high data rates can be obtained without loss of fade or burst error protection. When high data rate transmissions are employed, addresses directed to different groups of data communication receivers can be further interleaved, as described above by phases, thereby enabling the decoding of the interleaved address information at a bit rate considerably lower than the actual rate of address transmission on the channel. Partial interleaved address decoding is not affected when phase interleaved addresses transmissions occur which are directed to separate groups of data communication receivers .

I claim:

Claims

Claims :

1. A method for conserving power within a communication receiver comprising the steps of: supplying power to a receiver to enable reception of transmitted coded message signals comprising at least one block of up to N addresses of M bits interleaved to degree N, where M and N are integer numbers; recovering the received coded message signal to generate up to M N-bit data streams; correlating at least a portion of the M N-bit data streams with a corresponding portion of a predetermined M- bit code word to derive N error counts corresponding to the up to N addresses; and suspending the supply of power to the receiver when each of the up to N error counts exceeds a predetermined error count .

2. The method for conserving power within a communication receiver according to claim 1, wherein said step of suspending suspends the supply of power to the receiver when each of the N error counts is equal to or greater than three.

3. The method for conserving power within a communication receiver according to claim 1, further comprising the steps of maintaining the supply of power to the receiver when any one of the N error counts is less than three error counts during the step of correlating the M N-bit data stream.

4. The method for conserving power within a communication receiver according to claim 1, wherein said step of supplying power supplies power to the receiver for a minimum predetermined time interval.

5. The method for conserving power within a communication receiver according to claim 4, wherein said step of supplying power supplies power to the receiver for a minimum of two N-bit data streams .

6. A communication receiver comprising: a receiver for receiving transmitted coded message signals comprising at least one block of up to N addresses of M bits interleaved to degree N, where M and N are integer numbers; means for supplying power to said receiver; means, coupled to said receiver, for recovering the received coded message signals to generate up to M N-bit data streams; means, coupled to said recovery means, for correlating at least a portion of the M N-bit data streams with a corresponding portion of a predetermined M-bit code word to derive N error counts corresponding to the up to N received addresses; and means, responsive to said correlating means and coupled to said means for supplying, for suspending the supply of power to the receiver when each of the N error counts exceeds a predetermined error count.

7. The communication receiver according to claim 6, wherein said means for suspending suspends the supply of power to the receiver when each of the N error counts is equal to or greater than three.

8. The communication receiver according to claim 6, wherein said means for supplying maintains the supply of power to said receiver when any one of the N error counts is less than three error counts while correlating the M by N-bit data stream.

9. The communication receiver according to claim 6, wherein said means for supplying power supplies power to the receiver for a minimum predetermined time interval.

10. The communication receiver according to claim 9, wherein said means for supplying power supplies power to said receiver for a minimum of two N-bit data streams .

11. A method for conserving power within a communication receiver comprising the steps of: supplying power to a receiver to enable reception of transmitted coded message signals comprising a plurality of message streams interleaved to degree K, the message streams comprising at least one block of up to N addresses of M bits interleaved to degree N, where K, M and N are integer numbers; selecting one of the K interleaved message streams; recovering the selected message stream to generate up tp M N-bit data streams; correlating at least a portion of the M N-bit data streams with a corresponding portion of a predetermined M- bit code word to derive N error counts corresponding to the up to N addresses; and suspending the supply of power to the receiver when each of the up to N error counts exceeds a predetermined error count .

12. The method for conserving power within a communication receiver according to claim 11, wherein said step of suspending suspends the supply of power to the receiver when each of the N error counts is equal to or greater than three.

13. The method for conserving power within a communication receiver according to claim 11, further comprising the step of maintaining the supply of power to the receiver when any one of the N error counts in the selected message stream is less than three error counts during the step of correlating the M N-bit data stream.

14. The method for conserving power within a communication receiver according to claim 11, wherein said step of supplying power supplies power to the receiver for a minimum predetermined time interval.

15. The method for conserving power within a communication receiver according to claim 14, wherein said step of supplying power supplies power to the receiver for a minimum of two N-bit data streams during the selected message stream.

16. A communication receiver comprising: a receiver for receiving transmitted coded message signals comprising a plurality of message streams interleaved to degree K, the message streams comprising at least one block of up to N addresses of M bits interleaved to degree N, where K, M and N are integer numbers; means for supplying power to said receiver; means, coupled to said receiver, for selecting one of the K interleaved message streams; means, coupled to said means for selecting, for recovering the selected message stream to generate up to M N-bit data streams; means, coupled to said means for recovering, for correlating at least a portion of the M N-bit data streams with a corresponding portion of a predetermined M-bit code word to derive N error counts corresponding to the up to N addresses; and means, coupled to said means for supplying, for suspending the supply of power to the receiver when each of the N error counts exceeds a predetermined error count.

17. The communication receiver according to claim 16, wherein said means for suspending suspends the supply of power to said receiver when each of the N error counts is equal to or greater than three.

18. The communication receiver according to claim 16, wherein said means for supplying maintains the supply of power to said receiver when any one of the N error counts in the selected message stream is less than three error counts during the step of correlating the M N-bit data stream.

19. The communication receiver according to claim 16, wherein said means for supplying power supplies power to said receiver for a minimum of two N-bit data streams during the selected message stream.

20. The communication receiver according to claim 16, further comprising means, coupled to said receiver, for synchronizing said means for selecting to selected the one of the K interleaved message streams.