WO1993003500A1

WO1993003500A1 - Method of forming a resistive element in a semiconductor device and a sram cell made thereby

Info

Publication number: WO1993003500A1
Application number: PCT/US1992/006449
Authority: WO
Inventors: Sik K. Lui
Original assignee: Sierra Semiconductor Corporation
Priority date: 1991-08-01
Filing date: 1992-07-31
Publication date: 1993-02-18

Abstract

A method of forming a resistive element (18) for use in a semiconductor device is disclosed. The resistive element (18) can be used in a 4T SRAM memory cell. The resistive element (18) is formed by implanting a non-insulating element, such as silicon, into a layer of insulating material (40) such as silicon dioxide to decrease the resistivity of the layer to form the resistive element (18) having the desired resistance value.

Description

METHOD OF FORMING A RESISTIVE

ELEMENT IN A SEMICONDUCTOR DEVICE AND A

SRAM CELL MADE THEREBY

Technical Field The present invention relates to a method for making a resistive element having high resistivity in a semiconductor device. More particularly, the present invention relates to a method of forming a vertical resistor for use in a SRAM memory cell.

Background of the Invention

The use of resistive elements in an SRAM memory cell is well known in the art. The resistive element is used as a load device. In U.S. Patent No.

4,297,721, polycrystalline silicon is disclosed as a resistive element for use in an SRAM memory cell.

The polycrystalline silicon is positioned horizontally.

As the scale of integration increases and it is desired to increase the density of SRAM memory cells, it is well known to use vertically aligned resistors as the loading device. See for example U.S. Patent

No. 4,416,049.

In an article entitled "A Novel Scaled Down

Oxygen Implanted Polysilicon Resistor For Future Static RAMS", by R. Saito, Y. Sawahata, T. Nagano, and N. Momma published in the 1986 issue of IEDM (pp.

296-299) , a method is disclosed for forming a resistive element for use in an SRAM Cell. The method comprises implanting oxygen into polycrystalline silicon to form the resistive element. Summary of the Invention

Accordingly, in the present invention, a method of forming a resistive element between a first and a second conductive element in a semiconductor device is disclosed. The resistive element can be horizontal, vertical or any other shape and can be used in any application. However, the resistive element is particularly suited for use in a static ram memory cell. The resistive element has a resistance having a certain value. The method of the invention comprises the steps of forming the first conductive element. A layer of insulating material is deposited in contact with the first conductive element. A non-insulating element is implanted into the layer of insulating material to decrease the resistance of the layer to the desired certain value of the resistive element. Finally, the second conductive element is formed in contact with the layer of the implanted insulating material.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 is a schematic circuit diagram of an SRAM memory cell using resistive load elements of the prior art.

Figure 2 is a cross-sectional view of a semiconductor structure of the prior art, implementing the schematic circuit shown in figure 1.

Figure 3 (a-g) are steps in the method of the present invention in forming a vertical resistive element for use in a static ram memory cell whose circuit diagram is shown in figure 1.

Figure 4 is a plot of concentration of the silicon implant into an insulating layer of silicon dioxide, in accordance with the method of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS

Referring to Figure 1 there is shown a schematic circuit diagram of a SRAM memory cell 10 of the prior art. The SRAM memory cell 10 comprises two cross- coupled transistors Ql and Q2 with two access transistors Q3 and Q4. Thus, the SRAM memory cell 10 is known as a four transistor (or 4T) cell. In addition, the Cell 10 comprises two resistive load elements 18 (a and b) . Each of the resistive elements 18 (a and b) is connected to one of the transistors Ql or Q2.

As is well known, each of the transistors Q1-Q4 comprises a source 12, a gate 16 and a drain 14. The source 12 of the transistors Ql and Q2 are connected to a source of first voltage potential, i.e., ground potential. The drain 14 of the transistors Ql and Q2 are connected to transistors Q3 and Q4 respectively and to one end of the resistive elements 18 (a and b) . The other end of the resistive elements 18 (a and b) are connected to a source of second voltage potential, such as V_cc. Finally, the transistors Ql and Q2 have a gate 16 which is connected to the drain 14 of the other transistor. In this manner, the transistors Ql and Q2 are cross-coupled. Referring to Figure 2, there is shown a partial cross-sectional view a semiconductor structure showing portions of the SRAM Cell 10 shown in Figure 1. Transistor Ql is shown as having source 12, gate 16, and drain 14. A heavily doped polycrystalline layer labeled poly-2 is electrically connected to the drain region 14. The poly-2 has a region 18 which is undoped and forms the intrinsic poly or the resistive element 18. At its other end of the poly-2 is another heavily doped region forming the connection to the source of second voltage potential V_cc. In addition, the first heavily doped region of the poly- 2 is connected to a first layer of heavily doped polysilicon labelled poly-1 which is connected to the gate 16 of the transistor Q2 (not shown) .

As can be seen from Figure 2, the prior art SRAM memory cell 10 has a resistive element 18 which is horizontally displaced. As the scale of integration increases and it is desired to increase the density of the SRAM memory cell 10 in a device, it is desired to "shrink" the lateral area occupied by each SRAM cell 10. As previously discussed, U.S. Patent No. 4,416,049 discloses a vertically aligned resistive element 18 for use in an SRAM memory cell 10 in order to increase the density of an SRAM Memory Circuit. The present invention relates to a method for forming a vertically aligned resistive element which can be used in a 4-T SRAM cell 10. However, as will be shown, the method of the present invention can be used in any application where a resistive element in a semiconductor device is desired. In particular, the method of the present invention can also be used to form a horizontal resistive element.

Referring to Figure 3a there is shown the first step in the formation of the 4T SRAM memory cell 10 with the improved resistive element 18 of the present invention. In the first step, a semiconductor substrate 30 is shown as having field oxide regions 32 formed thereon. A layer of buffered oxide 34 is formed on top of the semiconductor substrate 30. The formation of the field oxide region 32 and the buffer oxide region 34 on the substrate 30 is well known in the art. One method is to begin with a semiconductor substrate 30 and forming the buffer oxide layer 34 on the entire surface of the substrate 30, by oxidizing the silicon substrate. Thereafter, silicon nitride is deposited over the buffered oxide layer 34. The silicon nitride layer is patterned and etched using conventional photolithographic techniques. This can be done, for example, by applying a photo-resist layer. The photo-resist layer is exposed and selected portions are removed, exposing portions of the silicon nitride. The exposed portions of silicon nitride is removed. Local oxidation is then applied. Since silicon nitride prevents oxygen from penetrating through to oxidize the silicon thereunder, silicon dioxide is formed on a shallow surface layer of the silicon nitride and in the exposed regions of the silicon substrate forming the field oxide regions 32. The silicon nitride layer and the buffered oxide layer are then removed exposing the silicon substrate 30. An oxide layer 42 is then thermally grown on the silicon substrate 30 as the gate dielectric of the MOS transistor. In the next step as shown in Figure 3c, a mask

36 is applied. The mask 36 is patterned exposing a selected region of the structure. The selected region exposes a portion of the gate oxide 42 and field oxide 32. The exposed region of silicon dioxide from the gate oxide layer 42 and the field oxide region 32 is then etched. The mask 36 is then removed. A 3,000-4,000 Angstrom thick polycrystalline silicon layer 38 is deposited over the entire structure by conventional LPCVD. The polysilicon layer 38 is then doped with an N type dopant such as phosphorus or arsenic at approximately 900-1,000°C. The high temperature drives the dopant into the substrate 30, where the polycrystalline silicon layer 38 is in direct contact with the silicon substrate 30, to form a buried contact with the drain 14a. Where the polycrystalline silicon layer 38 is in direct contact with the gate oxide 42 or the field oxide 32, the silicon dioxide prevents the dopant from being driven into the silicon substrate 30. The polysilicon layer 38 is patterned and etched by conventional lithographic methods to form the gate 16 of transistors Ql and Q2 and the cross-coupling or the electrical connection between the polycrystalline silicon 38 of transistor Ql (which is in contact with the drain 14a of Ql) to the gate 16 of Q2 (not shown, but is directly behind polysilicon 38) and from the polycrystalline silicon 38 of transistor Q2 (which is in contact with the drain 14a of Q2 - not shown, but is directly behind gate 16) to the gate 16 of Ql.

In the next step, a mask is then applied exposing the source 12 and drain 14b of the transistors Ql and Q2. Dopants are implanted into the source 12 and drain 14b regions and the gate 16 to render them conductive. A typical dopant is

Arsenic which is implanted at an energy level of 40- 80 Kev. Silicon dioxide 40 is then deposited over the entire structure. This can be done, for example, by LPCVD at 400-450°C temperature for 10-20 minutes to form approximately 2,000 Angstroms thick silicon dioxide 40. Thus far, the steps set forth hereinabove for the formation of the 4T SRAM cell is well known in the art.

A mask 42 is formed over the entire structure. The mask 42 is patterned and is exposed. The exposed area is removed. The exposed area is over the region where the vertical resistor 18 would be formed connected to the underlying polysilicon layer 38. Silicon ions are implanted through the exposed area of the mask 42, into the silicon dioxide region 40 between the dotted lines shown in Figure 3f. The silicon is implanted a number of times with each implant having an energy range from 20 KeV to 200 KeV and with the dosages ranging from 1.0 E15 to 1.0 E17. Thus, for example, referring to Figure 4 there is shown a graph of the concentration of silicon in a 2,000 Angstrom thick region of silicon dioxide.

After the silicon ions have been implanted, the mask 42 is removed. A second layer of polysilicon 44 is deposited over the entire structure. This can be done for example, by depositing 1,000-2,500 Angstrom thick polysilicon using conventional LPCVD. The second polysilicon layer 44 is then implanted with an N-type dopant such as phosphorus or arsenic. The structure is then annealed at a temperature range of approximately 900 to l,000°C in nitrogen. The annealing process joins the dopants from the drain regions 14a and 14b to form a single contiguous drain region 14. The second polysilicon layer 44 is then patterned and etched by conventional lithographic methods to form the necessary connection to the resistor 18 and to connect to the source of second voltage potential V_cc. The result is the structure shown in figure 3g. Although the method described heretofore is the preferred method, the method can be practiced by implanting any non-insulating element (such as a semiconductor element or a conductive element) into an insulating material. The implanted semiconductor element can be silicon. The implanted conductive element can be aluminum or carbon. The insulating material can be silicon dioxide, BPSG (boron phosphorous doped glass) , PSG (phosphorous doped glass) or silicon nitride. While it is preferred to use semiconductor ions implanted into an insulating material to decrease the resistance thereof, there is no reason why conductive elements such as aluminum or carbon cannot be used implanted into insulating material to change the resistivity. The use of semiconductor is preferred to form a resistor having high resistivity.

The theory of the method of the present invention is that the insulating material has a resistivity that is lowered by the implanting of a non-insulating element. The amount of implanted non- insulating element determines the degree to which the resistivity of the insulating material is lowered until the desired resistivity is achieved.

Finally, with the method of the present invention, the resistive element can be formed vertically, horizontally or in any other shape and is not necessarily limited to the vertical resistor described in the preferred embodiment. In addition, the resistor formed by the method of the present invention can be used for an SRAM cell or any other application in a semiconductor device.

Claims

1. A method of forming a resistive element having a resistance of a certain value connected between a first and a second conductive element in a semiconductor device, comprising the steps of: forming the first conductive element; depositing a layer of insulating material in contact with the first conductive element; implanting a non-insulating element into said layer of insulating material to decrease the resistance of said layer to said certain value; and forming said second conductive element in contact with said layer of implanted insulating material.

2. The method of Claim 1 wherein said insulating material is a material chosen from silicon dioxide, phosphorus doped glass, boron phosphorus doped glass, or silicon nitride.

3. The method of Claim 2 wherein said non- insulating element is a material chosen from silicon, aluminum or carbon.

4. The method of Claim 1 wherein said resistor is a vertical resistor and wherein said layer of insulating material is deposited over said first conductive element and wherein said second conductive element is formed over said layer of implanted insulating material.

5. The method of Claim 4 wherein said insulating material is silicon dioxide and said non- insulating element is silicon.

6. The method of Claim 5 wherein said implanting step comprises implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

7. The method of Claim 6 wherein said implanting step comprises a plurality of implanting step each step implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

8. The method of Claim 5 further comprising the steps of masking said layer of silicon dioxide prior to said implanting step.

9. The method of Claim 8 wherein said masking step comprises: covering said layer of silicon dioxide with a masking material having an exposed region; and wherein said implanting step implants through said exposed region.

10. The method of Claim 9 further comprising the step of: annealing said layer of implanted silicon dioxide.

11. A method of making a resistive load element for a transistor comprising the steps of: depositing a first layer of polycrystalline silicon on a face of a semiconductor substrate and patterning to define a gate area and buried contact area; doping said first layer of polycrystalline silicon to render said gate area and said buried contact area conductive; doping said semiconductor substrate in selective regions to form source/drain conductive regions on said semiconductor substrate thereby forming said transistor; depositing a layer of silicon dioxide over said first layer of polycrystalline silicon in said buried contact area; implanting silicon ions into said layer of silicon dioxide to form said resistive load; and forming a second conductive layer over said layer of resistive load.

12. The method of Claim 11 wherein said implanting step comprises implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

13. The method of Claim 12 wherein said implanting step comprises a plurality of implanting step each step implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

14. The method of Claim 11 further comprising the steps of masking said layer of silicon dioxide prior to said implanting step.

15. The method of Claim 14 wherein said masking step comprises: covering said layer of silicon dioxide with a masking material having an exposed region; and wherein said implanting step implants through said exposed region.

16. The method of Claim 15 further comprising the step of: annealing said layer of implanted silicon dioxide.

17. A static random access memory cell formed on a semiconductor substrate comprising: a first transistor means having a gate, a source, and a drain; a second transistor means having a gate, a source, and a drain; means for connecting the source of said first and second transistor means to a source of first voltage potential; means for connecting the drain of said first transistor means to the gate of the second transistor means; means for connection the drain of said second transistor means to the gate of the first transistor means; and a plurality of resistive load means for connecting the drain of said first or second transistor means to a source of second voltage potential wherein each resistive load means is formed by depositing a layer of silicon dioxide over a first conductive region electrically connected to the drain of said transistor means; implanting silicon ions into said layer of silicon dioxide to form said resistive load means; and forming a second conductive layer over said resistive load means to electrically connect said resistive load means to said source of second voltage potential.

18. The cell of Claim 17 wherein said implanting step comprises implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

19. The cell of Claim 18 wherein said implanting step comprises a plurality of implanting step, each step implanting silicon ions having an energy range from approximately 20 KeV to approximately 200 KeV and dosage range from approximately 1.0E15 to approximately 1.0E17.

20. The cell of Claim 17 wherein said resistive load means is further formed by the step of: masking said layer of silicon dioxide prior to said implanting step.

21. The cell of Claim 20 wherein said masking step comprises: covering said layer of silicon dioxide with a masking material having an exposed region; and wherein said implanting step implants through said exposed region.

22. The cell of Claim 21 wherein said resistive load means is further formed by the step of: annealing said layer of implanted silicon dioxide.