WO1989010609A1

WO1989010609A1 - Display controller

Info

Publication number: WO1989010609A1
Application number: PCT/JP1989/000405
Authority: WO
Inventors: Fumitaka Nishikawa
Original assignee: Seiko Epson Corporation
Priority date: 1988-04-27
Filing date: 1989-04-14
Publication date: 1989-11-02
Also published as: HK171795A; GB2237713A; KR900700985A; JPH0234894A; KR970008783B1; GB8928519D0; GB2237713B

Abstract

A display controller for controlling the display comprising first setting means for setting first data that indicate a first display size with which the display can be made, second setting means for setting second data that indicate a second display size used for the display, and control means which produces display data to produce display on said display region defined based on said first and second data.

Description

Description Display controller technology

The present invention relates to a display controller that generates a display control signal for a flat display (such as an LCD or a plasma display) used in a computer or the like. Background technology

In a conventional display controller, the display area setting means is limited to only one type. For example, when using a flat display with 640 dots in the horizontal direction and 400 dots in the vertical direction, set the display area (display size) in the controller to 640 x 400 and set the horizontal 640 dots. When using a flat display with x vertical 200 dots, change the display area setting in the controller to 640 x 200. Therefore, if there are multiple display areas in one system, for example, if there are two types of display areas, 640 x 400 and 640 x 200, two types of flat displays are prepared. Then I chose the display that suits each display mode and did ^ ffl. In a conventional display controller, there is only one type of display area setting means, so there is no problem if there is only one type of display area in one system.However, there are many types of software in one system. The display area of the power << If present, the display corresponding to the software must be selected. In other words, it is not possible to display many types of software on one display. For example, IBM personal computer IBM— Taking a PC as an example, this system has multiple display areas, such as 640x350 dots or 640x200 dots. Since the selection of the display page area is made by software, if the display is fixed at 640x350 dots, software that supports only a 640x200 dot display cannot be used.

The object of not being able to display a plurality of display areas on a single display in this way is solved by the mode setting method of the display controller so that a wide display area can be obtained even if the display area changes. is there. Disclosure of the invention

The display controller of the present invention has means for respectively setting a maximum display capacity (first display size) that can be displayed by the display and a display area (second display size) actually used for display.

Since the present invention has the above configuration, even if the display area (second display size) that actually displays i ^ m is smaller than the display capacity (first display size), the display can be performed by setting each of them to. Therefore, no matter how many display areas exist, if various values are set as the display areas, various display areas can be displayed for one type of display capacity. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a weaving example of the present invention.

Fig. 2 shows the format of the video data signal VD.

Figure 3 shows the correspondence between external sofa memory addresses and display positions.

FIG. 4 is a diagram showing an example of an LCD display.

FIG. 5 is a diagram showing a specific example of a write address conversion circuit. FIG. 6 shows a specific example of a blanking control.

Fig. 7 shows the operation timing chart of the blanking control.

FIG. 8 is a diagram showing an example of LCD display when blank data is provided in the upper, lower, left, and right directions. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an example in which the present invention is applied to an LCD controller (hereinafter, video-LCD interface) that converts a video signal for CRT into a signal for a liquid crystal display device (hereinafter, LCD). First, the operation of the controller will be briefly described. As shown in Fig. 2, VD video data for CRT usually has a display data period (shaded area) and a blanking period (portion outside the shaded area). In addition, the flyback period can be divided into four types: vertical back porch, vertical front porch, horizontal back porch, and horizontal front porch. The video data is scanned dot-sequentially from the upper left and is serially input from VD in Fig. 1 and taken into a serial / parallel conversion circuit (S / P conversion circuit) 115 with a dot clock CK synchronized with VD. This serial data is converted into parallel data every 8 bits and written to the external buffer memory 120 via the data bus 130. The write address at this time is determined by the write address counter 105, which counts the write clock 131, which is obtained by dividing CK by 1 to 8 by the frequency divider 104, as shown in Fig. 3. It is counted up for each bit and output. The write end address AW is switched every eight dots and output to the write address bus 122 via the write address conversion circuit 106. The read Z write control circuit 107 outputs the address switching signal 125 and the write control signals 126, 127 in synchronization with the rise and fall of the write clock 131. The address switching circuit 1 2 9 outputs one of the write address bus 1 2 2 and the read address 1 <2 3 to the address 1 2 4 by the address switch signal 1 2 5. — — Strengthen. Therefore, at the time of writing, the writing address force is output to the bus 124 in the first half of the writing clock 131 when the writing address force is switched every 8 dots of the dot clock << and the 8 bits are synchronized with the control signal 126 from the SZP conversion circuit 115. The parallel data is input to the external buffer memory 120, and the parallel signal is written to the address of the memory 120 according to the address data of the bus 124 by the control signal 127 to enter the external buffer memory 120 writing state.

Since the video data contains invalid data (retrace period) as described above, the horizontal back porch determination circuit / horizontal dot counter is ignored so that the display data can be captured by the SZP conversion circuit, ignoring that part. 113, vertical back porch determination circuit Controlled by Z vertical line number counter 114. 7 Flat back switch judgment circuit Input the horizontal synchronization signal HSC as the counter start pulse and the dot clock CK as the counter clock to the Z horizontal dot counter. To the vertical back porch determination circuit Z vertical line number counter, the vertical synchronizing signal V SC is input as the start pulse of the power counter, and the 7 horizontal synchronizing signal HS C is input as the clock of the counter.

Next, reading from the external buffer memory will be described. The clock generation circuit 111 outputs a read basic clock. The read address count 108 generates a read address by counting the read clock 132 obtained by dividing the basic read clock by a frequency divider 110 in a sequence suitable for the LCD. The data read from the external buffer memory 120 is input to the LCD data conversion circuit 118 via the data bus 130, converted into a format suitable for the LCD, and output via the blanking control 119C ^). . In addition, a control signal (data shift clock, data latch pulse, etc.) 121 required for the LCD counts the clock from the clock generation circuit 111 and is generated by the LCD control signal generation circuit 117 and supplied to the LLCD. At the time of reading, a control signal 128 is output from the read Z write control circuit 107, and the external buffer memory 120 is set to a read state by the control signal 127. The control signal 128 is output in synchronization with the write clock 131 when the read address changes and the read address changes. In response to the signal 128, the latch 109 latches the read address, and outputs the address data to the bus 123. At the time of the read cycle immediately after the change of the read address force, the read address data is output from the address switching circuit 129, and the data is read from the memory address corresponding to the address. The above is the outline of the video-LCD-in / out phase.

Next, details of a portion to which the present invention is applied will be described. First, the mode setting register 101 will be described. This register is a group of registers that set various settings such as the | g® method and display area of the LCD. The register 102 that sets the display capacity (first display size) that can be displayed on the LCD and the video It exists in the register 103 for setting the display area (second display size) where the signal is actually used for display, and in the input fc. For example, if a display area of 640 x 35 dots is to be displayed on a 640 x 480 dot matrix LCD (for example, EBM mode of IBM-PC, a personal computer manufactured by IBM), the register 102 contains 640 x 480 dots. Set the dots, and set 640 x 350 dots for the Regis 103. The display in this case is as shown in Fig. 4, and the buffer memory is reserved for the display capacity (640x480 dots). Here, the effective video data (shaded area) is only 350 lines, so in order to display on the LCD as shown in Fig. 4, it is necessary to have an offset in the address when writing to the buffer memory. . The power of performing this conversion is << write address conversion circuit 1◦6. Also, the write address counter 105 一 is counted by D103 indicating the display area. In the case of the display in Fig. 4, the address corresponding to the upper blank data

64 0 dots Χ 6 5 lines

= 5 2 0. Part-Time Job

S

May be added as an offset. As an example of this circuit, a circuit for adding the offset by using an adder is shown in FIG.

Here, the offset address register 501 is a register in which the offset value of the address is written. Since several types of offset values are required depending on the combination of the display capacity and the display area, a plurality of offset values are prepared. ing. One value is selected from the plurality of registers via the selector 502. At this time, the selector 502 selects based on the output signals D102 and D103 of the mode setting register shown in FIG. The 16-bit offset value thus selected is output to 503, and is input to the 16-bit adder 504 together with the output AW from the write address counter 105. As a result, an address power output A AW obtained by adding the offset address to the normal write address AW is obtained. In other words, the write address counter 105 has its count set by D103 as described above, and only counts 640 dots X350 lines. It adds a blank area of 640 dots X 65 lines to the address AW. Accordingly, the video data is not stored in the above-mentioned 520 bytes of the buffer memory 120, but is stored from the next address. If the contents of the mode setting registers 102 and 103 change, the ^ count number of the write address counter 105 and the offset amount of the address conversion circuit 106 also change accordingly, and thus have various display capacities. Various display areas for the display Can be set.

When writing is performed in this manner, the buffer memory in the portion corresponding to the blank data shown in FIG. 4 does not have the writing power <, and the effective video data is written from the address following the offset address. On the other hand, since reading is performed for the entire display capacity, that is, for all 640 × 480 dots, reading is also performed for the above-described buffer memory that does not perform writing power, and data is output to the LCD. Therefore, if the data is read out as is and transferred to the LCD, random data may be displayed on the upper and lower blank data portions. In order to avoid this, a memory clear sequence must be provided so that the buffer memory contents are cleared once (for example, when the power is turned on), or the blanking data is controlled so that it is not displayed on the LCD. Need to be done. The part that performs the latter control is the blanking control 119. This has a function of disabling the data output to the LCD corresponding to the blanking data section based on the information in the registers 1-2 and 103. In this case, the data output is disabled (fixed to low level) at the time of data transfer from the first line to the 65th line and at the time of data transfer from the 416th line to the 480th line. Figure 6 shows an example of a blanking control circuit. The operation will be briefly described below. Λ ^ Β 号 LI NEC is the output of a 9-bit LCD line counter. This LCD line counter is a 9-bit counter included in the LCD control signal generation circuit 117 shown in FIG. 1 and counting up the number of LCD lines (480 lines in this case). The counter output LINEC is input to the decoder 601 in the blanking control 119. This decoder switches the decoder output in response to the contents D102 and D103 of the mode registers 102 and 103. Here, LI based on D102 and D103 Decodes that the contents of the 65th line at the start of the NEC display area are output, and outputs signal 607. And output signal 608. Fig. 7 shows the evening chart. These signals are further input to the RZS flip-flop 602 to generate an LCD data enable signal LCD EN. Only when LCDEN is at a high level, the LCD data is enabled, and the LCD data conversion circuit 118 outputs the output LCD data LCDD to the LCD via AND gates 603 to 606. At other times, the outputs of the AND gates 603 to 606 are fixed at low level, and-LCD does not display. What should be noted here is that the read address counter 108 and the line counter in the LCD control signal generation circuit 117 each have a maximum count number of D102 indicating the display capacity of the LCD. Therefore, the read address counter 108 counts the addresses so that the data corresponding to the display capacity of the LCD is repeatedly read from the buffer memory 120. Also, the line counter repeats the count for 480 lines as shown in FIG. Based on the output of this line counter, the enable signal LCD EN is output for 350 lines from 65 lines to 414 lines in the count of 480 lines.

Therefore, if the counts of these counters are D102 and 103, the counts will be changed accordingly, so that various display areas can be displayed on a display having various display capacities.

Summarizing the above, the display controller of Fig. 1 defines the memory capacity for the displayable display capacity of the display in the buffer memory 120, and at the time of writing, the memory capacity of 640 dots X 65 lines. 640 dots X 350 lines of data from the next address without remembering the video data Is memorized. Therefore, if the display is read from the address corresponding to the display capacity and displayed, the display will be displayed in the set display area. However, if the data is simply read out, the wrong data may be contained in the address where the video data is not stored in the buffer memory. In the present invention, since the display position of the display is detected and the data is output to the display only during the display area, and the display is set to a fixed level during which the display is not performed during the other periods, an incorrect display may occur outside the display area. Don't worry.

In this way, the display outside the display area can be completely turned off. The operation for displaying 640x350 dots on a 640x480 dot LCD has been described above. If you want to change the display to 640 x 200 dots here, you only need to change the contents of register 103 that sets the display area to 640 x 200 dots. Then, the address offset 503 of the write address conversion circuit 1 ァ 6 and the output of the decoder 601 of the blanking control 119 are also automatically switched, and a display as shown in FIG. 8 can be obtained.

As described above, according to the present invention, since each of the display capacity setting register 102 and the display area register 103 is provided, one LCD, for example, a 640 × 480 dot LCD, can display various displays and 640 × 480. Of course, the display of 640x350 dots ゃ 640x200 dots can be switched and displayed simply by changing the value of the register 103 without changing the hardware. In the present example, a register which is a storage means which can be read and written is used as a means for setting the display capacity and the display area, but this is not limited to the register and other means may be used. For example, you can easily change the settings by providing an input terminal for each and changing the input signal at that terminal. In this explanation, the blanking area is up and down as shown in Fig. 4. Force explained in the case where it exists The same applies to the case where there are blanking areas at the top, bottom, left and right as shown in FIG. In this case, the offset address selector 501 in the write address conversion circuit and the decoder 601 in the blanking control are only slightly changed. Also, here, an LCD has been described as an example, but the present invention can be similarly applied to a controller for another flat display (for example, a plasma display).

By using the present invention, various display modes (display areas) can be displayed on one display. Therefore, even if the display mode is changed by software, it is not necessary to convert the hardware (display) each time, and it is possible to support various software. This is especially effective when applied to a laptop computer using a flat display, since a single flat display can support various software.

Claims

The scope of the claims

1. In a display controller for controlling display of a display, a first setting means for setting a first data size indicating a first display size capable of displaying the display force, and a second setting value indicating a second display size used for display. (2) second setting means for setting data, and control means for outputting display data to the display so as to display in a display area of the display defined based on the first and second data. Display control port characterized by having

―No

2. The control means includes: a display counter that indicates a display position of the display; and a display device that outputs the display data during a period in which the count content of the display counter indicates a display position in the display area. The display according to claim 1, further comprising blanking control means for outputting data for bringing the display into a blanking state during a period in which the count content of the display count indicates a display position other than the display area. controller.

3. The display counter is a line counter that indicates the number of lines at the display position, and the blanking control means displays the count of the line counter during a period from the display start line to the display end line of the display area. 3. The display controller according to claim 2, further comprising: means for generating an enable signal; and gate means for outputting the display data to the display during a period in which the display enable signal is generated.

4. The display controller according to claim 3, wherein the line counter is set with a maximum number of lines to be focused based on the first data indicating a first display size that can be displayed on the display.

5. The display data output by the blanking control means is read from an address of a designated storage device based on an output of a read address counter. 5. The display controller according to claim 4, wherein the read address count is set to a count value of S ^ C based on the 5H1 data.

6. The control means has a read address counter, and the control means outputs the display data to be read out to the display from the address of the storage device designated based on the output of the overflow address count. The display controller according to claim 1.

7. The control means writes a display address count for counting a clock signal synchronized with the display data written to the storage device, and writes the display data to an address of the storage device corresponding to the display area. An address conversion that converts the output of the write address counter to form an address data of the storage device so that the display data is not written to an address of the storage device corresponding to an area other than the display area. 7. The display controller according to claim 6, comprising means.

8. In the write address counter, a count is set based on the second data indicating the second display size at which the display is ^ ffl, and the read address counter is a first display size that can be displayed on the display. 8. The display controller according to claim 7, wherein the number of force points is calculated based on the first data indicating the following.

9. The display according to claim 8, wherein the number of waste counts of the write address counter corresponds to the second display size, and the number of power counts of the read address count corresponds to the first display size. Conto Ichino

10. The address conversion circuit reads the address as an offset by an address preceding the address of the storage device corresponding to the display start position of the display area. 10. The display controller according to claim 7, wherein the display controller forms the address data by adding to an output of an address counter.

11. The display controller according to claim 6, wherein the display data read from the storage device is data written by a write address designating unit.

1 2. The read address counter specifies an address of the storage device so as to read data of a first display size that can be displayed on the display from the storage device, and the write address counter includes: 12. The display controller according to claim 11, wherein an address of the storage device is designated so that the display data is written to an address corresponding to the display area in an address from which data is to be read.

13. The display data written in the storage device is video data, and the display data output by the control means is data for a liquid crystal display device or a plasma display. Display controller.

13. The display controller according to claim 12, wherein said first and second setting means are readable and writable storage means.