WO1989001235A1

WO1989001235A1 - High effective barrier height transistor and method of making same

Info

Publication number: WO1989001235A1
Application number: PCT/US1987/001880
Authority: WO
Inventors: Siang Ping Kwok; Milton Feng; He Bong Kim
Original assignee: Ford Microelectronics, Inc.
Priority date: 1987-08-03
Filing date: 1987-08-03
Publication date: 1989-02-09

Abstract

A high effective barrier height field effect transistor (10) includes a supporting substrate (12) having a surface (14) and including a channel region (16) below the surface containing a carrier concentration of a desired conductivity type. A barrier enhancement interfacial layer (20) is formed on top of the channel region (16) of the substrate (12) and has a thickness of a controlled dimension sufficient to produce barrier enhancement. A gate (22) of a conductive material is deposited on top of the interfacial layer (20) and a drain (24) and source (26) are deposited on the substrate (12). The interfacial layer (20) may be formed of an insulator layer or a thin p, high p or p+ layer. The interfacial layer enables the transistor to achieve a relatively high transconductance. A method for making the transistor is also described.

Description

HIGH EFFECTIVE BARRIER HEIGHT TRANSISTOR AND METHOD OF MAKING SAME

TECHNICAL FIELD

The present invention relates to field effect transistors, and, more particularly, to field effect transistors exhibiting high effective barrier height.

TECHNICAL FIELD

Field effect transistors (TET") are an integral part of the electronics industry. The industry needs electronic components which use relatively little power, are resistant to radiation, and exhibit high speeds. Recent developments in crystal growth, doping, material deposition and lithography technology have made progressively more complex circuits possible with these characteris¬ tics. It is desirable to have a FET capable of providing relatively high transconductance for higher speeds and higher barrier heights for larger noise immunities. In fields such as computers, communications, and instrumentation, higher speeds are very desirable.

Field effect transistors generally comprise source and drain electrodes interconnected by a semiconductor material. Electrical conduction between these electrodes is primarily within the semiconductor material. The flow of -current between the drain and the source is modulated by external voltage applied to a gate which is deposited on top of the semiconductor.

Gallium arsenide metal semiconductor Schottky barrier field effect transistors ("MESFET") having high transconductance values and stable characteristics have become the most commonly used devices for high speed digital integrated circuits and -microwave applications. For high speed, high density digital applications, an enhancement mode FET is desirable to keep power consumption low while maintaining a high transconductance at high current drive. However, the Schottky gate swing of conventional enhancement mode FETs is limited to less than + 0.7 volts because the barrier height of gallium arsenide Schottky diodes is invariably only 0.5 to 0.8 volts. Therefore, the noise immunity of the logic gate in current state of the art transistors is reduced due to the low barrier height. The device intrinsic transconductance of an enhancement mode FET is determined by the doping profile.of the channel region. A shallow channel is desired because carriers are highly confined within that region, causing a high transconductance until degradation of the carrier mobility dominates. The degree of electron confinement in a MESFET is limited by the ability to fabricate thin channel regions in the device. High electron confinement can be induced in an accumulation or inversion region having a ._^controlled dimension which is relatively thin.

Since stable and viable metal-insulator GaAs devices exhibiting a high effective barrier height were not previously feasible, direct metal to semiconductor junctions have been used to form MESFETs instead of the common metal-oxide- semiconductor devices ("MOSFET*) used in most conventional silicon integrated circuits.

The depletion mode MESFET consumes large quantities of power and is therefore not suitable for large scale integrated circuit applications. In looking for a replacement for the depletion mode MESFET, the industry has turned to enhancement mode MESFETs which are normally off and conduct current with a positive gate, using less power. A problem has arisen in manufacturing these enhancement mode MESFETs because it has been extremely difficult to produce thin gallium arsenide layers that are depleted of carriers with no applied bias, as residual charged surface states often form. Hence, it is desirable to create an enhancement mode MESFET having a low surface state density within a thin interfacial layer between the gate electrode and the n-channel in the substrate to enable the transistor to exhibit high transconductance, high speed, and to increase the effective barrier height to increase noise immunity.

Currently, MOSFETs or MESFETs use relatively thick insulator layers, on the order of 30 nanometers to several hundred nanometors in thickness, in order to prevent electron tunneling through the insulator. However, by permitting electron tunneling, high carrier confinement is induced, thereby increasing the effective Schottky barrier height.

U.S. Patenf No. 4,450,462 issued to Nuyen on May 22, 1984 describes a gallium arsenide field effect transistor having an MNOS structure with a- non-volatile memory including, among other portions, an insulant composed of a double dielectric layer, whose semi-insulating film has a thickness below 100 angstroms formed from a semiconductor material of groups III - V, and whose other insulant layer is an oxide having a thickness of several hundred angstroms. U.S. Patent No. 4,472,872 issued to Toyoda, et al. on September 25, 1984 describes a Schottky gate FET fabricated by forming on the substrate first and second stacks facing each other. An insulation layer is formed thereon and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. The insulation layer described has . a thickness of 3,000 to 10,000 angstroms.

DISCLOSURE OF THE INVENTION

The present invention -provides an -improvement to high effective barrier height type field effect transistors. More specifically, the present invention provides a field effect transistor of the type including a supporting substrate with a channel region, a gate, a drain, and a source deposited thereon, and a thin barrier enhancement interfacial layer interposed between the substrate and the gate electrode.

The interfacial layer is operative to form a barrier enhancement region interfacing the substrate with the gate electrode, thus enabling the transistor to achieve a relatively high trans- conductance. In accordance with the invention, the transistor includes a supporting substrate having a surface and including a channel region below the surface containing a carrier concentration of the desired conductivity type, a gate of conductive material deposited on top of the interfacial layer, a drain made of an ohmic material deposited on top of the substrate and a source also made of ohmic material deposited on top of the substrate.

The semiconductor material preferably includes semi-insulating gallium arsenide but may be other Group III-V compounds or silicon.

The interfacial layer is preferably from 10 to 300 angstroms thick and made of silicon dioxide, silicon nitride, or aluminum nitride or a thin p, 5 high p, or p layer manufactured by ion implanting P-type impurities such as magnesium, carbon or beryllium. In the case of an insulator, other oxides may achieve the same effect, whether deposited as monolayers, a superlattice, or as a

10 plurality of layers may be used.

A method is described for forming a field effect transistr^. including ion implanting a region below the surface of a substrate to form a channel containing a carrier concentration of a desired

15 conductivity type and annealing to activate the region. A layer or a multilayer of insulator or p- type materials is thereafter formed on the substrate.

In the instance of the interfacial layer

20 being a deposited insulator layer, the insulator layer is selectively etched to form a substitutional gate. A dopant is then ion implanted into the substrate while the etched insulator acts as a substitutional gate to mask the channel region.

25 Subsequent annealing activates the ion implanted dopant. Then, the substitutional gate is partially

-,-..-- removed to leave a thin layer of an insulated layer onto which the final gate material is deposited.

Ohmic contacts and interconnecting metallic ater-

30 ials are then deposited onto areas above the region left unmasked by the substitutional gate, thereby producing a transistor.

The deposition of insulator materials is preferably accomplished by plasma enhanced chemical

35 vapor deposition, but may be accomplished by other methods, such as chemical vapor deposition or sputter deposition. Also in accordance with the present invention, the transistor is preferably annealed during the fabrication steps at high temperatures after the initial implantation to activate the ion implanted regions.

In the instance of the interfacial layer being a p, high p or p layer, p-type impurities are either ion implanted to a shallow depth or grown by epitaxial method such as MBE or MOCVD. The optimal depth is determined by the interrelationship of the doping profile and the impurity implantation depth.

Other advantages and features of the present invention will be appreciated from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in greater detail hereinafter and the features which are believed to be novel are set forth with particularity in the claims. The invention may best be understood by making reference to the following attached drawings wherein:

FIGURE 1 is a cross-sectional side view of a field effect transistor fabricated in accordance with the present invention including an insulator layer;

FIGURE 2 is an energy band diagram of a MESFET structure embodying the present invention;

FIGURE 3 illustrates representative steps in the fabrication of the MESFET of the present invention;

FIGURE 4 is a cross-sectional view of a field effect transistor fabricated in accordance with the present invention including a p-type layer; and FIGURE 5 illustrates representative steps in the fabrication of another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to FIGURE 1, a high effect barrier height field effect transistor 10 illustrating one embodiment of the present invention including the use of an insulator material as the interfacial layer is presented. As shown, the transistor 10 is formed on a substrate 12 of semiconductor material made of a III-V composition such as semi-insulating gallium arsenide, silicon, indium phosphide, or a film of any of these on top of another substrate, such as glass, single crystal silicon, mylar, or stainless steel. The substrate 12 has a surface 14 and includes a channel region 16 below the surface thereof containing a carrier concentration of a desired conductivity type, such as n, n-, p, or p-.

Deposited on the substrate 12 is an insulator layer 20 having a thickness of a controlled dimension sufficient to cause high electron confinement in the adjacent channel region 16 of the substrate. The insulator layer 20 is operative to form an accumulation or inversion region 18 proximate the interface with the substrate 12, enabling the transistor 10 to achieve a relatively high transconductance. On top of the substrate 12 is a drain 24 and a source 26. A gate electrode 22 is deposited on top of the insulator layer 20.

The insulator layer 20 material is preferably silicon dioxide or silicon nitride, or may also be made of a composition selected from the group consisting of aluminum nitride, aluminum oxide, tantalum oxide, titanium oxide, tungsten oxide, gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, gallium arsenide oxide, aluminum gallium arsenide oxide, indium gallium arsenide phosphide oxide and indium phosphide oxide.

Insulator layer 20 may be composed of a monolayer of the above mentioned materials, or may be fabricated from a superlattice structure of a combination of the insulator ^"layer materials. A conformal layer of insulator layer 20 may also be deposited over the entire surface of the substrate. The insulator layer 20 may also be made of two or more layers, these layers being made of compositions selected from the group consisting of silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide, tantalum oxide, aluminum gallium arsenide oxide, titanium oxide, tungsten oxide, gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, indium gallium arsenide phosphide oxide, or indium phosphide oxide.

A plurality of layers may also comprise insulator layer 20 such as a very thin layer of gallium arsenide deposited directly on top of the substrate 12, a second very thin layer of silicon dioxide deposited «on top of the gallium arsenide layer and a third uppermost layer of titanium dioxide deposited on top of the silicon dioxide.

The thickness of insulator layer 20 has a controlled dimension of less than 1000 angstroms and preferably less than 300 angstroms. If insulator layer 20 is made of a plurality of layers, the total thickness should preferably be less than 300 angstroms. In the preferred embodiment, the thickness of insulator layer 20 is typically between ten and one hundred angstroms. The gate 22 is self-aligned and has a controlled gate length. Gate 22 is made of refrac¬ tory materials and their appropriate compounds or suicides, including titanium and tungsten contain- ing compositions, and is deposited directly on top of insulator layer 20.

Also deposited on the substrate 12 is a drain 24 of ohmic material, acting as the drain electrode. A source 26, also made of an ohmic material, is deposited over the substrate 12 on the opposite side of the gate 22 from drain 24. Drain 24 and source 26 may be formed of any suitable ohmic material, such as gold-germanium, nickel, nickel- containing compositions or any other suitable metal. The drain 24 and source 26 include an ion implanted region having a carrier concentration of a desired conductivity type, preferably n . Both the drain 24 and source 26 are self-aligned to the gate 22 and activated. Interconnecting metallic material 28 is deposited on top of both said drain 24 and source 26 to act as an electrical connection for current con¬ duction paths for the transistor.

Referring now to FIGURE 2, the energy band diagram for the field effect transistor including the insulator layer of the present invention is illustrated and corresponds to the application of a positive voltage bias. The conduction and valence bands of the semiconductor are curved which indicates an electron accumulation zone. If the voltage bias is sufficiently high, electrons will pass through the insulator layer by a tunnelling effect.

FIGURE 3 is an illustration of representative steps for the fabrication of the field effect transistor shown in FIGURE 1. A region below the surface of a substrate is ion implanted to form a channel containing a carrier concentration of a desired conductivity type and is thereafter annealed at a high temperature, from about 750 to 900 degrees Celsius, to activate the ion implanted region. A thin layer of insulator such as silicon nitride, silicon dioxide, nitride or aluminum oxide is deposited onto the substrate. Thereafter, a relatively thick layer of substitutional gate material, such as silicon dioxide, is deposited to a thickness of approximately one micron or less. The substitutional gate is then delineated and formed by dry etching. The deposition of insulator may be accomplished by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, sputter oxidation, molecular beam oxidation, molecular beam epitaxy oxidation, or thermal oxidation.

Additionally, the method may further comprise the step of forming an oxide of a III-V compound material on the substrate, such as gallium or arsenide oxide, before the deposition of the insulator. The insulator may be formed as a monolayer, as a superlattice, or as a plurality of layers of insulator materials. After the insulator deposition is accomplished, and the substitutional gate is delineated, a dopant is ion implanted into the substrate while the substitutional gate masks the channel region. This provides two doped regions on either side of the channel region. Subsequently, high temperature annealing, from 750° to 900° C. , is performed again to activate the dopant.

Preferably, planarizing polymer or photoresist is applied to the entire surface after the dopant is annealed. The planarizing polymer or photoresist is etched back to leave the substitutional gate exposed, and the unwanted insulator material is stripped, leaving the planarizing polymer or photoresist in place. The substitutional gate is removed by standard techniques, leaving a very thin insulator layer on top of the substrate.

Gate metal is then deposited over the entire surface of the substrate. Without the substitutional gate in place, the gate metal is deposited into the area where the substitutional gate was previously located. The planarizing polymer or photoresist is then stripped, which also removes the gate metal which had been deposited over the polymer or photoresist regions, leaving the gate metal deposited on top of the very thin insulator layer. Ohmic contacts are deposited over the region which was left unmasked by the substitutional gate. Interconnecting metallic material is deposited over the ohmic contacts to provide conduction paths for electricity through the transistor. Further conventional techniques are used to complete the transistor for incorporation into devices.

Referring now to FIGURE 4, a high-effective barrier height _afield effect transistor 30 illustrating another embodiment of the present invention is shown. Transistor 30 is formed on a substrate 32 of semiconductor material made of a similar composition as the transistor in FIGURE 1. The basic difference between the transistor in FIGURE 1 and FIGURE 4 is the inclusion of a shallow depth p-type interfacial layer 40 instead of the thin insulator layer 20 of FIGURE 1.

Substrate 32 has a surface 34 which includes a channel region 36 having charge carriers 38. P- type layer 40 may be manufactured by ion implantation or epitaxial growth may be performed by conventional methods. Direct implantation into the gallium arsenide substrate of selenium, silicon or sulphur ions may be used to form the device n- channel carriers 38. After annealing the n-channel, very shallow magnesium ion implantation is advantageously used to form a thin p, high p or p layer. Thereafter, a similar method as described in FIGURE 3 above is used to form self-aligned gate 40, drain 44, source 46 and interconnecting metallic layers 48. P-layer 40 can. be either p or p + material which may be formed by conventional ion implantation of p-type impurities, such as magnesium, carbon, beryllium and other such elements. If it is advantageous to use p material for the interfacial layer, epitaxial methods including molecular beam epitaxy and MOCVD can be used to grow the material. The carrier concentration of p material may be about 10 18 carriers per cubic cen^~timeter or higher.

A p-layer by itself does not normally create an inversion or accumulation layer like the insulator layer of FIGURE 1, rather it increases the barrier height and thereby enhances the transconductance. The addition of the p layer also allows more carriers in the n-channel.

Further embodiments of the present invention include the use of ttie thin p, high p or p⁺ layer in conjunction with an insulator layer, such as insulator layer 20 of FIGURE 1, preferably made of silicon oxide, the insulator layer being less than 100 angstroms thick. Similarly, the transconductance is enhanced. With reference to FIGURE 5, the embodiment of the present invention which includes a thin p, high- p or p layer is manufactured according to FIGURES 5A through 5G. The method as described in FIGURE 5 is substantially similar to the method as shown in FIGURE 3, with the exception that the p-layer formed in FIGURE 5B acts as the barrier-enhancement interfacial layer rather than the insulator described in FIGURE 3.

After the p-type barrier enhancement interfacial layer is formed in or on the substrate, a substitutional gate is formed on top of the interfacial layer to produce a self-aligned gate at a later time. Another method which is not shown in illustrations includes first performing the n- channel implantation, followed by the formation of the p-type interfacial layer and thereafter using refractory metal gate material as an n implant mask for the achievement of a self-aligned gate structure. To complete the transistor, FIGURE 5 illustrates the same final steps as described above in FIGURE 1. As above, further conventional techniques may be used to complete the transistor for incorporation into semiconductor devices. While the b st modes of the present invention are disclosed above, the invention.is not limited to those disclosures. The invention^" is not to be so limited, rather the invention should be interpreted with respect to the recitations of the following claims.

Claims

What is claimed is:

1. An improved field effect transistor of the type having a substrate with a channel region, a gate, a drain, and a source, wherein the improvement comprises: .^ a barrier enhancement interfacial layer interposed between the gate and the channel region of the substrate, said interfacial layer made of a material selected from the group consisting of

+ insulators, p-type, high p-type, and p -type

^'. materials, and said interfacial layer increasing the effective barrier height and transconductance of the transistor.

2. A high effective barrier height field effect transistor, comprising: a) a semi-insulating gallium arsenide substrate having a surface and including an n-type conductivity region below the surface thereof; b) a barrier enhancement interfacial layer on said substrate, said layer having a thickness from ten to three hundred angstroms; c) a delineated, self-aligned gate of refractory material deposited on top of said interfacial layer; d) an ion implanted, activated drain having an n-type conductivity, said drain being self- aligned to the gate; e) an ion implanted, activated source having an n-type conductivity, said source being self- aligned to gate; f) a layer of a metallic material capable of ohmic contact with the substrate, said metallic layer being formed at the drain and source; and g) an interconnecting metallic layer deposited on top of the surface of the ohmic contact material.

3. A high effective barrier height field effect transistor, comprising: a) a supporting substrate having a surface and including a channel region below the surface thereof containing a carrier concentration of a desired conductivity type; b) a barrier enhancement interfacial layer made of a material selected from the group consisting of insulators, p-type, high p-type and p⁺ type materials; c) a gate of conductive material deposited on top of said interfacial layer; d) a drain made of ohmic material deposited on top of said substrate; e) a source made of ohmic material deposited on top of said substrate; and f) said interfacial layer being operative to enable the transistor to achieve a relatively high transconductance.

4. A field effect transistor as in claims 1, 2 or 3, wherein said substrate includes a semi- insulating gallium arsenide material substrate.

5. A field effect transistor as in claim 4, wherein said gallium arsenide material includes n- type conductivity material.

6. - A field effect transistor as in claim 4, wherein said gallium arsenide material includes n~- type conductivity material.

7. A field effect transistor as in claim 4, wherein said gallium arsenide material includes p~- type conductivity material.

8. A field effect transistor as in claim 1, 2 or 3, wherein said substrate includes a silicon substrate.

9. A field effect transistor as in claim 1, 2 or 3, wherein said substrate includes an indium phosphide substrate.

10. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer includes a silicon dioxide layer.

11. A field effect transistor as in claim l or 3, wherein said insulator layer includes a silicon nitride layer.

12. A field effect transistor as in claim 1,

2 or 3, wherein said interfacial layer is made of an insulator composition selected from the group consisting of aluminum nitride, aluminum oxide, tantalum oxide, titanium oxide, tungsten oxide, gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, gallium arsenide oxide, aluminum gallium arsenide oxide, indium gallium arsenide phosphide oxide and indium phosphide oxide.

13. A ield eff ct transistor as in claim 1, 2 or 3, wherein said interfacial layer is a monolayer.

14. A field effect transistor as in claim 4, further comprising a superlattice layer of insulating material between said substrate and said gate. «.

15. A field effect transistor as in claim 1, 2 or-3, wherein said interfacial layer is made of at least two layers, said layers being made of insulator compositions selected from the group consisting of silicon dioxide, silicon nitride, aluminum nitride, aluminum oxide, tantalum^" oxide, aluminum gallium arsenide oxide, titanium oxide, tungsten oxide, gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, indium gallium arsenide phosphide oxide, and indium phosphide oxide.

16. A field effect transistor as in claim 15, wherein said insulator layers have a total thickness of less than three hundred angstroms.

17. A field effect transistor as in claim 1,

2 or 3, wherein said interfacial layer further includes a very thin layer of material selected from the group consisting of gallium oxide and arsenide oxide formed on top of the gallium arsenide material substrate, a second very thin layer of silicon dioxide deposited on top of said gallium oxide layer, and a third uppermost layer of titanium dioxide deposited on top of said silicon dioxide layer.

18. A field effect transistor as in claim 1,

2 or 3, wherein said interfacial layer has a thickness of less than one thousand angstroms.

19. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer has a thickness of less than three hundred angrstoms.

20. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer has a thickness from about ten to about one hundred angstroms.

21. A field effect transistor as in claim 1,

2 or 3, wherein said interfacial layer includes a p- type material layer.

22. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer includes a high p-type material layer.

23. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer includes a P -type material layer.

2.4. A field effect transistor as in claim 21, 22 or 23, wherein said material layer is formed from a material selected from the group consisting of magnesium, carbon and beryllium.

25. A field effect transistor as in claim 1, 2 or 3, wherein said interfacial layer is located under the gate material layer.

26. A field effect transistor as in claim 1, 2 or 3, wherein said gate is self-aligned and has a controlled gate length.

27. A field effect transistor as in claim 1, 2 or 3, wherein said gate is made of refractory materials.

28. A field effect transistor as in claim 1, 2 or 3, wherein said gate is made of titanium and tungsten containing materials.

29. A field effect transistor as in claim 1,

2 or 3, wherein said drain includes an ion implanted region having a carrier concentration of a desired conductivity type, said drain being self-aligned to said gate, and said drain being activated.

30. A field effect transistor as in claim 1,

2 or 3, wherein said source is an ion implanted region having a carrier concentration of a desired conductivity type, said source being self-aligned to said gate, and said source being activated.

31. A method for forming a high effective barrier height field effect transistor, comprising: a) ion implanting a region below the surface of a substrate to form a channel containing a carrier concentration of a desired conductivity type and thereafter annealing to activate said region; b) forming a barrier enhancement interfacial layer on the substrate and forming thereon a substitutional gate; c) thereafter ion implanting a dopant into the substrate while the substitutional gate masks the channel region and annealing to activate the implanted dopant; d) removing the substitutional gate and depositing gate metal over the interfacial layer; e) depositing ohmic contacts onto areas above said unmasked regions; and f) depositing interconnecting metallic material over the ohmic contacts.

32. A method for forming a high effective barrier height field effect transistor, comprising: a) ion implanting a region below the surface of a substrate to form a channel containing a carrier concentration of a desired conductivity type and thereafter annealing to activate said region; b) depositing at least one layer of insulator and selectively etching said insulator to form a substitutional gate; c) thereafter ion implanting a dopant into the substrate while the substitutional gate masks the channel region and annealing to activate the implanted dopant; d) removing the substitutional gate and further reducing the thickness of the insulator to provide a very thin insulator layer; e) depositing gate metal over the thin insulator layer and providing an insulated gate; f) depositing ohmic contacts onto areas above said unmasked region; and g) depositing interconnecting metallic material over the ohmic contacts.

33. A method as in claim 31 or 32, wherein said annealing is performed at high temperatures.

34. A method as in claim 32, wherein said deposition of insulator is accomplished by oxidation.

35. A method as in claim 32, wherein said deposition of insulator is accomplished by plasma enhanced chemical vapor deposition.

36. A method as in claim 32, wherein said deposition of insulator is accomplished by chemical vapor deposition.

37. A method as in claim 32, wherein said deposition of insulator is accomplished by low pressure chemical vapor deposition.

38. A method as in claim 32, wherein said deposition of insulator is accomplished by sputter oxidation.

39. A method as in claim 32, wherein said deposition of insulator is accomplished by molecular beam oxidation.

40. A method as in claim 32, wherein said deposition of insulator is accomplished by molecular beam epitaxy oxidation.

41. A method as in claim 32„ wherein said deposition of insulator is accomplished by thermal oxidation.

42. A method as in claim 32, wherein said deposition of insulator is performed to initially provide a thickness from about two to five hundred angstroms. «,

43. A method as in claim 32, wherein said selective etching the insulator delineates the substitutional gate to a thickness of about one micron.

44. A method as in claim 32, further comprising the step of depositing an oxide of a III- V compound material before^' the formation of the insulator.

45. A method as in claim 32, wherein said deposition of insulator is performed by depositing a monolayer of said insulator.

46. A method as in claim 32, wherein said deposition of insulator is performed by depositing a superlattice of insulator materials.

47. A method as in claim 32, wherein said deposition of insulator is performed by depositing a plurality of layers of insulator materials.

48. A method as in claim 32, wherein said deposition of insulator is accomplished by depositing a layer of silicon dioxide.

49. A method as in claim 32, wherein said deposition of insulator is accomplished by deposit¬ ing a layer of silicon nitride.

50. A method for forming a high effective barrier height field effect transistor, comprising: a) ion implanting a region below the surface of a substrate to form a channel containing a carrier concentration of a desired conductivity type and thereafter annealing to activate said region; b) forming a p-type material layer to a shallow dimension in the channel to form a thin barrier enhancement layer in the substrate; c) forming a substitutional gate on top of the thin p-type material layer; d) ion implanting a dopant into the substrate while the substitutional gate masks the channel region and annealing to activate. the implanted dopant; e) removing the substitutional gate and depositing gate metal over the barrier enhancement layer; f) depositing ohmic contacts onto areas above said unmasked region ; and g ) depositing interconnecting metallic material over the ohmic contacts .

51. A method as in claim 50 wherein said forming a p-type material layer includes ion implanting p-type impurities.

52. A method as in claim 50, wherein said forming a p-type material layer includes epitaxially growing p-type material.

53. A method as in claim 51, wherein said epitaxial growing is accomplished by molecular beam epitaxy.

54. A method as in claim 52, wherein said epitaxial growing is accomplished by chemical vapor deposition.