WO1987001866A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- WO1987001866A1 WO1987001866A1 PCT/JP1986/000145 JP8600145W WO8701866A1 WO 1987001866 A1 WO1987001866 A1 WO 1987001866A1 JP 8600145 W JP8600145 W JP 8600145W WO 8701866 A1 WO8701866 A1 WO 8701866A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- semiconductor device
- anode
- pressure contact
- main
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005219 brazing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Definitions
- the present invention relates to a semiconductor device having pressure contact, structure for use in high power application.
- Fig. 1 is a cross-sectional view of a conventional thyristor having pressure contact structure, wherein 1 denotes an n-type base layer, 2 denotes a p-type base layer, 3 denotes an n-type emitter layer, 4 denotes a p-type emitter layer, 5 denotes an anode, 6 denotes a cathode, and 7 denotes a gate electrode, and the anode 5 is made of a metal plate such as molybdenum plate or a tungsten plate, having a coefficient of thermal expansion which is similar to that of silicon, and it is brazed to a silicon substrate in view of mechanical reinforcement on the occasion of pressure contact.
- 1 denotes an n-type base layer
- 2 denotes a p-type base layer
- 3 denotes an n-type emitter layer
- 4 denotes a p-type emitter layer
- 5 denotes an anode
- 6 denotes a catho
- Electrode 8 is an electrode connecting plate made of a molybdenum plate or a tungsten plate attached to said cathode 6
- 9 and 10 are electrode blocks of the anode side and the cathode side, respectively, coupled to a package, and the blocks are generally placed in pressure contact in the directions shown by the arrows.
- 11 is a surface covering made of an organic substance or the like such as polyimide vanish or silicone rubber
- J» and J 2 are junctions controlling a main breakdown voltage.
- Semiconductor devices of an ordinary pressure contact structure employ mesa structure having these junctions J 1 and J_ terminated at the side surface.
- mesa structure is used in a semiconductor device of a pressure contact structure
- the breakdown voltage characteristic of the device may be deteriorated by contamination of an insulating film covering the planar junction in brazing the anode 5
- surface processing of the junctions is possible after the brazing.
- Conventional semiconductor devices of pressure contact structure as described above involve problems such that the quality of a device is hard to be stabilized as an organic substance such as polyimide vanish or silicone rubber is used as a surface covering, and, in addition, a process becomes complicated and operation efficiency is greatly impaired as the surface processing is carried out with an electrode connecting plate made of a molybdenum plate or a tungsten plate attached thereto.
- a semiconductor device comprises a semiconductor device of pressure contact structure, in which first and second main electrodes formed on a semiconductor chip of planar structure are in pressure contact by means of electrode blocks of the first electrode side and the second electrode side, respectively, connected to a package, wherein an electrode reinforcing plate is interposed between said first electrode and the electrode block of the first electrode side, whereby the quality of the device can be stabilized, and a semiconductor device of pressure contacts structure of a simple manufacturing process and high operation efficiency can be obtained.
- Fig. 1 is a cross-sectional view of a thyristor having conventional pressure contact structure
- GTO gate turn off thyristor
- Fig. 2 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, wherein 21 is an n-type base layer, 22 is a p-type base layer, 25 are guardring regions, 26, 27 and 28 are anode, gate electrode and cathode, respectively, formed of a metal such as Al, these forming a semiconductor chip 20 having planar structure.
- 29 and 30 are electrode blocks of the anode side and the cathode side, respectively, 31 is an electrode connecting plate formed of molybdenum or tungsten, etc., mounted on said cathode 28, 32 is an anode reinforcing plate formed of molybdenum or tungsten, etc, interposed between said anode 26 and the electrode block 29 on the anode side.
- the mechanical stress upon pressure contact can be buffered by interposing the anode reinforcing plate 32 between the anode 26 and the electrode block 29 on the anode side and, therefore, conventional necessity of brazing the anode is eliminated.
- the semiconductor chip 20 can be made in planar structure, passivation can be performed in a wafer state, whereby necessity of surface processing of a junction using an organic substance after the brazing of the anode, which is done in a semiconductor device having conventional mesa structure, is eliminated. Accordingly, the quality of a device can be stabilized, and in addition, the operation becomes easy, especially in the case of multi chip structure in which a number of elements are obtained by cutting out one wafer. Meanwhile, since this GTO is provided with guardring regions 25 to reduce the concentration of an electric field at a curved portion A of the junction, it provides a breakdown voltage which is close to that of mesa structure, although it has planar structure itself.
- Fig. 3 is a cross-sectional view of another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: the structure of this embodiments has guardring regions 25 formed in the n-type base layer 21 which is adjacent to both sides of the p-type emitter layer 24 of the anode side.
- Fig. 4 is also a cross-sectional view of yet another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: instead of forming guardring regions 25 in the anode side as in the above embodiment shown in Fig. 3, this embodiment being structured with both sides of the p-type emitter layer extended to the surface of the cathode side.
- an anode in a GTO corresponds to a collector electrode
- a cathode corresponds to a base electrode
- a gate electrode corresponds to an emitter electrode, respectively.
- the present invention comprises an anode reinforcing plate interposed between an anode and an electrode block of the anode side of a semiconductor chip having planar structure, passivation can be done in a wafer state, and, since there is no necessity of surface processing of the junction using an organic substance, such meritorious effects are brought about that the devices can be stabilized, the manufacturing process becomes simple, and the operation efficiency is improved.
- the present invention is utilized in a semiconductor device for high power application, such as a thyristor, transistor, and a diode.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
- Thyristors (AREA)
Abstract
Semiconductor device having pressure contact structure for high power use, in which main electrodes formed on a semiconductor chip of planar structure are in pressure contact by means of first and second electrode blocks (29, 30) connected to a package, wherein an electrode reinforcing plate (32) is interposed between said electrode (26) and electrode block (29).
Description
SPECIFICATION
Semiconductor Device FIELD OF THE INVENTION The present invention relates to a semiconductor device having pressure contact, structure for use in high power application.
BACKGROUND OF THE INVENTION Generally, in a semiconductor device for high power application requiring control of a large current, neither soldering nor wire-bonding method is used, but pressure contact structure is used as a method of forming electrodes, in view of such problems as thermal fatigue on the occasion of large current conduction.
Fig. 1 is a cross-sectional view of a conventional thyristor having pressure contact structure, wherein 1 denotes an n-type base layer, 2 denotes a p-type base layer, 3 denotes an n-type emitter layer, 4 denotes a p-type emitter layer, 5 denotes an anode, 6 denotes a cathode, and 7 denotes a gate electrode, and the anode 5 is made of a metal plate such as molybdenum plate or a tungsten plate, having a coefficient of thermal expansion which is similar to that of silicon, and it is brazed to a silicon substrate in view of mechanical reinforcement on the occasion of pressure contact. 8 is an electrode
connecting plate made of a molybdenum plate or a tungsten plate attached to said cathode 6, and 9 and 10 are electrode blocks of the anode side and the cathode side, respectively, coupled to a package, and the blocks are generally placed in pressure contact in the directions shown by the arrows. 11 is a surface covering made of an organic substance or the like such as polyimide vanish or silicone rubber, and J» and J2 are junctions controlling a main breakdown voltage. Semiconductor devices of an ordinary pressure contact structure employ mesa structure having these junctions J1 and J_ terminated at the side surface. The reason why mesa structure is used in a semiconductor device of a pressure contact structure is that, in the case of planar structure the breakdown voltage characteristic of the device may be deteriorated by contamination of an insulating film covering the planar junction in brazing the anode 5, while in the case of mesa structure, surface processing of the junctions is possible after the brazing. Conventional semiconductor devices of pressure contact structure as described above involve problems such that the quality of a device is hard to be stabilized as an organic substance such as polyimide vanish or silicone rubber is used as a surface covering, and, in addition, a process becomes complicated and operation efficiency is
greatly impaired as the surface processing is carried out with an electrode connecting plate made of a molybdenum plate or a tungsten plate attached thereto.
DISCLOSURE OF THE INVENTION A semiconductor device according to the present invention comprises a semiconductor device of pressure contact structure, in which first and second main electrodes formed on a semiconductor chip of planar structure are in pressure contact by means of electrode blocks of the first electrode side and the second electrode side, respectively, connected to a package, wherein an electrode reinforcing plate is interposed between said first electrode and the electrode block of the first electrode side, whereby the quality of the device can be stabilized, and a semiconductor device of pressure contacts structure of a simple manufacturing process and high operation efficiency can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a thyristor having conventional pressure contact structure; Fig. 2 is a cross-sectional view of a gate turn off thyristor (hereinafter referred to as "GTO") of one embodiment of a semiconductor according to the present invention; Fig. 3 is a cross-sectional view showing another embodiment of a semiconductor device according to the present invention;
Fig. 4 is a cross-sectional view showing yet another embodiment of a semiconductor device according to the present invention.
BEST MODES OF CARRYING OUT THE INVENTION The embodiments of this invention will be hereinafter described with reference to the drawings. Fig. 2 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, wherein 21 is an n-type base layer, 22 is a p-type base layer, 25 are guardring regions, 26, 27 and 28 are anode, gate electrode and cathode, respectively, formed of a metal such as Al, these forming a semiconductor chip 20 having planar structure. 29 and 30 are electrode blocks of the anode side and the cathode side, respectively, 31 is an electrode connecting plate formed of molybdenum or tungsten, etc., mounted on said cathode 28, 32 is an anode reinforcing plate formed of molybdenum or tungsten, etc, interposed between said anode 26 and the electrode block 29 on the anode side. In this GTO, the mechanical stress upon pressure contact can be buffered by interposing the anode reinforcing plate 32 between the anode 26 and the electrode block 29 on the anode side and, therefore, conventional necessity of brazing the anode is eliminated. In particular, since the semiconductor chip 20 can be made
in planar structure, passivation can be performed in a wafer state, whereby necessity of surface processing of a junction using an organic substance after the brazing of the anode, which is done in a semiconductor device having conventional mesa structure, is eliminated. Accordingly, the quality of a device can be stabilized, and in addition, the operation becomes easy, especially in the case of multi chip structure in which a number of elements are obtained by cutting out one wafer. Meanwhile, since this GTO is provided with guardring regions 25 to reduce the concentration of an electric field at a curved portion A of the junction, it provides a breakdown voltage which is close to that of mesa structure, although it has planar structure itself. The storage carriers in the n-type base layer 21 are caused to disappear as the p-type emitter region 24 and the n-type base layer 21 are short-circuited by the anode 26 to form an anode-emitter short-circuited structure, thereby enabling a rapid operation. Fig. 3 is a cross-sectional view of another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: the structure of this embodiments has guardring regions 25 formed in the n-type
base layer 21 which is adjacent to both sides of the p-type emitter layer 24 of the anode side.
Fig. 4 is also a cross-sectional view of yet another embodiment of a semiconductor device of the present invention, which is designed to enhance a reverse directional breakdown voltage as well as a forward directional breakdown voltage: instead of forming guardring regions 25 in the anode side as in the above embodiment shown in Fig. 3, this embodiment being structured with both sides of the p-type emitter layer extended to the surface of the cathode side.
Although the above embodiments were described with regard to GTO, this invention is not limited to this, and it may be applied to a common thyristor, a transistor, or a diode. In the case of a transistor, an anode in a GTO corresponds to a collector electrode, a cathode corresponds to a base electrode, and a gate electrode corresponds to an emitter electrode, respectively.
As described above, since the present invention comprises an anode reinforcing plate interposed between an anode and an electrode block of the anode side of a semiconductor chip having planar structure, passivation can be done in a wafer state, and, since there is no necessity of surface processing of the junction using an organic substance, such meritorious effects are brought
about that the devices can be stabilized, the manufacturing process becomes simple, and the operation efficiency is improved.
POSSIBILITY OF INDUSTRIAL UTILIZATION The present invention is utilized in a semiconductor device for high power application, such as a thyristor, transistor, and a diode.
Claims
(1) A semiconductor device having pressure contact structure with first and second main electrodes formed on a semiconductor chip of planar structure, being in pressure contact by means of the electrode blocks on the sides of the first main electrode and the second main electrode, respectively, connected to a package, characterized in that an electrode reinforcing plate is interposed between said first main electrode and the electrode block of the first main electrode side.
(2) A semiconductor device recited in claim (1) , wherein the electrode reinforcing plate is formed of molybdenum.
(3) A semiconductor device recited in claim (1) wherein the electrode reinforcing plate is formed of tungsten.
(4) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a thyristor, and the first and second main electrodes are an anode and a cathode, respectively.
(5) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a transistor, and first and second main electrodes are a collector electrode and an emitter electrode, respectively.
(6) A semiconductor device recited in claim (1) , wherein the semiconductor chip is a diode, and the first and second main electrodes are an anode and a cathode, respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60/209407 | 1985-09-20 | ||
| JP20940785A JPH079919B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1987001866A1 true WO1987001866A1 (en) | 1987-03-26 |
Family
ID=16572372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1986/000145 WO1987001866A1 (en) | 1985-09-20 | 1986-03-27 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0238665A1 (en) |
| JP (1) | JPH079919B2 (en) |
| IT (1) | IT1213490B (en) |
| WO (1) | WO1987001866A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0428916A1 (en) * | 1989-10-31 | 1991-05-29 | Kabushiki Kaisha Toshiba | Compression contacted semiconductor device and method for making of the same |
| US5040051A (en) * | 1988-12-05 | 1991-08-13 | Sundstrand Corporation | Hydrostatic clamp and method for compression type power semiconductors |
| US5063436A (en) * | 1989-02-02 | 1991-11-05 | Asea Brown Boveri Ltd. | Pressure-contacted semiconductor component |
| US5210601A (en) * | 1989-10-31 | 1993-05-11 | Kabushiki Kaisha Toshiba | Compression contacted semiconductor device and method for making of the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4099201A (en) * | 1977-04-11 | 1978-07-04 | General Electric Company | Semiconductor rectifier assembly having an insulating material therein that evolves gases when exposed to an arc |
| EP0080953A1 (en) * | 1981-12-02 | 1983-06-08 | Le Silicium Semiconducteur Ssc | Mounting of power components with a branched electrode structure in a pressure contact housing |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153767A (en) * | 1980-04-28 | 1981-11-27 | Mitsubishi Electric Corp | Manufacture of planar type thyristor |
| JPS5778178A (en) * | 1980-11-04 | 1982-05-15 | Toshiba Corp | Input protective circuit |
| JPS59218774A (en) * | 1983-05-26 | 1984-12-10 | Nec Corp | Thyristor |
-
1985
- 1985-09-20 JP JP20940785A patent/JPH079919B2/en not_active Expired - Lifetime
-
1986
- 1986-03-27 EP EP86902027A patent/EP0238665A1/en not_active Withdrawn
- 1986-03-27 WO PCT/JP1986/000145 patent/WO1987001866A1/en not_active Application Discontinuation
- 1986-09-09 IT IT2165586A patent/IT1213490B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4099201A (en) * | 1977-04-11 | 1978-07-04 | General Electric Company | Semiconductor rectifier assembly having an insulating material therein that evolves gases when exposed to an arc |
| EP0080953A1 (en) * | 1981-12-02 | 1983-06-08 | Le Silicium Semiconducteur Ssc | Mounting of power components with a branched electrode structure in a pressure contact housing |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040051A (en) * | 1988-12-05 | 1991-08-13 | Sundstrand Corporation | Hydrostatic clamp and method for compression type power semiconductors |
| US5063436A (en) * | 1989-02-02 | 1991-11-05 | Asea Brown Boveri Ltd. | Pressure-contacted semiconductor component |
| EP0428916A1 (en) * | 1989-10-31 | 1991-05-29 | Kabushiki Kaisha Toshiba | Compression contacted semiconductor device and method for making of the same |
| US5210601A (en) * | 1989-10-31 | 1993-05-11 | Kabushiki Kaisha Toshiba | Compression contacted semiconductor device and method for making of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| IT8621655A0 (en) | 1986-09-09 |
| JPH079919B2 (en) | 1995-02-01 |
| IT1213490B (en) | 1989-12-20 |
| EP0238665A1 (en) | 1987-09-30 |
| JPS6269522A (en) | 1987-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4815885B2 (en) | Method for controlling semiconductor device | |
| EP1643561A2 (en) | GaN-based semiconductor integrated circuit | |
| US7635892B2 (en) | Semiconductor device | |
| JP4696337B2 (en) | Semiconductor device | |
| US20130168700A1 (en) | Power semiconductor device | |
| US20070007614A1 (en) | Schottky diode with improved surge capability | |
| JPH06318708A (en) | High output mosfet | |
| WO2001059842A1 (en) | Vertical conduction flip-chip device with bump contacts on single surface | |
| JP2005236288A (en) | Lateral conduction schottky diode with plural mesas | |
| JPH05152574A (en) | Semiconductor device | |
| JP3848479B2 (en) | Power semiconductor device manufacturing method | |
| EP0756324A2 (en) | Bump electrode for transistor and method for producing the same | |
| EP1367649A2 (en) | Power device having electrodes on a top surface thereof | |
| CN113632238B (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
| JP3432708B2 (en) | Semiconductor devices and semiconductor modules | |
| JP6540563B2 (en) | Semiconductor device | |
| JP2005079462A (en) | Semiconductor device and method for manufacturing the same | |
| US5210601A (en) | Compression contacted semiconductor device and method for making of the same | |
| WO1987001866A1 (en) | Semiconductor device | |
| US20210035882A1 (en) | Power Semiconductor Device and Method | |
| US20230131163A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP2020150137A (en) | Semiconductor device | |
| JPH06140633A (en) | Mos driving type semiconductor device | |
| JPH05275688A (en) | Planar type power semiconductor element | |
| GB2289372A (en) | Method of manufacturing ohmic contact |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WWE | Wipo information: entry into national phase |
Ref document number: 1986902027 Country of ref document: EP |
|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): DE FR GB |
|
| WWP | Wipo information: published in national office |
Ref document number: 1986902027 Country of ref document: EP |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 1986902027 Country of ref document: EP |