WO1987000943A1

WO1987000943A1 - Circuit and process for coefficient transmission

Info

Publication number: WO1987000943A1
Application number: PCT/DE1986/000240
Authority: WO
Inventors: Thomas Hirschberg
Original assignee: Ant Nachrichtentechnik Gmbh
Priority date: 1985-08-02
Filing date: 1986-06-10
Publication date: 1987-02-12
Also published as: GB2194658A; DK161087D0; JPS63501451A; GB8719958D0; GB2194658B; DK161087A

Abstract

Sets of coefficients have to be fed in close succession and in an alternating manner from one of two RAM memories (RA, RB) to a transmission component (U) for digital signals, for example a level selector, comprising a channel processor (KP). The sets of coefficients coming from a processor, (P) which can be controlled by an adjusting element, arrive in alternation at the RAM memory which precisely is not delivering its memorized data to the channel processor (KP). In the event of fast transmission of the coefficients, the obstacle is that the latter have to be stored in the RAM memories under disseminated addresses. A transmission circuit (AR, DR, S1 to S8), in which the RAM addresses and coefficients are stored in an intermediate memory in parallel under the same continual addresses supplied by an address generator (AG), ensures rapid transmission of the coefficients.

Description

Circuit and method for transferring coefficients.

The invention relates to a transfer circuit and a transfer method as specified in the preambles of the claims. It is preferably used in a transmission link. Such a transmission element can be contained in a mixer, for example, the transmission properties of which can be determined by adjustable coefficients. To set the coefficients, an actuator is provided on the mixer with which an actuator is actuated, which in turn causes the coefficients to change. A set of coefficients is required in each case to determine the transmission properties of the transmission element at a specific point in time. If the actuator is now actuated and moved from one position to another, the coefficient set, which was initially decisive for the transmission properties, must not be suddenly changed to the coefficient set that corresponds to the new position of the actuator; if it is too strong and too sudden Changing the transmission properties of the transmission element would cause undesirable distortions. In order to avoid this, coefficient sets are successively supplied to the transmission element at short intervals, each of which leads to only a slight change in the transmission properties compared to the previous state. This results in an almost constant change in the transmission properties, which has no disruptive consequences.

A channel processor is located in the transmission element. It reads out coefficients from RAM (randam access memory), i.e. from a random access memory. So that the channel processor can work without interruption, two RAM areas that are identical to one another are assigned to it. In this way, one of these RAM areas can be read out by the channel processor, while the other is loaded in each case by a further processor with new coefficients, in accordance with the commands that this further processor has received from the actuator. At the end of a cycle, the two RAM areas swap roles so that one is always loaded and the other is read by the channel processor. In the following, this RAM is referred to as the main RAM.

Due to the properties of the channel processor, the coefficients that the channel processor requires in each case are not stored in the main RAM area under consecutive addresses, but are stored scattered therein. The result of this is that insufficient coefficients can be transmitted from the further processor to the channel processor within a sufficiently short time if a microprocessor is used for this transmission. Such a microprocessor would help with the correct classification the coefficients in the main RAMs take too much time. There are so-called DMA modules (direct memory access) with which the required amount of data could be transferred in the required time, but this would only be possible if the data to be transferred had consecutive addresses.

It is an object of the invention to enable the transfer of a sufficiently large number of coefficients to the channel processor in a short time despite the difficulties described.

This object is achieved by the transfer circuit or the transfer method with the features of the claims. The transfer circuit or the transfer method according to the invention acts like a DMA circuit.

This will be explained in more detail using the drawings. A processor P controlled by an actuator (not shown) is to alternately write sets of coefficients into a main RAM RA or RB, the memory contents of which the channel processor KP of a transmission element U accesses in alternating directions. So while the channel processor KP is currently obtaining a set of coefficients from the main RAM RA, the main RAM RB receives coefficients from the processor P via a data bus DB with switch S2 and via an address bus AB with switch S1 via a transfer circuit. In addition to the switches S1, S2, the transfer circuit consists of an address RAM AR and a data RAM DR with associated switches S3, S4 and Sβ in the data or address bus coming from the processor P and a switch S5 in an address -Bus AB, which comes from an address generator AG.

The transfer circuit manages the data flow in the Direction D in two steps of a transfer cycle:

First step:

First, the address RAM AR and the data RAM DR are loaded by the processor P. Switches S3, S4, S6 are closed and S5, S7, S8 are open. This phase is not critical in terms of time!

Second step:

For a second step, the switches S3 to S8 change their positions; the processor P is disconnected from the address bus AB and from the data bus DB. To read out the memory contents of the address RAM AR and the data RAM DR, consecutive addresses are output by the address generator AG via the switch S5.

In a first sub-step, a first part of the memory content of the data RAM DR is written into the main RAM RB with the switch positions S1 and S2 shown; the memory content of the address RAM AR is used to address the memory cells of the 'main RAM RB.

In a second sub-step, a further part of the memory content of the address RAM AR and of the data RAM DR is used in the changed positions of the switches S1, S2 for reloading the main RAM RA in a period in which the channel processor KP has coefficients from the main -RAM RB takes.

The switching between the main RAM RA and the main RAM RB with opposite writing and reading is now repeated until the entire data content of the data RAM DR has been transferred. During this transfer of the entire data content, the address generator AG continuously generates addresses in the same way as it did when loading the address RAM AR and the data RAM DR. So far it has not been mentioned what actually loads the address RAM AR and the data RAM DR. In this regard, reference is made to FIG. 2:

The address RAM AR and the data RAM DR are preferably given the same address RAM or data RAM addresses (columns 1 and 3), but in any case consecutive addresses 0, 1, ... n -1, n, n + 1 ... etc. Those addresses are stored under these addresses in the address RAM AR, under which the storage of individual coefficients should take place in the main RAM RA or RB. For example, the RAM-RA or RAM-RB addresses for a first coefficient set I are stored in the address RAM under its addresses 0, 1, ... n-1.

This first coefficient set I consists of the coefficients 1 / I, 2 / I, ... n / I. The processor P stores these coefficients in parallel with the loading of the address RAM in the memory cells of the data RAM DR, again at the addresses 0, 1,... N-1.

In the same way, the second coefficient set II and further coefficient sets are stored with their associated addresses.

By arranging the transfer circuit AR, DR, etc., it has been achieved in this way that the coefficients may be stored in the main RAMs RA or RB under non-consecutive addresses, as required for the operation of the channel processor KP; nevertheless, a sufficiently large number of coefficients can be transferred from the processor P to the channel processor KP in the required short time.

So that the address generator AG for reading out the address RAM AR and the data RAM DR the same number of address RAM or Da Ten-RAM addresses generated, as when storing, it is still necessary that the address generator AG before closing the switch S5, that is, before reading out the address and data RAM, the number of coefficients per coefficient set and the total number of coefficients to be transferred is transmitted by the processor P. In addition, the address generator requires information (not shown here) from the channel processor KP about the times of the switchover from the main RAM RA to the main RAM RB and vice versa, so that a new coefficient loading cycle can be started at the correct time.

Claims

Transfer circuit for transferring coefficients from a processor (P), which is preferably controlled by an actuator, to a coefficient processor (KP), which is preferably contained in a transmission element (U), with two main RAMs or RAM areas (RA , RB), into which coefficients can be alternately written and which can then be connected alternately in opposite directions to the coefficient processor (KP) for reading out the coefficients, characterized by the following features: a) the transfer circuit has two additional RAMs or RAM areas, namely an address RAM (AR) and a data RAM (DR), which can be repeatedly loaded in transfer cycles, first in a write-in phase and discharged in several readout phases, b) the address bus inputs (AB) of the additional RAMs or RAM Areas (AR, DR) are with the address bus output (AB) of the processor (P) during the write-in phase of a transfer cycle and with the address during the read-out phases sensor generator (AG) connectable, c) data bus inputs (DB) of the address RAM (AR) and data RAM (DR) are connected to the data bus output (DB) of the processor (P) during the write-in phase connectable so that the address RAM (AR) receives the main RAM addresses and the data RAM (DR) the associated coefficients as data, d) the transfer circuit (AR, DR, S1 to S8) can be controlled, that in each case during the successive readout phases of a transfer cycle, that is to say as long as within a transfer cycle from any one (RA, RB) of the mutually alternating main RAMs or RAM areas, coefficients are read into the transmission element (U, KP), the processor (P) is separated from the transfer circuit and addresses (0, 1 ... n-1) to the address RAM (AR) and the data RAM (DR) and their data are read out and written into the other main RAM or main RAM area (RB, RA), wherein the stored data of the address RAM (AR) serve to address that main RAM or RAM area (RB) in which the coefficients are currently being written.

Transfer method for transferring coefficients from a processor (P), which is preferably controlled by an actuator, to a coefficient processor (KP), which is preferably contained in a transmission element (U), two main RAMs or RAM areas ( RA, RB), alternately, coefficients are written, which are then read out alternately in opposite directions in the coefficient processor (KP), characterized by the following features: a) two additional RAMs or RAM areas, namely an address RAM (AR) and a data RAM (DR) are repeatedly loaded in transfer cycles, first in a write-in phase and discharged in several read-out phases, for which purpose the address bus inputs (AB) of the additional RAMs or RAM areas (AR, DR) during the write-in phase of the address -Bus output (AB) of the processor (P) and are fed by the address generator (AG) during the readout phases, b). Data bus inputs (DB) of the address RAM (AR) and the data RAM (DR) are used by the da The ten-bus output (DB) of the processor (P) is fed such that the address RAM (AR) receives the main RAM addresses and the data RAM (DR) the associated coefficients each as data during the successive ones Reading phases of a transfer cycle, that is, as long as coefficients are read out from any (RA, RB) of the alternating main RAMs or RAM areas within the transfer cycle into the transfer element (U, KP), the transfer of coefficients from the processor (P) to the additional RAMs or RAM areas (AR, DR) are interrupted and the address generator (AG) sends consecutive addresses (0, 1 ... n-1) to the address RAM (AR) and the data -RAM (DR) and its data read out and written into the other main RAM or main RAM area (RB, RA), the stored data of the address RAM (AR) for addressing that main RAM or - RAM area (RB, RA) serve, in which the coefficients are currently limited be sifted.